mbed library sources
Dependents: frdm_kl05z_gpio_test
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pit.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_pit.h@146:f64d43ff0c18
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
mbed_official | 146:f64d43ff0c18 | 4 | * |
mbed_official | 146:f64d43ff0c18 | 5 | * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 146:f64d43ff0c18 | 6 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 146:f64d43ff0c18 | 7 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT |
mbed_official | 146:f64d43ff0c18 | 8 | * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
mbed_official | 146:f64d43ff0c18 | 9 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
mbed_official | 146:f64d43ff0c18 | 10 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
mbed_official | 146:f64d43ff0c18 | 11 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
mbed_official | 146:f64d43ff0c18 | 12 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
mbed_official | 146:f64d43ff0c18 | 13 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
mbed_official | 146:f64d43ff0c18 | 14 | * OF SUCH DAMAGE. |
mbed_official | 146:f64d43ff0c18 | 15 | */ |
mbed_official | 146:f64d43ff0c18 | 16 | /* |
mbed_official | 146:f64d43ff0c18 | 17 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
mbed_official | 146:f64d43ff0c18 | 18 | * |
mbed_official | 146:f64d43ff0c18 | 19 | * This file was generated automatically and any changes may be lost. |
mbed_official | 146:f64d43ff0c18 | 20 | */ |
mbed_official | 146:f64d43ff0c18 | 21 | #ifndef __HW_PIT_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 22 | #define __HW_PIT_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 23 | |
mbed_official | 146:f64d43ff0c18 | 24 | #include "regs.h" |
mbed_official | 146:f64d43ff0c18 | 25 | |
mbed_official | 146:f64d43ff0c18 | 26 | /* |
mbed_official | 146:f64d43ff0c18 | 27 | * MK64F12 PIT |
mbed_official | 146:f64d43ff0c18 | 28 | * |
mbed_official | 146:f64d43ff0c18 | 29 | * Periodic Interrupt Timer |
mbed_official | 146:f64d43ff0c18 | 30 | * |
mbed_official | 146:f64d43ff0c18 | 31 | * Registers defined in this header file: |
mbed_official | 146:f64d43ff0c18 | 32 | * - HW_PIT_MCR - PIT Module Control Register |
mbed_official | 146:f64d43ff0c18 | 33 | * - HW_PIT_LDVALn - Timer Load Value Register |
mbed_official | 146:f64d43ff0c18 | 34 | * - HW_PIT_CVALn - Current Timer Value Register |
mbed_official | 146:f64d43ff0c18 | 35 | * - HW_PIT_TCTRLn - Timer Control Register |
mbed_official | 146:f64d43ff0c18 | 36 | * - HW_PIT_TFLGn - Timer Flag Register |
mbed_official | 146:f64d43ff0c18 | 37 | * |
mbed_official | 146:f64d43ff0c18 | 38 | * - hw_pit_t - Struct containing all module registers. |
mbed_official | 146:f64d43ff0c18 | 39 | */ |
mbed_official | 146:f64d43ff0c18 | 40 | |
mbed_official | 146:f64d43ff0c18 | 41 | //! @name Module base addresses |
mbed_official | 146:f64d43ff0c18 | 42 | //@{ |
mbed_official | 146:f64d43ff0c18 | 43 | #ifndef REGS_PIT_BASE |
mbed_official | 146:f64d43ff0c18 | 44 | #define HW_PIT_INSTANCE_COUNT (1U) //!< Number of instances of the PIT module. |
mbed_official | 146:f64d43ff0c18 | 45 | #define REGS_PIT_BASE (0x40037000U) //!< Base address for PIT. |
mbed_official | 146:f64d43ff0c18 | 46 | #endif |
mbed_official | 146:f64d43ff0c18 | 47 | //@} |
mbed_official | 146:f64d43ff0c18 | 48 | |
mbed_official | 146:f64d43ff0c18 | 49 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 50 | // HW_PIT_MCR - PIT Module Control Register |
mbed_official | 146:f64d43ff0c18 | 51 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 52 | |
mbed_official | 146:f64d43ff0c18 | 53 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 54 | /*! |
mbed_official | 146:f64d43ff0c18 | 55 | * @brief HW_PIT_MCR - PIT Module Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 56 | * |
mbed_official | 146:f64d43ff0c18 | 57 | * Reset value: 0x00000006U |
mbed_official | 146:f64d43ff0c18 | 58 | * |
mbed_official | 146:f64d43ff0c18 | 59 | * This register enables or disables the PIT timer clocks and controls the |
mbed_official | 146:f64d43ff0c18 | 60 | * timers when the PIT enters the Debug mode. |
mbed_official | 146:f64d43ff0c18 | 61 | */ |
mbed_official | 146:f64d43ff0c18 | 62 | typedef union _hw_pit_mcr |
mbed_official | 146:f64d43ff0c18 | 63 | { |
mbed_official | 146:f64d43ff0c18 | 64 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 65 | struct _hw_pit_mcr_bitfields |
mbed_official | 146:f64d43ff0c18 | 66 | { |
mbed_official | 146:f64d43ff0c18 | 67 | uint32_t FRZ : 1; //!< [0] Freeze |
mbed_official | 146:f64d43ff0c18 | 68 | uint32_t MDIS : 1; //!< [1] Module Disable - (PIT section) |
mbed_official | 146:f64d43ff0c18 | 69 | uint32_t RESERVED0 : 30; //!< [31:2] |
mbed_official | 146:f64d43ff0c18 | 70 | } B; |
mbed_official | 146:f64d43ff0c18 | 71 | } hw_pit_mcr_t; |
mbed_official | 146:f64d43ff0c18 | 72 | #endif |
mbed_official | 146:f64d43ff0c18 | 73 | |
mbed_official | 146:f64d43ff0c18 | 74 | /*! |
mbed_official | 146:f64d43ff0c18 | 75 | * @name Constants and macros for entire PIT_MCR register |
mbed_official | 146:f64d43ff0c18 | 76 | */ |
mbed_official | 146:f64d43ff0c18 | 77 | //@{ |
mbed_official | 146:f64d43ff0c18 | 78 | #define HW_PIT_MCR_ADDR (REGS_PIT_BASE + 0x0U) |
mbed_official | 146:f64d43ff0c18 | 79 | |
mbed_official | 146:f64d43ff0c18 | 80 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 81 | #define HW_PIT_MCR (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR) |
mbed_official | 146:f64d43ff0c18 | 82 | #define HW_PIT_MCR_RD() (HW_PIT_MCR.U) |
mbed_official | 146:f64d43ff0c18 | 83 | #define HW_PIT_MCR_WR(v) (HW_PIT_MCR.U = (v)) |
mbed_official | 146:f64d43ff0c18 | 84 | #define HW_PIT_MCR_SET(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() | (v))) |
mbed_official | 146:f64d43ff0c18 | 85 | #define HW_PIT_MCR_CLR(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 86 | #define HW_PIT_MCR_TOG(v) (HW_PIT_MCR_WR(HW_PIT_MCR_RD() ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 87 | #endif |
mbed_official | 146:f64d43ff0c18 | 88 | //@} |
mbed_official | 146:f64d43ff0c18 | 89 | |
mbed_official | 146:f64d43ff0c18 | 90 | /* |
mbed_official | 146:f64d43ff0c18 | 91 | * Constants & macros for individual PIT_MCR bitfields |
mbed_official | 146:f64d43ff0c18 | 92 | */ |
mbed_official | 146:f64d43ff0c18 | 93 | |
mbed_official | 146:f64d43ff0c18 | 94 | /*! |
mbed_official | 146:f64d43ff0c18 | 95 | * @name Register PIT_MCR, field FRZ[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 96 | * |
mbed_official | 146:f64d43ff0c18 | 97 | * Allows the timers to be stopped when the device enters the Debug mode. |
mbed_official | 146:f64d43ff0c18 | 98 | * |
mbed_official | 146:f64d43ff0c18 | 99 | * Values: |
mbed_official | 146:f64d43ff0c18 | 100 | * - 0 - Timers continue to run in Debug mode. |
mbed_official | 146:f64d43ff0c18 | 101 | * - 1 - Timers are stopped in Debug mode. |
mbed_official | 146:f64d43ff0c18 | 102 | */ |
mbed_official | 146:f64d43ff0c18 | 103 | //@{ |
mbed_official | 146:f64d43ff0c18 | 104 | #define BP_PIT_MCR_FRZ (0U) //!< Bit position for PIT_MCR_FRZ. |
mbed_official | 146:f64d43ff0c18 | 105 | #define BM_PIT_MCR_FRZ (0x00000001U) //!< Bit mask for PIT_MCR_FRZ. |
mbed_official | 146:f64d43ff0c18 | 106 | #define BS_PIT_MCR_FRZ (1U) //!< Bit field size in bits for PIT_MCR_FRZ. |
mbed_official | 146:f64d43ff0c18 | 107 | |
mbed_official | 146:f64d43ff0c18 | 108 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 109 | //! @brief Read current value of the PIT_MCR_FRZ field. |
mbed_official | 146:f64d43ff0c18 | 110 | #define BR_PIT_MCR_FRZ (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ)) |
mbed_official | 146:f64d43ff0c18 | 111 | #endif |
mbed_official | 146:f64d43ff0c18 | 112 | |
mbed_official | 146:f64d43ff0c18 | 113 | //! @brief Format value for bitfield PIT_MCR_FRZ. |
mbed_official | 146:f64d43ff0c18 | 114 | #define BF_PIT_MCR_FRZ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_FRZ), uint32_t) & BM_PIT_MCR_FRZ) |
mbed_official | 146:f64d43ff0c18 | 115 | |
mbed_official | 146:f64d43ff0c18 | 116 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 117 | //! @brief Set the FRZ field to a new value. |
mbed_official | 146:f64d43ff0c18 | 118 | #define BW_PIT_MCR_FRZ(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_FRZ) = (v)) |
mbed_official | 146:f64d43ff0c18 | 119 | #endif |
mbed_official | 146:f64d43ff0c18 | 120 | //@} |
mbed_official | 146:f64d43ff0c18 | 121 | |
mbed_official | 146:f64d43ff0c18 | 122 | /*! |
mbed_official | 146:f64d43ff0c18 | 123 | * @name Register PIT_MCR, field MDIS[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 124 | * |
mbed_official | 146:f64d43ff0c18 | 125 | * Disables the standard timers. This field must be enabled before any other |
mbed_official | 146:f64d43ff0c18 | 126 | * setup is done. |
mbed_official | 146:f64d43ff0c18 | 127 | * |
mbed_official | 146:f64d43ff0c18 | 128 | * Values: |
mbed_official | 146:f64d43ff0c18 | 129 | * - 0 - Clock for standard PIT timers is enabled. |
mbed_official | 146:f64d43ff0c18 | 130 | * - 1 - Clock for standard PIT timers is disabled. |
mbed_official | 146:f64d43ff0c18 | 131 | */ |
mbed_official | 146:f64d43ff0c18 | 132 | //@{ |
mbed_official | 146:f64d43ff0c18 | 133 | #define BP_PIT_MCR_MDIS (1U) //!< Bit position for PIT_MCR_MDIS. |
mbed_official | 146:f64d43ff0c18 | 134 | #define BM_PIT_MCR_MDIS (0x00000002U) //!< Bit mask for PIT_MCR_MDIS. |
mbed_official | 146:f64d43ff0c18 | 135 | #define BS_PIT_MCR_MDIS (1U) //!< Bit field size in bits for PIT_MCR_MDIS. |
mbed_official | 146:f64d43ff0c18 | 136 | |
mbed_official | 146:f64d43ff0c18 | 137 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 138 | //! @brief Read current value of the PIT_MCR_MDIS field. |
mbed_official | 146:f64d43ff0c18 | 139 | #define BR_PIT_MCR_MDIS (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS)) |
mbed_official | 146:f64d43ff0c18 | 140 | #endif |
mbed_official | 146:f64d43ff0c18 | 141 | |
mbed_official | 146:f64d43ff0c18 | 142 | //! @brief Format value for bitfield PIT_MCR_MDIS. |
mbed_official | 146:f64d43ff0c18 | 143 | #define BF_PIT_MCR_MDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_MCR_MDIS), uint32_t) & BM_PIT_MCR_MDIS) |
mbed_official | 146:f64d43ff0c18 | 144 | |
mbed_official | 146:f64d43ff0c18 | 145 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 146 | //! @brief Set the MDIS field to a new value. |
mbed_official | 146:f64d43ff0c18 | 147 | #define BW_PIT_MCR_MDIS(v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR, BP_PIT_MCR_MDIS) = (v)) |
mbed_official | 146:f64d43ff0c18 | 148 | #endif |
mbed_official | 146:f64d43ff0c18 | 149 | //@} |
mbed_official | 146:f64d43ff0c18 | 150 | |
mbed_official | 146:f64d43ff0c18 | 151 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 152 | // HW_PIT_LDVALn - Timer Load Value Register |
mbed_official | 146:f64d43ff0c18 | 153 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 154 | |
mbed_official | 146:f64d43ff0c18 | 155 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 156 | /*! |
mbed_official | 146:f64d43ff0c18 | 157 | * @brief HW_PIT_LDVALn - Timer Load Value Register (RW) |
mbed_official | 146:f64d43ff0c18 | 158 | * |
mbed_official | 146:f64d43ff0c18 | 159 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 160 | * |
mbed_official | 146:f64d43ff0c18 | 161 | * These registers select the timeout period for the timer interrupts. |
mbed_official | 146:f64d43ff0c18 | 162 | */ |
mbed_official | 146:f64d43ff0c18 | 163 | typedef union _hw_pit_ldvaln |
mbed_official | 146:f64d43ff0c18 | 164 | { |
mbed_official | 146:f64d43ff0c18 | 165 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 166 | struct _hw_pit_ldvaln_bitfields |
mbed_official | 146:f64d43ff0c18 | 167 | { |
mbed_official | 146:f64d43ff0c18 | 168 | uint32_t TSV : 32; //!< [31:0] Timer Start Value |
mbed_official | 146:f64d43ff0c18 | 169 | } B; |
mbed_official | 146:f64d43ff0c18 | 170 | } hw_pit_ldvaln_t; |
mbed_official | 146:f64d43ff0c18 | 171 | #endif |
mbed_official | 146:f64d43ff0c18 | 172 | |
mbed_official | 146:f64d43ff0c18 | 173 | /*! |
mbed_official | 146:f64d43ff0c18 | 174 | * @name Constants and macros for entire PIT_LDVALn register |
mbed_official | 146:f64d43ff0c18 | 175 | */ |
mbed_official | 146:f64d43ff0c18 | 176 | //@{ |
mbed_official | 146:f64d43ff0c18 | 177 | #define HW_PIT_LDVALn_COUNT (4U) |
mbed_official | 146:f64d43ff0c18 | 178 | |
mbed_official | 146:f64d43ff0c18 | 179 | #define HW_PIT_LDVALn_ADDR(n) (REGS_PIT_BASE + 0x100U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 180 | |
mbed_official | 146:f64d43ff0c18 | 181 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 182 | #define HW_PIT_LDVALn(n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 183 | #define HW_PIT_LDVALn_RD(n) (HW_PIT_LDVALn(n).U) |
mbed_official | 146:f64d43ff0c18 | 184 | #define HW_PIT_LDVALn_WR(n, v) (HW_PIT_LDVALn(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 185 | #define HW_PIT_LDVALn_SET(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 186 | #define HW_PIT_LDVALn_CLR(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 187 | #define HW_PIT_LDVALn_TOG(n, v) (HW_PIT_LDVALn_WR(n, HW_PIT_LDVALn_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 188 | #endif |
mbed_official | 146:f64d43ff0c18 | 189 | //@} |
mbed_official | 146:f64d43ff0c18 | 190 | |
mbed_official | 146:f64d43ff0c18 | 191 | /* |
mbed_official | 146:f64d43ff0c18 | 192 | * Constants & macros for individual PIT_LDVALn bitfields |
mbed_official | 146:f64d43ff0c18 | 193 | */ |
mbed_official | 146:f64d43ff0c18 | 194 | |
mbed_official | 146:f64d43ff0c18 | 195 | /*! |
mbed_official | 146:f64d43ff0c18 | 196 | * @name Register PIT_LDVALn, field TSV[31:0] (RW) |
mbed_official | 146:f64d43ff0c18 | 197 | * |
mbed_official | 146:f64d43ff0c18 | 198 | * Sets the timer start value. The timer will count down until it reaches 0, |
mbed_official | 146:f64d43ff0c18 | 199 | * then it will generate an interrupt and load this register value again. Writing a |
mbed_official | 146:f64d43ff0c18 | 200 | * new value to this register will not restart the timer; instead the value will |
mbed_official | 146:f64d43ff0c18 | 201 | * be loaded after the timer expires. To abort the current cycle and start a |
mbed_official | 146:f64d43ff0c18 | 202 | * timer period with the new value, the timer must be disabled and enabled again. |
mbed_official | 146:f64d43ff0c18 | 203 | */ |
mbed_official | 146:f64d43ff0c18 | 204 | //@{ |
mbed_official | 146:f64d43ff0c18 | 205 | #define BP_PIT_LDVALn_TSV (0U) //!< Bit position for PIT_LDVALn_TSV. |
mbed_official | 146:f64d43ff0c18 | 206 | #define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) //!< Bit mask for PIT_LDVALn_TSV. |
mbed_official | 146:f64d43ff0c18 | 207 | #define BS_PIT_LDVALn_TSV (32U) //!< Bit field size in bits for PIT_LDVALn_TSV. |
mbed_official | 146:f64d43ff0c18 | 208 | |
mbed_official | 146:f64d43ff0c18 | 209 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 210 | //! @brief Read current value of the PIT_LDVALn_TSV field. |
mbed_official | 146:f64d43ff0c18 | 211 | #define BR_PIT_LDVALn_TSV(n) (HW_PIT_LDVALn(n).U) |
mbed_official | 146:f64d43ff0c18 | 212 | #endif |
mbed_official | 146:f64d43ff0c18 | 213 | |
mbed_official | 146:f64d43ff0c18 | 214 | //! @brief Format value for bitfield PIT_LDVALn_TSV. |
mbed_official | 146:f64d43ff0c18 | 215 | #define BF_PIT_LDVALn_TSV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_LDVALn_TSV), uint32_t) & BM_PIT_LDVALn_TSV) |
mbed_official | 146:f64d43ff0c18 | 216 | |
mbed_official | 146:f64d43ff0c18 | 217 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 218 | //! @brief Set the TSV field to a new value. |
mbed_official | 146:f64d43ff0c18 | 219 | #define BW_PIT_LDVALn_TSV(n, v) (HW_PIT_LDVALn_WR(n, v)) |
mbed_official | 146:f64d43ff0c18 | 220 | #endif |
mbed_official | 146:f64d43ff0c18 | 221 | //@} |
mbed_official | 146:f64d43ff0c18 | 222 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 223 | // HW_PIT_CVALn - Current Timer Value Register |
mbed_official | 146:f64d43ff0c18 | 224 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 225 | |
mbed_official | 146:f64d43ff0c18 | 226 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 227 | /*! |
mbed_official | 146:f64d43ff0c18 | 228 | * @brief HW_PIT_CVALn - Current Timer Value Register (RO) |
mbed_official | 146:f64d43ff0c18 | 229 | * |
mbed_official | 146:f64d43ff0c18 | 230 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 231 | * |
mbed_official | 146:f64d43ff0c18 | 232 | * These registers indicate the current timer position. |
mbed_official | 146:f64d43ff0c18 | 233 | */ |
mbed_official | 146:f64d43ff0c18 | 234 | typedef union _hw_pit_cvaln |
mbed_official | 146:f64d43ff0c18 | 235 | { |
mbed_official | 146:f64d43ff0c18 | 236 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 237 | struct _hw_pit_cvaln_bitfields |
mbed_official | 146:f64d43ff0c18 | 238 | { |
mbed_official | 146:f64d43ff0c18 | 239 | uint32_t TVL : 32; //!< [31:0] Current Timer Value |
mbed_official | 146:f64d43ff0c18 | 240 | } B; |
mbed_official | 146:f64d43ff0c18 | 241 | } hw_pit_cvaln_t; |
mbed_official | 146:f64d43ff0c18 | 242 | #endif |
mbed_official | 146:f64d43ff0c18 | 243 | |
mbed_official | 146:f64d43ff0c18 | 244 | /*! |
mbed_official | 146:f64d43ff0c18 | 245 | * @name Constants and macros for entire PIT_CVALn register |
mbed_official | 146:f64d43ff0c18 | 246 | */ |
mbed_official | 146:f64d43ff0c18 | 247 | //@{ |
mbed_official | 146:f64d43ff0c18 | 248 | #define HW_PIT_CVALn_COUNT (4U) |
mbed_official | 146:f64d43ff0c18 | 249 | |
mbed_official | 146:f64d43ff0c18 | 250 | #define HW_PIT_CVALn_ADDR(n) (REGS_PIT_BASE + 0x104U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 251 | |
mbed_official | 146:f64d43ff0c18 | 252 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 253 | #define HW_PIT_CVALn(n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 254 | #define HW_PIT_CVALn_RD(n) (HW_PIT_CVALn(n).U) |
mbed_official | 146:f64d43ff0c18 | 255 | #endif |
mbed_official | 146:f64d43ff0c18 | 256 | //@} |
mbed_official | 146:f64d43ff0c18 | 257 | |
mbed_official | 146:f64d43ff0c18 | 258 | /* |
mbed_official | 146:f64d43ff0c18 | 259 | * Constants & macros for individual PIT_CVALn bitfields |
mbed_official | 146:f64d43ff0c18 | 260 | */ |
mbed_official | 146:f64d43ff0c18 | 261 | |
mbed_official | 146:f64d43ff0c18 | 262 | /*! |
mbed_official | 146:f64d43ff0c18 | 263 | * @name Register PIT_CVALn, field TVL[31:0] (RO) |
mbed_official | 146:f64d43ff0c18 | 264 | * |
mbed_official | 146:f64d43ff0c18 | 265 | * Represents the current timer value, if the timer is enabled. If the timer is |
mbed_official | 146:f64d43ff0c18 | 266 | * disabled, do not use this field as its value is unreliable. The timer uses a |
mbed_official | 146:f64d43ff0c18 | 267 | * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set. |
mbed_official | 146:f64d43ff0c18 | 268 | */ |
mbed_official | 146:f64d43ff0c18 | 269 | //@{ |
mbed_official | 146:f64d43ff0c18 | 270 | #define BP_PIT_CVALn_TVL (0U) //!< Bit position for PIT_CVALn_TVL. |
mbed_official | 146:f64d43ff0c18 | 271 | #define BM_PIT_CVALn_TVL (0xFFFFFFFFU) //!< Bit mask for PIT_CVALn_TVL. |
mbed_official | 146:f64d43ff0c18 | 272 | #define BS_PIT_CVALn_TVL (32U) //!< Bit field size in bits for PIT_CVALn_TVL. |
mbed_official | 146:f64d43ff0c18 | 273 | |
mbed_official | 146:f64d43ff0c18 | 274 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 275 | //! @brief Read current value of the PIT_CVALn_TVL field. |
mbed_official | 146:f64d43ff0c18 | 276 | #define BR_PIT_CVALn_TVL(n) (HW_PIT_CVALn(n).U) |
mbed_official | 146:f64d43ff0c18 | 277 | #endif |
mbed_official | 146:f64d43ff0c18 | 278 | //@} |
mbed_official | 146:f64d43ff0c18 | 279 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 280 | // HW_PIT_TCTRLn - Timer Control Register |
mbed_official | 146:f64d43ff0c18 | 281 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 282 | |
mbed_official | 146:f64d43ff0c18 | 283 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 284 | /*! |
mbed_official | 146:f64d43ff0c18 | 285 | * @brief HW_PIT_TCTRLn - Timer Control Register (RW) |
mbed_official | 146:f64d43ff0c18 | 286 | * |
mbed_official | 146:f64d43ff0c18 | 287 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 288 | * |
mbed_official | 146:f64d43ff0c18 | 289 | * These registers contain the control bits for each timer. |
mbed_official | 146:f64d43ff0c18 | 290 | */ |
mbed_official | 146:f64d43ff0c18 | 291 | typedef union _hw_pit_tctrln |
mbed_official | 146:f64d43ff0c18 | 292 | { |
mbed_official | 146:f64d43ff0c18 | 293 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 294 | struct _hw_pit_tctrln_bitfields |
mbed_official | 146:f64d43ff0c18 | 295 | { |
mbed_official | 146:f64d43ff0c18 | 296 | uint32_t TEN : 1; //!< [0] Timer Enable |
mbed_official | 146:f64d43ff0c18 | 297 | uint32_t TIE : 1; //!< [1] Timer Interrupt Enable |
mbed_official | 146:f64d43ff0c18 | 298 | uint32_t CHN : 1; //!< [2] Chain Mode |
mbed_official | 146:f64d43ff0c18 | 299 | uint32_t RESERVED0 : 29; //!< [31:3] |
mbed_official | 146:f64d43ff0c18 | 300 | } B; |
mbed_official | 146:f64d43ff0c18 | 301 | } hw_pit_tctrln_t; |
mbed_official | 146:f64d43ff0c18 | 302 | #endif |
mbed_official | 146:f64d43ff0c18 | 303 | |
mbed_official | 146:f64d43ff0c18 | 304 | /*! |
mbed_official | 146:f64d43ff0c18 | 305 | * @name Constants and macros for entire PIT_TCTRLn register |
mbed_official | 146:f64d43ff0c18 | 306 | */ |
mbed_official | 146:f64d43ff0c18 | 307 | //@{ |
mbed_official | 146:f64d43ff0c18 | 308 | #define HW_PIT_TCTRLn_COUNT (4U) |
mbed_official | 146:f64d43ff0c18 | 309 | |
mbed_official | 146:f64d43ff0c18 | 310 | #define HW_PIT_TCTRLn_ADDR(n) (REGS_PIT_BASE + 0x108U + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 311 | |
mbed_official | 146:f64d43ff0c18 | 312 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 313 | #define HW_PIT_TCTRLn(n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 314 | #define HW_PIT_TCTRLn_RD(n) (HW_PIT_TCTRLn(n).U) |
mbed_official | 146:f64d43ff0c18 | 315 | #define HW_PIT_TCTRLn_WR(n, v) (HW_PIT_TCTRLn(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 316 | #define HW_PIT_TCTRLn_SET(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 317 | #define HW_PIT_TCTRLn_CLR(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 318 | #define HW_PIT_TCTRLn_TOG(n, v) (HW_PIT_TCTRLn_WR(n, HW_PIT_TCTRLn_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 319 | #endif |
mbed_official | 146:f64d43ff0c18 | 320 | //@} |
mbed_official | 146:f64d43ff0c18 | 321 | |
mbed_official | 146:f64d43ff0c18 | 322 | /* |
mbed_official | 146:f64d43ff0c18 | 323 | * Constants & macros for individual PIT_TCTRLn bitfields |
mbed_official | 146:f64d43ff0c18 | 324 | */ |
mbed_official | 146:f64d43ff0c18 | 325 | |
mbed_official | 146:f64d43ff0c18 | 326 | /*! |
mbed_official | 146:f64d43ff0c18 | 327 | * @name Register PIT_TCTRLn, field TEN[0] (RW) |
mbed_official | 146:f64d43ff0c18 | 328 | * |
mbed_official | 146:f64d43ff0c18 | 329 | * Enables or disables the timer. |
mbed_official | 146:f64d43ff0c18 | 330 | * |
mbed_official | 146:f64d43ff0c18 | 331 | * Values: |
mbed_official | 146:f64d43ff0c18 | 332 | * - 0 - Timer n is disabled. |
mbed_official | 146:f64d43ff0c18 | 333 | * - 1 - Timer n is enabled. |
mbed_official | 146:f64d43ff0c18 | 334 | */ |
mbed_official | 146:f64d43ff0c18 | 335 | //@{ |
mbed_official | 146:f64d43ff0c18 | 336 | #define BP_PIT_TCTRLn_TEN (0U) //!< Bit position for PIT_TCTRLn_TEN. |
mbed_official | 146:f64d43ff0c18 | 337 | #define BM_PIT_TCTRLn_TEN (0x00000001U) //!< Bit mask for PIT_TCTRLn_TEN. |
mbed_official | 146:f64d43ff0c18 | 338 | #define BS_PIT_TCTRLn_TEN (1U) //!< Bit field size in bits for PIT_TCTRLn_TEN. |
mbed_official | 146:f64d43ff0c18 | 339 | |
mbed_official | 146:f64d43ff0c18 | 340 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 341 | //! @brief Read current value of the PIT_TCTRLn_TEN field. |
mbed_official | 146:f64d43ff0c18 | 342 | #define BR_PIT_TCTRLn_TEN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN)) |
mbed_official | 146:f64d43ff0c18 | 343 | #endif |
mbed_official | 146:f64d43ff0c18 | 344 | |
mbed_official | 146:f64d43ff0c18 | 345 | //! @brief Format value for bitfield PIT_TCTRLn_TEN. |
mbed_official | 146:f64d43ff0c18 | 346 | #define BF_PIT_TCTRLn_TEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TEN), uint32_t) & BM_PIT_TCTRLn_TEN) |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 349 | //! @brief Set the TEN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 350 | #define BW_PIT_TCTRLn_TEN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TEN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 351 | #endif |
mbed_official | 146:f64d43ff0c18 | 352 | //@} |
mbed_official | 146:f64d43ff0c18 | 353 | |
mbed_official | 146:f64d43ff0c18 | 354 | /*! |
mbed_official | 146:f64d43ff0c18 | 355 | * @name Register PIT_TCTRLn, field TIE[1] (RW) |
mbed_official | 146:f64d43ff0c18 | 356 | * |
mbed_official | 146:f64d43ff0c18 | 357 | * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt |
mbed_official | 146:f64d43ff0c18 | 358 | * will immediately cause an interrupt event. To avoid this, the associated |
mbed_official | 146:f64d43ff0c18 | 359 | * TFLGn[TIF] must be cleared first. |
mbed_official | 146:f64d43ff0c18 | 360 | * |
mbed_official | 146:f64d43ff0c18 | 361 | * Values: |
mbed_official | 146:f64d43ff0c18 | 362 | * - 0 - Interrupt requests from Timer n are disabled. |
mbed_official | 146:f64d43ff0c18 | 363 | * - 1 - Interrupt will be requested whenever TIF is set. |
mbed_official | 146:f64d43ff0c18 | 364 | */ |
mbed_official | 146:f64d43ff0c18 | 365 | //@{ |
mbed_official | 146:f64d43ff0c18 | 366 | #define BP_PIT_TCTRLn_TIE (1U) //!< Bit position for PIT_TCTRLn_TIE. |
mbed_official | 146:f64d43ff0c18 | 367 | #define BM_PIT_TCTRLn_TIE (0x00000002U) //!< Bit mask for PIT_TCTRLn_TIE. |
mbed_official | 146:f64d43ff0c18 | 368 | #define BS_PIT_TCTRLn_TIE (1U) //!< Bit field size in bits for PIT_TCTRLn_TIE. |
mbed_official | 146:f64d43ff0c18 | 369 | |
mbed_official | 146:f64d43ff0c18 | 370 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 371 | //! @brief Read current value of the PIT_TCTRLn_TIE field. |
mbed_official | 146:f64d43ff0c18 | 372 | #define BR_PIT_TCTRLn_TIE(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE)) |
mbed_official | 146:f64d43ff0c18 | 373 | #endif |
mbed_official | 146:f64d43ff0c18 | 374 | |
mbed_official | 146:f64d43ff0c18 | 375 | //! @brief Format value for bitfield PIT_TCTRLn_TIE. |
mbed_official | 146:f64d43ff0c18 | 376 | #define BF_PIT_TCTRLn_TIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_TIE), uint32_t) & BM_PIT_TCTRLn_TIE) |
mbed_official | 146:f64d43ff0c18 | 377 | |
mbed_official | 146:f64d43ff0c18 | 378 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 379 | //! @brief Set the TIE field to a new value. |
mbed_official | 146:f64d43ff0c18 | 380 | #define BW_PIT_TCTRLn_TIE(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_TIE) = (v)) |
mbed_official | 146:f64d43ff0c18 | 381 | #endif |
mbed_official | 146:f64d43ff0c18 | 382 | //@} |
mbed_official | 146:f64d43ff0c18 | 383 | |
mbed_official | 146:f64d43ff0c18 | 384 | /*! |
mbed_official | 146:f64d43ff0c18 | 385 | * @name Register PIT_TCTRLn, field CHN[2] (RW) |
mbed_official | 146:f64d43ff0c18 | 386 | * |
mbed_official | 146:f64d43ff0c18 | 387 | * When activated, Timer n-1 needs to expire before timer n can decrement by 1. |
mbed_official | 146:f64d43ff0c18 | 388 | * Timer 0 cannot be chained. |
mbed_official | 146:f64d43ff0c18 | 389 | * |
mbed_official | 146:f64d43ff0c18 | 390 | * Values: |
mbed_official | 146:f64d43ff0c18 | 391 | * - 0 - Timer is not chained. |
mbed_official | 146:f64d43ff0c18 | 392 | * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this |
mbed_official | 146:f64d43ff0c18 | 393 | * field is set, Timer 2 is chained to Timer 1. |
mbed_official | 146:f64d43ff0c18 | 394 | */ |
mbed_official | 146:f64d43ff0c18 | 395 | //@{ |
mbed_official | 146:f64d43ff0c18 | 396 | #define BP_PIT_TCTRLn_CHN (2U) //!< Bit position for PIT_TCTRLn_CHN. |
mbed_official | 146:f64d43ff0c18 | 397 | #define BM_PIT_TCTRLn_CHN (0x00000004U) //!< Bit mask for PIT_TCTRLn_CHN. |
mbed_official | 146:f64d43ff0c18 | 398 | #define BS_PIT_TCTRLn_CHN (1U) //!< Bit field size in bits for PIT_TCTRLn_CHN. |
mbed_official | 146:f64d43ff0c18 | 399 | |
mbed_official | 146:f64d43ff0c18 | 400 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 401 | //! @brief Read current value of the PIT_TCTRLn_CHN field. |
mbed_official | 146:f64d43ff0c18 | 402 | #define BR_PIT_TCTRLn_CHN(n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN)) |
mbed_official | 146:f64d43ff0c18 | 403 | #endif |
mbed_official | 146:f64d43ff0c18 | 404 | |
mbed_official | 146:f64d43ff0c18 | 405 | //! @brief Format value for bitfield PIT_TCTRLn_CHN. |
mbed_official | 146:f64d43ff0c18 | 406 | #define BF_PIT_TCTRLn_CHN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TCTRLn_CHN), uint32_t) & BM_PIT_TCTRLn_CHN) |
mbed_official | 146:f64d43ff0c18 | 407 | |
mbed_official | 146:f64d43ff0c18 | 408 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 409 | //! @brief Set the CHN field to a new value. |
mbed_official | 146:f64d43ff0c18 | 410 | #define BW_PIT_TCTRLn_CHN(n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(n), BP_PIT_TCTRLn_CHN) = (v)) |
mbed_official | 146:f64d43ff0c18 | 411 | #endif |
mbed_official | 146:f64d43ff0c18 | 412 | //@} |
mbed_official | 146:f64d43ff0c18 | 413 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 414 | // HW_PIT_TFLGn - Timer Flag Register |
mbed_official | 146:f64d43ff0c18 | 415 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 416 | |
mbed_official | 146:f64d43ff0c18 | 417 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 418 | /*! |
mbed_official | 146:f64d43ff0c18 | 419 | * @brief HW_PIT_TFLGn - Timer Flag Register (RW) |
mbed_official | 146:f64d43ff0c18 | 420 | * |
mbed_official | 146:f64d43ff0c18 | 421 | * Reset value: 0x00000000U |
mbed_official | 146:f64d43ff0c18 | 422 | * |
mbed_official | 146:f64d43ff0c18 | 423 | * These registers hold the PIT interrupt flags. |
mbed_official | 146:f64d43ff0c18 | 424 | */ |
mbed_official | 146:f64d43ff0c18 | 425 | typedef union _hw_pit_tflgn |
mbed_official | 146:f64d43ff0c18 | 426 | { |
mbed_official | 146:f64d43ff0c18 | 427 | uint32_t U; |
mbed_official | 146:f64d43ff0c18 | 428 | struct _hw_pit_tflgn_bitfields |
mbed_official | 146:f64d43ff0c18 | 429 | { |
mbed_official | 146:f64d43ff0c18 | 430 | uint32_t TIF : 1; //!< [0] Timer Interrupt Flag |
mbed_official | 146:f64d43ff0c18 | 431 | uint32_t RESERVED0 : 31; //!< [31:1] |
mbed_official | 146:f64d43ff0c18 | 432 | } B; |
mbed_official | 146:f64d43ff0c18 | 433 | } hw_pit_tflgn_t; |
mbed_official | 146:f64d43ff0c18 | 434 | #endif |
mbed_official | 146:f64d43ff0c18 | 435 | |
mbed_official | 146:f64d43ff0c18 | 436 | /*! |
mbed_official | 146:f64d43ff0c18 | 437 | * @name Constants and macros for entire PIT_TFLGn register |
mbed_official | 146:f64d43ff0c18 | 438 | */ |
mbed_official | 146:f64d43ff0c18 | 439 | //@{ |
mbed_official | 146:f64d43ff0c18 | 440 | #define HW_PIT_TFLGn_COUNT (4U) |
mbed_official | 146:f64d43ff0c18 | 441 | |
mbed_official | 146:f64d43ff0c18 | 442 | #define HW_PIT_TFLGn_ADDR(n) (REGS_PIT_BASE + 0x10CU + (0x10U * n)) |
mbed_official | 146:f64d43ff0c18 | 443 | |
mbed_official | 146:f64d43ff0c18 | 444 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 445 | #define HW_PIT_TFLGn(n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(n)) |
mbed_official | 146:f64d43ff0c18 | 446 | #define HW_PIT_TFLGn_RD(n) (HW_PIT_TFLGn(n).U) |
mbed_official | 146:f64d43ff0c18 | 447 | #define HW_PIT_TFLGn_WR(n, v) (HW_PIT_TFLGn(n).U = (v)) |
mbed_official | 146:f64d43ff0c18 | 448 | #define HW_PIT_TFLGn_SET(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) | (v))) |
mbed_official | 146:f64d43ff0c18 | 449 | #define HW_PIT_TFLGn_CLR(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) & ~(v))) |
mbed_official | 146:f64d43ff0c18 | 450 | #define HW_PIT_TFLGn_TOG(n, v) (HW_PIT_TFLGn_WR(n, HW_PIT_TFLGn_RD(n) ^ (v))) |
mbed_official | 146:f64d43ff0c18 | 451 | #endif |
mbed_official | 146:f64d43ff0c18 | 452 | //@} |
mbed_official | 146:f64d43ff0c18 | 453 | |
mbed_official | 146:f64d43ff0c18 | 454 | /* |
mbed_official | 146:f64d43ff0c18 | 455 | * Constants & macros for individual PIT_TFLGn bitfields |
mbed_official | 146:f64d43ff0c18 | 456 | */ |
mbed_official | 146:f64d43ff0c18 | 457 | |
mbed_official | 146:f64d43ff0c18 | 458 | /*! |
mbed_official | 146:f64d43ff0c18 | 459 | * @name Register PIT_TFLGn, field TIF[0] (W1C) |
mbed_official | 146:f64d43ff0c18 | 460 | * |
mbed_official | 146:f64d43ff0c18 | 461 | * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. |
mbed_official | 146:f64d43ff0c18 | 462 | * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an |
mbed_official | 146:f64d43ff0c18 | 463 | * interrupt request. |
mbed_official | 146:f64d43ff0c18 | 464 | * |
mbed_official | 146:f64d43ff0c18 | 465 | * Values: |
mbed_official | 146:f64d43ff0c18 | 466 | * - 0 - Timeout has not yet occurred. |
mbed_official | 146:f64d43ff0c18 | 467 | * - 1 - Timeout has occurred. |
mbed_official | 146:f64d43ff0c18 | 468 | */ |
mbed_official | 146:f64d43ff0c18 | 469 | //@{ |
mbed_official | 146:f64d43ff0c18 | 470 | #define BP_PIT_TFLGn_TIF (0U) //!< Bit position for PIT_TFLGn_TIF. |
mbed_official | 146:f64d43ff0c18 | 471 | #define BM_PIT_TFLGn_TIF (0x00000001U) //!< Bit mask for PIT_TFLGn_TIF. |
mbed_official | 146:f64d43ff0c18 | 472 | #define BS_PIT_TFLGn_TIF (1U) //!< Bit field size in bits for PIT_TFLGn_TIF. |
mbed_official | 146:f64d43ff0c18 | 473 | |
mbed_official | 146:f64d43ff0c18 | 474 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 475 | //! @brief Read current value of the PIT_TFLGn_TIF field. |
mbed_official | 146:f64d43ff0c18 | 476 | #define BR_PIT_TFLGn_TIF(n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF)) |
mbed_official | 146:f64d43ff0c18 | 477 | #endif |
mbed_official | 146:f64d43ff0c18 | 478 | |
mbed_official | 146:f64d43ff0c18 | 479 | //! @brief Format value for bitfield PIT_TFLGn_TIF. |
mbed_official | 146:f64d43ff0c18 | 480 | #define BF_PIT_TFLGn_TIF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_PIT_TFLGn_TIF), uint32_t) & BM_PIT_TFLGn_TIF) |
mbed_official | 146:f64d43ff0c18 | 481 | |
mbed_official | 146:f64d43ff0c18 | 482 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 483 | //! @brief Set the TIF field to a new value. |
mbed_official | 146:f64d43ff0c18 | 484 | #define BW_PIT_TFLGn_TIF(n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(n), BP_PIT_TFLGn_TIF) = (v)) |
mbed_official | 146:f64d43ff0c18 | 485 | #endif |
mbed_official | 146:f64d43ff0c18 | 486 | //@} |
mbed_official | 146:f64d43ff0c18 | 487 | |
mbed_official | 146:f64d43ff0c18 | 488 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 489 | // hw_pit_t - module struct |
mbed_official | 146:f64d43ff0c18 | 490 | //------------------------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 491 | /*! |
mbed_official | 146:f64d43ff0c18 | 492 | * @brief All PIT module registers. |
mbed_official | 146:f64d43ff0c18 | 493 | */ |
mbed_official | 146:f64d43ff0c18 | 494 | #ifndef __LANGUAGE_ASM__ |
mbed_official | 146:f64d43ff0c18 | 495 | #pragma pack(1) |
mbed_official | 146:f64d43ff0c18 | 496 | typedef struct _hw_pit |
mbed_official | 146:f64d43ff0c18 | 497 | { |
mbed_official | 146:f64d43ff0c18 | 498 | __IO hw_pit_mcr_t MCR; //!< [0x0] PIT Module Control Register |
mbed_official | 146:f64d43ff0c18 | 499 | uint8_t _reserved0[252]; |
mbed_official | 146:f64d43ff0c18 | 500 | struct { |
mbed_official | 146:f64d43ff0c18 | 501 | __IO hw_pit_ldvaln_t LDVALn; //!< [0x100] Timer Load Value Register |
mbed_official | 146:f64d43ff0c18 | 502 | __I hw_pit_cvaln_t CVALn; //!< [0x104] Current Timer Value Register |
mbed_official | 146:f64d43ff0c18 | 503 | __IO hw_pit_tctrln_t TCTRLn; //!< [0x108] Timer Control Register |
mbed_official | 146:f64d43ff0c18 | 504 | __IO hw_pit_tflgn_t TFLGn; //!< [0x10C] Timer Flag Register |
mbed_official | 146:f64d43ff0c18 | 505 | } CHANNEL[4]; |
mbed_official | 146:f64d43ff0c18 | 506 | } hw_pit_t; |
mbed_official | 146:f64d43ff0c18 | 507 | #pragma pack() |
mbed_official | 146:f64d43ff0c18 | 508 | |
mbed_official | 146:f64d43ff0c18 | 509 | //! @brief Macro to access all PIT registers. |
mbed_official | 146:f64d43ff0c18 | 510 | //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
mbed_official | 146:f64d43ff0c18 | 511 | //! use the '&' operator, like <code>&HW_PIT</code>. |
mbed_official | 146:f64d43ff0c18 | 512 | #define HW_PIT (*(hw_pit_t *) REGS_PIT_BASE) |
mbed_official | 146:f64d43ff0c18 | 513 | #endif |
mbed_official | 146:f64d43ff0c18 | 514 | |
mbed_official | 146:f64d43ff0c18 | 515 | #endif // __HW_PIT_REGISTERS_H__ |
mbed_official | 146:f64d43ff0c18 | 516 | // v22/130726/0.9 |
mbed_official | 146:f64d43ff0c18 | 517 | // EOF |