shao ziyang / mbed-src-kl05

mbed library sources

Dependents:   frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.c@87:085cde657901, 2014-02-08 (annotated)

Committer:
mbed_official
Date:
Sat Feb 08 19:45:06 2014 +0000
Revision:
87:085cde657901
Child:
106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2



Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/



Add NUCLEO_F401RE, improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_ll_fmc.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 87:085cde657901 5 * @version V1.0.0RC2
mbed_official 87:085cde657901 6 * @date 04-February-2014
mbed_official 87:085cde657901 7 * @brief FMC Low Layer HAL module driver.
mbed_official 87:085cde657901 8 *
mbed_official 87:085cde657901 9 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
mbed_official 87:085cde657901 11 * + Initialization/de-initialization functions
mbed_official 87:085cde657901 12 * + Peripheral Control functions
mbed_official 87:085cde657901 13 * + Peripheral State functions
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### FMC peripheral features #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
mbed_official 87:085cde657901 20 (+) The NOR/PSRAM memory controller
mbed_official 87:085cde657901 21 (+) The NAND/PC Card memory controller
mbed_official 87:085cde657901 22 (+) The Synchronous DRAM (SDRAM) controller
mbed_official 87:085cde657901 23
mbed_official 87:085cde657901 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
mbed_official 87:085cde657901 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
mbed_official 87:085cde657901 26 (+) to translate AHB transactions into the appropriate external device protocol
mbed_official 87:085cde657901 27 (+) to meet the access time requirements of the external memory devices
mbed_official 87:085cde657901 28
mbed_official 87:085cde657901 29 [..] All external memories share the addresses, data and control signals with the controller.
mbed_official 87:085cde657901 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
mbed_official 87:085cde657901 31 only one access at a time to an external device.
mbed_official 87:085cde657901 32 The main features of the FMC controller are the following:
mbed_official 87:085cde657901 33 (+) Interface with static-memory mapped devices including:
mbed_official 87:085cde657901 34 (++) Static random access memory (SRAM)
mbed_official 87:085cde657901 35 (++) Read-only memory (ROM)
mbed_official 87:085cde657901 36 (++) NOR Flash memory/OneNAND Flash memory
mbed_official 87:085cde657901 37 (++) PSRAM (4 memory banks)
mbed_official 87:085cde657901 38 (++) 16-bit PC Card compatible devices
mbed_official 87:085cde657901 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
mbed_official 87:085cde657901 40 data
mbed_official 87:085cde657901 41 (+) Interface with synchronous DRAM (SDRAM) memories
mbed_official 87:085cde657901 42 (+) Independent Chip Select control for each memory bank
mbed_official 87:085cde657901 43 (+) Independent configuration for each memory bank
mbed_official 87:085cde657901 44
mbed_official 87:085cde657901 45 @endverbatim
mbed_official 87:085cde657901 46 ******************************************************************************
mbed_official 87:085cde657901 47 * @attention
mbed_official 87:085cde657901 48 *
mbed_official 87:085cde657901 49 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 50 *
mbed_official 87:085cde657901 51 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 52 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 53 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 54 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 56 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 57 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 59 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 60 * without specific prior written permission.
mbed_official 87:085cde657901 61 *
mbed_official 87:085cde657901 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 72 *
mbed_official 87:085cde657901 73 ******************************************************************************
mbed_official 87:085cde657901 74 */
mbed_official 87:085cde657901 75
mbed_official 87:085cde657901 76 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 77 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 78
mbed_official 87:085cde657901 79 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 80 * @{
mbed_official 87:085cde657901 81 */
mbed_official 87:085cde657901 82
mbed_official 87:085cde657901 83 /** @defgroup FMC
mbed_official 87:085cde657901 84 * @brief FMC driver modules
mbed_official 87:085cde657901 85 * @{
mbed_official 87:085cde657901 86 */
mbed_official 87:085cde657901 87
mbed_official 87:085cde657901 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
mbed_official 87:085cde657901 89
mbed_official 87:085cde657901 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 91
mbed_official 87:085cde657901 92 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 93 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 94 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 95 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 96 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 97 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 98
mbed_official 87:085cde657901 99 /** @defgroup FMC_Private_Functions
mbed_official 87:085cde657901 100 * @{
mbed_official 87:085cde657901 101 */
mbed_official 87:085cde657901 102
mbed_official 87:085cde657901 103 /** @defgroup FMC_NORSRAM Controller functions
mbed_official 87:085cde657901 104 * @brief NORSRAM Controller functions
mbed_official 87:085cde657901 105 *
mbed_official 87:085cde657901 106 @verbatim
mbed_official 87:085cde657901 107 ==============================================================================
mbed_official 87:085cde657901 108 ##### How to use NORSRAM device driver #####
mbed_official 87:085cde657901 109 ==============================================================================
mbed_official 87:085cde657901 110
mbed_official 87:085cde657901 111 [..]
mbed_official 87:085cde657901 112 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
mbed_official 87:085cde657901 113 to run the NORSRAM external devices.
mbed_official 87:085cde657901 114
mbed_official 87:085cde657901 115 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
mbed_official 87:085cde657901 116 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
mbed_official 87:085cde657901 117 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
mbed_official 87:085cde657901 118 (+) FMC NORSRAM bank extended timing configuration using the function
mbed_official 87:085cde657901 119 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 87:085cde657901 120 (+) FMC NORSRAM bank enable/disable write operation using the functions
mbed_official 87:085cde657901 121 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
mbed_official 87:085cde657901 122
mbed_official 87:085cde657901 123
mbed_official 87:085cde657901 124 @endverbatim
mbed_official 87:085cde657901 125 * @{
mbed_official 87:085cde657901 126 */
mbed_official 87:085cde657901 127
mbed_official 87:085cde657901 128 /** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
mbed_official 87:085cde657901 129 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 130 *
mbed_official 87:085cde657901 131 @verbatim
mbed_official 87:085cde657901 132 ==============================================================================
mbed_official 87:085cde657901 133 ##### Initialization and de_initialization functions #####
mbed_official 87:085cde657901 134 ==============================================================================
mbed_official 87:085cde657901 135 [..]
mbed_official 87:085cde657901 136 This section provides functions allowing to:
mbed_official 87:085cde657901 137 (+) Initialize and configure the FMC NORSRAM interface
mbed_official 87:085cde657901 138 (+) De-initialize the FMC NORSRAM interface
mbed_official 87:085cde657901 139 (+) Configure the FMC clock and associated GPIOs
mbed_official 87:085cde657901 140
mbed_official 87:085cde657901 141 @endverbatim
mbed_official 87:085cde657901 142 * @{
mbed_official 87:085cde657901 143 */
mbed_official 87:085cde657901 144
mbed_official 87:085cde657901 145 /**
mbed_official 87:085cde657901 146 * @brief Initialize the FMC_NORSRAM device according to the specified
mbed_official 87:085cde657901 147 * control parameters in the FMC_NORSRAM_InitTypeDef
mbed_official 87:085cde657901 148 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 149 * @param Init: Pointer to NORSRAM Initialization structure
mbed_official 87:085cde657901 150 * @retval HAL status
mbed_official 87:085cde657901 151 */
mbed_official 87:085cde657901 152 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
mbed_official 87:085cde657901 153 {
mbed_official 87:085cde657901 154 uint32_t tmpr = 0;
mbed_official 87:085cde657901 155
mbed_official 87:085cde657901 156 /* Check the parameters */
mbed_official 87:085cde657901 157 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 87:085cde657901 158 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
mbed_official 87:085cde657901 159 assert_param(IS_FMC_MUX(Init->DataAddressMux));
mbed_official 87:085cde657901 160 assert_param(IS_FMC_MEMORY(Init->MemoryType));
mbed_official 87:085cde657901 161 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 87:085cde657901 162 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
mbed_official 87:085cde657901 163 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
mbed_official 87:085cde657901 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
mbed_official 87:085cde657901 165 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
mbed_official 87:085cde657901 166 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
mbed_official 87:085cde657901 167 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
mbed_official 87:085cde657901 168 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
mbed_official 87:085cde657901 169 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
mbed_official 87:085cde657901 170 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
mbed_official 87:085cde657901 171 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
mbed_official 87:085cde657901 172
mbed_official 87:085cde657901 173 /* Set NORSRAM device control parameters */
mbed_official 87:085cde657901 174 tmpr = (uint32_t)(Init->DataAddressMux |\
mbed_official 87:085cde657901 175 Init->MemoryType |\
mbed_official 87:085cde657901 176 Init->MemoryDataWidth |\
mbed_official 87:085cde657901 177 Init->BurstAccessMode |\
mbed_official 87:085cde657901 178 Init->WaitSignalPolarity |\
mbed_official 87:085cde657901 179 Init->WrapMode |\
mbed_official 87:085cde657901 180 Init->WaitSignalActive |\
mbed_official 87:085cde657901 181 Init->WriteOperation |\
mbed_official 87:085cde657901 182 Init->WaitSignal |\
mbed_official 87:085cde657901 183 Init->ExtendedMode |\
mbed_official 87:085cde657901 184 Init->AsynchronousWait |\
mbed_official 87:085cde657901 185 Init->WriteBurst |\
mbed_official 87:085cde657901 186 Init->ContinuousClock
mbed_official 87:085cde657901 187 );
mbed_official 87:085cde657901 188
mbed_official 87:085cde657901 189 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
mbed_official 87:085cde657901 190 {
mbed_official 87:085cde657901 191 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
mbed_official 87:085cde657901 192 }
mbed_official 87:085cde657901 193
mbed_official 87:085cde657901 194 Device->BTCR[Init->NSBank] = tmpr;
mbed_official 87:085cde657901 195
mbed_official 87:085cde657901 196 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
mbed_official 87:085cde657901 197 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
mbed_official 87:085cde657901 198 {
mbed_official 87:085cde657901 199 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
mbed_official 87:085cde657901 200 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
mbed_official 87:085cde657901 201 Init->ContinuousClock);
mbed_official 87:085cde657901 202 }
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 return HAL_OK;
mbed_official 87:085cde657901 205 }
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207
mbed_official 87:085cde657901 208 /**
mbed_official 87:085cde657901 209 * @brief DeInitialize the FMC_NORSRAM peripheral
mbed_official 87:085cde657901 210 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 211 * @param ExDevice: Pointer to NORSRAM extended mode device instance
mbed_official 87:085cde657901 212 * @param Bank: NORSRAM bank number
mbed_official 87:085cde657901 213 * @retval HAL status
mbed_official 87:085cde657901 214 */
mbed_official 87:085cde657901 215 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
mbed_official 87:085cde657901 216 {
mbed_official 87:085cde657901 217 /* Check the parameters */
mbed_official 87:085cde657901 218 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 87:085cde657901 219 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
mbed_official 87:085cde657901 220 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 87:085cde657901 221
mbed_official 87:085cde657901 222 /* Disable the FMC_NORSRAM device */
mbed_official 87:085cde657901 223 __FMC_NORSRAM_DISABLE(Device, Bank);
mbed_official 87:085cde657901 224
mbed_official 87:085cde657901 225 /* De-initialize the FMC_NORSRAM device */
mbed_official 87:085cde657901 226 /* FMC_NORSRAM_BANK1 */
mbed_official 87:085cde657901 227 if(Bank == FMC_NORSRAM_BANK1)
mbed_official 87:085cde657901 228 {
mbed_official 87:085cde657901 229 Device->BTCR[Bank] = 0x000030DB;
mbed_official 87:085cde657901 230 }
mbed_official 87:085cde657901 231 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
mbed_official 87:085cde657901 232 else
mbed_official 87:085cde657901 233 {
mbed_official 87:085cde657901 234 Device->BTCR[Bank] = 0x000030D2;
mbed_official 87:085cde657901 235 }
mbed_official 87:085cde657901 236
mbed_official 87:085cde657901 237 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
mbed_official 87:085cde657901 238 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 87:085cde657901 239
mbed_official 87:085cde657901 240 return HAL_OK;
mbed_official 87:085cde657901 241 }
mbed_official 87:085cde657901 242
mbed_official 87:085cde657901 243
mbed_official 87:085cde657901 244 /**
mbed_official 87:085cde657901 245 * @brief Initialize the FMC_NORSRAM Timing according to the specified
mbed_official 87:085cde657901 246 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 87:085cde657901 247 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 248 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 87:085cde657901 249 * @param Bank: NORSRAM bank number
mbed_official 87:085cde657901 250 * @retval HAL status
mbed_official 87:085cde657901 251 */
mbed_official 87:085cde657901 252 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 87:085cde657901 253 {
mbed_official 87:085cde657901 254 uint32_t tmpr = 0;
mbed_official 87:085cde657901 255
mbed_official 87:085cde657901 256 /* Check the parameters */
mbed_official 87:085cde657901 257 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 87:085cde657901 258 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 87:085cde657901 259 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 87:085cde657901 260 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 87:085cde657901 261 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 87:085cde657901 262 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 87:085cde657901 263 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 87:085cde657901 264 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 87:085cde657901 265 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 87:085cde657901 266
mbed_official 87:085cde657901 267 /* Set FMC_NORSRAM device timing parameters */
mbed_official 87:085cde657901 268 tmpr = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 87:085cde657901 269 ((Timing->AddressHoldTime) << 4) |\
mbed_official 87:085cde657901 270 ((Timing->DataSetupTime) << 8) |\
mbed_official 87:085cde657901 271 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 87:085cde657901 272 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 87:085cde657901 273 (((Timing->DataLatency)-2) << 24) |\
mbed_official 87:085cde657901 274 (Timing->AccessMode)
mbed_official 87:085cde657901 275 );
mbed_official 87:085cde657901 276
mbed_official 87:085cde657901 277 Device->BTCR[Bank + 1] = tmpr;
mbed_official 87:085cde657901 278
mbed_official 87:085cde657901 279 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
mbed_official 87:085cde657901 280 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
mbed_official 87:085cde657901 281 {
mbed_official 87:085cde657901 282 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
mbed_official 87:085cde657901 283 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
mbed_official 87:085cde657901 284 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
mbed_official 87:085cde657901 285 }
mbed_official 87:085cde657901 286
mbed_official 87:085cde657901 287 return HAL_OK;
mbed_official 87:085cde657901 288 }
mbed_official 87:085cde657901 289
mbed_official 87:085cde657901 290 /**
mbed_official 87:085cde657901 291 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
mbed_official 87:085cde657901 292 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 87:085cde657901 293 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 294 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 87:085cde657901 295 * @param Bank: NORSRAM bank number
mbed_official 87:085cde657901 296 * @retval HAL status
mbed_official 87:085cde657901 297 */
mbed_official 87:085cde657901 298 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
mbed_official 87:085cde657901 299 {
mbed_official 87:085cde657901 300 /* Check the parameters */
mbed_official 87:085cde657901 301 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
mbed_official 87:085cde657901 302
mbed_official 87:085cde657901 303 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
mbed_official 87:085cde657901 304 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
mbed_official 87:085cde657901 305 {
mbed_official 87:085cde657901 306 /* Check the parameters */
mbed_official 87:085cde657901 307 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
mbed_official 87:085cde657901 308 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 87:085cde657901 309 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 87:085cde657901 310 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 87:085cde657901 311 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 87:085cde657901 312 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 87:085cde657901 313 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 87:085cde657901 314 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 87:085cde657901 315 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 87:085cde657901 316
mbed_official 87:085cde657901 317 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 87:085cde657901 318 ((Timing->AddressHoldTime) << 4) |\
mbed_official 87:085cde657901 319 ((Timing->DataSetupTime) << 8) |\
mbed_official 87:085cde657901 320 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 87:085cde657901 321 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 87:085cde657901 322 (((Timing->DataLatency)-2) << 24) |\
mbed_official 87:085cde657901 323 (Timing->AccessMode));
mbed_official 87:085cde657901 324 }
mbed_official 87:085cde657901 325 else
mbed_official 87:085cde657901 326 {
mbed_official 87:085cde657901 327 Device->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 87:085cde657901 328 }
mbed_official 87:085cde657901 329
mbed_official 87:085cde657901 330 return HAL_OK;
mbed_official 87:085cde657901 331 }
mbed_official 87:085cde657901 332
mbed_official 87:085cde657901 333
mbed_official 87:085cde657901 334 /**
mbed_official 87:085cde657901 335 * @}
mbed_official 87:085cde657901 336 */
mbed_official 87:085cde657901 337
mbed_official 87:085cde657901 338
mbed_official 87:085cde657901 339 /** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
mbed_official 87:085cde657901 340 * @brief management functions
mbed_official 87:085cde657901 341 *
mbed_official 87:085cde657901 342 @verbatim
mbed_official 87:085cde657901 343 ==============================================================================
mbed_official 87:085cde657901 344 ##### FMC_NORSRAM Control functions #####
mbed_official 87:085cde657901 345 ==============================================================================
mbed_official 87:085cde657901 346 [..]
mbed_official 87:085cde657901 347 This subsection provides a set of functions allowing to control dynamically
mbed_official 87:085cde657901 348 the FMC NORSRAM interface.
mbed_official 87:085cde657901 349
mbed_official 87:085cde657901 350 @endverbatim
mbed_official 87:085cde657901 351 * @{
mbed_official 87:085cde657901 352 */
mbed_official 87:085cde657901 353
mbed_official 87:085cde657901 354 /**
mbed_official 87:085cde657901 355 * @brief Enables dynamically FMC_NORSRAM write operation.
mbed_official 87:085cde657901 356 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 357 * @param Bank: NORSRAM bank number
mbed_official 87:085cde657901 358 * @retval HAL status
mbed_official 87:085cde657901 359 */
mbed_official 87:085cde657901 360 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 361 {
mbed_official 87:085cde657901 362 /* Check the parameters */
mbed_official 87:085cde657901 363 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 87:085cde657901 364 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 87:085cde657901 365
mbed_official 87:085cde657901 366 /* Enable write operation */
mbed_official 87:085cde657901 367 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
mbed_official 87:085cde657901 368
mbed_official 87:085cde657901 369 return HAL_OK;
mbed_official 87:085cde657901 370 }
mbed_official 87:085cde657901 371
mbed_official 87:085cde657901 372 /**
mbed_official 87:085cde657901 373 * @brief Disables dynamically FMC_NORSRAM write operation.
mbed_official 87:085cde657901 374 * @param Device: Pointer to NORSRAM device instance
mbed_official 87:085cde657901 375 * @param Bank: NORSRAM bank number
mbed_official 87:085cde657901 376 * @retval HAL status
mbed_official 87:085cde657901 377 */
mbed_official 87:085cde657901 378 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 379 {
mbed_official 87:085cde657901 380 /* Check the parameters */
mbed_official 87:085cde657901 381 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 87:085cde657901 382 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 87:085cde657901 383
mbed_official 87:085cde657901 384 /* Disable write operation */
mbed_official 87:085cde657901 385 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 return HAL_OK;
mbed_official 87:085cde657901 388 }
mbed_official 87:085cde657901 389
mbed_official 87:085cde657901 390 /**
mbed_official 87:085cde657901 391 * @}
mbed_official 87:085cde657901 392 */
mbed_official 87:085cde657901 393
mbed_official 87:085cde657901 394 /**
mbed_official 87:085cde657901 395 * @}
mbed_official 87:085cde657901 396 */
mbed_official 87:085cde657901 397
mbed_official 87:085cde657901 398 /** @defgroup FMC_PCCARD Controller functions
mbed_official 87:085cde657901 399 * @brief PCCARD Controller functions
mbed_official 87:085cde657901 400 *
mbed_official 87:085cde657901 401 @verbatim
mbed_official 87:085cde657901 402 ==============================================================================
mbed_official 87:085cde657901 403 ##### How to use NAND device driver #####
mbed_official 87:085cde657901 404 ==============================================================================
mbed_official 87:085cde657901 405 [..]
mbed_official 87:085cde657901 406 This driver contains a set of APIs to interface with the FMC NAND banks in order
mbed_official 87:085cde657901 407 to run the NAND external devices.
mbed_official 87:085cde657901 408
mbed_official 87:085cde657901 409 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
mbed_official 87:085cde657901 410 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
mbed_official 87:085cde657901 411 (+) FMC NAND bank common space timing configuration using the function
mbed_official 87:085cde657901 412 FMC_NAND_CommonSpace_Timing_Init()
mbed_official 87:085cde657901 413 (+) FMC NAND bank attribute space timing configuration using the function
mbed_official 87:085cde657901 414 FMC_NAND_AttributeSpace_Timing_Init()
mbed_official 87:085cde657901 415 (+) FMC NAND bank enable/disable ECC correction feature using the functions
mbed_official 87:085cde657901 416 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
mbed_official 87:085cde657901 417 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
mbed_official 87:085cde657901 418
mbed_official 87:085cde657901 419 @endverbatim
mbed_official 87:085cde657901 420 * @{
mbed_official 87:085cde657901 421 */
mbed_official 87:085cde657901 422
mbed_official 87:085cde657901 423 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
mbed_official 87:085cde657901 424 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 425 *
mbed_official 87:085cde657901 426 @verbatim
mbed_official 87:085cde657901 427 ==============================================================================
mbed_official 87:085cde657901 428 ##### Initialization and de_initialization functions #####
mbed_official 87:085cde657901 429 ==============================================================================
mbed_official 87:085cde657901 430 [..]
mbed_official 87:085cde657901 431 This section provides functions allowing to:
mbed_official 87:085cde657901 432 (+) Initialize and configure the FMC NAND interface
mbed_official 87:085cde657901 433 (+) De-initialize the FMC NAND interface
mbed_official 87:085cde657901 434 (+) Configure the FMC clock and associated GPIOs
mbed_official 87:085cde657901 435
mbed_official 87:085cde657901 436 @endverbatim
mbed_official 87:085cde657901 437 * @{
mbed_official 87:085cde657901 438 */
mbed_official 87:085cde657901 439
mbed_official 87:085cde657901 440 /**
mbed_official 87:085cde657901 441 * @brief Initializes the FMC_NAND device according to the specified
mbed_official 87:085cde657901 442 * control parameters in the FMC_NAND_HandleTypeDef
mbed_official 87:085cde657901 443 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 444 * @param Init: Pointer to NAND Initialization structure
mbed_official 87:085cde657901 445 * @retval HAL status
mbed_official 87:085cde657901 446 */
mbed_official 87:085cde657901 447 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
mbed_official 87:085cde657901 448 {
mbed_official 87:085cde657901 449 uint32_t tmppcr = 0;
mbed_official 87:085cde657901 450
mbed_official 87:085cde657901 451 /* Check the parameters */
mbed_official 87:085cde657901 452 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 453 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
mbed_official 87:085cde657901 454 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 87:085cde657901 455 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 87:085cde657901 456 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
mbed_official 87:085cde657901 457 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
mbed_official 87:085cde657901 458 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 87:085cde657901 459 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 87:085cde657901 460
mbed_official 87:085cde657901 461 /* Set NAND device control parameters */
mbed_official 87:085cde657901 462 tmppcr = (uint32_t)(Init->Waitfeature |\
mbed_official 87:085cde657901 463 FMC_PCR_MEMORY_TYPE_NAND |\
mbed_official 87:085cde657901 464 Init->MemoryDataWidth |\
mbed_official 87:085cde657901 465 Init->EccComputation |\
mbed_official 87:085cde657901 466 Init->ECCPageSize |\
mbed_official 87:085cde657901 467 ((Init->TCLRSetupTime) << 9) |\
mbed_official 87:085cde657901 468 ((Init->TARSetupTime) << 13)
mbed_official 87:085cde657901 469 );
mbed_official 87:085cde657901 470
mbed_official 87:085cde657901 471 if(Init->NandBank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 472 {
mbed_official 87:085cde657901 473 /* NAND bank 2 registers configuration */
mbed_official 87:085cde657901 474 Device->PCR2 = tmppcr;
mbed_official 87:085cde657901 475 }
mbed_official 87:085cde657901 476 else
mbed_official 87:085cde657901 477 {
mbed_official 87:085cde657901 478 /* NAND bank 3 registers configuration */
mbed_official 87:085cde657901 479 Device->PCR3 = tmppcr;
mbed_official 87:085cde657901 480 }
mbed_official 87:085cde657901 481
mbed_official 87:085cde657901 482 return HAL_OK;
mbed_official 87:085cde657901 483
mbed_official 87:085cde657901 484 }
mbed_official 87:085cde657901 485
mbed_official 87:085cde657901 486 /**
mbed_official 87:085cde657901 487 * @brief Initializes the FMC_NAND Common space Timing according to the specified
mbed_official 87:085cde657901 488 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 87:085cde657901 489 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 490 * @param Timing: Pointer to NAND timing structure
mbed_official 87:085cde657901 491 * @param Bank: NAND bank number
mbed_official 87:085cde657901 492 * @retval HAL status
mbed_official 87:085cde657901 493 */
mbed_official 87:085cde657901 494 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 87:085cde657901 495 {
mbed_official 87:085cde657901 496 uint32_t tmppmem = 0;
mbed_official 87:085cde657901 497
mbed_official 87:085cde657901 498 /* Check the parameters */
mbed_official 87:085cde657901 499 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 500 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 87:085cde657901 501 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 87:085cde657901 502 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 87:085cde657901 503 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 87:085cde657901 504 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 505
mbed_official 87:085cde657901 506 /* Set FMC_NAND device timing parameters */
mbed_official 87:085cde657901 507 tmppmem = (uint32_t)(Timing->SetupTime |\
mbed_official 87:085cde657901 508 ((Timing->WaitSetupTime) << 8) |\
mbed_official 87:085cde657901 509 ((Timing->HoldSetupTime) << 16) |\
mbed_official 87:085cde657901 510 ((Timing->HiZSetupTime) << 24)
mbed_official 87:085cde657901 511 );
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 514 {
mbed_official 87:085cde657901 515 /* NAND bank 2 registers configuration */
mbed_official 87:085cde657901 516 Device->PMEM2 = tmppmem;
mbed_official 87:085cde657901 517 }
mbed_official 87:085cde657901 518 else
mbed_official 87:085cde657901 519 {
mbed_official 87:085cde657901 520 /* NAND bank 3 registers configuration */
mbed_official 87:085cde657901 521 Device->PMEM3 = tmppmem;
mbed_official 87:085cde657901 522 }
mbed_official 87:085cde657901 523
mbed_official 87:085cde657901 524 return HAL_OK;
mbed_official 87:085cde657901 525 }
mbed_official 87:085cde657901 526
mbed_official 87:085cde657901 527 /**
mbed_official 87:085cde657901 528 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
mbed_official 87:085cde657901 529 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 87:085cde657901 530 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 531 * @param Timing: Pointer to NAND timing structure
mbed_official 87:085cde657901 532 * @param Bank: NAND bank number
mbed_official 87:085cde657901 533 * @retval HAL status
mbed_official 87:085cde657901 534 */
mbed_official 87:085cde657901 535 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 87:085cde657901 536 {
mbed_official 87:085cde657901 537 uint32_t tmppatt = 0;
mbed_official 87:085cde657901 538
mbed_official 87:085cde657901 539 /* Check the parameters */
mbed_official 87:085cde657901 540 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 541 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 87:085cde657901 542 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 87:085cde657901 543 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 87:085cde657901 544 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 87:085cde657901 545 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 546
mbed_official 87:085cde657901 547 /* Set FMC_NAND device timing parameters */
mbed_official 87:085cde657901 548 tmppatt = (uint32_t)(Timing->SetupTime |\
mbed_official 87:085cde657901 549 ((Timing->WaitSetupTime) << 8) |\
mbed_official 87:085cde657901 550 ((Timing->HoldSetupTime) << 16) |\
mbed_official 87:085cde657901 551 ((Timing->HiZSetupTime) << 24)
mbed_official 87:085cde657901 552 );
mbed_official 87:085cde657901 553
mbed_official 87:085cde657901 554 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 555 {
mbed_official 87:085cde657901 556 /* NAND bank 2 registers configuration */
mbed_official 87:085cde657901 557 Device->PATT2 = tmppatt;
mbed_official 87:085cde657901 558 }
mbed_official 87:085cde657901 559 else
mbed_official 87:085cde657901 560 {
mbed_official 87:085cde657901 561 /* NAND bank 3 registers configuration */
mbed_official 87:085cde657901 562 Device->PATT3 = tmppatt;
mbed_official 87:085cde657901 563 }
mbed_official 87:085cde657901 564
mbed_official 87:085cde657901 565 return HAL_OK;
mbed_official 87:085cde657901 566 }
mbed_official 87:085cde657901 567
mbed_official 87:085cde657901 568
mbed_official 87:085cde657901 569 /**
mbed_official 87:085cde657901 570 * @brief DeInitializes the FMC_NAND device
mbed_official 87:085cde657901 571 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 572 * @param Bank: NAND bank number
mbed_official 87:085cde657901 573 * @retval HAL status
mbed_official 87:085cde657901 574 */
mbed_official 87:085cde657901 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 576 {
mbed_official 87:085cde657901 577 /* Check the parameters */
mbed_official 87:085cde657901 578 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 579 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 580
mbed_official 87:085cde657901 581 /* Disable the NAND Bank */
mbed_official 87:085cde657901 582 __FMC_NAND_DISABLE(Device, Bank);
mbed_official 87:085cde657901 583
mbed_official 87:085cde657901 584 /* De-initialize the NAND Bank */
mbed_official 87:085cde657901 585 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 586 {
mbed_official 87:085cde657901 587 /* Set the FMC_NAND_BANK2 registers to their reset values */
mbed_official 87:085cde657901 588 Device->PCR2 = 0x00000018;
mbed_official 87:085cde657901 589 Device->SR2 = 0x00000040;
mbed_official 87:085cde657901 590 Device->PMEM2 = 0xFCFCFCFC;
mbed_official 87:085cde657901 591 Device->PATT2 = 0xFCFCFCFC;
mbed_official 87:085cde657901 592 }
mbed_official 87:085cde657901 593 /* FMC_Bank3_NAND */
mbed_official 87:085cde657901 594 else
mbed_official 87:085cde657901 595 {
mbed_official 87:085cde657901 596 /* Set the FMC_NAND_BANK3 registers to their reset values */
mbed_official 87:085cde657901 597 Device->PCR3 = 0x00000018;
mbed_official 87:085cde657901 598 Device->SR3 = 0x00000040;
mbed_official 87:085cde657901 599 Device->PMEM3 = 0xFCFCFCFC;
mbed_official 87:085cde657901 600 Device->PATT3 = 0xFCFCFCFC;
mbed_official 87:085cde657901 601 }
mbed_official 87:085cde657901 602
mbed_official 87:085cde657901 603 return HAL_OK;
mbed_official 87:085cde657901 604 }
mbed_official 87:085cde657901 605
mbed_official 87:085cde657901 606 /**
mbed_official 87:085cde657901 607 * @}
mbed_official 87:085cde657901 608 */
mbed_official 87:085cde657901 609
mbed_official 87:085cde657901 610
mbed_official 87:085cde657901 611 /** @defgroup HAL_FMC_NAND_Group3 Control functions
mbed_official 87:085cde657901 612 * @brief management functions
mbed_official 87:085cde657901 613 *
mbed_official 87:085cde657901 614 @verbatim
mbed_official 87:085cde657901 615 ==============================================================================
mbed_official 87:085cde657901 616 ##### FMC_NAND Control functions #####
mbed_official 87:085cde657901 617 ==============================================================================
mbed_official 87:085cde657901 618 [..]
mbed_official 87:085cde657901 619 This subsection provides a set of functions allowing to control dynamically
mbed_official 87:085cde657901 620 the FMC NAND interface.
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 @endverbatim
mbed_official 87:085cde657901 623 * @{
mbed_official 87:085cde657901 624 */
mbed_official 87:085cde657901 625
mbed_official 87:085cde657901 626
mbed_official 87:085cde657901 627 /**
mbed_official 87:085cde657901 628 * @brief Enables dynamically FMC_NAND ECC feature.
mbed_official 87:085cde657901 629 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 630 * @param Bank: NAND bank number
mbed_official 87:085cde657901 631 * @retval HAL status
mbed_official 87:085cde657901 632 */
mbed_official 87:085cde657901 633 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 634 {
mbed_official 87:085cde657901 635 /* Check the parameters */
mbed_official 87:085cde657901 636 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 637 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 638
mbed_official 87:085cde657901 639 /* Enable ECC feature */
mbed_official 87:085cde657901 640 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 641 {
mbed_official 87:085cde657901 642 Device->PCR2 |= FMC_PCR2_ECCEN;
mbed_official 87:085cde657901 643 }
mbed_official 87:085cde657901 644 else
mbed_official 87:085cde657901 645 {
mbed_official 87:085cde657901 646 Device->PCR3 |= FMC_PCR3_ECCEN;
mbed_official 87:085cde657901 647 }
mbed_official 87:085cde657901 648
mbed_official 87:085cde657901 649 return HAL_OK;
mbed_official 87:085cde657901 650 }
mbed_official 87:085cde657901 651
mbed_official 87:085cde657901 652
mbed_official 87:085cde657901 653 /**
mbed_official 87:085cde657901 654 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 87:085cde657901 655 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 656 * @param Bank: NAND bank number
mbed_official 87:085cde657901 657 * @retval HAL status
mbed_official 87:085cde657901 658 */
mbed_official 87:085cde657901 659 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 660 {
mbed_official 87:085cde657901 661 /* Check the parameters */
mbed_official 87:085cde657901 662 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 663 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 664
mbed_official 87:085cde657901 665 /* Disable ECC feature */
mbed_official 87:085cde657901 666 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 667 {
mbed_official 87:085cde657901 668 Device->PCR2 &= ~FMC_PCR2_ECCEN;
mbed_official 87:085cde657901 669 }
mbed_official 87:085cde657901 670 else
mbed_official 87:085cde657901 671 {
mbed_official 87:085cde657901 672 Device->PCR3 &= ~FMC_PCR3_ECCEN;
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674
mbed_official 87:085cde657901 675 return HAL_OK;
mbed_official 87:085cde657901 676 }
mbed_official 87:085cde657901 677
mbed_official 87:085cde657901 678 /**
mbed_official 87:085cde657901 679 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 87:085cde657901 680 * @param Device: Pointer to NAND device instance
mbed_official 87:085cde657901 681 * @param ECCval: Pointer to ECC value
mbed_official 87:085cde657901 682 * @param Bank: NAND bank number
mbed_official 87:085cde657901 683 * @param Timeout: Timeout wait value
mbed_official 87:085cde657901 684 * @retval HAL status
mbed_official 87:085cde657901 685 */
mbed_official 87:085cde657901 686 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
mbed_official 87:085cde657901 687 {
mbed_official 87:085cde657901 688 uint32_t timeout = 0;
mbed_official 87:085cde657901 689
mbed_official 87:085cde657901 690 /* Check the parameters */
mbed_official 87:085cde657901 691 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 87:085cde657901 692 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 87:085cde657901 693
mbed_official 87:085cde657901 694 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 695
mbed_official 87:085cde657901 696 /* Wait untill FIFO is empty */
mbed_official 87:085cde657901 697 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
mbed_official 87:085cde657901 698 {
mbed_official 87:085cde657901 699 /* Check for the Timeout */
mbed_official 87:085cde657901 700 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 701 {
mbed_official 87:085cde657901 702 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 703 {
mbed_official 87:085cde657901 704 return HAL_TIMEOUT;
mbed_official 87:085cde657901 705 }
mbed_official 87:085cde657901 706 }
mbed_official 87:085cde657901 707 }
mbed_official 87:085cde657901 708
mbed_official 87:085cde657901 709 if(Bank == FMC_NAND_BANK2)
mbed_official 87:085cde657901 710 {
mbed_official 87:085cde657901 711 /* Get the ECCR2 register value */
mbed_official 87:085cde657901 712 *ECCval = (uint32_t)Device->ECCR2;
mbed_official 87:085cde657901 713 }
mbed_official 87:085cde657901 714 else
mbed_official 87:085cde657901 715 {
mbed_official 87:085cde657901 716 /* Get the ECCR3 register value */
mbed_official 87:085cde657901 717 *ECCval = (uint32_t)Device->ECCR3;
mbed_official 87:085cde657901 718 }
mbed_official 87:085cde657901 719
mbed_official 87:085cde657901 720 return HAL_OK;
mbed_official 87:085cde657901 721 }
mbed_official 87:085cde657901 722
mbed_official 87:085cde657901 723 /**
mbed_official 87:085cde657901 724 * @}
mbed_official 87:085cde657901 725 */
mbed_official 87:085cde657901 726
mbed_official 87:085cde657901 727 /**
mbed_official 87:085cde657901 728 * @}
mbed_official 87:085cde657901 729 */
mbed_official 87:085cde657901 730
mbed_official 87:085cde657901 731 /** @defgroup FMC_PCCARD Controller functions
mbed_official 87:085cde657901 732 * @brief PCCARD Controller functions
mbed_official 87:085cde657901 733 *
mbed_official 87:085cde657901 734 @verbatim
mbed_official 87:085cde657901 735 ==============================================================================
mbed_official 87:085cde657901 736 ##### How to use PCCARD device driver #####
mbed_official 87:085cde657901 737 ==============================================================================
mbed_official 87:085cde657901 738 [..]
mbed_official 87:085cde657901 739 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
mbed_official 87:085cde657901 740 to run the PCCARD/compact flash external devices.
mbed_official 87:085cde657901 741
mbed_official 87:085cde657901 742 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
mbed_official 87:085cde657901 743 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
mbed_official 87:085cde657901 744 (+) FMC PCCARD bank common space timing configuration using the function
mbed_official 87:085cde657901 745 FMC_PCCARD_CommonSpace_Timing_Init()
mbed_official 87:085cde657901 746 (+) FMC PCCARD bank attribute space timing configuration using the function
mbed_official 87:085cde657901 747 FMC_PCCARD_AttributeSpace_Timing_Init()
mbed_official 87:085cde657901 748 (+) FMC PCCARD bank IO space timing configuration using the function
mbed_official 87:085cde657901 749 FMC_PCCARD_IOSpace_Timing_Init()
mbed_official 87:085cde657901 750
mbed_official 87:085cde657901 751
mbed_official 87:085cde657901 752 @endverbatim
mbed_official 87:085cde657901 753 * @{
mbed_official 87:085cde657901 754 */
mbed_official 87:085cde657901 755
mbed_official 87:085cde657901 756 /** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
mbed_official 87:085cde657901 757 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 758 *
mbed_official 87:085cde657901 759 @verbatim
mbed_official 87:085cde657901 760 ==============================================================================
mbed_official 87:085cde657901 761 ##### Initialization and de_initialization functions #####
mbed_official 87:085cde657901 762 ==============================================================================
mbed_official 87:085cde657901 763 [..]
mbed_official 87:085cde657901 764 This section provides functions allowing to:
mbed_official 87:085cde657901 765 (+) Initialize and configure the FMC PCCARD interface
mbed_official 87:085cde657901 766 (+) De-initialize the FMC PCCARD interface
mbed_official 87:085cde657901 767 (+) Configure the FMC clock and associated GPIOs
mbed_official 87:085cde657901 768
mbed_official 87:085cde657901 769 @endverbatim
mbed_official 87:085cde657901 770 * @{
mbed_official 87:085cde657901 771 */
mbed_official 87:085cde657901 772
mbed_official 87:085cde657901 773 /**
mbed_official 87:085cde657901 774 * @brief Initializes the FMC_PCCARD device according to the specified
mbed_official 87:085cde657901 775 * control parameters in the FMC_PCCARD_HandleTypeDef
mbed_official 87:085cde657901 776 * @param Device: Pointer to PCCARD device instance
mbed_official 87:085cde657901 777 * @param Init: Pointer to PCCARD Initialization structure
mbed_official 87:085cde657901 778 * @retval HAL status
mbed_official 87:085cde657901 779 */
mbed_official 87:085cde657901 780 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
mbed_official 87:085cde657901 781 {
mbed_official 87:085cde657901 782 /* Check the parameters */
mbed_official 87:085cde657901 783 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 87:085cde657901 784 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 87:085cde657901 785 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 87:085cde657901 786 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 87:085cde657901 787
mbed_official 87:085cde657901 788 /* Set FMC_PCCARD device control parameters */
mbed_official 87:085cde657901 789 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
mbed_official 87:085cde657901 790 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
mbed_official 87:085cde657901 791 (Init->TCLRSetupTime << 9) |\
mbed_official 87:085cde657901 792 (Init->TARSetupTime << 13));
mbed_official 87:085cde657901 793
mbed_official 87:085cde657901 794 return HAL_OK;
mbed_official 87:085cde657901 795
mbed_official 87:085cde657901 796 }
mbed_official 87:085cde657901 797
mbed_official 87:085cde657901 798 /**
mbed_official 87:085cde657901 799 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
mbed_official 87:085cde657901 800 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 87:085cde657901 801 * @param Device: Pointer to PCCARD device instance
mbed_official 87:085cde657901 802 * @param Timing: Pointer to PCCARD timing structure
mbed_official 87:085cde657901 803 * @retval HAL status
mbed_official 87:085cde657901 804 */
mbed_official 87:085cde657901 805 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 87:085cde657901 806 {
mbed_official 87:085cde657901 807 /* Check the parameters */
mbed_official 87:085cde657901 808 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 87:085cde657901 809 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 87:085cde657901 810 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 87:085cde657901 811 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 87:085cde657901 812 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 87:085cde657901 813
mbed_official 87:085cde657901 814 /* Set PCCARD timing parameters */
mbed_official 87:085cde657901 815 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
mbed_official 87:085cde657901 816 ((Timing->WaitSetupTime) << 8) |\
mbed_official 87:085cde657901 817 (Timing->HoldSetupTime) << 16) |\
mbed_official 87:085cde657901 818 ((Timing->HiZSetupTime) << 24)
mbed_official 87:085cde657901 819 );
mbed_official 87:085cde657901 820
mbed_official 87:085cde657901 821 return HAL_OK;
mbed_official 87:085cde657901 822 }
mbed_official 87:085cde657901 823
mbed_official 87:085cde657901 824 /**
mbed_official 87:085cde657901 825 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
mbed_official 87:085cde657901 826 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 87:085cde657901 827 * @param Device: Pointer to PCCARD device instance
mbed_official 87:085cde657901 828 * @param Timing: Pointer to PCCARD timing structure
mbed_official 87:085cde657901 829 * @retval HAL status
mbed_official 87:085cde657901 830 */
mbed_official 87:085cde657901 831 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 87:085cde657901 832 {
mbed_official 87:085cde657901 833 /* Check the parameters */
mbed_official 87:085cde657901 834 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 87:085cde657901 835 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 87:085cde657901 836 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 87:085cde657901 837 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 87:085cde657901 838 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 87:085cde657901 839
mbed_official 87:085cde657901 840 /* Set PCCARD timing parameters */
mbed_official 87:085cde657901 841 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
mbed_official 87:085cde657901 842 ((Timing->WaitSetupTime) << 8) |\
mbed_official 87:085cde657901 843 (Timing->HoldSetupTime) << 16) |\
mbed_official 87:085cde657901 844 ((Timing->HiZSetupTime) << 24)
mbed_official 87:085cde657901 845 );
mbed_official 87:085cde657901 846
mbed_official 87:085cde657901 847 return HAL_OK;
mbed_official 87:085cde657901 848 }
mbed_official 87:085cde657901 849
mbed_official 87:085cde657901 850 /**
mbed_official 87:085cde657901 851 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
mbed_official 87:085cde657901 852 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 87:085cde657901 853 * @param Device: Pointer to PCCARD device instance
mbed_official 87:085cde657901 854 * @param Timing: Pointer to PCCARD timing structure
mbed_official 87:085cde657901 855 * @retval HAL status
mbed_official 87:085cde657901 856 */
mbed_official 87:085cde657901 857 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 87:085cde657901 858 {
mbed_official 87:085cde657901 859 /* Check the parameters */
mbed_official 87:085cde657901 860 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 87:085cde657901 861 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 87:085cde657901 862 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 87:085cde657901 863 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 87:085cde657901 864 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 87:085cde657901 865
mbed_official 87:085cde657901 866 /* Set FMC_PCCARD device timing parameters */
mbed_official 87:085cde657901 867 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
mbed_official 87:085cde657901 868 ((Timing->WaitSetupTime) << 8) |\
mbed_official 87:085cde657901 869 (Timing->HoldSetupTime) << 16) |\
mbed_official 87:085cde657901 870 ((Timing->HiZSetupTime) << 24)
mbed_official 87:085cde657901 871 );
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 return HAL_OK;
mbed_official 87:085cde657901 874 }
mbed_official 87:085cde657901 875
mbed_official 87:085cde657901 876 /**
mbed_official 87:085cde657901 877 * @brief DeInitializes the FMC_PCCARD device
mbed_official 87:085cde657901 878 * @param Device: Pointer to PCCARD device instance
mbed_official 87:085cde657901 879 * @retval HAL status
mbed_official 87:085cde657901 880 */
mbed_official 87:085cde657901 881 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
mbed_official 87:085cde657901 882 {
mbed_official 87:085cde657901 883 /* Check the parameters */
mbed_official 87:085cde657901 884 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 /* Disable the FMC_PCCARD device */
mbed_official 87:085cde657901 887 __FMC_PCCARD_DISABLE(Device);
mbed_official 87:085cde657901 888
mbed_official 87:085cde657901 889 /* De-initialize the FMC_PCCARD device */
mbed_official 87:085cde657901 890 Device->PCR4 = 0x00000018;
mbed_official 87:085cde657901 891 Device->SR4 = 0x00000000;
mbed_official 87:085cde657901 892 Device->PMEM4 = 0xFCFCFCFC;
mbed_official 87:085cde657901 893 Device->PATT4 = 0xFCFCFCFC;
mbed_official 87:085cde657901 894 Device->PIO4 = 0xFCFCFCFC;
mbed_official 87:085cde657901 895
mbed_official 87:085cde657901 896 return HAL_OK;
mbed_official 87:085cde657901 897 }
mbed_official 87:085cde657901 898
mbed_official 87:085cde657901 899 /**
mbed_official 87:085cde657901 900 * @}
mbed_official 87:085cde657901 901 */
mbed_official 87:085cde657901 902
mbed_official 87:085cde657901 903
mbed_official 87:085cde657901 904 /** @defgroup FMC_SDRAM Controller functions
mbed_official 87:085cde657901 905 * @brief SDRAM Controller functions
mbed_official 87:085cde657901 906 *
mbed_official 87:085cde657901 907 @verbatim
mbed_official 87:085cde657901 908 ==============================================================================
mbed_official 87:085cde657901 909 ##### How to use SDRAM device driver #####
mbed_official 87:085cde657901 910 ==============================================================================
mbed_official 87:085cde657901 911 [..]
mbed_official 87:085cde657901 912 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
mbed_official 87:085cde657901 913 to run the SDRAM external devices.
mbed_official 87:085cde657901 914
mbed_official 87:085cde657901 915 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
mbed_official 87:085cde657901 916 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
mbed_official 87:085cde657901 917 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
mbed_official 87:085cde657901 918 (+) FMC SDRAM bank enable/disable write operation using the functions
mbed_official 87:085cde657901 919 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
mbed_official 87:085cde657901 920 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
mbed_official 87:085cde657901 921
mbed_official 87:085cde657901 922 @endverbatim
mbed_official 87:085cde657901 923 * @{
mbed_official 87:085cde657901 924 */
mbed_official 87:085cde657901 925
mbed_official 87:085cde657901 926 /** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
mbed_official 87:085cde657901 927 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 928 *
mbed_official 87:085cde657901 929 @verbatim
mbed_official 87:085cde657901 930 ==============================================================================
mbed_official 87:085cde657901 931 ##### Initialization and de_initialization functions #####
mbed_official 87:085cde657901 932 ==============================================================================
mbed_official 87:085cde657901 933 [..]
mbed_official 87:085cde657901 934 This section provides functions allowing to:
mbed_official 87:085cde657901 935 (+) Initialize and configure the FMC SDRAM interface
mbed_official 87:085cde657901 936 (+) De-initialize the FMC SDRAM interface
mbed_official 87:085cde657901 937 (+) Configure the FMC clock and associated GPIOs
mbed_official 87:085cde657901 938
mbed_official 87:085cde657901 939 @endverbatim
mbed_official 87:085cde657901 940 * @{
mbed_official 87:085cde657901 941 */
mbed_official 87:085cde657901 942
mbed_official 87:085cde657901 943 /**
mbed_official 87:085cde657901 944 * @brief Initializes the FMC_SDRAM device according to the specified
mbed_official 87:085cde657901 945 * control parameters in the FMC_SDRAM_InitTypeDef
mbed_official 87:085cde657901 946 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 947 * @param Init: Pointer to SDRAM Initialization structure
mbed_official 87:085cde657901 948 * @retval HAL status
mbed_official 87:085cde657901 949 */
mbed_official 87:085cde657901 950 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
mbed_official 87:085cde657901 951 {
mbed_official 87:085cde657901 952 uint32_t tmpr1 = 0;
mbed_official 87:085cde657901 953 uint32_t tmpr2 = 0;
mbed_official 87:085cde657901 954
mbed_official 87:085cde657901 955 /* Check the parameters */
mbed_official 87:085cde657901 956 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 957 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
mbed_official 87:085cde657901 958 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
mbed_official 87:085cde657901 959 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
mbed_official 87:085cde657901 960 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 87:085cde657901 961 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
mbed_official 87:085cde657901 962 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
mbed_official 87:085cde657901 963 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
mbed_official 87:085cde657901 964 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
mbed_official 87:085cde657901 965 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
mbed_official 87:085cde657901 966 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
mbed_official 87:085cde657901 967
mbed_official 87:085cde657901 968 /* Set SDRAM bank configuration parameters */
mbed_official 87:085cde657901 969 if (Init->SDBank != FMC_SDRAM_BANK2)
mbed_official 87:085cde657901 970 {
mbed_official 87:085cde657901 971 Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 87:085cde657901 972 Init->RowBitsNumber |\
mbed_official 87:085cde657901 973 Init->MemoryDataWidth |\
mbed_official 87:085cde657901 974 Init->InternalBankNumber |\
mbed_official 87:085cde657901 975 Init->CASLatency |\
mbed_official 87:085cde657901 976 Init->WriteProtection |\
mbed_official 87:085cde657901 977 Init->SDClockPeriod |\
mbed_official 87:085cde657901 978 Init->ReadBurst |\
mbed_official 87:085cde657901 979 Init->ReadPipeDelay
mbed_official 87:085cde657901 980 );
mbed_official 87:085cde657901 981 }
mbed_official 87:085cde657901 982 else /* FMC_Bank2_SDRAM */
mbed_official 87:085cde657901 983 {
mbed_official 87:085cde657901 984 tmpr1 = (uint32_t)(Init->SDClockPeriod |\
mbed_official 87:085cde657901 985 Init->ReadBurst |\
mbed_official 87:085cde657901 986 Init->ReadPipeDelay
mbed_official 87:085cde657901 987 );
mbed_official 87:085cde657901 988
mbed_official 87:085cde657901 989 tmpr2 = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 87:085cde657901 990 Init->RowBitsNumber |\
mbed_official 87:085cde657901 991 Init->MemoryDataWidth |\
mbed_official 87:085cde657901 992 Init->InternalBankNumber |\
mbed_official 87:085cde657901 993 Init->CASLatency |\
mbed_official 87:085cde657901 994 Init->WriteProtection
mbed_official 87:085cde657901 995 );
mbed_official 87:085cde657901 996
mbed_official 87:085cde657901 997 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 87:085cde657901 998 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
mbed_official 87:085cde657901 999 }
mbed_official 87:085cde657901 1000
mbed_official 87:085cde657901 1001 return HAL_OK;
mbed_official 87:085cde657901 1002 }
mbed_official 87:085cde657901 1003
mbed_official 87:085cde657901 1004 /**
mbed_official 87:085cde657901 1005 * @brief Initializes the FMC_SDRAM device timing according to the specified
mbed_official 87:085cde657901 1006 * parameters in the FMC_SDRAM_TimingTypeDef
mbed_official 87:085cde657901 1007 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1008 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 87:085cde657901 1009 * @param Bank: SDRAM bank number
mbed_official 87:085cde657901 1010 * @retval HAL status
mbed_official 87:085cde657901 1011 */
mbed_official 87:085cde657901 1012 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 87:085cde657901 1013 {
mbed_official 87:085cde657901 1014 uint32_t tmpr1 = 0;
mbed_official 87:085cde657901 1015 uint32_t tmpr2 = 0;
mbed_official 87:085cde657901 1016
mbed_official 87:085cde657901 1017 /* Check the parameters */
mbed_official 87:085cde657901 1018 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1019 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
mbed_official 87:085cde657901 1020 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
mbed_official 87:085cde657901 1021 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
mbed_official 87:085cde657901 1022 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
mbed_official 87:085cde657901 1023 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
mbed_official 87:085cde657901 1024 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
mbed_official 87:085cde657901 1025 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
mbed_official 87:085cde657901 1026 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 87:085cde657901 1027
mbed_official 87:085cde657901 1028 /* Set SDRAM device timing parameters */
mbed_official 87:085cde657901 1029 if (Bank != FMC_SDRAM_BANK2)
mbed_official 87:085cde657901 1030 {
mbed_official 87:085cde657901 1031 Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 87:085cde657901 1032 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 87:085cde657901 1033 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 87:085cde657901 1034 (((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 87:085cde657901 1035 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 87:085cde657901 1036 (((Timing->RPDelay)-1) << 20) |\
mbed_official 87:085cde657901 1037 (((Timing->RCDDelay)-1) << 24)
mbed_official 87:085cde657901 1038 );
mbed_official 87:085cde657901 1039 }
mbed_official 87:085cde657901 1040 else /* FMC_Bank2_SDRAM */
mbed_official 87:085cde657901 1041 {
mbed_official 87:085cde657901 1042
mbed_official 87:085cde657901 1043 tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 87:085cde657901 1044 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 87:085cde657901 1045 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 87:085cde657901 1046 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 87:085cde657901 1047 (((Timing->RCDDelay)-1) << 24)
mbed_official 87:085cde657901 1048 );
mbed_official 87:085cde657901 1049
mbed_official 87:085cde657901 1050 tmpr2 = (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 87:085cde657901 1051 (((Timing->RPDelay)-1) << 20)
mbed_official 87:085cde657901 1052 );
mbed_official 87:085cde657901 1053
mbed_official 87:085cde657901 1054 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
mbed_official 87:085cde657901 1055 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
mbed_official 87:085cde657901 1056 }
mbed_official 87:085cde657901 1057
mbed_official 87:085cde657901 1058 return HAL_OK;
mbed_official 87:085cde657901 1059 }
mbed_official 87:085cde657901 1060
mbed_official 87:085cde657901 1061 /**
mbed_official 87:085cde657901 1062 * @brief DeInitializes the FMC_SDRAM peripheral
mbed_official 87:085cde657901 1063 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1064 * @retval HAL status
mbed_official 87:085cde657901 1065 */
mbed_official 87:085cde657901 1066 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 1067 {
mbed_official 87:085cde657901 1068 /* Check the parameters */
mbed_official 87:085cde657901 1069 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1070 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 87:085cde657901 1071
mbed_official 87:085cde657901 1072 /* De-initialize the SDRAM device */
mbed_official 87:085cde657901 1073 Device->SDCR[Bank] = 0x000002D0;
mbed_official 87:085cde657901 1074 Device->SDTR[Bank] = 0x0FFFFFFF;
mbed_official 87:085cde657901 1075 Device->SDCMR = 0x00000000;
mbed_official 87:085cde657901 1076 Device->SDRTR = 0x00000000;
mbed_official 87:085cde657901 1077 Device->SDSR = 0x00000000;
mbed_official 87:085cde657901 1078
mbed_official 87:085cde657901 1079 return HAL_OK;
mbed_official 87:085cde657901 1080 }
mbed_official 87:085cde657901 1081
mbed_official 87:085cde657901 1082 /**
mbed_official 87:085cde657901 1083 * @}
mbed_official 87:085cde657901 1084 */
mbed_official 87:085cde657901 1085
mbed_official 87:085cde657901 1086
mbed_official 87:085cde657901 1087 /** @defgroup HAL_FMC_SDRAM_Group3 Control functions
mbed_official 87:085cde657901 1088 * @brief management functions
mbed_official 87:085cde657901 1089 *
mbed_official 87:085cde657901 1090 @verbatim
mbed_official 87:085cde657901 1091 ==============================================================================
mbed_official 87:085cde657901 1092 ##### FMC_SDRAM Control functions #####
mbed_official 87:085cde657901 1093 ==============================================================================
mbed_official 87:085cde657901 1094 [..]
mbed_official 87:085cde657901 1095 This subsection provides a set of functions allowing to control dynamically
mbed_official 87:085cde657901 1096 the FMC SDRAM interface.
mbed_official 87:085cde657901 1097
mbed_official 87:085cde657901 1098 @endverbatim
mbed_official 87:085cde657901 1099 * @{
mbed_official 87:085cde657901 1100 */
mbed_official 87:085cde657901 1101
mbed_official 87:085cde657901 1102 /**
mbed_official 87:085cde657901 1103 * @brief Enables dynamically FMC_SDRAM write protection.
mbed_official 87:085cde657901 1104 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1105 * @param Bank: SDRAM bank number
mbed_official 87:085cde657901 1106 * @retval HAL status
mbed_official 87:085cde657901 1107 */
mbed_official 87:085cde657901 1108 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 1109 {
mbed_official 87:085cde657901 1110 /* Check the parameters */
mbed_official 87:085cde657901 1111 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1112 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 87:085cde657901 1113
mbed_official 87:085cde657901 1114 /* Enable write protection */
mbed_official 87:085cde657901 1115 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 87:085cde657901 1116
mbed_official 87:085cde657901 1117 return HAL_OK;
mbed_official 87:085cde657901 1118 }
mbed_official 87:085cde657901 1119
mbed_official 87:085cde657901 1120 /**
mbed_official 87:085cde657901 1121 * @brief Disables dynamically FMC_SDRAM write protection.
mbed_official 87:085cde657901 1122 * @param hsdram: FMC_SDRAM handle
mbed_official 87:085cde657901 1123 * @retval HAL status
mbed_official 87:085cde657901 1124 */
mbed_official 87:085cde657901 1125 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 1126 {
mbed_official 87:085cde657901 1127 /* Check the parameters */
mbed_official 87:085cde657901 1128 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1129 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 87:085cde657901 1130
mbed_official 87:085cde657901 1131 /* Disable write protection */
mbed_official 87:085cde657901 1132 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 87:085cde657901 1133
mbed_official 87:085cde657901 1134 return HAL_OK;
mbed_official 87:085cde657901 1135 }
mbed_official 87:085cde657901 1136
mbed_official 87:085cde657901 1137 /**
mbed_official 87:085cde657901 1138 * @brief Send Command to the FMC SDRAM bank
mbed_official 87:085cde657901 1139 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1140 * @param Command: Pointer to SDRAM command structure
mbed_official 87:085cde657901 1141 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 87:085cde657901 1142 * @param Timeout: Timeout wait value
mbed_official 87:085cde657901 1143 * @retval HAL state
mbed_official 87:085cde657901 1144 */
mbed_official 87:085cde657901 1145 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 87:085cde657901 1146 {
mbed_official 87:085cde657901 1147 __IO uint32_t tmpr = 0;
mbed_official 87:085cde657901 1148 uint32_t timeout = 0;
mbed_official 87:085cde657901 1149
mbed_official 87:085cde657901 1150 /* Check the parameters */
mbed_official 87:085cde657901 1151 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1152 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
mbed_official 87:085cde657901 1153 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
mbed_official 87:085cde657901 1154 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
mbed_official 87:085cde657901 1155 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
mbed_official 87:085cde657901 1156
mbed_official 87:085cde657901 1157 /* Set command register */
mbed_official 87:085cde657901 1158 tmpr = (uint32_t)((Command->CommandMode) |\
mbed_official 87:085cde657901 1159 (Command->CommandTarget) |\
mbed_official 87:085cde657901 1160 (((Command->AutoRefreshNumber)-1) << 5) |\
mbed_official 87:085cde657901 1161 ((Command->ModeRegisterDefinition) << 9)
mbed_official 87:085cde657901 1162 );
mbed_official 87:085cde657901 1163
mbed_official 87:085cde657901 1164 Device->SDCMR = tmpr;
mbed_official 87:085cde657901 1165
mbed_official 87:085cde657901 1166 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 1167
mbed_official 87:085cde657901 1168 /* wait until command is send */
mbed_official 87:085cde657901 1169 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
mbed_official 87:085cde657901 1170 {
mbed_official 87:085cde657901 1171 /* Check for the Timeout */
mbed_official 87:085cde657901 1172 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 1173 {
mbed_official 87:085cde657901 1174 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 1175 {
mbed_official 87:085cde657901 1176 return HAL_TIMEOUT;
mbed_official 87:085cde657901 1177 }
mbed_official 87:085cde657901 1178 }
mbed_official 87:085cde657901 1179
mbed_official 87:085cde657901 1180 return HAL_ERROR;
mbed_official 87:085cde657901 1181 }
mbed_official 87:085cde657901 1182
mbed_official 87:085cde657901 1183 return HAL_OK;
mbed_official 87:085cde657901 1184 }
mbed_official 87:085cde657901 1185
mbed_official 87:085cde657901 1186 /**
mbed_official 87:085cde657901 1187 * @brief Program the SDRAM Memory Refresh rate.
mbed_official 87:085cde657901 1188 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1189 * @param RefreshRate: The SDRAM refresh rate value.
mbed_official 87:085cde657901 1190 * @retval HAL state
mbed_official 87:085cde657901 1191 */
mbed_official 87:085cde657901 1192 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
mbed_official 87:085cde657901 1193 {
mbed_official 87:085cde657901 1194 /* Check the parameters */
mbed_official 87:085cde657901 1195 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1196 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
mbed_official 87:085cde657901 1197
mbed_official 87:085cde657901 1198 /* Set the refresh rate in command register */
mbed_official 87:085cde657901 1199 Device->SDRTR |= (RefreshRate<<1);
mbed_official 87:085cde657901 1200
mbed_official 87:085cde657901 1201 return HAL_OK;
mbed_official 87:085cde657901 1202 }
mbed_official 87:085cde657901 1203
mbed_official 87:085cde657901 1204 /**
mbed_official 87:085cde657901 1205 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 87:085cde657901 1206 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1207 * @param AutoRefreshNumber: Specifies the auto Refresh number.
mbed_official 87:085cde657901 1208 * @retval None
mbed_official 87:085cde657901 1209 */
mbed_official 87:085cde657901 1210 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
mbed_official 87:085cde657901 1211 {
mbed_official 87:085cde657901 1212 /* Check the parameters */
mbed_official 87:085cde657901 1213 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1214 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
mbed_official 87:085cde657901 1215
mbed_official 87:085cde657901 1216 /* Set the Auto-refresh number in command register */
mbed_official 87:085cde657901 1217 Device->SDCMR |= (AutoRefreshNumber << 5);
mbed_official 87:085cde657901 1218
mbed_official 87:085cde657901 1219 return HAL_OK;
mbed_official 87:085cde657901 1220 }
mbed_official 87:085cde657901 1221
mbed_official 87:085cde657901 1222 /**
mbed_official 87:085cde657901 1223 * @brief Returns the indicated FMC SDRAM bank mode status.
mbed_official 87:085cde657901 1224 * @param Device: Pointer to SDRAM device instance
mbed_official 87:085cde657901 1225 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
mbed_official 87:085cde657901 1226 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
mbed_official 87:085cde657901 1227 * @retval The FMC SDRAM bank mode status, could be on of the following values:
mbed_official 87:085cde657901 1228 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
mbed_official 87:085cde657901 1229 * FMC_SDRAM_POWER_DOWN_MODE.
mbed_official 87:085cde657901 1230 */
mbed_official 87:085cde657901 1231 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 87:085cde657901 1232 {
mbed_official 87:085cde657901 1233 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1234
mbed_official 87:085cde657901 1235 /* Check the parameters */
mbed_official 87:085cde657901 1236 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 87:085cde657901 1237 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 87:085cde657901 1238
mbed_official 87:085cde657901 1239 /* Get the corresponding bank mode */
mbed_official 87:085cde657901 1240 if(Bank == FMC_SDRAM_BANK1)
mbed_official 87:085cde657901 1241 {
mbed_official 87:085cde657901 1242 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
mbed_official 87:085cde657901 1243 }
mbed_official 87:085cde657901 1244 else
mbed_official 87:085cde657901 1245 {
mbed_official 87:085cde657901 1246 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
mbed_official 87:085cde657901 1247 }
mbed_official 87:085cde657901 1248
mbed_official 87:085cde657901 1249 /* Return the mode status */
mbed_official 87:085cde657901 1250 return tmpreg;
mbed_official 87:085cde657901 1251 }
mbed_official 87:085cde657901 1252
mbed_official 87:085cde657901 1253 /**
mbed_official 87:085cde657901 1254 * @}
mbed_official 87:085cde657901 1255 */
mbed_official 87:085cde657901 1256
mbed_official 87:085cde657901 1257 /**
mbed_official 87:085cde657901 1258 * @}
mbed_official 87:085cde657901 1259 */
mbed_official 87:085cde657901 1260
mbed_official 87:085cde657901 1261 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1262
mbed_official 87:085cde657901 1263 #endif /* HAL_FMC_MODULE_ENABLED */
mbed_official 87:085cde657901 1264
mbed_official 87:085cde657901 1265 /**
mbed_official 87:085cde657901 1266 * @}
mbed_official 87:085cde657901 1267 */
mbed_official 87:085cde657901 1268
mbed_official 87:085cde657901 1269 /**
mbed_official 87:085cde657901 1270 * @}
mbed_official 87:085cde657901 1271 */
mbed_official 87:085cde657901 1272
mbed_official 87:085cde657901 1273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/