mbed-src-kl05 - mbed library sources

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mbed library sources

Dependents: frdm_kl05z_gpio_test

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c@87:085cde657901, 2014-02-08 (annotated)

Committer:: mbed_official
Date:: Sat Feb 08 19:45:06 2014 +0000
Revision:: 87:085cde657901
Child:: 106:ced8cbb51063

Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2

Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/

Add NUCLEO_F401RE, improvements

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_eth.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	87:085cde657901	5	* @version V1.0.0RC2
mbed_official	87:085cde657901	6	* @date 04-February-2014
mbed_official	87:085cde657901	7	* @brief ETH HAL module driver.
mbed_official	87:085cde657901	8	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	9	* functionalities of the Ethernet (ETH) peripheral:
mbed_official	87:085cde657901	10	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	11	* + IO operation functions
mbed_official	87:085cde657901	12	* + Peripheral Control functions
mbed_official	87:085cde657901	13	* + Peripheral State and Errors functions
mbed_official	87:085cde657901	14	*
mbed_official	87:085cde657901	15	@verbatim
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	##### How to use this driver #####
mbed_official	87:085cde657901	18	==============================================================================
mbed_official	87:085cde657901	19	[..]
mbed_official	87:085cde657901	20	(#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official	87:085cde657901	21	ETH_HandleTypeDef heth;
mbed_official	87:085cde657901	22
mbed_official	87:085cde657901	23	(#)Fill parameters of Init structure in heth handle
mbed_official	87:085cde657901	24
mbed_official	87:085cde657901	25	(#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official	87:085cde657901	26
mbed_official	87:085cde657901	27	(#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official	87:085cde657901	28	(##) Enable the Ethernet interface clock using
mbed_official	87:085cde657901	29	(+++) __ETHMAC_CLK_ENABLE();
mbed_official	87:085cde657901	30	(+++) __ETHMACTX_CLK_ENABLE();
mbed_official	87:085cde657901	31	(+++) __ETHMACRX_CLK_ENABLE();
mbed_official	87:085cde657901	32
mbed_official	87:085cde657901	33	(##) Initialize the related GPIO clocks
mbed_official	87:085cde657901	34	(##) Configure Ethernet pin-out
mbed_official	87:085cde657901	35	(##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official	87:085cde657901	36
mbed_official	87:085cde657901	37	(#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official	87:085cde657901	38	(##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official	87:085cde657901	39	(##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official	87:085cde657901	40
mbed_official	87:085cde657901	41	(#)Enable MAC and DMA transmission and reception:
mbed_official	87:085cde657901	42	(##) HAL_ETH_Start();
mbed_official	87:085cde657901	43
mbed_official	87:085cde657901	44	(#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official	87:085cde657901	45	the frame to MAC TX FIFO:
mbed_official	87:085cde657901	46	(##) HAL_ETH_TransmitFrame();
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	(#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official	87:085cde657901	49	frame parameters
mbed_official	87:085cde657901	50	(##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official	87:085cde657901	51
mbed_official	87:085cde657901	52	(#) Get a received frame when an ETH RX interrupt occurs:
mbed_official	87:085cde657901	53	(##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official	87:085cde657901	54
mbed_official	87:085cde657901	55	(#) Communicate with external PHY device:
mbed_official	87:085cde657901	56	(##) Read a specific register from the PHY
mbed_official	87:085cde657901	57	HAL_ETH_ReadPHYRegister();
mbed_official	87:085cde657901	58	(##) Write data to a specific RHY register:
mbed_official	87:085cde657901	59	HAL_ETH_WritePHYRegister();
mbed_official	87:085cde657901	60
mbed_official	87:085cde657901	61	(#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official	87:085cde657901	62	HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official	87:085cde657901	63
mbed_official	87:085cde657901	64	(#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official	87:085cde657901	65	HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official	87:085cde657901	66
mbed_official	87:085cde657901	67	@endverbatim
mbed_official	87:085cde657901	68	******************************************************************************
mbed_official	87:085cde657901	69	* @attention
mbed_official	87:085cde657901	70	*
mbed_official	87:085cde657901	71	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	72	*
mbed_official	87:085cde657901	73	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	74	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	75	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	76	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	77	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	78	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	79	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	80	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	81	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	82	* without specific prior written permission.
mbed_official	87:085cde657901	83	*
mbed_official	87:085cde657901	84	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	85	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	86	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	87	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	88	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	89	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	90	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	91	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	92	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	93	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	94	*
mbed_official	87:085cde657901	95	******************************************************************************
mbed_official	87:085cde657901	96	*/
mbed_official	87:085cde657901	97
mbed_official	87:085cde657901	98	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	99	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	100
mbed_official	87:085cde657901	101	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	102	* @{
mbed_official	87:085cde657901	103	*/
mbed_official	87:085cde657901	104
mbed_official	87:085cde657901	105	/** @defgroup ETH
mbed_official	87:085cde657901	106	* @brief ETH HAL module driver
mbed_official	87:085cde657901	107	* @{
mbed_official	87:085cde657901	108	*/
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110	#ifdef HAL_ETH_MODULE_ENABLED
mbed_official	87:085cde657901	111
mbed_official	87:085cde657901	112	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	87:085cde657901	113
mbed_official	87:085cde657901	114	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	115	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	116	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	117	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	118	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	119	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official	87:085cde657901	120	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr);
mbed_official	87:085cde657901	121	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	122	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	123	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	124	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	125	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	126	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	127	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	128	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	129	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	132
mbed_official	87:085cde657901	133	/** @defgroup ETH_Private_Functions
mbed_official	87:085cde657901	134	* @{
mbed_official	87:085cde657901	135	*/
mbed_official	87:085cde657901	136
mbed_official	87:085cde657901	137	/** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	138	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	139	*
mbed_official	87:085cde657901	140	@verbatim
mbed_official	87:085cde657901	141	===============================================================================
mbed_official	87:085cde657901	142	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	143	===============================================================================
mbed_official	87:085cde657901	144	[..] This section provides functions allowing to:
mbed_official	87:085cde657901	145	(+) Initialize and configure the Ethernet peripheral
mbed_official	87:085cde657901	146	(+) De-initialize the Ethernet peripheral
mbed_official	87:085cde657901	147
mbed_official	87:085cde657901	148	@endverbatim
mbed_official	87:085cde657901	149	* @{
mbed_official	87:085cde657901	150	*/
mbed_official	87:085cde657901	151
mbed_official	87:085cde657901	152	/**
mbed_official	87:085cde657901	153	* @brief Initializes the Ethernet MAC and DMA according to default
mbed_official	87:085cde657901	154	* parameters.
mbed_official	87:085cde657901	155	* @param heth: ETH handle
mbed_official	87:085cde657901	156	* @retval HAL status
mbed_official	87:085cde657901	157	*/
mbed_official	87:085cde657901	158	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	159	{
mbed_official	87:085cde657901	160	uint32_t tmpreg = 0, phyreg = 0;
mbed_official	87:085cde657901	161	uint32_t hclk = 60000000;
mbed_official	87:085cde657901	162	uint32_t timeout = 0;
mbed_official	87:085cde657901	163	uint32_t err = ETH_SUCCESS;
mbed_official	87:085cde657901	164
mbed_official	87:085cde657901	165	/* Check the ETH peripheral state */
mbed_official	87:085cde657901	166	if(heth == NULL)
mbed_official	87:085cde657901	167	{
mbed_official	87:085cde657901	168	return HAL_ERROR;
mbed_official	87:085cde657901	169	}
mbed_official	87:085cde657901	170
mbed_official	87:085cde657901	171	/* Check parameters */
mbed_official	87:085cde657901	172	assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official	87:085cde657901	173	assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official	87:085cde657901	174	assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official	87:085cde657901	175	assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official	87:085cde657901	176
mbed_official	87:085cde657901	177	if(heth->State == HAL_ETH_STATE_RESET)
mbed_official	87:085cde657901	178	{
mbed_official	87:085cde657901	179	/* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official	87:085cde657901	180	HAL_ETH_MspInit(heth);
mbed_official	87:085cde657901	181	}
mbed_official	87:085cde657901	182
mbed_official	87:085cde657901	183	/* Enable SYSCFG Clock */
mbed_official	87:085cde657901	184	__SYSCFG_CLK_ENABLE();
mbed_official	87:085cde657901	185
mbed_official	87:085cde657901	186	/* Select MII or RMII Mode*/
mbed_official	87:085cde657901	187	SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official	87:085cde657901	188	SYSCFG->PMC \|= (uint32_t)heth->Init.MediaInterface;
mbed_official	87:085cde657901	189
mbed_official	87:085cde657901	190	/* Ethernet Software reset */
mbed_official	87:085cde657901	191	/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official	87:085cde657901	192	/* After reset all the registers holds their respective reset values */
mbed_official	87:085cde657901	193	(heth->Instance)->DMABMR \|= ETH_DMABMR_SR;
mbed_official	87:085cde657901	194
mbed_official	87:085cde657901	195	/* Wait for software reset */
mbed_official	87:085cde657901	196	while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official	87:085cde657901	197	{
mbed_official	87:085cde657901	198	}
mbed_official	87:085cde657901	199
mbed_official	87:085cde657901	200	/-------------------------------- MAC Initialization ----------------------/
mbed_official	87:085cde657901	201	/* Get the ETHERNET MACMIIAR value */
mbed_official	87:085cde657901	202	tmpreg = (heth->Instance)->MACMIIAR;
mbed_official	87:085cde657901	203	/* Clear CSR Clock Range CR[2:0] bits */
mbed_official	87:085cde657901	204	tmpreg &= MACMIIAR_CR_MASK;
mbed_official	87:085cde657901	205
mbed_official	87:085cde657901	206	/* Get hclk frequency value */
mbed_official	87:085cde657901	207	hclk = HAL_RCC_GetHCLKFreq();
mbed_official	87:085cde657901	208
mbed_official	87:085cde657901	209	/* Set CR bits depending on hclk value */
mbed_official	87:085cde657901	210	if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official	87:085cde657901	211	{
mbed_official	87:085cde657901	212	/* CSR Clock Range between 20-35 MHz */
mbed_official	87:085cde657901	213	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official	87:085cde657901	214	}
mbed_official	87:085cde657901	215	else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official	87:085cde657901	216	{
mbed_official	87:085cde657901	217	/* CSR Clock Range between 35-60 MHz */
mbed_official	87:085cde657901	218	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official	87:085cde657901	219	}
mbed_official	87:085cde657901	220	else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official	87:085cde657901	221	{
mbed_official	87:085cde657901	222	/* CSR Clock Range between 60-100 MHz */
mbed_official	87:085cde657901	223	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official	87:085cde657901	224	}
mbed_official	87:085cde657901	225	else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official	87:085cde657901	226	{
mbed_official	87:085cde657901	227	/* CSR Clock Range between 100-150 MHz */
mbed_official	87:085cde657901	228	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official	87:085cde657901	229	}
mbed_official	87:085cde657901	230	else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official	87:085cde657901	231	{
mbed_official	87:085cde657901	232	/* CSR Clock Range between 150-168 MHz */
mbed_official	87:085cde657901	233	tmpreg \|= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official	87:085cde657901	234	}
mbed_official	87:085cde657901	235
mbed_official	87:085cde657901	236	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official	87:085cde657901	237	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	238
mbed_official	87:085cde657901	239	/-------------------- PHY initialization and configuration ----------------/
mbed_official	87:085cde657901	240	/* Put the PHY in reset mode */
mbed_official	87:085cde657901	241	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official	87:085cde657901	242	{
mbed_official	87:085cde657901	243	/* In case of write timeout */
mbed_official	87:085cde657901	244	err = ETH_ERROR;
mbed_official	87:085cde657901	245
mbed_official	87:085cde657901	246	/* Config MAC and DMA */
mbed_official	87:085cde657901	247	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	248
mbed_official	87:085cde657901	249	/* Set the ETH peripheral state to READY */
mbed_official	87:085cde657901	250	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	251
mbed_official	87:085cde657901	252	/* Return HAL_ERROR */
mbed_official	87:085cde657901	253	return HAL_ERROR;
mbed_official	87:085cde657901	254	}
mbed_official	87:085cde657901	255
mbed_official	87:085cde657901	256	/* Delay to assure PHY reset */
mbed_official	87:085cde657901	257	HAL_Delay(PHY_RESET_DELAY);
mbed_official	87:085cde657901	258
mbed_official	87:085cde657901	259	if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official	87:085cde657901	260	{
mbed_official	87:085cde657901	261	/* We wait for linked status */
mbed_official	87:085cde657901	262	do
mbed_official	87:085cde657901	263	{
mbed_official	87:085cde657901	264	timeout++;
mbed_official	87:085cde657901	265	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official	87:085cde657901	266	} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
mbed_official	87:085cde657901	267
mbed_official	87:085cde657901	268	if(timeout == PHY_READ_TO)
mbed_official	87:085cde657901	269	{
mbed_official	87:085cde657901	270	/* In case of write timeout */
mbed_official	87:085cde657901	271	err = ETH_ERROR;
mbed_official	87:085cde657901	272
mbed_official	87:085cde657901	273	/* Config MAC and DMA */
mbed_official	87:085cde657901	274	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	275
mbed_official	87:085cde657901	276	/* Set the ETH peripheral state to READY */
mbed_official	87:085cde657901	277	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	278
mbed_official	87:085cde657901	279	/* Return HAL_ERROR */
mbed_official	87:085cde657901	280	return HAL_ERROR;
mbed_official	87:085cde657901	281	}
mbed_official	87:085cde657901	282
mbed_official	87:085cde657901	283	/* Reset Timeout counter */
mbed_official	87:085cde657901	284	timeout = 0;
mbed_official	87:085cde657901	285
mbed_official	87:085cde657901	286	/* Enable Auto-Negotiation */
mbed_official	87:085cde657901	287	if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official	87:085cde657901	288	{
mbed_official	87:085cde657901	289	/* In case of write timeout */
mbed_official	87:085cde657901	290	err = ETH_ERROR;
mbed_official	87:085cde657901	291
mbed_official	87:085cde657901	292	/* Config MAC and DMA */
mbed_official	87:085cde657901	293	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	294
mbed_official	87:085cde657901	295	/* Set the ETH peripheral state to READY */
mbed_official	87:085cde657901	296	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	297
mbed_official	87:085cde657901	298	/* Return HAL_ERROR */
mbed_official	87:085cde657901	299	return HAL_ERROR;
mbed_official	87:085cde657901	300	}
mbed_official	87:085cde657901	301
mbed_official	87:085cde657901	302	/* Wait until the auto-negotiation will be completed */
mbed_official	87:085cde657901	303	do
mbed_official	87:085cde657901	304	{
mbed_official	87:085cde657901	305	timeout++;
mbed_official	87:085cde657901	306	HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official	87:085cde657901	307	} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
mbed_official	87:085cde657901	308
mbed_official	87:085cde657901	309	if(timeout == PHY_READ_TO)
mbed_official	87:085cde657901	310	{
mbed_official	87:085cde657901	311	/* In case of timeout */
mbed_official	87:085cde657901	312	err = ETH_ERROR;
mbed_official	87:085cde657901	313
mbed_official	87:085cde657901	314	/* Config MAC and DMA */
mbed_official	87:085cde657901	315	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	316
mbed_official	87:085cde657901	317	/* Set the ETH peripheral state to READY */
mbed_official	87:085cde657901	318	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	319
mbed_official	87:085cde657901	320	/* Return HAL_ERROR */
mbed_official	87:085cde657901	321	return HAL_ERROR;
mbed_official	87:085cde657901	322	}
mbed_official	87:085cde657901	323
mbed_official	87:085cde657901	324	/* Reset Timeout counter */
mbed_official	87:085cde657901	325	timeout = 0;
mbed_official	87:085cde657901	326
mbed_official	87:085cde657901	327	/* Read the result of the auto-negotiation */
mbed_official	87:085cde657901	328	HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
mbed_official	87:085cde657901	329
mbed_official	87:085cde657901	330	/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official	87:085cde657901	331	if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official	87:085cde657901	332	{
mbed_official	87:085cde657901	333	/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official	87:085cde657901	334	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official	87:085cde657901	335	}
mbed_official	87:085cde657901	336	else
mbed_official	87:085cde657901	337	{
mbed_official	87:085cde657901	338	/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official	87:085cde657901	339	(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official	87:085cde657901	340	}
mbed_official	87:085cde657901	341	/* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official	87:085cde657901	342	if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official	87:085cde657901	343	{
mbed_official	87:085cde657901	344	/* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official	87:085cde657901	345	(heth->Init).Speed = ETH_SPEED_10M;
mbed_official	87:085cde657901	346	}
mbed_official	87:085cde657901	347	else
mbed_official	87:085cde657901	348	{
mbed_official	87:085cde657901	349	/* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official	87:085cde657901	350	(heth->Init).Speed = ETH_SPEED_100M;
mbed_official	87:085cde657901	351	}
mbed_official	87:085cde657901	352	}
mbed_official	87:085cde657901	353	else /* AutoNegotiation Disable */
mbed_official	87:085cde657901	354	{
mbed_official	87:085cde657901	355	/* Check parameters */
mbed_official	87:085cde657901	356	assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official	87:085cde657901	357	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official	87:085cde657901	358
mbed_official	87:085cde657901	359	/* Set MAC Speed and Duplex Mode */
mbed_official	87:085cde657901	360	if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) \|
mbed_official	87:085cde657901	361	(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official	87:085cde657901	362	{
mbed_official	87:085cde657901	363	/* In case of write timeout */
mbed_official	87:085cde657901	364	err = ETH_ERROR;
mbed_official	87:085cde657901	365
mbed_official	87:085cde657901	366	/* Config MAC and DMA */
mbed_official	87:085cde657901	367	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	368
mbed_official	87:085cde657901	369	/* Set the ETH peripheral state to READY */
mbed_official	87:085cde657901	370	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	371
mbed_official	87:085cde657901	372	/* Return HAL_ERROR */
mbed_official	87:085cde657901	373	return HAL_ERROR;
mbed_official	87:085cde657901	374	}
mbed_official	87:085cde657901	375
mbed_official	87:085cde657901	376	/* Delay to assure PHY configuration */
mbed_official	87:085cde657901	377	HAL_Delay(PHY_CONFIG_DELAY);
mbed_official	87:085cde657901	378	}
mbed_official	87:085cde657901	379
mbed_official	87:085cde657901	380	/* Config MAC and DMA */
mbed_official	87:085cde657901	381	ETH_MACDMAConfig(heth, err);
mbed_official	87:085cde657901	382
mbed_official	87:085cde657901	383	/* Set ETH HAL State to Ready */
mbed_official	87:085cde657901	384	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	385
mbed_official	87:085cde657901	386	/* Return function status */
mbed_official	87:085cde657901	387	return HAL_OK;
mbed_official	87:085cde657901	388	}
mbed_official	87:085cde657901	389
mbed_official	87:085cde657901	390	/**
mbed_official	87:085cde657901	391	* @brief De-Initializes the ETH peripheral.
mbed_official	87:085cde657901	392	* @param heth: ETH handle
mbed_official	87:085cde657901	393	* @retval HAL status
mbed_official	87:085cde657901	394	*/
mbed_official	87:085cde657901	395	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	396	{
mbed_official	87:085cde657901	397	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	398	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	399
mbed_official	87:085cde657901	400	/* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official	87:085cde657901	401	HAL_ETH_MspDeInit(heth);
mbed_official	87:085cde657901	402
mbed_official	87:085cde657901	403	/* Set ETH HAL state to Disabled */
mbed_official	87:085cde657901	404	heth->State= HAL_ETH_STATE_RESET;
mbed_official	87:085cde657901	405
mbed_official	87:085cde657901	406	/* Return function status */
mbed_official	87:085cde657901	407	return HAL_OK;
mbed_official	87:085cde657901	408	}
mbed_official	87:085cde657901	409
mbed_official	87:085cde657901	410	/**
mbed_official	87:085cde657901	411	* @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official	87:085cde657901	412	* @param heth: ETH handle
mbed_official	87:085cde657901	413	* @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official	87:085cde657901	414	* @param TxBuff: Pointer to the first TxBuffer list
mbed_official	87:085cde657901	415	* @param TxBuffCount: Number of the used Tx desc in the list
mbed_official	87:085cde657901	416	* @retval HAL status
mbed_official	87:085cde657901	417	*/
mbed_official	87:085cde657901	418	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official	87:085cde657901	419	{
mbed_official	87:085cde657901	420	uint32_t i = 0;
mbed_official	87:085cde657901	421	ETH_DMADescTypeDef *dmatxdesc;
mbed_official	87:085cde657901	422
mbed_official	87:085cde657901	423	/* Process Locked */
mbed_official	87:085cde657901	424	__HAL_LOCK(heth);
mbed_official	87:085cde657901	425
mbed_official	87:085cde657901	426	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	427	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	428
mbed_official	87:085cde657901	429	/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official	87:085cde657901	430	heth->TxDesc = DMATxDescTab;
mbed_official	87:085cde657901	431
mbed_official	87:085cde657901	432	/* Fill each DMATxDesc descriptor with the right values */
mbed_official	87:085cde657901	433	for(i=0; i < TxBuffCount; i++)
mbed_official	87:085cde657901	434	{
mbed_official	87:085cde657901	435	/* Get the pointer on the ith member of the Tx Desc list */
mbed_official	87:085cde657901	436	dmatxdesc = DMATxDescTab + i;
mbed_official	87:085cde657901	437
mbed_official	87:085cde657901	438	/* Set Second Address Chained bit */
mbed_official	87:085cde657901	439	dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official	87:085cde657901	440
mbed_official	87:085cde657901	441	/* Set Buffer1 address pointer */
mbed_official	87:085cde657901	442	dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official	87:085cde657901	443
mbed_official	87:085cde657901	444	if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official	87:085cde657901	445	{
mbed_official	87:085cde657901	446	/* Set the DMA Tx descriptors checksum insertion */
mbed_official	87:085cde657901	447	dmatxdesc->Status \|= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official	87:085cde657901	448	}
mbed_official	87:085cde657901	449
mbed_official	87:085cde657901	450	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official	87:085cde657901	451	if(i < (TxBuffCount-1))
mbed_official	87:085cde657901	452	{
mbed_official	87:085cde657901	453	/* Set next descriptor address register with next descriptor base address */
mbed_official	87:085cde657901	454	dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official	87:085cde657901	455	}
mbed_official	87:085cde657901	456	else
mbed_official	87:085cde657901	457	{
mbed_official	87:085cde657901	458	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official	87:085cde657901	459	dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official	87:085cde657901	460	}
mbed_official	87:085cde657901	461	}
mbed_official	87:085cde657901	462
mbed_official	87:085cde657901	463	/* Set Transmit Descriptor List Address Register */
mbed_official	87:085cde657901	464	(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official	87:085cde657901	465
mbed_official	87:085cde657901	466	/* Set ETH HAL State to Ready */
mbed_official	87:085cde657901	467	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	468
mbed_official	87:085cde657901	469	/* Process Unlocked */
mbed_official	87:085cde657901	470	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	471
mbed_official	87:085cde657901	472	/* Return function status */
mbed_official	87:085cde657901	473	return HAL_OK;
mbed_official	87:085cde657901	474	}
mbed_official	87:085cde657901	475
mbed_official	87:085cde657901	476	/**
mbed_official	87:085cde657901	477	* @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official	87:085cde657901	478	* @param heth: ETH handle
mbed_official	87:085cde657901	479	* @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official	87:085cde657901	480	* @param RxBuff: Pointer to the first RxBuffer list
mbed_official	87:085cde657901	481	* @param RxBuffCount: Number of the used Rx desc in the list
mbed_official	87:085cde657901	482	* @retval HAL status
mbed_official	87:085cde657901	483	*/
mbed_official	87:085cde657901	484	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official	87:085cde657901	485	{
mbed_official	87:085cde657901	486	uint32_t i = 0;
mbed_official	87:085cde657901	487	ETH_DMADescTypeDef *DMARxDesc;
mbed_official	87:085cde657901	488
mbed_official	87:085cde657901	489	/* Process Locked */
mbed_official	87:085cde657901	490	__HAL_LOCK(heth);
mbed_official	87:085cde657901	491
mbed_official	87:085cde657901	492	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	493	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	494
mbed_official	87:085cde657901	495	/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official	87:085cde657901	496	heth->RxDesc = DMARxDescTab;
mbed_official	87:085cde657901	497
mbed_official	87:085cde657901	498	/* Fill each DMARxDesc descriptor with the right values */
mbed_official	87:085cde657901	499	for(i=0; i < RxBuffCount; i++)
mbed_official	87:085cde657901	500	{
mbed_official	87:085cde657901	501	/* Get the pointer on the ith member of the Rx Desc list */
mbed_official	87:085cde657901	502	DMARxDesc = DMARxDescTab+i;
mbed_official	87:085cde657901	503
mbed_official	87:085cde657901	504	/* Set Own bit of the Rx descriptor Status */
mbed_official	87:085cde657901	505	DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official	87:085cde657901	506
mbed_official	87:085cde657901	507	/* Set Buffer1 size and Second Address Chained bit */
mbed_official	87:085cde657901	508	DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH \| ETH_RX_BUF_SIZE;
mbed_official	87:085cde657901	509
mbed_official	87:085cde657901	510	/* Set Buffer1 address pointer */
mbed_official	87:085cde657901	511	DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official	87:085cde657901	512
mbed_official	87:085cde657901	513	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official	87:085cde657901	514	{
mbed_official	87:085cde657901	515	/* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official	87:085cde657901	516	DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official	87:085cde657901	517	}
mbed_official	87:085cde657901	518
mbed_official	87:085cde657901	519	/* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official	87:085cde657901	520	if(i < (RxBuffCount-1))
mbed_official	87:085cde657901	521	{
mbed_official	87:085cde657901	522	/* Set next descriptor address register with next descriptor base address */
mbed_official	87:085cde657901	523	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official	87:085cde657901	524	}
mbed_official	87:085cde657901	525	else
mbed_official	87:085cde657901	526	{
mbed_official	87:085cde657901	527	/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official	87:085cde657901	528	DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official	87:085cde657901	529	}
mbed_official	87:085cde657901	530	}
mbed_official	87:085cde657901	531
mbed_official	87:085cde657901	532	/* Set Receive Descriptor List Address Register */
mbed_official	87:085cde657901	533	(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official	87:085cde657901	534
mbed_official	87:085cde657901	535	/* Set ETH HAL State to Ready */
mbed_official	87:085cde657901	536	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	537
mbed_official	87:085cde657901	538	/* Process Unlocked */
mbed_official	87:085cde657901	539	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	540
mbed_official	87:085cde657901	541	/* Return function status */
mbed_official	87:085cde657901	542	return HAL_OK;
mbed_official	87:085cde657901	543	}
mbed_official	87:085cde657901	544
mbed_official	87:085cde657901	545	/**
mbed_official	87:085cde657901	546	* @brief Initializes the ETH MSP.
mbed_official	87:085cde657901	547	* @param heth: ETH handle
mbed_official	87:085cde657901	548	* @retval None
mbed_official	87:085cde657901	549	*/
mbed_official	87:085cde657901	550	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	551	{
mbed_official	87:085cde657901	552	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	553	the HAL_ETH_MspInit could be implemented in the user file
mbed_official	87:085cde657901	554	*/
mbed_official	87:085cde657901	555	}
mbed_official	87:085cde657901	556
mbed_official	87:085cde657901	557	/**
mbed_official	87:085cde657901	558	* @brief DeInitializes ETH MSP.
mbed_official	87:085cde657901	559	* @param heth: ETH handle
mbed_official	87:085cde657901	560	* @retval None
mbed_official	87:085cde657901	561	*/
mbed_official	87:085cde657901	562	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	563	{
mbed_official	87:085cde657901	564	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	565	the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	566	*/
mbed_official	87:085cde657901	567	}
mbed_official	87:085cde657901	568
mbed_official	87:085cde657901	569	/**
mbed_official	87:085cde657901	570	* @}
mbed_official	87:085cde657901	571	*/
mbed_official	87:085cde657901	572
mbed_official	87:085cde657901	573	/** @defgroup ETH_Group2 IO operation functions
mbed_official	87:085cde657901	574	* @brief Data transfers functions
mbed_official	87:085cde657901	575	*
mbed_official	87:085cde657901	576	@verbatim
mbed_official	87:085cde657901	577	==============================================================================
mbed_official	87:085cde657901	578	##### IO operation functions #####
mbed_official	87:085cde657901	579	==============================================================================
mbed_official	87:085cde657901	580	[..] This section provides functions allowing to:
mbed_official	87:085cde657901	581	(+) Transmit a frame
mbed_official	87:085cde657901	582	HAL_ETH_TransmitFrame();
mbed_official	87:085cde657901	583	(+) Receive a frame
mbed_official	87:085cde657901	584	HAL_ETH_GetReceivedFrame();
mbed_official	87:085cde657901	585	HAL_ETH_GetReceivedFrame_IT();
mbed_official	87:085cde657901	586	(+) Read from an External PHY register
mbed_official	87:085cde657901	587	HAL_ETH_ReadPHYRegister();
mbed_official	87:085cde657901	588	(+) Writo to an External PHY register
mbed_official	87:085cde657901	589	HAL_ETH_WritePHYRegister();
mbed_official	87:085cde657901	590
mbed_official	87:085cde657901	591	@endverbatim
mbed_official	87:085cde657901	592
mbed_official	87:085cde657901	593	* @{
mbed_official	87:085cde657901	594	*/
mbed_official	87:085cde657901	595
mbed_official	87:085cde657901	596	/**
mbed_official	87:085cde657901	597	* @brief Sends an Ethernet frame.
mbed_official	87:085cde657901	598	* @param heth: ETH handle
mbed_official	87:085cde657901	599	* @param FrameLength: Amount of data to be sent
mbed_official	87:085cde657901	600	* @retval HAL status
mbed_official	87:085cde657901	601	*/
mbed_official	87:085cde657901	602	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official	87:085cde657901	603	{
mbed_official	87:085cde657901	604	uint32_t bufcount = 0, size = 0, i = 0;
mbed_official	87:085cde657901	605
mbed_official	87:085cde657901	606	/* Process Locked */
mbed_official	87:085cde657901	607	__HAL_LOCK(heth);
mbed_official	87:085cde657901	608
mbed_official	87:085cde657901	609	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	610	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	611
mbed_official	87:085cde657901	612	if (FrameLength == 0)
mbed_official	87:085cde657901	613	{
mbed_official	87:085cde657901	614	/* Set ETH HAL state to READY */
mbed_official	87:085cde657901	615	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	616
mbed_official	87:085cde657901	617	/* Process Unlocked */
mbed_official	87:085cde657901	618	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	619
mbed_official	87:085cde657901	620	return HAL_ERROR;
mbed_official	87:085cde657901	621	}
mbed_official	87:085cde657901	622
mbed_official	87:085cde657901	623	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official	87:085cde657901	624	if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official	87:085cde657901	625	{
mbed_official	87:085cde657901	626	/* OWN bit set */
mbed_official	87:085cde657901	627	heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official	87:085cde657901	628
mbed_official	87:085cde657901	629	/* Process Unlocked */
mbed_official	87:085cde657901	630	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	631
mbed_official	87:085cde657901	632	return HAL_ERROR;
mbed_official	87:085cde657901	633	}
mbed_official	87:085cde657901	634
mbed_official	87:085cde657901	635	/* Get the number of needed Tx buffers for the current frame */
mbed_official	87:085cde657901	636	if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official	87:085cde657901	637	{
mbed_official	87:085cde657901	638	bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official	87:085cde657901	639	if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official	87:085cde657901	640	{
mbed_official	87:085cde657901	641	bufcount++;
mbed_official	87:085cde657901	642	}
mbed_official	87:085cde657901	643	}
mbed_official	87:085cde657901	644	else
mbed_official	87:085cde657901	645	{
mbed_official	87:085cde657901	646	bufcount = 1;
mbed_official	87:085cde657901	647	}
mbed_official	87:085cde657901	648	if (bufcount == 1)
mbed_official	87:085cde657901	649	{
mbed_official	87:085cde657901	650	/* Set LAST and FIRST segment */
mbed_official	87:085cde657901	651	heth->TxDesc->Status \|=ETH_DMATXDESC_FS\|ETH_DMATXDESC_LS;
mbed_official	87:085cde657901	652	/* Set frame size */
mbed_official	87:085cde657901	653	heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official	87:085cde657901	654	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official	87:085cde657901	655	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
mbed_official	87:085cde657901	656	/* Point to next descriptor */
mbed_official	87:085cde657901	657	heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	658	}
mbed_official	87:085cde657901	659	else
mbed_official	87:085cde657901	660	{
mbed_official	87:085cde657901	661	for (i=0; i< bufcount; i++)
mbed_official	87:085cde657901	662	{
mbed_official	87:085cde657901	663	/* Clear FIRST and LAST segment bits */
mbed_official	87:085cde657901	664	heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS \| ETH_DMATXDESC_LS);
mbed_official	87:085cde657901	665
mbed_official	87:085cde657901	666	if (i == 0)
mbed_official	87:085cde657901	667	{
mbed_official	87:085cde657901	668	/* Setting the first segment bit */
mbed_official	87:085cde657901	669	heth->TxDesc->Status \|= ETH_DMATXDESC_FS;
mbed_official	87:085cde657901	670	}
mbed_official	87:085cde657901	671
mbed_official	87:085cde657901	672	/* Program size */
mbed_official	87:085cde657901	673	heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official	87:085cde657901	674
mbed_official	87:085cde657901	675	if (i == (bufcount-1))
mbed_official	87:085cde657901	676	{
mbed_official	87:085cde657901	677	/* Setting the last segment bit */
mbed_official	87:085cde657901	678	heth->TxDesc->Status \|= ETH_DMATXDESC_LS;
mbed_official	87:085cde657901	679	size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official	87:085cde657901	680	heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official	87:085cde657901	681	}
mbed_official	87:085cde657901	682
mbed_official	87:085cde657901	683	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official	87:085cde657901	684	heth->TxDesc->Status \|= ETH_DMATXDESC_OWN;
mbed_official	87:085cde657901	685	/* point to next descriptor */
mbed_official	87:085cde657901	686	heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	687	}
mbed_official	87:085cde657901	688	}
mbed_official	87:085cde657901	689
mbed_official	87:085cde657901	690	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official	87:085cde657901	691	if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official	87:085cde657901	692	{
mbed_official	87:085cde657901	693	/* Clear TBUS ETHERNET DMA flag */
mbed_official	87:085cde657901	694	(heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official	87:085cde657901	695	/* Resume DMA transmission*/
mbed_official	87:085cde657901	696	(heth->Instance)->DMATPDR = 0;
mbed_official	87:085cde657901	697	}
mbed_official	87:085cde657901	698
mbed_official	87:085cde657901	699	/* Set ETH HAL State to Ready */
mbed_official	87:085cde657901	700	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	701
mbed_official	87:085cde657901	702	/* Process Unlocked */
mbed_official	87:085cde657901	703	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	704
mbed_official	87:085cde657901	705	/* Return function status */
mbed_official	87:085cde657901	706	return HAL_OK;
mbed_official	87:085cde657901	707	}
mbed_official	87:085cde657901	708
mbed_official	87:085cde657901	709	/**
mbed_official	87:085cde657901	710	* @brief Checks for received frames.
mbed_official	87:085cde657901	711	* @param heth: ETH handle
mbed_official	87:085cde657901	712	* @retval HAL status
mbed_official	87:085cde657901	713	*/
mbed_official	87:085cde657901	714	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	715	{
mbed_official	87:085cde657901	716	uint32_t framelength = 0;
mbed_official	87:085cde657901	717
mbed_official	87:085cde657901	718	/* Process Locked */
mbed_official	87:085cde657901	719	__HAL_LOCK(heth);
mbed_official	87:085cde657901	720
mbed_official	87:085cde657901	721	/* Check the ETH state to BUSY */
mbed_official	87:085cde657901	722	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	723
mbed_official	87:085cde657901	724	/* Check if segment is not owned by DMA */
mbed_official	87:085cde657901	725	/* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official	87:085cde657901	726	if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official	87:085cde657901	727	{
mbed_official	87:085cde657901	728	/* Check if last segment */
mbed_official	87:085cde657901	729	if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official	87:085cde657901	730	{
mbed_official	87:085cde657901	731	/* increment segment count */
mbed_official	87:085cde657901	732	(heth->RxFrameInfos).SegCount++;
mbed_official	87:085cde657901	733
mbed_official	87:085cde657901	734	/* Check if last segment is first segment: one segment contains the frame */
mbed_official	87:085cde657901	735	if ((heth->RxFrameInfos).SegCount == 1)
mbed_official	87:085cde657901	736	{
mbed_official	87:085cde657901	737	(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official	87:085cde657901	738	}
mbed_official	87:085cde657901	739
mbed_official	87:085cde657901	740	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official	87:085cde657901	741
mbed_official	87:085cde657901	742	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official	87:085cde657901	743	framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official	87:085cde657901	744	heth->RxFrameInfos.length = framelength;
mbed_official	87:085cde657901	745
mbed_official	87:085cde657901	746	/* Get the address of the buffer start address */
mbed_official	87:085cde657901	747	heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official	87:085cde657901	748	/* point to next descriptor */
mbed_official	87:085cde657901	749	heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official	87:085cde657901	750
mbed_official	87:085cde657901	751	/* Set HAL State to Ready */
mbed_official	87:085cde657901	752	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	753
mbed_official	87:085cde657901	754	/* Process Unlocked */
mbed_official	87:085cde657901	755	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	756
mbed_official	87:085cde657901	757	/* Return function status */
mbed_official	87:085cde657901	758	return HAL_OK;
mbed_official	87:085cde657901	759	}
mbed_official	87:085cde657901	760	/* Check if first segment */
mbed_official	87:085cde657901	761	else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official	87:085cde657901	762	{
mbed_official	87:085cde657901	763	(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official	87:085cde657901	764	(heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official	87:085cde657901	765	(heth->RxFrameInfos).SegCount = 1;
mbed_official	87:085cde657901	766	/* Point to next descriptor */
mbed_official	87:085cde657901	767	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	768	}
mbed_official	87:085cde657901	769	/* Check if intermediate segment */
mbed_official	87:085cde657901	770	else
mbed_official	87:085cde657901	771	{
mbed_official	87:085cde657901	772	(heth->RxFrameInfos).SegCount++;
mbed_official	87:085cde657901	773	/* Point to next descriptor */
mbed_official	87:085cde657901	774	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	775	}
mbed_official	87:085cde657901	776	}
mbed_official	87:085cde657901	777
mbed_official	87:085cde657901	778	/* Set ETH HAL State to Ready */
mbed_official	87:085cde657901	779	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	780
mbed_official	87:085cde657901	781	/* Process Unlocked */
mbed_official	87:085cde657901	782	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	783
mbed_official	87:085cde657901	784	return HAL_ERROR;
mbed_official	87:085cde657901	785	}
mbed_official	87:085cde657901	786
mbed_official	87:085cde657901	787	/**
mbed_official	87:085cde657901	788	* @brief Gets the Received frame in interrupt mode.
mbed_official	87:085cde657901	789	* @param heth: ETH handle
mbed_official	87:085cde657901	790	* @retval HAL status
mbed_official	87:085cde657901	791	*/
mbed_official	87:085cde657901	792	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	793	{
mbed_official	87:085cde657901	794	uint32_t descriptorscancounter = 0;
mbed_official	87:085cde657901	795
mbed_official	87:085cde657901	796	/* Process Locked */
mbed_official	87:085cde657901	797	__HAL_LOCK(heth);
mbed_official	87:085cde657901	798
mbed_official	87:085cde657901	799	/* Set ETH HAL State to BUSY */
mbed_official	87:085cde657901	800	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	801
mbed_official	87:085cde657901	802	/* Scan descriptors owned by CPU */
mbed_official	87:085cde657901	803	while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official	87:085cde657901	804	{
mbed_official	87:085cde657901	805	/* Just for security */
mbed_official	87:085cde657901	806	descriptorscancounter++;
mbed_official	87:085cde657901	807
mbed_official	87:085cde657901	808	/* Check if first segment in frame */
mbed_official	87:085cde657901	809	/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official	87:085cde657901	810	if((heth->RxDesc->Status & (ETH_DMARXDESC_FS \| ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official	87:085cde657901	811	{
mbed_official	87:085cde657901	812	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official	87:085cde657901	813	heth->RxFrameInfos.SegCount = 1;
mbed_official	87:085cde657901	814	/* Point to next descriptor */
mbed_official	87:085cde657901	815	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	816	}
mbed_official	87:085cde657901	817	/* Check if intermediate segment */
mbed_official	87:085cde657901	818	/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official	87:085cde657901	819	else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS \| ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official	87:085cde657901	820	{
mbed_official	87:085cde657901	821	/* Increment segment count */
mbed_official	87:085cde657901	822	(heth->RxFrameInfos.SegCount)++;
mbed_official	87:085cde657901	823	/* Point to next descriptor */
mbed_official	87:085cde657901	824	heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	825	}
mbed_official	87:085cde657901	826	/* Should be last segment */
mbed_official	87:085cde657901	827	else
mbed_official	87:085cde657901	828	{
mbed_official	87:085cde657901	829	/* Last segment */
mbed_official	87:085cde657901	830	heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official	87:085cde657901	831
mbed_official	87:085cde657901	832	/* Increment segment count */
mbed_official	87:085cde657901	833	(heth->RxFrameInfos.SegCount)++;
mbed_official	87:085cde657901	834
mbed_official	87:085cde657901	835	/* Check if last segment is first segment: one segment contains the frame */
mbed_official	87:085cde657901	836	if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official	87:085cde657901	837	{
mbed_official	87:085cde657901	838	heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official	87:085cde657901	839	}
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official	87:085cde657901	842	heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official	87:085cde657901	843
mbed_official	87:085cde657901	844	/* Get the address of the buffer start address */
mbed_official	87:085cde657901	845	heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official	87:085cde657901	846
mbed_official	87:085cde657901	847	/* Point to next descriptor */
mbed_official	87:085cde657901	848	heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official	87:085cde657901	849
mbed_official	87:085cde657901	850	/* Set HAL State to Ready */
mbed_official	87:085cde657901	851	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	852
mbed_official	87:085cde657901	853	/* Process Unlocked */
mbed_official	87:085cde657901	854	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	855
mbed_official	87:085cde657901	856	/* Return function status */
mbed_official	87:085cde657901	857	return HAL_OK;
mbed_official	87:085cde657901	858	}
mbed_official	87:085cde657901	859	}
mbed_official	87:085cde657901	860
mbed_official	87:085cde657901	861	/* Set HAL State to Ready */
mbed_official	87:085cde657901	862	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	863
mbed_official	87:085cde657901	864	/* Process Unlocked */
mbed_official	87:085cde657901	865	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	866
mbed_official	87:085cde657901	867	/* Return function status */
mbed_official	87:085cde657901	868	return HAL_OK;
mbed_official	87:085cde657901	869	}
mbed_official	87:085cde657901	870
mbed_official	87:085cde657901	871	/**
mbed_official	87:085cde657901	872	* @brief This function handles ETH interrupt request.
mbed_official	87:085cde657901	873	* @param heth: ETH handle
mbed_official	87:085cde657901	874	* @retval HAL status
mbed_official	87:085cde657901	875	*/
mbed_official	87:085cde657901	876	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	877	{
mbed_official	87:085cde657901	878	/* Frame received */
mbed_official	87:085cde657901	879	if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official	87:085cde657901	880	{
mbed_official	87:085cde657901	881	/* Receive complete callback */
mbed_official	87:085cde657901	882	HAL_ETH_RxCpltCallback(heth);
mbed_official	87:085cde657901	883
mbed_official	87:085cde657901	884	/* Clear the Eth DMA Rx IT pending bits */
mbed_official	87:085cde657901	885	__HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(heth, ETH_DMA_IT_R);
mbed_official	87:085cde657901	886
mbed_official	87:085cde657901	887	/* Set HAL State to Ready */
mbed_official	87:085cde657901	888	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	889
mbed_official	87:085cde657901	890	/* Process Unlocked */
mbed_official	87:085cde657901	891	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	892
mbed_official	87:085cde657901	893	}
mbed_official	87:085cde657901	894	/* Frame transmitted */
mbed_official	87:085cde657901	895	else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official	87:085cde657901	896	{
mbed_official	87:085cde657901	897	/* Transfer complete callback */
mbed_official	87:085cde657901	898	HAL_ETH_TxCpltCallback(heth);
mbed_official	87:085cde657901	899
mbed_official	87:085cde657901	900	/* Clear the Eth DMA Tx IT pending bits */
mbed_official	87:085cde657901	901	__HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(heth, ETH_DMA_IT_T);
mbed_official	87:085cde657901	902
mbed_official	87:085cde657901	903	/* Set HAL State to Ready */
mbed_official	87:085cde657901	904	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	905
mbed_official	87:085cde657901	906	/* Process Unlocked */
mbed_official	87:085cde657901	907	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	908	}
mbed_official	87:085cde657901	909
mbed_official	87:085cde657901	910	/* Clear the interrupt flags */
mbed_official	87:085cde657901	911	__HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(heth, ETH_DMA_IT_NIS);
mbed_official	87:085cde657901	912
mbed_official	87:085cde657901	913	/* ETH DMA Error */
mbed_official	87:085cde657901	914	if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official	87:085cde657901	915	{
mbed_official	87:085cde657901	916	/* Ethernet Error callback */
mbed_official	87:085cde657901	917	HAL_ETH_ErrorCallback(heth);
mbed_official	87:085cde657901	918
mbed_official	87:085cde657901	919	/* Clear the interrupt flags */
mbed_official	87:085cde657901	920	__HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(heth, ETH_DMA_FLAG_AIS);
mbed_official	87:085cde657901	921
mbed_official	87:085cde657901	922	/* Set HAL State to Ready */
mbed_official	87:085cde657901	923	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	924
mbed_official	87:085cde657901	925	/* Process Unlocked */
mbed_official	87:085cde657901	926	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	927	}
mbed_official	87:085cde657901	928	}
mbed_official	87:085cde657901	929
mbed_official	87:085cde657901	930	/**
mbed_official	87:085cde657901	931	* @brief Tx Transfer completed callbacks.
mbed_official	87:085cde657901	932	* @param heth: ETH handle
mbed_official	87:085cde657901	933	* @retval None
mbed_official	87:085cde657901	934	*/
mbed_official	87:085cde657901	935	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	936	{
mbed_official	87:085cde657901	937	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	938	the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official	87:085cde657901	939	*/
mbed_official	87:085cde657901	940	}
mbed_official	87:085cde657901	941
mbed_official	87:085cde657901	942	/**
mbed_official	87:085cde657901	943	* @brief Rx Transfer completed callbacks.
mbed_official	87:085cde657901	944	* @param heth: ETH handle
mbed_official	87:085cde657901	945	* @retval None
mbed_official	87:085cde657901	946	*/
mbed_official	87:085cde657901	947	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	948	{
mbed_official	87:085cde657901	949	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	950	the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official	87:085cde657901	951	*/
mbed_official	87:085cde657901	952	}
mbed_official	87:085cde657901	953
mbed_official	87:085cde657901	954	/**
mbed_official	87:085cde657901	955	* @brief Ethernet transfer error callbacks
mbed_official	87:085cde657901	956	* @param heth: ETH handle
mbed_official	87:085cde657901	957	* @retval None
mbed_official	87:085cde657901	958	*/
mbed_official	87:085cde657901	959	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	960	{
mbed_official	87:085cde657901	961	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	962	the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official	87:085cde657901	963	*/
mbed_official	87:085cde657901	964	}
mbed_official	87:085cde657901	965
mbed_official	87:085cde657901	966	/**
mbed_official	87:085cde657901	967	* @brief Reads a PHY register
mbed_official	87:085cde657901	968	* @param heth: ETH handle
mbed_official	87:085cde657901	969	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official	87:085cde657901	970	* This parameter can be one of the following values:
mbed_official	87:085cde657901	971	* @arg PHY_BCR: Transceiver Basic Control Register
mbed_official	87:085cde657901	972	* @arg PHY_BSR: Transceiver Basic Status Register
mbed_official	87:085cde657901	973	* @arg More PHY register could be read depending on the used PHY
mbed_official	87:085cde657901	974	* @param RegValue: PHY register value
mbed_official	87:085cde657901	975	* @retval HAL_TIMEOUT: in case of timeout
mbed_official	87:085cde657901	976	* MACMIIDR register value: Data read from the selected PHY register (correct read )
mbed_official	87:085cde657901	977	*/
mbed_official	87:085cde657901	978	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official	87:085cde657901	979	{
mbed_official	87:085cde657901	980	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	981	uint32_t timeout = 0;
mbed_official	87:085cde657901	982
mbed_official	87:085cde657901	983	/* Check parameters */
mbed_official	87:085cde657901	984	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official	87:085cde657901	985
mbed_official	87:085cde657901	986	/* Check the ETH peripheral state */
mbed_official	87:085cde657901	987	if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official	87:085cde657901	988	{
mbed_official	87:085cde657901	989	return HAL_BUSY;
mbed_official	87:085cde657901	990	}
mbed_official	87:085cde657901	991	/* Set ETH HAL State to BUSY_RD */
mbed_official	87:085cde657901	992	heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official	87:085cde657901	993
mbed_official	87:085cde657901	994	/* Get the ETHERNET MACMIIAR value */
mbed_official	87:085cde657901	995	tmpreg = heth->Instance->MACMIIAR;
mbed_official	87:085cde657901	996
mbed_official	87:085cde657901	997	/* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official	87:085cde657901	998	tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official	87:085cde657901	999
mbed_official	87:085cde657901	1000	/* Prepare the MII address register value */
mbed_official	87:085cde657901	1001	tmpreg \|=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official	87:085cde657901	1002	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official	87:085cde657901	1003	tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official	87:085cde657901	1004	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official	87:085cde657901	1005
mbed_official	87:085cde657901	1006	/* Write the result value into the MII Address register */
mbed_official	87:085cde657901	1007	heth->Instance->MACMIIAR = tmpreg;
mbed_official	87:085cde657901	1008
mbed_official	87:085cde657901	1009	/* Check for the Busy flag */
mbed_official	87:085cde657901	1010	do
mbed_official	87:085cde657901	1011	{
mbed_official	87:085cde657901	1012	timeout++;
mbed_official	87:085cde657901	1013	tmpreg = heth->Instance->MACMIIAR;
mbed_official	87:085cde657901	1014	} while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
mbed_official	87:085cde657901	1015
mbed_official	87:085cde657901	1016	/* Return ERROR in case of timeout */
mbed_official	87:085cde657901	1017	if(timeout == PHY_READ_TO)
mbed_official	87:085cde657901	1018	{
mbed_official	87:085cde657901	1019	/* Set ETH HAL State to READY */
mbed_official	87:085cde657901	1020	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1021	/* Return HAL_TIMEOUT */
mbed_official	87:085cde657901	1022	return HAL_TIMEOUT;
mbed_official	87:085cde657901	1023	}
mbed_official	87:085cde657901	1024
mbed_official	87:085cde657901	1025	/* Get MACMIIDR value */
mbed_official	87:085cde657901	1026	*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official	87:085cde657901	1027
mbed_official	87:085cde657901	1028	/* Set ETH HAL State to READY */
mbed_official	87:085cde657901	1029	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1030
mbed_official	87:085cde657901	1031	/* Return function status */
mbed_official	87:085cde657901	1032	return HAL_OK;
mbed_official	87:085cde657901	1033	}
mbed_official	87:085cde657901	1034
mbed_official	87:085cde657901	1035	/**
mbed_official	87:085cde657901	1036	* @brief Writes to a PHY register.
mbed_official	87:085cde657901	1037	* @param heth: ETH handle
mbed_official	87:085cde657901	1038	* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official	87:085cde657901	1039	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1040	* @arg PHY_BCR: Transceiver Control Register
mbed_official	87:085cde657901	1041	* @arg More PHY register could be written depending on the used PHY
mbed_official	87:085cde657901	1042	* @param RegValue: the value to write
mbed_official	87:085cde657901	1043	* @retval HAL status
mbed_official	87:085cde657901	1044	*/
mbed_official	87:085cde657901	1045	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official	87:085cde657901	1046	{
mbed_official	87:085cde657901	1047	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1048	uint32_t timeout = 0;
mbed_official	87:085cde657901	1049
mbed_official	87:085cde657901	1050	/* Check parameters */
mbed_official	87:085cde657901	1051	assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official	87:085cde657901	1052
mbed_official	87:085cde657901	1053	/* Check the ETH peripheral state */
mbed_official	87:085cde657901	1054	if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official	87:085cde657901	1055	{
mbed_official	87:085cde657901	1056	return HAL_BUSY;
mbed_official	87:085cde657901	1057	}
mbed_official	87:085cde657901	1058	/* Set ETH HAL State to BUSY_WR */
mbed_official	87:085cde657901	1059	heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official	87:085cde657901	1060
mbed_official	87:085cde657901	1061	/* Get the ETHERNET MACMIIAR value */
mbed_official	87:085cde657901	1062	tmpreg = heth->Instance->MACMIIAR;
mbed_official	87:085cde657901	1063
mbed_official	87:085cde657901	1064	/* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official	87:085cde657901	1065	tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official	87:085cde657901	1066
mbed_official	87:085cde657901	1067	/* Prepare the MII register address value */
mbed_official	87:085cde657901	1068	tmpreg \|=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official	87:085cde657901	1069	tmpreg \|=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official	87:085cde657901	1070	tmpreg \|= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official	87:085cde657901	1071	tmpreg \|= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official	87:085cde657901	1072
mbed_official	87:085cde657901	1073	/* Give the value to the MII data register */
mbed_official	87:085cde657901	1074	heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official	87:085cde657901	1075
mbed_official	87:085cde657901	1076	/* Write the result value into the MII Address register */
mbed_official	87:085cde657901	1077	heth->Instance->MACMIIAR = tmpreg;
mbed_official	87:085cde657901	1078
mbed_official	87:085cde657901	1079	/* Check for the Busy flag */
mbed_official	87:085cde657901	1080	do
mbed_official	87:085cde657901	1081	{
mbed_official	87:085cde657901	1082	timeout++;
mbed_official	87:085cde657901	1083	tmpreg = heth->Instance->MACMIIAR;
mbed_official	87:085cde657901	1084	} while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
mbed_official	87:085cde657901	1085
mbed_official	87:085cde657901	1086	/* Return TIMETOUT in case of timeout */
mbed_official	87:085cde657901	1087	if(timeout == PHY_WRITE_TO)
mbed_official	87:085cde657901	1088	{
mbed_official	87:085cde657901	1089	/* Set ETH HAL State to READY */
mbed_official	87:085cde657901	1090	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1091
mbed_official	87:085cde657901	1092	return HAL_TIMEOUT;
mbed_official	87:085cde657901	1093	}
mbed_official	87:085cde657901	1094
mbed_official	87:085cde657901	1095	/* Set ETH HAL State to READY */
mbed_official	87:085cde657901	1096	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1097
mbed_official	87:085cde657901	1098	/* Return function status */
mbed_official	87:085cde657901	1099	return HAL_OK;
mbed_official	87:085cde657901	1100	}
mbed_official	87:085cde657901	1101
mbed_official	87:085cde657901	1102	/**
mbed_official	87:085cde657901	1103	* @}
mbed_official	87:085cde657901	1104	*/
mbed_official	87:085cde657901	1105
mbed_official	87:085cde657901	1106	/** @defgroup ETH_Group3 Peripheral Control functions
mbed_official	87:085cde657901	1107	* @brief Peripheral Control functions
mbed_official	87:085cde657901	1108	*
mbed_official	87:085cde657901	1109	@verbatim
mbed_official	87:085cde657901	1110	===============================================================================
mbed_official	87:085cde657901	1111	##### Peripheral Control functions #####
mbed_official	87:085cde657901	1112	===============================================================================
mbed_official	87:085cde657901	1113	[..] This section provides functions allowing to:
mbed_official	87:085cde657901	1114	(+) Enable MAC and DMA transmission and reception.
mbed_official	87:085cde657901	1115	HAL_ETH_Start();
mbed_official	87:085cde657901	1116	(+) Disable MAC and DMA transmission and reception.
mbed_official	87:085cde657901	1117	HAL_ETH_Stop();
mbed_official	87:085cde657901	1118	(+) Set the MAC configuration in runtime mode
mbed_official	87:085cde657901	1119	HAL_ETH_ConfigMAC();
mbed_official	87:085cde657901	1120	(+) Set the DMA configuration in runtime mode
mbed_official	87:085cde657901	1121	HAL_ETH_ConfigDMA();
mbed_official	87:085cde657901	1122
mbed_official	87:085cde657901	1123	@endverbatim
mbed_official	87:085cde657901	1124	* @{
mbed_official	87:085cde657901	1125	*/
mbed_official	87:085cde657901	1126
mbed_official	87:085cde657901	1127	/**
mbed_official	87:085cde657901	1128	* @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official	87:085cde657901	1129	* @param heth: ETH handle
mbed_official	87:085cde657901	1130	* @retval HAL status
mbed_official	87:085cde657901	1131	*/
mbed_official	87:085cde657901	1132	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1133	{
mbed_official	87:085cde657901	1134	/* Process Locked */
mbed_official	87:085cde657901	1135	__HAL_LOCK(heth);
mbed_official	87:085cde657901	1136
mbed_official	87:085cde657901	1137	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	1138	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	1139
mbed_official	87:085cde657901	1140	/* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official	87:085cde657901	1141	ETH_MACTransmissionEnable(heth);
mbed_official	87:085cde657901	1142
mbed_official	87:085cde657901	1143	/* Enable receive state machine of the MAC for reception from the MII */
mbed_official	87:085cde657901	1144	ETH_MACReceptionEnable(heth);
mbed_official	87:085cde657901	1145
mbed_official	87:085cde657901	1146	/* Flush Transmit FIFO */
mbed_official	87:085cde657901	1147	ETH_FlushTransmitFIFO(heth);
mbed_official	87:085cde657901	1148
mbed_official	87:085cde657901	1149	/* Start DMA transmission */
mbed_official	87:085cde657901	1150	ETH_DMATransmissionEnable(heth);
mbed_official	87:085cde657901	1151
mbed_official	87:085cde657901	1152	/* Start DMA reception */
mbed_official	87:085cde657901	1153	ETH_DMAReceptionEnable(heth);
mbed_official	87:085cde657901	1154
mbed_official	87:085cde657901	1155	/* Set the ETH state to READY*/
mbed_official	87:085cde657901	1156	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1157
mbed_official	87:085cde657901	1158	/* Process Unlocked */
mbed_official	87:085cde657901	1159	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	1160
mbed_official	87:085cde657901	1161	/* Return function status */
mbed_official	87:085cde657901	1162	return HAL_OK;
mbed_official	87:085cde657901	1163	}
mbed_official	87:085cde657901	1164
mbed_official	87:085cde657901	1165	/**
mbed_official	87:085cde657901	1166	* @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official	87:085cde657901	1167	* @param heth: ETH handle
mbed_official	87:085cde657901	1168	* @retval HAL status
mbed_official	87:085cde657901	1169	*/
mbed_official	87:085cde657901	1170	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1171	{
mbed_official	87:085cde657901	1172	/* Process Locked */
mbed_official	87:085cde657901	1173	__HAL_LOCK(heth);
mbed_official	87:085cde657901	1174
mbed_official	87:085cde657901	1175	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	1176	heth->State = HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	1177
mbed_official	87:085cde657901	1178	/* Stop DMA transmission */
mbed_official	87:085cde657901	1179	ETH_DMATransmissionDisable(heth);
mbed_official	87:085cde657901	1180
mbed_official	87:085cde657901	1181	/* Stop DMA reception */
mbed_official	87:085cde657901	1182	ETH_DMAReceptionDisable(heth);
mbed_official	87:085cde657901	1183
mbed_official	87:085cde657901	1184	/* Disable receive state machine of the MAC for reception from the MII */
mbed_official	87:085cde657901	1185	ETH_MACReceptionDisable(heth);
mbed_official	87:085cde657901	1186
mbed_official	87:085cde657901	1187	/* Flush Transmit FIFO */
mbed_official	87:085cde657901	1188	ETH_FlushTransmitFIFO(heth);
mbed_official	87:085cde657901	1189
mbed_official	87:085cde657901	1190	/* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official	87:085cde657901	1191	ETH_MACTransmissionDisable(heth);
mbed_official	87:085cde657901	1192
mbed_official	87:085cde657901	1193	/* Set the ETH state*/
mbed_official	87:085cde657901	1194	heth->State = HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1195
mbed_official	87:085cde657901	1196	/* Process Unlocked */
mbed_official	87:085cde657901	1197	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	1198
mbed_official	87:085cde657901	1199	/* Return function status */
mbed_official	87:085cde657901	1200	return HAL_OK;
mbed_official	87:085cde657901	1201	}
mbed_official	87:085cde657901	1202
mbed_official	87:085cde657901	1203	/**
mbed_official	87:085cde657901	1204	* @brief Set ETH MAC Configuration.
mbed_official	87:085cde657901	1205	* @param heth: ETH handle
mbed_official	87:085cde657901	1206	* @param macconf: MAC Configuration structure
mbed_official	87:085cde657901	1207	* @retval HAL status
mbed_official	87:085cde657901	1208	*/
mbed_official	87:085cde657901	1209	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf)
mbed_official	87:085cde657901	1210	{
mbed_official	87:085cde657901	1211	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1212
mbed_official	87:085cde657901	1213	/* Process Locked */
mbed_official	87:085cde657901	1214	__HAL_LOCK(heth);
mbed_official	87:085cde657901	1215
mbed_official	87:085cde657901	1216	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	1217	heth->State= HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	1218
mbed_official	87:085cde657901	1219	assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official	87:085cde657901	1220	assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official	87:085cde657901	1221
mbed_official	87:085cde657901	1222	if (macconf != NULL)
mbed_official	87:085cde657901	1223	{
mbed_official	87:085cde657901	1224	/* Check the parameters */
mbed_official	87:085cde657901	1225	assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official	87:085cde657901	1226	assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official	87:085cde657901	1227	assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official	87:085cde657901	1228	assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official	87:085cde657901	1229	assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official	87:085cde657901	1230	assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official	87:085cde657901	1231	assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official	87:085cde657901	1232	assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official	87:085cde657901	1233	assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official	87:085cde657901	1234	assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official	87:085cde657901	1235	assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official	87:085cde657901	1236	assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official	87:085cde657901	1237	assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official	87:085cde657901	1238	assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official	87:085cde657901	1239	assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official	87:085cde657901	1240	assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official	87:085cde657901	1241	assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official	87:085cde657901	1242	assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official	87:085cde657901	1243	assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official	87:085cde657901	1244	assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official	87:085cde657901	1245	assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official	87:085cde657901	1246	assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official	87:085cde657901	1247	assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official	87:085cde657901	1248	assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official	87:085cde657901	1249	assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official	87:085cde657901	1250	assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official	87:085cde657901	1251	assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official	87:085cde657901	1252
mbed_official	87:085cde657901	1253	/------------------------ ETHERNET MACCR Configuration --------------------/
mbed_official	87:085cde657901	1254	/* Get the ETHERNET MACCR value */
mbed_official	87:085cde657901	1255	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1256	/* Clear WD, PCE, PS, TE and RE bits */
mbed_official	87:085cde657901	1257	tmpreg &= MACCR_CLEAR_MASK;
mbed_official	87:085cde657901	1258
mbed_official	87:085cde657901	1259	tmpreg \|= (uint32_t)(macconf->Watchdog \|
mbed_official	87:085cde657901	1260	macconf->Jabber \|
mbed_official	87:085cde657901	1261	macconf->InterFrameGap \|
mbed_official	87:085cde657901	1262	macconf->CarrierSense \|
mbed_official	87:085cde657901	1263	(heth->Init).Speed \|
mbed_official	87:085cde657901	1264	macconf->ReceiveOwn \|
mbed_official	87:085cde657901	1265	macconf->LoopbackMode \|
mbed_official	87:085cde657901	1266	(heth->Init).DuplexMode \|
mbed_official	87:085cde657901	1267	macconf->ChecksumOffload \|
mbed_official	87:085cde657901	1268	macconf->RetryTransmission \|
mbed_official	87:085cde657901	1269	macconf->AutomaticPadCRCStrip \|
mbed_official	87:085cde657901	1270	macconf->BackOffLimit \|
mbed_official	87:085cde657901	1271	macconf->DeferralCheck);
mbed_official	87:085cde657901	1272
mbed_official	87:085cde657901	1273	/* Write to ETHERNET MACCR */
mbed_official	87:085cde657901	1274	(heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1275
mbed_official	87:085cde657901	1276	/* Wait until the write operation will be taken into account :
mbed_official	87:085cde657901	1277	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1278	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1279	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1280	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1281
mbed_official	87:085cde657901	1282	/----------------------- ETHERNET MACFFR Configuration --------------------/
mbed_official	87:085cde657901	1283	/* Write to ETHERNET MACFFR */
mbed_official	87:085cde657901	1284	(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll \|
mbed_official	87:085cde657901	1285	macconf->SourceAddrFilter \|
mbed_official	87:085cde657901	1286	macconf->PassControlFrames \|
mbed_official	87:085cde657901	1287	macconf->BroadcastFramesReception \|
mbed_official	87:085cde657901	1288	macconf->DestinationAddrFilter \|
mbed_official	87:085cde657901	1289	macconf->PromiscuousMode \|
mbed_official	87:085cde657901	1290	macconf->MulticastFramesFilter \|
mbed_official	87:085cde657901	1291	macconf->UnicastFramesFilter);
mbed_official	87:085cde657901	1292
mbed_official	87:085cde657901	1293	/* Wait until the write operation will be taken into account :
mbed_official	87:085cde657901	1294	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1295	tmpreg = (heth->Instance)->MACFFR;
mbed_official	87:085cde657901	1296	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1297	(heth->Instance)->MACFFR = tmpreg;
mbed_official	87:085cde657901	1298
mbed_official	87:085cde657901	1299	/--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------/
mbed_official	87:085cde657901	1300	/* Write to ETHERNET MACHTHR */
mbed_official	87:085cde657901	1301	(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official	87:085cde657901	1302
mbed_official	87:085cde657901	1303	/* Write to ETHERNET MACHTLR */
mbed_official	87:085cde657901	1304	(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official	87:085cde657901	1305	/----------------------- ETHERNET MACFCR Configuration --------------------/
mbed_official	87:085cde657901	1306
mbed_official	87:085cde657901	1307	/* Get the ETHERNET MACFCR value */
mbed_official	87:085cde657901	1308	tmpreg = (heth->Instance)->MACFCR;
mbed_official	87:085cde657901	1309	/* Clear xx bits */
mbed_official	87:085cde657901	1310	tmpreg &= MACFCR_CLEAR_MASK;
mbed_official	87:085cde657901	1311
mbed_official	87:085cde657901	1312	tmpreg \|= (uint32_t)((macconf->PauseTime << 16) \|
mbed_official	87:085cde657901	1313	macconf->ZeroQuantaPause \|
mbed_official	87:085cde657901	1314	macconf->PauseLowThreshold \|
mbed_official	87:085cde657901	1315	macconf->UnicastPauseFrameDetect \|
mbed_official	87:085cde657901	1316	macconf->ReceiveFlowControl \|
mbed_official	87:085cde657901	1317	macconf->TransmitFlowControl);
mbed_official	87:085cde657901	1318
mbed_official	87:085cde657901	1319	/* Write to ETHERNET MACFCR */
mbed_official	87:085cde657901	1320	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1321
mbed_official	87:085cde657901	1322	/* Wait until the write operation will be taken into account :
mbed_official	87:085cde657901	1323	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1324	tmpreg = (heth->Instance)->MACFCR;
mbed_official	87:085cde657901	1325	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1326	(heth->Instance)->MACFCR = tmpreg;
mbed_official	87:085cde657901	1327
mbed_official	87:085cde657901	1328	/----------------------- ETHERNET MACVLANTR Configuration -----------------/
mbed_official	87:085cde657901	1329	(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison \|
mbed_official	87:085cde657901	1330	macconf->VLANTagIdentifier);
mbed_official	87:085cde657901	1331
mbed_official	87:085cde657901	1332	/* Wait until the write operation will be taken into account :
mbed_official	87:085cde657901	1333	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1334	tmpreg = (heth->Instance)->MACVLANTR;
mbed_official	87:085cde657901	1335	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1336	(heth->Instance)->MACVLANTR = tmpreg;
mbed_official	87:085cde657901	1337	}
mbed_official	87:085cde657901	1338	else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official	87:085cde657901	1339	{
mbed_official	87:085cde657901	1340	/------------------------ ETHERNET MACCR Configuration --------------------/
mbed_official	87:085cde657901	1341	/* Get the ETHERNET MACCR value */
mbed_official	87:085cde657901	1342	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1343
mbed_official	87:085cde657901	1344	/* Clear FES and DM bits */
mbed_official	87:085cde657901	1345	tmpreg &= ~((uint32_t)0x00004800);
mbed_official	87:085cde657901	1346
mbed_official	87:085cde657901	1347	tmpreg \|= (uint32_t)(heth->Init.Speed \| heth->Init.DuplexMode);
mbed_official	87:085cde657901	1348
mbed_official	87:085cde657901	1349	/* Write to ETHERNET MACCR */
mbed_official	87:085cde657901	1350	(heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1351
mbed_official	87:085cde657901	1352	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1353	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1354	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1355	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1356	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1357	}
mbed_official	87:085cde657901	1358
mbed_official	87:085cde657901	1359	/* Set the ETH state to Ready */
mbed_official	87:085cde657901	1360	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1361
mbed_official	87:085cde657901	1362	/* Process Unlocked */
mbed_official	87:085cde657901	1363	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	1364
mbed_official	87:085cde657901	1365	/* Return function status */
mbed_official	87:085cde657901	1366	return HAL_OK;
mbed_official	87:085cde657901	1367	}
mbed_official	87:085cde657901	1368
mbed_official	87:085cde657901	1369	/**
mbed_official	87:085cde657901	1370	* @brief Sets ETH DMA Configuration.
mbed_official	87:085cde657901	1371	* @param heth: ETH handle
mbed_official	87:085cde657901	1372	* @param dmaconf: DMA Configuration structure
mbed_official	87:085cde657901	1373	* @retval HAL status
mbed_official	87:085cde657901	1374	*/
mbed_official	87:085cde657901	1375	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf)
mbed_official	87:085cde657901	1376	{
mbed_official	87:085cde657901	1377	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1378
mbed_official	87:085cde657901	1379	/* Process Locked */
mbed_official	87:085cde657901	1380	__HAL_LOCK(heth);
mbed_official	87:085cde657901	1381
mbed_official	87:085cde657901	1382	/* Set the ETH peripheral state to BUSY */
mbed_official	87:085cde657901	1383	heth->State= HAL_ETH_STATE_BUSY;
mbed_official	87:085cde657901	1384
mbed_official	87:085cde657901	1385	/* Check parameters */
mbed_official	87:085cde657901	1386	assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official	87:085cde657901	1387	assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official	87:085cde657901	1388	assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official	87:085cde657901	1389	assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official	87:085cde657901	1390	assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official	87:085cde657901	1391	assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official	87:085cde657901	1392	assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official	87:085cde657901	1393	assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official	87:085cde657901	1394	assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official	87:085cde657901	1395	assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official	87:085cde657901	1396	assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official	87:085cde657901	1397	assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official	87:085cde657901	1398	assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official	87:085cde657901	1399	assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official	87:085cde657901	1400	assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official	87:085cde657901	1401	assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official	87:085cde657901	1402
mbed_official	87:085cde657901	1403	/----------------------- ETHERNET DMAOMR Configuration --------------------/
mbed_official	87:085cde657901	1404	/* Get the ETHERNET DMAOMR value */
mbed_official	87:085cde657901	1405	tmpreg = (heth->Instance)->DMAOMR;
mbed_official	87:085cde657901	1406	/* Clear xx bits */
mbed_official	87:085cde657901	1407	tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official	87:085cde657901	1408
mbed_official	87:085cde657901	1409	tmpreg \|= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame \|
mbed_official	87:085cde657901	1410	dmaconf->ReceiveStoreForward \|
mbed_official	87:085cde657901	1411	dmaconf->FlushReceivedFrame \|
mbed_official	87:085cde657901	1412	dmaconf->TransmitStoreForward \|
mbed_official	87:085cde657901	1413	dmaconf->TransmitThresholdControl \|
mbed_official	87:085cde657901	1414	dmaconf->ForwardErrorFrames \|
mbed_official	87:085cde657901	1415	dmaconf->ForwardUndersizedGoodFrames \|
mbed_official	87:085cde657901	1416	dmaconf->ReceiveThresholdControl \|
mbed_official	87:085cde657901	1417	dmaconf->SecondFrameOperate);
mbed_official	87:085cde657901	1418
mbed_official	87:085cde657901	1419	/* Write to ETHERNET DMAOMR */
mbed_official	87:085cde657901	1420	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1421
mbed_official	87:085cde657901	1422	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1423	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1424	tmpreg = (heth->Instance)->DMAOMR;
mbed_official	87:085cde657901	1425	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1426	(heth->Instance)->DMAOMR = tmpreg;
mbed_official	87:085cde657901	1427
mbed_official	87:085cde657901	1428	/----------------------- ETHERNET DMABMR Configuration --------------------/
mbed_official	87:085cde657901	1429	(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats \|
mbed_official	87:085cde657901	1430	dmaconf->FixedBurst \|
mbed_official	87:085cde657901	1431	dmaconf->RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official	87:085cde657901	1432	dmaconf->TxDMABurstLength \|
mbed_official	87:085cde657901	1433	dmaconf->EnhancedDescriptorFormat \|
mbed_official	87:085cde657901	1434	(dmaconf->DescriptorSkipLength << 2) \|
mbed_official	87:085cde657901	1435	dmaconf->DMAArbitration \|
mbed_official	87:085cde657901	1436	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official	87:085cde657901	1437
mbed_official	87:085cde657901	1438	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1439	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1440	tmpreg = (heth->Instance)->DMABMR;
mbed_official	87:085cde657901	1441	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1442	(heth->Instance)->DMABMR = tmpreg;
mbed_official	87:085cde657901	1443
mbed_official	87:085cde657901	1444	/* Set the ETH state to Ready */
mbed_official	87:085cde657901	1445	heth->State= HAL_ETH_STATE_READY;
mbed_official	87:085cde657901	1446
mbed_official	87:085cde657901	1447	/* Process Unlocked */
mbed_official	87:085cde657901	1448	__HAL_UNLOCK(heth);
mbed_official	87:085cde657901	1449
mbed_official	87:085cde657901	1450	/* Return function status */
mbed_official	87:085cde657901	1451	return HAL_OK;
mbed_official	87:085cde657901	1452	}
mbed_official	87:085cde657901	1453
mbed_official	87:085cde657901	1454	/**
mbed_official	87:085cde657901	1455	* @}
mbed_official	87:085cde657901	1456	*/
mbed_official	87:085cde657901	1457
mbed_official	87:085cde657901	1458	/** @defgroup ETH_Group4 Peripheral State functions
mbed_official	87:085cde657901	1459	* @brief Peripheral State functions
mbed_official	87:085cde657901	1460	*
mbed_official	87:085cde657901	1461	@verbatim
mbed_official	87:085cde657901	1462	===============================================================================
mbed_official	87:085cde657901	1463	##### Peripheral State functions #####
mbed_official	87:085cde657901	1464	===============================================================================
mbed_official	87:085cde657901	1465	[..]
mbed_official	87:085cde657901	1466	This subsection permits to get in run-time the status of the peripheral
mbed_official	87:085cde657901	1467	and the data flow.
mbed_official	87:085cde657901	1468	(+) Get the ETH handle state:
mbed_official	87:085cde657901	1469	HAL_ETH_GetState();
mbed_official	87:085cde657901	1470
mbed_official	87:085cde657901	1471
mbed_official	87:085cde657901	1472	@endverbatim
mbed_official	87:085cde657901	1473	* @{
mbed_official	87:085cde657901	1474	*/
mbed_official	87:085cde657901	1475
mbed_official	87:085cde657901	1476	/**
mbed_official	87:085cde657901	1477	* @brief Return the ETH HAL state
mbed_official	87:085cde657901	1478	* @param heth: ETH handle
mbed_official	87:085cde657901	1479	* @retval HAL state
mbed_official	87:085cde657901	1480	*/
mbed_official	87:085cde657901	1481	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1482	{
mbed_official	87:085cde657901	1483	/* Return ETH state */
mbed_official	87:085cde657901	1484	return heth->State;
mbed_official	87:085cde657901	1485	}
mbed_official	87:085cde657901	1486
mbed_official	87:085cde657901	1487	/**
mbed_official	87:085cde657901	1488	* @}
mbed_official	87:085cde657901	1489	*/
mbed_official	87:085cde657901	1490
mbed_official	87:085cde657901	1491	/**
mbed_official	87:085cde657901	1492	* @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official	87:085cde657901	1493	* @param heth: ETH handle
mbed_official	87:085cde657901	1494	* @param err: Ethernet Init error
mbed_official	87:085cde657901	1495	* @retval HAL status
mbed_official	87:085cde657901	1496	*/
mbed_official	87:085cde657901	1497	static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official	87:085cde657901	1498	{
mbed_official	87:085cde657901	1499	ETH_MACInitTypeDef macinit;
mbed_official	87:085cde657901	1500	ETH_DMAInitTypeDef dmainit;
mbed_official	87:085cde657901	1501	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1502
mbed_official	87:085cde657901	1503	if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official	87:085cde657901	1504	{
mbed_official	87:085cde657901	1505	/* Set Ethernet duplex mode to Full-duplex */
mbed_official	87:085cde657901	1506	(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official	87:085cde657901	1507
mbed_official	87:085cde657901	1508	/* Set Ethernet speed to 100M */
mbed_official	87:085cde657901	1509	(heth->Init).Speed = ETH_SPEED_100M;
mbed_official	87:085cde657901	1510	}
mbed_official	87:085cde657901	1511
mbed_official	87:085cde657901	1512	/* Ethernet MAC default initialization **************************************/
mbed_official	87:085cde657901	1513	macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official	87:085cde657901	1514	macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official	87:085cde657901	1515	macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official	87:085cde657901	1516	macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official	87:085cde657901	1517	macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official	87:085cde657901	1518	macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official	87:085cde657901	1519	if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official	87:085cde657901	1520	{
mbed_official	87:085cde657901	1521	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official	87:085cde657901	1522	}
mbed_official	87:085cde657901	1523	else
mbed_official	87:085cde657901	1524	{
mbed_official	87:085cde657901	1525	macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official	87:085cde657901	1526	}
mbed_official	87:085cde657901	1527	macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official	87:085cde657901	1528	macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official	87:085cde657901	1529	macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official	87:085cde657901	1530	macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official	87:085cde657901	1531	macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official	87:085cde657901	1532	macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official	87:085cde657901	1533	macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official	87:085cde657901	1534	macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official	87:085cde657901	1535	macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official	87:085cde657901	1536	macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official	87:085cde657901	1537	macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official	87:085cde657901	1538	macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official	87:085cde657901	1539	macinit.HashTableHigh = 0x0;
mbed_official	87:085cde657901	1540	macinit.HashTableLow = 0x0;
mbed_official	87:085cde657901	1541	macinit.PauseTime = 0x0;
mbed_official	87:085cde657901	1542	macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official	87:085cde657901	1543	macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official	87:085cde657901	1544	macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official	87:085cde657901	1545	macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official	87:085cde657901	1546	macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official	87:085cde657901	1547	macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official	87:085cde657901	1548	macinit.VLANTagIdentifier = 0x0;
mbed_official	87:085cde657901	1549
mbed_official	87:085cde657901	1550	/------------------------ ETHERNET MACCR Configuration --------------------/
mbed_official	87:085cde657901	1551	/* Get the ETHERNET MACCR value */
mbed_official	87:085cde657901	1552	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1553	/* Clear WD, PCE, PS, TE and RE bits */
mbed_official	87:085cde657901	1554	tmpreg &= MACCR_CLEAR_MASK;
mbed_official	87:085cde657901	1555	/* Set the WD bit according to ETH Watchdog value */
mbed_official	87:085cde657901	1556	/* Set the JD: bit according to ETH Jabber value */
mbed_official	87:085cde657901	1557	/* Set the IFG bit according to ETH InterFrameGap value */
mbed_official	87:085cde657901	1558	/* Set the DCRS bit according to ETH CarrierSense value */
mbed_official	87:085cde657901	1559	/* Set the FES bit according to ETH Speed value */
mbed_official	87:085cde657901	1560	/* Set the DO bit according to ETH ReceiveOwn value */
mbed_official	87:085cde657901	1561	/* Set the LM bit according to ETH LoopbackMode value */
mbed_official	87:085cde657901	1562	/* Set the DM bit according to ETH Mode value */
mbed_official	87:085cde657901	1563	/* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official	87:085cde657901	1564	/* Set the DR bit according to ETH RetryTransmission value */
mbed_official	87:085cde657901	1565	/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official	87:085cde657901	1566	/* Set the BL bit according to ETH BackOffLimit value */
mbed_official	87:085cde657901	1567	/* Set the DC bit according to ETH DeferralCheck value */
mbed_official	87:085cde657901	1568	tmpreg \|= (uint32_t)(macinit.Watchdog \|
mbed_official	87:085cde657901	1569	macinit.Jabber \|
mbed_official	87:085cde657901	1570	macinit.InterFrameGap \|
mbed_official	87:085cde657901	1571	macinit.CarrierSense \|
mbed_official	87:085cde657901	1572	(heth->Init).Speed \|
mbed_official	87:085cde657901	1573	macinit.ReceiveOwn \|
mbed_official	87:085cde657901	1574	macinit.LoopbackMode \|
mbed_official	87:085cde657901	1575	(heth->Init).DuplexMode \|
mbed_official	87:085cde657901	1576	macinit.ChecksumOffload \|
mbed_official	87:085cde657901	1577	macinit.RetryTransmission \|
mbed_official	87:085cde657901	1578	macinit.AutomaticPadCRCStrip \|
mbed_official	87:085cde657901	1579	macinit.BackOffLimit \|
mbed_official	87:085cde657901	1580	macinit.DeferralCheck);
mbed_official	87:085cde657901	1581
mbed_official	87:085cde657901	1582	/* Write to ETHERNET MACCR */
mbed_official	87:085cde657901	1583	(heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1584
mbed_official	87:085cde657901	1585	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1586	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1587	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1588	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1589	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1590
mbed_official	87:085cde657901	1591	/----------------------- ETHERNET MACFFR Configuration --------------------/
mbed_official	87:085cde657901	1592	/* Set the RA bit according to ETH ReceiveAll value */
mbed_official	87:085cde657901	1593	/* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official	87:085cde657901	1594	/* Set the PCF bit according to ETH PassControlFrames value */
mbed_official	87:085cde657901	1595	/* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official	87:085cde657901	1596	/* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official	87:085cde657901	1597	/* Set the PR bit according to ETH PromiscuousMode value */
mbed_official	87:085cde657901	1598	/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official	87:085cde657901	1599	/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official	87:085cde657901	1600	/* Write to ETHERNET MACFFR */
mbed_official	87:085cde657901	1601	(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll \|
mbed_official	87:085cde657901	1602	macinit.SourceAddrFilter \|
mbed_official	87:085cde657901	1603	macinit.PassControlFrames \|
mbed_official	87:085cde657901	1604	macinit.BroadcastFramesReception \|
mbed_official	87:085cde657901	1605	macinit.DestinationAddrFilter \|
mbed_official	87:085cde657901	1606	macinit.PromiscuousMode \|
mbed_official	87:085cde657901	1607	macinit.MulticastFramesFilter \|
mbed_official	87:085cde657901	1608	macinit.UnicastFramesFilter);
mbed_official	87:085cde657901	1609
mbed_official	87:085cde657901	1610	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1611	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1612	tmpreg = (heth->Instance)->MACFFR;
mbed_official	87:085cde657901	1613	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1614	(heth->Instance)->MACFFR = tmpreg;
mbed_official	87:085cde657901	1615
mbed_official	87:085cde657901	1616	/--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------/
mbed_official	87:085cde657901	1617	/* Write to ETHERNET MACHTHR */
mbed_official	87:085cde657901	1618	(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official	87:085cde657901	1619
mbed_official	87:085cde657901	1620	/* Write to ETHERNET MACHTLR */
mbed_official	87:085cde657901	1621	(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official	87:085cde657901	1622	/----------------------- ETHERNET MACFCR Configuration -------------------/
mbed_official	87:085cde657901	1623
mbed_official	87:085cde657901	1624	/* Get the ETHERNET MACFCR value */
mbed_official	87:085cde657901	1625	tmpreg = (heth->Instance)->MACFCR;
mbed_official	87:085cde657901	1626	/* Clear xx bits */
mbed_official	87:085cde657901	1627	tmpreg &= MACFCR_CLEAR_MASK;
mbed_official	87:085cde657901	1628
mbed_official	87:085cde657901	1629	/* Set the PT bit according to ETH PauseTime value */
mbed_official	87:085cde657901	1630	/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official	87:085cde657901	1631	/* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official	87:085cde657901	1632	/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official	87:085cde657901	1633	/* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official	87:085cde657901	1634	/* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official	87:085cde657901	1635	tmpreg \|= (uint32_t)((macinit.PauseTime << 16) \|
mbed_official	87:085cde657901	1636	macinit.ZeroQuantaPause \|
mbed_official	87:085cde657901	1637	macinit.PauseLowThreshold \|
mbed_official	87:085cde657901	1638	macinit.UnicastPauseFrameDetect \|
mbed_official	87:085cde657901	1639	macinit.ReceiveFlowControl \|
mbed_official	87:085cde657901	1640	macinit.TransmitFlowControl);
mbed_official	87:085cde657901	1641
mbed_official	87:085cde657901	1642	/* Write to ETHERNET MACFCR */
mbed_official	87:085cde657901	1643	(heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1644
mbed_official	87:085cde657901	1645	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1646	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1647	tmpreg = (heth->Instance)->MACFCR;
mbed_official	87:085cde657901	1648	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1649	(heth->Instance)->MACFCR = tmpreg;
mbed_official	87:085cde657901	1650
mbed_official	87:085cde657901	1651	/----------------------- ETHERNET MACVLANTR Configuration ----------------/
mbed_official	87:085cde657901	1652	/* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official	87:085cde657901	1653	/* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official	87:085cde657901	1654	(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison \|
mbed_official	87:085cde657901	1655	macinit.VLANTagIdentifier);
mbed_official	87:085cde657901	1656
mbed_official	87:085cde657901	1657	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1658	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1659	tmpreg = (heth->Instance)->MACVLANTR;
mbed_official	87:085cde657901	1660	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1661	(heth->Instance)->MACVLANTR = tmpreg;
mbed_official	87:085cde657901	1662
mbed_official	87:085cde657901	1663	/* Ethernet DMA default initialization ************************************/
mbed_official	87:085cde657901	1664	dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official	87:085cde657901	1665	dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official	87:085cde657901	1666	dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official	87:085cde657901	1667	dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official	87:085cde657901	1668	dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official	87:085cde657901	1669	dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official	87:085cde657901	1670	dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official	87:085cde657901	1671	dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official	87:085cde657901	1672	dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official	87:085cde657901	1673	dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official	87:085cde657901	1674	dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official	87:085cde657901	1675	dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official	87:085cde657901	1676	dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official	87:085cde657901	1677	dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official	87:085cde657901	1678	dmainit.DescriptorSkipLength = 0x0;
mbed_official	87:085cde657901	1679	dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official	87:085cde657901	1680
mbed_official	87:085cde657901	1681	/* Get the ETHERNET DMAOMR value */
mbed_official	87:085cde657901	1682	tmpreg = (heth->Instance)->DMAOMR;
mbed_official	87:085cde657901	1683	/* Clear xx bits */
mbed_official	87:085cde657901	1684	tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official	87:085cde657901	1685
mbed_official	87:085cde657901	1686	/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official	87:085cde657901	1687	/* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official	87:085cde657901	1688	/* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official	87:085cde657901	1689	/* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official	87:085cde657901	1690	/* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official	87:085cde657901	1691	/* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official	87:085cde657901	1692	/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official	87:085cde657901	1693	/* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official	87:085cde657901	1694	/* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official	87:085cde657901	1695	tmpreg \|= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame \|
mbed_official	87:085cde657901	1696	dmainit.ReceiveStoreForward \|
mbed_official	87:085cde657901	1697	dmainit.FlushReceivedFrame \|
mbed_official	87:085cde657901	1698	dmainit.TransmitStoreForward \|
mbed_official	87:085cde657901	1699	dmainit.TransmitThresholdControl \|
mbed_official	87:085cde657901	1700	dmainit.ForwardErrorFrames \|
mbed_official	87:085cde657901	1701	dmainit.ForwardUndersizedGoodFrames \|
mbed_official	87:085cde657901	1702	dmainit.ReceiveThresholdControl \|
mbed_official	87:085cde657901	1703	dmainit.SecondFrameOperate);
mbed_official	87:085cde657901	1704
mbed_official	87:085cde657901	1705	/* Write to ETHERNET DMAOMR */
mbed_official	87:085cde657901	1706	(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official	87:085cde657901	1707
mbed_official	87:085cde657901	1708	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1709	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1710	tmpreg = (heth->Instance)->DMAOMR;
mbed_official	87:085cde657901	1711	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1712	(heth->Instance)->DMAOMR = tmpreg;
mbed_official	87:085cde657901	1713
mbed_official	87:085cde657901	1714	/----------------------- ETHERNET DMABMR Configuration ------------------/
mbed_official	87:085cde657901	1715	/* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official	87:085cde657901	1716	/* Set the FB bit according to ETH FixedBurst value */
mbed_official	87:085cde657901	1717	/* Set the RPBL and 4PBL bits according to ETH RxDMABurstLength value /
mbed_official	87:085cde657901	1718	/* Set the PBL and 4PBL bits according to ETH TxDMABurstLength value /
mbed_official	87:085cde657901	1719	/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official	87:085cde657901	1720	/* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official	87:085cde657901	1721	/* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official	87:085cde657901	1722	(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats \|
mbed_official	87:085cde657901	1723	dmainit.FixedBurst \|
mbed_official	87:085cde657901	1724	dmainit.RxDMABurstLength \| /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official	87:085cde657901	1725	dmainit.TxDMABurstLength \|
mbed_official	87:085cde657901	1726	dmainit.EnhancedDescriptorFormat \|
mbed_official	87:085cde657901	1727	(dmainit.DescriptorSkipLength << 2) \|
mbed_official	87:085cde657901	1728	dmainit.DMAArbitration \|
mbed_official	87:085cde657901	1729	ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official	87:085cde657901	1730
mbed_official	87:085cde657901	1731	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1732	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1733	tmpreg = (heth->Instance)->DMABMR;
mbed_official	87:085cde657901	1734	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1735	(heth->Instance)->DMABMR = tmpreg;
mbed_official	87:085cde657901	1736
mbed_official	87:085cde657901	1737	if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official	87:085cde657901	1738	{
mbed_official	87:085cde657901	1739	/* Enable the Ethernet Rx Interrupt */
mbed_official	87:085cde657901	1740	__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS \| ETH_DMA_IT_R);
mbed_official	87:085cde657901	1741	}
mbed_official	87:085cde657901	1742
mbed_official	87:085cde657901	1743	/* Initialize MAC address in ethernet MAC */
mbed_official	87:085cde657901	1744	ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official	87:085cde657901	1745	}
mbed_official	87:085cde657901	1746
mbed_official	87:085cde657901	1747	/**
mbed_official	87:085cde657901	1748	* @brief Configures the selected MAC address.
mbed_official	87:085cde657901	1749	* @param heth: ETH handle
mbed_official	87:085cde657901	1750	* @param MacAddr: The MAC address to configure
mbed_official	87:085cde657901	1751	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1752	* @arg ETH_MAC_Address0: MAC Address0
mbed_official	87:085cde657901	1753	* @arg ETH_MAC_Address1: MAC Address1
mbed_official	87:085cde657901	1754	* @arg ETH_MAC_Address2: MAC Address2
mbed_official	87:085cde657901	1755	* @arg ETH_MAC_Address3: MAC Address3
mbed_official	87:085cde657901	1756	* @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official	87:085cde657901	1757	* @retval HAL status
mbed_official	87:085cde657901	1758	*/
mbed_official	87:085cde657901	1759	static void ETH_MACAddressConfig(ETH_HandleTypeDef heth, uint32_t MacAddr, uint8_t Addr)
mbed_official	87:085cde657901	1760	{
mbed_official	87:085cde657901	1761	uint32_t tmpreg;
mbed_official	87:085cde657901	1762
mbed_official	87:085cde657901	1763	/* Check the parameters */
mbed_official	87:085cde657901	1764	assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official	87:085cde657901	1765
mbed_official	87:085cde657901	1766	/* Calculate the selected MAC address high register */
mbed_official	87:085cde657901	1767	tmpreg = ((uint32_t)Addr[5] << 8) \| (uint32_t)Addr[4];
mbed_official	87:085cde657901	1768	/* Load the selected MAC address high register */
mbed_official	87:085cde657901	1769	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official	87:085cde657901	1770	/* Calculate the selected MAC address low register */
mbed_official	87:085cde657901	1771	tmpreg = ((uint32_t)Addr[3] << 24) \| ((uint32_t)Addr[2] << 16) \| ((uint32_t)Addr[1] << 8) \| Addr[0];
mbed_official	87:085cde657901	1772
mbed_official	87:085cde657901	1773	/* Load the selected MAC address low register */
mbed_official	87:085cde657901	1774	((__IO uint32_t )((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official	87:085cde657901	1775	}
mbed_official	87:085cde657901	1776
mbed_official	87:085cde657901	1777	/**
mbed_official	87:085cde657901	1778	* @brief Enables the MAC transmission.
mbed_official	87:085cde657901	1779	* @param heth: ETH handle
mbed_official	87:085cde657901	1780	* @retval None
mbed_official	87:085cde657901	1781	*/
mbed_official	87:085cde657901	1782	static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1783	{
mbed_official	87:085cde657901	1784	__IO uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1785
mbed_official	87:085cde657901	1786	/* Enable the MAC transmission */
mbed_official	87:085cde657901	1787	(heth->Instance)->MACCR \|= ETH_MACCR_TE;
mbed_official	87:085cde657901	1788
mbed_official	87:085cde657901	1789	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1790	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1791	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1792	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1793	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1794	}
mbed_official	87:085cde657901	1795
mbed_official	87:085cde657901	1796	/**
mbed_official	87:085cde657901	1797	* @brief Disables the MAC transmission.
mbed_official	87:085cde657901	1798	* @param heth: ETH handle
mbed_official	87:085cde657901	1799	* @retval None
mbed_official	87:085cde657901	1800	*/
mbed_official	87:085cde657901	1801	static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1802	{
mbed_official	87:085cde657901	1803	__IO uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1804
mbed_official	87:085cde657901	1805	/* Disable the MAC transmission */
mbed_official	87:085cde657901	1806	(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official	87:085cde657901	1807
mbed_official	87:085cde657901	1808	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1809	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1810	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1811	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1812	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1813	}
mbed_official	87:085cde657901	1814
mbed_official	87:085cde657901	1815	/**
mbed_official	87:085cde657901	1816	* @brief Enables the MAC reception.
mbed_official	87:085cde657901	1817	* @param heth: ETH handle
mbed_official	87:085cde657901	1818	* @retval None
mbed_official	87:085cde657901	1819	*/
mbed_official	87:085cde657901	1820	static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1821	{
mbed_official	87:085cde657901	1822	__IO uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1823
mbed_official	87:085cde657901	1824	/* Enable the MAC reception */
mbed_official	87:085cde657901	1825	(heth->Instance)->MACCR \|= ETH_MACCR_RE;
mbed_official	87:085cde657901	1826
mbed_official	87:085cde657901	1827	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1828	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1829	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1830	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1831	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1832	}
mbed_official	87:085cde657901	1833
mbed_official	87:085cde657901	1834	/**
mbed_official	87:085cde657901	1835	* @brief Disables the MAC reception.
mbed_official	87:085cde657901	1836	* @param heth: ETH handle
mbed_official	87:085cde657901	1837	* @retval None
mbed_official	87:085cde657901	1838	*/
mbed_official	87:085cde657901	1839	static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1840	{
mbed_official	87:085cde657901	1841	__IO uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1842
mbed_official	87:085cde657901	1843	/* Disable the MAC reception */
mbed_official	87:085cde657901	1844	(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official	87:085cde657901	1845
mbed_official	87:085cde657901	1846	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1847	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1848	tmpreg = (heth->Instance)->MACCR;
mbed_official	87:085cde657901	1849	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1850	(heth->Instance)->MACCR = tmpreg;
mbed_official	87:085cde657901	1851	}
mbed_official	87:085cde657901	1852
mbed_official	87:085cde657901	1853	/**
mbed_official	87:085cde657901	1854	* @brief Enables the DMA transmission.
mbed_official	87:085cde657901	1855	* @param heth: ETH handle
mbed_official	87:085cde657901	1856	* @retval None
mbed_official	87:085cde657901	1857	*/
mbed_official	87:085cde657901	1858	static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1859	{
mbed_official	87:085cde657901	1860	/* Enable the DMA transmission */
mbed_official	87:085cde657901	1861	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_ST;
mbed_official	87:085cde657901	1862	}
mbed_official	87:085cde657901	1863
mbed_official	87:085cde657901	1864	/**
mbed_official	87:085cde657901	1865	* @brief Disables the DMA transmission.
mbed_official	87:085cde657901	1866	* @param heth: ETH handle
mbed_official	87:085cde657901	1867	* @retval None
mbed_official	87:085cde657901	1868	*/
mbed_official	87:085cde657901	1869	static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1870	{
mbed_official	87:085cde657901	1871	/* Disable the DMA transmission */
mbed_official	87:085cde657901	1872	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official	87:085cde657901	1873	}
mbed_official	87:085cde657901	1874
mbed_official	87:085cde657901	1875	/**
mbed_official	87:085cde657901	1876	* @brief Enables the DMA reception.
mbed_official	87:085cde657901	1877	* @param heth: ETH handle
mbed_official	87:085cde657901	1878	* @retval None
mbed_official	87:085cde657901	1879	*/
mbed_official	87:085cde657901	1880	static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1881	{
mbed_official	87:085cde657901	1882	/* Enable the DMA reception */
mbed_official	87:085cde657901	1883	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_SR;
mbed_official	87:085cde657901	1884	}
mbed_official	87:085cde657901	1885
mbed_official	87:085cde657901	1886	/**
mbed_official	87:085cde657901	1887	* @brief Disables the DMA reception.
mbed_official	87:085cde657901	1888	* @param heth: ETH handle
mbed_official	87:085cde657901	1889	* @retval None
mbed_official	87:085cde657901	1890	*/
mbed_official	87:085cde657901	1891	static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1892	{
mbed_official	87:085cde657901	1893	/* Disable the DMA reception */
mbed_official	87:085cde657901	1894	(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official	87:085cde657901	1895	}
mbed_official	87:085cde657901	1896
mbed_official	87:085cde657901	1897	/**
mbed_official	87:085cde657901	1898	* @brief Clears the ETHERNET transmit FIFO.
mbed_official	87:085cde657901	1899	* @param heth: ETH handle
mbed_official	87:085cde657901	1900	* @retval None
mbed_official	87:085cde657901	1901	*/
mbed_official	87:085cde657901	1902	static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official	87:085cde657901	1903	{
mbed_official	87:085cde657901	1904	__IO uint32_t tmpreg = 0;
mbed_official	87:085cde657901	1905
mbed_official	87:085cde657901	1906	/* Set the Flush Transmit FIFO bit */
mbed_official	87:085cde657901	1907	(heth->Instance)->DMAOMR \|= ETH_DMAOMR_FTF;
mbed_official	87:085cde657901	1908
mbed_official	87:085cde657901	1909	/* Wait until the write operation will be taken into account:
mbed_official	87:085cde657901	1910	at least four TX_CLK/RX_CLK clock cycles */
mbed_official	87:085cde657901	1911	tmpreg = (heth->Instance)->DMAOMR;
mbed_official	87:085cde657901	1912	HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official	87:085cde657901	1913	(heth->Instance)->DMAOMR = tmpreg;
mbed_official	87:085cde657901	1914	}
mbed_official	87:085cde657901	1915
mbed_official	87:085cde657901	1916	/**
mbed_official	87:085cde657901	1917	* @}
mbed_official	87:085cde657901	1918	*/
mbed_official	87:085cde657901	1919
mbed_official	87:085cde657901	1920	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	87:085cde657901	1921	#endif /* HAL_ETH_MODULE_ENABLED */
mbed_official	87:085cde657901	1922	/**
mbed_official	87:085cde657901	1923	* @}
mbed_official	87:085cde657901	1924	*/
mbed_official	87:085cde657901	1925
mbed_official	87:085cde657901	1926	/**
mbed_official	87:085cde657901	1927	* @}
mbed_official	87:085cde657901	1928	*/
mbed_official	87:085cde657901	1929
mbed_official	87:085cde657901	1930	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Sep 2014
Imports:	4
Forks:	0
Commits:	324
Dependents:	1
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c@87:085cde657901, 2014-02-08 (annotated)

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