shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/aes_map.h@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
149:156823d33999 
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file aes_map.h
<> 144:ef7eb2e8f9f7 4 * @brief AES HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev: 2110 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup aes
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 * <p>
<> 144:ef7eb2e8f9f7 31 * AES HW register map description
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 36 #pragma anon_unions
<> 144:ef7eb2e8f9f7 37 #endif
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef AES_MAP_H_
<> 144:ef7eb2e8f9f7 40 #define AES_MAP_H_
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #include "architecture.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** AES Encryption HW Structure Overlay */
<> 144:ef7eb2e8f9f7 45 typedef struct {
<> 144:ef7eb2e8f9f7 46 __IO uint32_t KEY0; /**< Bits[31:00] of the 128-bit key */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t KEY1; /**< Bits[63:32] of the 128-bit key */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t KEY2; /**< Bits[95:64] of the 128-bit key */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t KEY3; /**< Bits[127:96] of the 128-bit key */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t KEY4; /**< Bits[159:128] of the 256-bit key */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t KEY5; /**< Bits[191:160] of the 256-bit key */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t KEY6; /**< Bits[223:192] of the 256-bit key */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t KEY7; /**< Bits[255:224] of the 256-bit key */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 __IO uint32_t CNTi0; /**< Bits[31:00] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t CNTi1; /**< Bits[63:32] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t CNTi2; /**< Bits[95:64] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t CNTi3; /**< Bits[127:96] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 59 __I uint32_t CNTo0; /**< Bits[31:00] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 60 __I uint32_t CNTo1; /**< Bits[63:32] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 61 __I uint32_t CNTo2; /**< Bits[95:64] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 62 __I uint32_t CNTo3; /**< Bits[127:96] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 __I uint32_t CBCo0; /**< Bits[31:00] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 65 __I uint32_t CBCo1; /**< Bits[63:32] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 66 __I uint32_t CBCo2; /**< Bits[95:64] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 67 __I uint32_t CBCo3; /**< Bits[127:96] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 68 union {
<> 144:ef7eb2e8f9f7 69 struct {
<> 153:fa9ff456f731 70 __IO uint32_t START:1; /**< start the encryption : 0 = no-effect , 1 = enable */
<> 153:fa9ff456f731 71 __IO uint32_t ACC_CLR:1; /**< Clear the CBC accumulator : 0 = no-effect 1 = clears the CBC accumulator */
<> 153:fa9ff456f731 72 __IO uint32_t INT_CLEAR:1; /**< interrupt clear : 0 = no-effect 1 = clear the interrupt */
<> 144:ef7eb2e8f9f7 73 } BITS;
<> 153:fa9ff456f731 74 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 75 } CTL;
<> 144:ef7eb2e8f9f7 76 union {
<> 144:ef7eb2e8f9f7 77 struct {
<> 144:ef7eb2e8f9f7 78 __IO uint32_t CBC_MODE:1; /**< counter mode : 0 = counter mode , 1 = CBC mode */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t BYPASS:1; /**< encryption : 0 = Normal Mode , 1 = Bypasss any encryption */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t INT_EN:1; /**< interrupt mask : 0 = disabled 1 = enabled */
<> 153:fa9ff456f731 81 __IO uint32_t KEY_LENGTH:1; /**< Key Length: 0 = 128 Bit Encryption 1 = 256 Bit Encryption */
<> 153:fa9ff456f731 82
<> 144:ef7eb2e8f9f7 83 } BITS;
<> 144:ef7eb2e8f9f7 84 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 85 } MODE;
<> 144:ef7eb2e8f9f7 86 union {
<> 144:ef7eb2e8f9f7 87 struct {
<> 144:ef7eb2e8f9f7 88 __I uint32_t COMPLETE:1;/**< status : 0 = not complete , 1 = complete */
<> 144:ef7eb2e8f9f7 89 } BITS;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 91 } STAT;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 __O uint32_t MAC_INIT0; /**< Bits[31:00] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 94 __O uint32_t MAC_INIT1; /**< Bits[63:32] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 95 __O uint32_t MAC_INIT2; /**< Bits[95:64] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 96 __O uint32_t MAC_INIT3; /**< Bits[127:96] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 __IO uint32_t RESERVED;
<> 144:ef7eb2e8f9f7 99 __O uint32_t DATA0; /**< Bits[31:00] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 100 __O uint32_t DATA1; /**< Bits[63:32] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 101 __O uint32_t DATA2; /**< Bits[95:64] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 102 __O uint32_t DATA3; /**< Bits[127:96] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 103 } AesReg_t, *AesReg_pt;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #endif /* AES_MAP_H_ */