shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/device/M451Series.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /******************************************************************************
<> 149:156823d33999 2 * @file M451Series.h
<> 149:156823d33999 3 * @version V3.10
<> 149:156823d33999 4 * $Revision: 179 $
<> 149:156823d33999 5 * $Date: 15/09/04 3:45p $
<> 149:156823d33999 6 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11
<> 149:156823d33999 12
<> 149:156823d33999 13 /**
<> 149:156823d33999 14 \mainpage Introduction
<> 149:156823d33999 15 *
<> 149:156823d33999 16 *
<> 149:156823d33999 17 * This user manual describes the usage of M451 Series MCU device driver
<> 149:156823d33999 18 *
<> 149:156823d33999 19 * <b>Disclaimer</b>
<> 149:156823d33999 20 *
<> 149:156823d33999 21 * The Software is furnished "AS IS", without warranty as to performance or results, and
<> 149:156823d33999 22 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
<> 149:156823d33999 23 * warranties, express, implied or otherwise, with regard to the Software, its use, or
<> 149:156823d33999 24 * operation, including without limitation any and all warranties of merchantability, fitness
<> 149:156823d33999 25 * for a particular purpose, and non-infringement of intellectual property rights.
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * <b>Copyright Notice</b>
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 /**
<> 149:156823d33999 33 * \page PG_REV Revision History
<> 149:156823d33999 34 *
<> 149:156823d33999 35 * <b>Revision 3.01.001</b>
<> 149:156823d33999 36 * \li Added Nu-LB-M451, NuEdu and USB device sample code.
<> 149:156823d33999 37 * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
<> 149:156823d33999 38 * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
<> 149:156823d33999 39 * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
<> 149:156823d33999 40 * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
<> 149:156823d33999 41 * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
<> 149:156823d33999 42 * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
<> 149:156823d33999 43 * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
<> 149:156823d33999 44 * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
<> 149:156823d33999 45 * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
<> 149:156823d33999 46 * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
<> 149:156823d33999 47 * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
<> 149:156823d33999 48 * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
<> 149:156823d33999 49 * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register.
<> 149:156823d33999 50 * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
<> 149:156823d33999 51 * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
<> 149:156823d33999 52 * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
<> 149:156823d33999 53 * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
<> 149:156823d33999 54 * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
<> 149:156823d33999 55 * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
<> 149:156823d33999 56 * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
<> 149:156823d33999 57 * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
<> 149:156823d33999 58 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
<> 149:156823d33999 59 * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
<> 149:156823d33999 60 * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
<> 149:156823d33999 61 * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
<> 149:156823d33999 62 * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
<> 149:156823d33999 63 * \li Fixed SC_SET_STOP_BIT_LEN definition error.
<> 149:156823d33999 64 * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
<> 149:156823d33999 65 * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
<> 149:156823d33999 66 * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
<> 149:156823d33999 67 * \li Fixed SMBD_Enable constant value definition error in I2C driver.
<> 149:156823d33999 68 * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
<> 149:156823d33999 69 * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
<> 149:156823d33999 70 * \li Improved compatibility of USBH driver for pen driver.
<> 149:156823d33999 71 * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
<> 149:156823d33999 72 * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
<> 149:156823d33999 73 * \li Improved SC driver to support more than one SC port.
<> 149:156823d33999 74 * \li Improved USBH driver to support composite HID devices
<> 149:156823d33999 75 * \li Improved USBD driver to support more USB device sample code.
<> 149:156823d33999 76 * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
<> 149:156823d33999 77 * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
<> 149:156823d33999 78 * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
<> 149:156823d33999 79 * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
<> 149:156823d33999 80 *
<> 149:156823d33999 81 * <b>Revision 3.00.005</b>
<> 149:156823d33999 82 * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
<> 149:156823d33999 83 * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
<> 149:156823d33999 84 * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
<> 149:156823d33999 85 * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
<> 149:156823d33999 86 * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
<> 149:156823d33999 87 * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
<> 149:156823d33999 88 * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
<> 149:156823d33999 89 * \li Fixed isochronous transfer bugs of USB Host library.
<> 149:156823d33999 90 * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
<> 149:156823d33999 91 * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
<> 149:156823d33999 92 * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
<> 149:156823d33999 93 * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
<> 149:156823d33999 94 * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
<> 149:156823d33999 95 * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
<> 149:156823d33999 96 * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
<> 149:156823d33999 97 * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
<> 149:156823d33999 98 * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
<> 149:156823d33999 99 * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
<> 149:156823d33999 100 * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library.
<> 149:156823d33999 101 * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
<> 149:156823d33999 102 *
<> 149:156823d33999 103 * <b>Revision 3.00.004</b>
<> 149:156823d33999 104 * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
<> 149:156823d33999 105 * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
<> 149:156823d33999 106 * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
<> 149:156823d33999 107 * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
<> 149:156823d33999 108 * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
<> 149:156823d33999 109 * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
<> 149:156823d33999 110 * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
<> 149:156823d33999 111 * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
<> 149:156823d33999 112 * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
<> 149:156823d33999 113 * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
<> 149:156823d33999 114 * \li Fixed UART data transfer bug of USBD_VCOM sample code.
<> 149:156823d33999 115 * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
<> 149:156823d33999 116 * \li Updated USBD driver to pass USB-IF MSC test.
<> 149:156823d33999 117 * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
<> 149:156823d33999 118 * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
<> 149:156823d33999 119 * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
<> 149:156823d33999 120 * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
<> 149:156823d33999 121 * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
<> 149:156823d33999 122 *
<> 149:156823d33999 123 * <b>Revision 3.00.003</b>
<> 149:156823d33999 124 * \li Added USBD_Audio_HID_NAU8822 sample code.
<> 149:156823d33999 125 *
<> 149:156823d33999 126 * <b>Revision 3.00.002</b>
<> 149:156823d33999 127 * \li Fixed serial number code in device descriptor.
<> 149:156823d33999 128 * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
<> 149:156823d33999 129 * \li Fixed SMBus bus time-out and Clock Lo time-out API.
<> 149:156823d33999 130 * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
<> 149:156823d33999 131 * \li Fixed include path of CMSIS.
<> 149:156823d33999 132 * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
<> 149:156823d33999 133 * \li Fixed USBD_INT_WAKEUP definition.
<> 149:156823d33999 134 * \li Modified USBD driver to support USB remote wake-up function.
<> 149:156823d33999 135 *
<> 149:156823d33999 136 * <b>Revision 3.00.001</b>
<> 149:156823d33999 137 * \li Initial Release.
<> 149:156823d33999 138 */
<> 149:156823d33999 139
<> 149:156823d33999 140 #ifndef __M451SERIES_H__
<> 149:156823d33999 141 #define __M451SERIES_H__
<> 149:156823d33999 142
<> 149:156823d33999 143 #ifdef __cplusplus
<> 149:156823d33999 144 extern "C" {
<> 149:156823d33999 145 #endif
<> 149:156823d33999 146
<> 149:156823d33999 147 /******************************************************************************/
<> 149:156823d33999 148 /* Processor and Core Peripherals */
<> 149:156823d33999 149 /******************************************************************************/
<> 149:156823d33999 150 /** @addtogroup CMSIS Device CMSIS Definitions
<> 149:156823d33999 151 Configuration of the Cortex-M4 Processor and Core Peripherals
<> 149:156823d33999 152 @{
<> 149:156823d33999 153 */
<> 149:156823d33999 154
<> 149:156823d33999 155 /*
<> 149:156823d33999 156 * ==========================================================================
<> 149:156823d33999 157 * ---------- Interrupt Number Definition -----------------------------------
<> 149:156823d33999 158 * ==========================================================================
<> 149:156823d33999 159 */
<> 149:156823d33999 160
<> 149:156823d33999 161 typedef enum IRQn
<> 149:156823d33999 162 {
<> 149:156823d33999 163 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
<> 149:156823d33999 164 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 149:156823d33999 165 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
<> 149:156823d33999 166 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
<> 149:156823d33999 167 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
<> 149:156823d33999 168 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
<> 149:156823d33999 169 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
<> 149:156823d33999 170 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
<> 149:156823d33999 171 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
<> 149:156823d33999 172
<> 149:156823d33999 173 /****** M451 Specific Interrupt Numbers ********************************************************/
<> 149:156823d33999 174
<> 149:156823d33999 175 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
<> 149:156823d33999 176 IRC_IRQn = 1, /*!< Internal RC Interrupt */
<> 149:156823d33999 177 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
<> 149:156823d33999 178 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
<> 149:156823d33999 179 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
<> 149:156823d33999 180 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
<> 149:156823d33999 181 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
<> 149:156823d33999 182 WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
<> 149:156823d33999 183 WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
<> 149:156823d33999 184 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
<> 149:156823d33999 185 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
<> 149:156823d33999 186 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
<> 149:156823d33999 187 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
<> 149:156823d33999 188 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
<> 149:156823d33999 189 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
<> 149:156823d33999 190 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
<> 149:156823d33999 191 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
<> 149:156823d33999 192 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
<> 149:156823d33999 193 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
<> 149:156823d33999 194 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
<> 149:156823d33999 195 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
<> 149:156823d33999 196 SPI0_IRQn = 22, /*!< SPI0 Interrupt */
<> 149:156823d33999 197 SPI1_IRQn = 23, /*!< SPI1 Interrupt */
<> 149:156823d33999 198 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
<> 149:156823d33999 199 PWM0P0_IRQn = 25, /*!< PWM0P0 Interrupt */
<> 149:156823d33999 200 PWM0P1_IRQn = 26, /*!< PWM0P1 Interrupt */
<> 149:156823d33999 201 PWM0P2_IRQn = 27, /*!< PWM0P2 Interrupt */
<> 149:156823d33999 202 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
<> 149:156823d33999 203 PWM1P0_IRQn = 29, /*!< PWM1P0 Interrupt */
<> 149:156823d33999 204 PWM1P1_IRQn = 30, /*!< PWM1P1 Interrupt */
<> 149:156823d33999 205 PWM1P2_IRQn = 31, /*!< PWM1P2 Interrupt */
<> 149:156823d33999 206 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
<> 149:156823d33999 207 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
<> 149:156823d33999 208 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
<> 149:156823d33999 209 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
<> 149:156823d33999 210 UART0_IRQn = 36, /*!< UART 0 Interrupt */
<> 149:156823d33999 211 UART1_IRQn = 37, /*!< UART 1 Interrupt */
<> 149:156823d33999 212 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
<> 149:156823d33999 213 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
<> 149:156823d33999 214 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
<> 149:156823d33999 215 DAC_IRQn = 41, /*!< DAC Interrupt */
<> 149:156823d33999 216 ADC00_IRQn = 42, /*!< ADC0 Source 0 Interrupt */
<> 149:156823d33999 217 ADC01_IRQn = 43, /*!< ADC0 Source 1 Interrupt */
<> 149:156823d33999 218 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
<> 149:156823d33999 219 ADC02_IRQn = 46, /*!< ADC0 Source 2 Interrupt */
<> 149:156823d33999 220 ADC03_IRQn = 47, /*!< ADC0 Source 3 Interrupt */
<> 149:156823d33999 221 UART2_IRQn = 48, /*!< UART2 Interrupt */
<> 149:156823d33999 222 UART3_IRQn = 49, /*!< UART3 Interrupt */
<> 149:156823d33999 223 SPI2_IRQn = 51, /*!< SPI2 Interrupt */
<> 149:156823d33999 224 USBD_IRQn = 53, /*!< USB device Interrupt */
<> 149:156823d33999 225 USBH_IRQn = 54, /*!< USB host Interrupt */
<> 149:156823d33999 226 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
<> 149:156823d33999 227 CAN0_IRQn = 56, /*!< CAN0 Interrupt */
<> 149:156823d33999 228 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
<> 149:156823d33999 229 TK_IRQn = 63 /*!< Touch Key Interrupt */
<> 149:156823d33999 230 } IRQn_Type;
<> 149:156823d33999 231
<> 149:156823d33999 232
<> 149:156823d33999 233 /*
<> 149:156823d33999 234 * ==========================================================================
<> 149:156823d33999 235 * ----------- Processor and Core Peripheral Section ------------------------
<> 149:156823d33999 236 * ==========================================================================
<> 149:156823d33999 237 */
<> 149:156823d33999 238
<> 149:156823d33999 239 /* Configuration of the Cortex-M# Processor and Core Peripherals */
<> 149:156823d33999 240 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
<> 149:156823d33999 241 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
<> 149:156823d33999 242 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 149:156823d33999 243 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 149:156823d33999 244 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 149:156823d33999 245
<> 149:156823d33999 246 /*@}*/ /* end of group CMSIS */
<> 149:156823d33999 247
<> 149:156823d33999 248 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 149:156823d33999 249 #include "system_M451Series.h" /* M451 System include file */
<> 149:156823d33999 250 #include <stdint.h>
<> 149:156823d33999 251
<> 149:156823d33999 252
<> 149:156823d33999 253
<> 149:156823d33999 254 /******************************************************************************/
<> 149:156823d33999 255 /* Device Specific Peripheral registers structures */
<> 149:156823d33999 256 /******************************************************************************/
<> 149:156823d33999 257
<> 149:156823d33999 258 /** @addtogroup REGISTER Control Register
<> 149:156823d33999 259
<> 149:156823d33999 260 @{
<> 149:156823d33999 261
<> 149:156823d33999 262 */
<> 149:156823d33999 263
<> 149:156823d33999 264
<> 149:156823d33999 265 /*---------------------- Analog Comparator Controller -------------------------*/
<> 149:156823d33999 266 /**
<> 149:156823d33999 267 @addtogroup ACMP Analog Comparator Controller(ACMP)
<> 149:156823d33999 268 Memory Mapped Structure for ACMP Controller
<> 149:156823d33999 269 @{ */
<> 149:156823d33999 270
<> 149:156823d33999 271
<> 149:156823d33999 272 typedef struct
<> 149:156823d33999 273 {
<> 149:156823d33999 274
<> 149:156823d33999 275
<> 149:156823d33999 276 /**
<> 149:156823d33999 277 * @var ACMP_T::CTL
<> 149:156823d33999 278 * Offset: 0x00 Analog Comparator 0 Control Register
<> 149:156823d33999 279 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 280 * |Bits |Field |Descriptions
<> 149:156823d33999 281 * | :----: | :----: | :---- |
<> 149:156823d33999 282 * |[0] |ACMPEN |Comparator Enable Bit
<> 149:156823d33999 283 * | | |0 = Comparator 0 Disabled.
<> 149:156823d33999 284 * | | |1 = Comparator 0 Enabled.
<> 149:156823d33999 285 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
<> 149:156823d33999 286 * | | |0 = Comparator 0 interrupt Disabled.
<> 149:156823d33999 287 * | | |1 = Comparator 0 interrupt Enabled.
<> 149:156823d33999 288 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
<> 149:156823d33999 289 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
<> 149:156823d33999 290 * | | |0 = Comparator 0 hysteresis Disabled.
<> 149:156823d33999 291 * | | |1 = Comparator 0 hysteresis Enabled.
<> 149:156823d33999 292 * |[3] |ACMPOINV |Comparator Output Inverse
<> 149:156823d33999 293 * | | |0 = Comparator 0 output inverse Disabled.
<> 149:156823d33999 294 * | | |1 = Comparator 0 output inverse Enabled.
<> 149:156823d33999 295 * |[5:4] |NEGSEL |Comparator Negative Input Selection
<> 149:156823d33999 296 * | | |00 = ACMP0_N pin.
<> 149:156823d33999 297 * | | |01 = Internal comparator reference voltage (CRV).
<> 149:156823d33999 298 * | | |10 = Band-gap voltage.
<> 149:156823d33999 299 * | | |11 = DAC output.
<> 149:156823d33999 300 * |[7:6] |POSSEL |Comparator Positive Input Selection
<> 149:156823d33999 301 * | | |00 = Input from ACMP0_P0.
<> 149:156823d33999 302 * | | |01 = Input from ACMP0_P1.
<> 149:156823d33999 303 * | | |10 = Input from ACMP0_P2.
<> 149:156823d33999 304 * | | |11 = Input from ACMP0_P3.
<> 149:156823d33999 305 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
<> 149:156823d33999 306 * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
<> 149:156823d33999 307 * | | |00 = Rising edge or falling edge.
<> 149:156823d33999 308 * | | |01 = Rising edge.
<> 149:156823d33999 309 * | | |10 = Falling edge.
<> 149:156823d33999 310 * | | |11 = Reserved.
<> 149:156823d33999 311 * |[12] |OUTSEL |Comparator Output Select
<> 149:156823d33999 312 * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
<> 149:156823d33999 313 * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
<> 149:156823d33999 314 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
<> 149:156823d33999 315 * | | |000 = Filter function is Disabled.
<> 149:156823d33999 316 * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
<> 149:156823d33999 317 * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
<> 149:156823d33999 318 * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
<> 149:156823d33999 319 * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
<> 149:156823d33999 320 * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
<> 149:156823d33999 321 * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
<> 149:156823d33999 322 * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
<> 149:156823d33999 323 * |[16] |WKEN |Power Down Wake-Up Enable Bit
<> 149:156823d33999 324 * | | |0 = Wake-up function Disabled.
<> 149:156823d33999 325 * | | |1 = Wake-up function Enabled.
<> 149:156823d33999 326 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 327 * Offset: 0x04 Analog Comparator 1 Control Register
<> 149:156823d33999 328 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 329 * |Bits |Field |Descriptions
<> 149:156823d33999 330 * | :----: | :----: | :---- |
<> 149:156823d33999 331 * |[0] |ACMPEN |Comparator Enable Bit
<> 149:156823d33999 332 * | | |0 = Comparator 1 Disabled.
<> 149:156823d33999 333 * | | |1 = Comparator 1 Enabled.
<> 149:156823d33999 334 * |[1] |ACMPIE |Comparator Interrupt Enable Bit
<> 149:156823d33999 335 * | | |0 = Comparator 1 interrupt Disabled.
<> 149:156823d33999 336 * | | |1 = Comparator 1 interrupt Enabled.
<> 149:156823d33999 337 * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
<> 149:156823d33999 338 * |[2] |HYSEN |Comparator Hysteresis Enable Bit
<> 149:156823d33999 339 * | | |0 = Comparator 1 hysteresis Disabled.
<> 149:156823d33999 340 * | | |1 = Comparator 1 hysteresis Enabled.
<> 149:156823d33999 341 * |[3] |ACMPOINV |Comparator Output Inverse Control
<> 149:156823d33999 342 * | | |0 = Comparator 1 output inverse Disabled.
<> 149:156823d33999 343 * | | |1 = Comparator 1 output inverse Enabled.
<> 149:156823d33999 344 * |[5:4] |NEGSEL |Comparator Negative Input Selection
<> 149:156823d33999 345 * | | |00 = ACMP1_N pin.
<> 149:156823d33999 346 * | | |01 = Internal comparator reference voltage (CRV).
<> 149:156823d33999 347 * | | |10 = Band-gap voltage.
<> 149:156823d33999 348 * | | |11 = DAC output.
<> 149:156823d33999 349 * |[7:6] |POSSEL |Comparator Positive Input Selection
<> 149:156823d33999 350 * | | |00 = Input from ACMP1_P0.
<> 149:156823d33999 351 * | | |01 = Input from ACMP1_P1.
<> 149:156823d33999 352 * | | |10 = Input from ACMP1_P2.
<> 149:156823d33999 353 * | | |11 = Input from ACMP1_P3.
<> 149:156823d33999 354 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
<> 149:156823d33999 355 * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
<> 149:156823d33999 356 * | | |00 = Rising edge or falling edge.
<> 149:156823d33999 357 * | | |01 = Rising edge.
<> 149:156823d33999 358 * | | |10 = Falling edge.
<> 149:156823d33999 359 * | | |11 = Reserved.
<> 149:156823d33999 360 * |[12] |OUTSEL |Comparator Output Select
<> 149:156823d33999 361 * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
<> 149:156823d33999 362 * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
<> 149:156823d33999 363 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
<> 149:156823d33999 364 * | | |000 = Filter function is Disabled.
<> 149:156823d33999 365 * | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
<> 149:156823d33999 366 * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
<> 149:156823d33999 367 * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
<> 149:156823d33999 368 * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
<> 149:156823d33999 369 * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
<> 149:156823d33999 370 * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
<> 149:156823d33999 371 * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
<> 149:156823d33999 372 * |[16] |WKEN |Power Down Wakeup Enable Bit
<> 149:156823d33999 373 * | | |0 = Wake-up function Disabled.
<> 149:156823d33999 374 * | | |1 = Wake-up function Enabled.
<> 149:156823d33999 375 * @var ACMP_T::STATUS
<> 149:156823d33999 376 * Offset: 0x08 Analog Comparator Status Register
<> 149:156823d33999 377 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 378 * |Bits |Field |Descriptions
<> 149:156823d33999 379 * | :----: | :----: | :---- |
<> 149:156823d33999 380 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
<> 149:156823d33999 381 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
<> 149:156823d33999 382 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
<> 149:156823d33999 383 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 384 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
<> 149:156823d33999 385 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
<> 149:156823d33999 386 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
<> 149:156823d33999 387 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 388 * |[4] |ACMPO0 |Comparator 0 Output
<> 149:156823d33999 389 * | | |Synchronized to the PCLK to allow reading by software.
<> 149:156823d33999 390 * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
<> 149:156823d33999 391 * |[5] |ACMPO1 |Comparator 1 Output
<> 149:156823d33999 392 * | | |Synchronized to the PCLK to allow reading by software.
<> 149:156823d33999 393 * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
<> 149:156823d33999 394 * |[8] |WKIF0 |Comparator 0 Power Down Wake-Up Interrupt Flag
<> 149:156823d33999 395 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
<> 149:156823d33999 396 * | | |0 = No power down wake-up occurred.
<> 149:156823d33999 397 * | | |1 = Power down wake-up occurred.
<> 149:156823d33999 398 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 399 * |[9] |WKIF1 |Comparator 1 Power Down Wake-Up Interrupt Flag
<> 149:156823d33999 400 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
<> 149:156823d33999 401 * | | |0 = No power down wake-up occurred.
<> 149:156823d33999 402 * | | |1 = Power down wake-up occurred.
<> 149:156823d33999 403 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 404 * @var ACMP_T::VREF
<> 149:156823d33999 405 * Offset: 0x0C Analog Comparator Reference Voltage Control Register
<> 149:156823d33999 406 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 407 * |Bits |Field |Descriptions
<> 149:156823d33999 408 * | :----: | :----: | :---- |
<> 149:156823d33999 409 * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
<> 149:156823d33999 410 * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
<> 149:156823d33999 411 * |[6] |CRVSSEL |CRV Source Voltage Selection
<> 149:156823d33999 412 * | | |0 = VDDA is selected as CRV source voltage.
<> 149:156823d33999 413 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
<> 149:156823d33999 414 */
<> 149:156823d33999 415
<> 149:156823d33999 416 __IO uint32_t CTL[2]; /* Offset: 0x00 Analog Comparator Control Register */
<> 149:156823d33999 417 __IO uint32_t STATUS; /* Offset: 0x08 Analog Comparator Status Register */
<> 149:156823d33999 418 __IO uint32_t VREF; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
<> 149:156823d33999 419
<> 149:156823d33999 420 } ACMP_T;
<> 149:156823d33999 421
<> 149:156823d33999 422
<> 149:156823d33999 423
<> 149:156823d33999 424 /**
<> 149:156823d33999 425 @addtogroup ACMP_CONST ACMP Bit Field Definition
<> 149:156823d33999 426 Constant Definitions for ACMP Controller
<> 149:156823d33999 427 @{ */
<> 149:156823d33999 428
<> 149:156823d33999 429 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
<> 149:156823d33999 430 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
<> 149:156823d33999 431
<> 149:156823d33999 432 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
<> 149:156823d33999 433 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
<> 149:156823d33999 434
<> 149:156823d33999 435 #define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
<> 149:156823d33999 436 #define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
<> 149:156823d33999 437
<> 149:156823d33999 438 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
<> 149:156823d33999 439 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
<> 149:156823d33999 440
<> 149:156823d33999 441 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
<> 149:156823d33999 442 #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
<> 149:156823d33999 443
<> 149:156823d33999 444 #define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
<> 149:156823d33999 445 #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
<> 149:156823d33999 446
<> 149:156823d33999 447 #define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
<> 149:156823d33999 448 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
<> 149:156823d33999 449
<> 149:156823d33999 450 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
<> 149:156823d33999 451 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
<> 149:156823d33999 452
<> 149:156823d33999 453 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
<> 149:156823d33999 454 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
<> 149:156823d33999 455
<> 149:156823d33999 456 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
<> 149:156823d33999 457 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
<> 149:156823d33999 458
<> 149:156823d33999 459 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
<> 149:156823d33999 460 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
<> 149:156823d33999 461
<> 149:156823d33999 462 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
<> 149:156823d33999 463 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
<> 149:156823d33999 464
<> 149:156823d33999 465 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
<> 149:156823d33999 466 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
<> 149:156823d33999 467
<> 149:156823d33999 468 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
<> 149:156823d33999 469 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
<> 149:156823d33999 470
<> 149:156823d33999 471 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
<> 149:156823d33999 472 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
<> 149:156823d33999 473
<> 149:156823d33999 474 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
<> 149:156823d33999 475 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
<> 149:156823d33999 476
<> 149:156823d33999 477 #define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
<> 149:156823d33999 478 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
<> 149:156823d33999 479
<> 149:156823d33999 480 #define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
<> 149:156823d33999 481 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
<> 149:156823d33999 482
<> 149:156823d33999 483 /**@}*/ /* ACMP_CONST */
<> 149:156823d33999 484 /**@}*/ /* end of ACMP register group */
<> 149:156823d33999 485
<> 149:156823d33999 486
<> 149:156823d33999 487 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/
<> 149:156823d33999 488 /**
<> 149:156823d33999 489 @addtogroup Enhanced Analog to Digital Converter(EADC)
<> 149:156823d33999 490 Memory Mapped Structure for EADC Controller
<> 149:156823d33999 491 @{ */
<> 149:156823d33999 492
<> 149:156823d33999 493
<> 149:156823d33999 494 typedef struct
<> 149:156823d33999 495 {
<> 149:156823d33999 496
<> 149:156823d33999 497
<> 149:156823d33999 498 /**
<> 149:156823d33999 499 * @var EADC_T::DAT
<> 149:156823d33999 500 * Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18
<> 149:156823d33999 501 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 502 * |Bits |Field |Descriptions
<> 149:156823d33999 503 * | :----: | :----: | :---- |
<> 149:156823d33999 504 * |[15:0] |RESULT |A/D Conversion Result
<> 149:156823d33999 505 * | | |This field contains 12 bits conversion result.
<> 149:156823d33999 506 * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
<> 149:156823d33999 507 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
<> 149:156823d33999 508 * |[16] |OV |Overrun Flag
<> 149:156823d33999 509 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
<> 149:156823d33999 510 * | | |0 = Data in RESULT[11:0] is recent conversion result.
<> 149:156823d33999 511 * | | |1 = Data in RESULT[11:0] is overwrite.
<> 149:156823d33999 512 * | | |Note: It is cleared by hardware after EADC_DAT register is read.
<> 149:156823d33999 513 * |[17] |VALID |Valid Flag
<> 149:156823d33999 514 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
<> 149:156823d33999 515 * | | |0 = Data in RESULT[11:0] bits is not valid.
<> 149:156823d33999 516 * | | |1 = Data in RESULT[11:0] bits is valid.
<> 149:156823d33999 517 * @var EADC_T::CURDAT
<> 149:156823d33999 518 * Offset: 0x4C EADC PDMA Current Transfer Data Register
<> 149:156823d33999 519 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 520 * |Bits |Field |Descriptions
<> 149:156823d33999 521 * | :----: | :----: | :---- |
<> 149:156823d33999 522 * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
<> 149:156823d33999 523 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
<> 149:156823d33999 524 * | | |This is a read only register.
<> 149:156823d33999 525 * @var EADC_T::CTL
<> 149:156823d33999 526 * Offset: 0x50 A/D Control Register
<> 149:156823d33999 527 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 528 * |Bits |Field |Descriptions
<> 149:156823d33999 529 * | :----: | :----: | :---- |
<> 149:156823d33999 530 * |[0] |ADCEN |A/D Converter Enable Bit
<> 149:156823d33999 531 * | | |0 = Disabled.
<> 149:156823d33999 532 * | | |1 = Enabled.
<> 149:156823d33999 533 * | | |Note: Before starting A/D conversion function, this bit should be set to 1.
<> 149:156823d33999 534 * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
<> 149:156823d33999 535 * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
<> 149:156823d33999 536 * | | |0 = No effect.
<> 149:156823d33999 537 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
<> 149:156823d33999 538 * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
<> 149:156823d33999 539 * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
<> 149:156823d33999 540 * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
<> 149:156823d33999 541 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
<> 149:156823d33999 542 * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
<> 149:156823d33999 543 * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
<> 149:156823d33999 544 * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
<> 149:156823d33999 545 * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
<> 149:156823d33999 546 * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
<> 149:156823d33999 547 * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
<> 149:156823d33999 548 * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
<> 149:156823d33999 549 * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
<> 149:156823d33999 550 * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
<> 149:156823d33999 551 * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
<> 149:156823d33999 552 * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
<> 149:156823d33999 553 * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
<> 149:156823d33999 554 * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
<> 149:156823d33999 555 * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
<> 149:156823d33999 556 * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
<> 149:156823d33999 557 * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
<> 149:156823d33999 558 * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
<> 149:156823d33999 559 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
<> 149:156823d33999 560 * | | |0 = Single-end analog input mode.
<> 149:156823d33999 561 * | | |1 = Differential analog input mode.
<> 149:156823d33999 562 * |[9] |DMOF |ADC Differential Input Mode Output Format
<> 149:156823d33999 563 * | | |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
<> 149:156823d33999 564 * | | |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
<> 149:156823d33999 565 * |[11] |PDMAEN |PDMA Transfer Enable Bit
<> 149:156823d33999 566 * | | |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
<> 149:156823d33999 567 * | | |0 = PDMA data transfer Disabled.
<> 149:156823d33999 568 * | | |1 = PDMA data transfer Enabled.
<> 149:156823d33999 569 * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
<> 149:156823d33999 570 * |[18:16] |SMPTSEL |ADC Internal Sampling Time Selection
<> 149:156823d33999 571 * | | |ADC internal sampling cycle = SMPTSEL + 1.
<> 149:156823d33999 572 * | | |000 = 1 ADC clock sampling time.
<> 149:156823d33999 573 * | | |001 = 2 ADC clock sampling time.
<> 149:156823d33999 574 * | | |010 = 3 ADC clock sampling time.
<> 149:156823d33999 575 * | | |011 = 4 ADC clock sampling time.
<> 149:156823d33999 576 * | | |100 = 5 ADC clock sampling time.
<> 149:156823d33999 577 * | | |101 = 6 ADC clock sampling time.
<> 149:156823d33999 578 * | | |110 = 7 ADC clock sampling time.
<> 149:156823d33999 579 * | | |111 = 8 ADC clock sampling time.
<> 149:156823d33999 580 * @var EADC_T::SWTRG
<> 149:156823d33999 581 * Offset: 0x54 A/D Sample Module Software Start Register
<> 149:156823d33999 582 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 583 * |Bits |Field |Descriptions
<> 149:156823d33999 584 * | :----: | :----: | :---- |
<> 149:156823d33999 585 * |[18:0] |SWTRG |A/D Sample Module
<> 149:156823d33999 586 * | | |0~18 Software Force To Start ADC Conversion
<> 149:156823d33999 587 * | | |0 = No effect.
<> 149:156823d33999 588 * | | |1 = Cause an ADC conversion when the priority is given to sample module.
<> 149:156823d33999 589 * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
<> 149:156823d33999 590 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
<> 149:156823d33999 591 * @var EADC_T::PENDSTS
<> 149:156823d33999 592 * Offset: 0x58 A/D Start of Conversion Pending Flag Register
<> 149:156823d33999 593 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 594 * |Bits |Field |Descriptions
<> 149:156823d33999 595 * | :----: | :----: | :---- |
<> 149:156823d33999 596 * |[18:0] |STPF |A/D Sample Module 0~18 Start Of Conversion Pending Flag
<> 149:156823d33999 597 * | | |Read:
<> 149:156823d33999 598 * | | |0 = There is no pending conversion for sample module.
<> 149:156823d33999 599 * | | |1 = Sample module ADC start of conversion is pending.
<> 149:156823d33999 600 * | | |Write:
<> 149:156823d33999 601 * | | |1 = clear pending flag and cancel the conversion for sample module.
<> 149:156823d33999 602 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
<> 149:156823d33999 603 * @var EADC_T::OVSTS
<> 149:156823d33999 604 * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
<> 149:156823d33999 605 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 606 * |Bits |Field |Descriptions
<> 149:156823d33999 607 * | :----: | :----: | :---- |
<> 149:156823d33999 608 * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
<> 149:156823d33999 609 * | | |0 = No sample module event overrun.
<> 149:156823d33999 610 * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
<> 149:156823d33999 611 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 612 * @var EADC_T::SCTL
<> 149:156823d33999 613 * Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3
<> 149:156823d33999 614 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 615 * |Bits |Field |Descriptions
<> 149:156823d33999 616 * | :----: | :----: | :---- |
<> 149:156823d33999 617 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
<> 149:156823d33999 618 * | | |00H = EADC_CH0.
<> 149:156823d33999 619 * | | |01H = EADC_CH1.
<> 149:156823d33999 620 * | | |02H = EADC_CH2.
<> 149:156823d33999 621 * | | |03H = EADC_CH3.
<> 149:156823d33999 622 * | | |04H = EADC_CH4.
<> 149:156823d33999 623 * | | |05H = EADC_CH5.
<> 149:156823d33999 624 * | | |06H = EADC_CH6.
<> 149:156823d33999 625 * | | |07H = EADC_CH7.
<> 149:156823d33999 626 * | | |08H = EADC_CH8.
<> 149:156823d33999 627 * | | |09H = EADC_CH9.
<> 149:156823d33999 628 * | | |0AH = EADC_CH10.
<> 149:156823d33999 629 * | | |0BH = EADC_CH11.
<> 149:156823d33999 630 * | | |0CH = EADC_CH12.
<> 149:156823d33999 631 * | | |0DH = EADC_CH13.
<> 149:156823d33999 632 * | | |0EH = EADC_CH14.
<> 149:156823d33999 633 * | | |0FH = EADC_CH15.
<> 149:156823d33999 634 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
<> 149:156823d33999 635 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
<> 149:156823d33999 636 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
<> 149:156823d33999 637 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
<> 149:156823d33999 638 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
<> 149:156823d33999 639 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
<> 149:156823d33999 640 * |[7:6] |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
<> 149:156823d33999 641 * | | |Trigger delay clock frequency:
<> 149:156823d33999 642 * | | |00 = ADC_CLK/1.
<> 149:156823d33999 643 * | | |01 = ADC_CLK/2.
<> 149:156823d33999 644 * | | |10 = ADC_CLK/4.
<> 149:156823d33999 645 * | | |11 = ADC_CLK/16.
<> 149:156823d33999 646 * |[15:8] |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
<> 149:156823d33999 647 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
<> 149:156823d33999 648 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
<> 149:156823d33999 649 * | | |0H = Disable trigger.
<> 149:156823d33999 650 * | | |1H = External trigger from STADC pin input.
<> 149:156823d33999 651 * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
<> 149:156823d33999 652 * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
<> 149:156823d33999 653 * | | |4H = Timer0 overflow pulse trigger.
<> 149:156823d33999 654 * | | |5H = Timer1 overflow pulse trigger.
<> 149:156823d33999 655 * | | |6H = Timer2 overflow pulse trigger.
<> 149:156823d33999 656 * | | |7H = Timer3 overflow pulse trigger.
<> 149:156823d33999 657 * | | |8H = PWM0TG0.
<> 149:156823d33999 658 * | | |9H = PWM0TG1.
<> 149:156823d33999 659 * | | |AH = PWM0TG2.
<> 149:156823d33999 660 * | | |BH = PWM0TG3.
<> 149:156823d33999 661 * | | |CH = PWM0TG4.
<> 149:156823d33999 662 * | | |DH = PWM0TG5.
<> 149:156823d33999 663 * | | |EH = PWM1TG0.
<> 149:156823d33999 664 * | | |FH = PWM1TG1.
<> 149:156823d33999 665 * | | |10H = PWM1TG2.
<> 149:156823d33999 666 * | | |11H = PWM1TG3.
<> 149:156823d33999 667 * | | |12H = PWM1TG4.
<> 149:156823d33999 668 * | | |13H = PWM1TG5.
<> 149:156823d33999 669 * | | |other = Reserved.
<> 149:156823d33999 670 * |[22] |INTPOS |Interrupt Flag Position Select
<> 149:156823d33999 671 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
<> 149:156823d33999 672 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
<> 149:156823d33999 673 * |[23] |DBMEN |Double Buffer Mode Enable Bit
<> 149:156823d33999 674 * | | |0 = Sample has one sample result register. (default).
<> 149:156823d33999 675 * | | |1 = Sample has two sample result registers.
<> 149:156823d33999 676 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
<> 149:156823d33999 677 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
<> 149:156823d33999 678 * | | |The range of start delay time is from 0~255 ADC clock.
<> 149:156823d33999 679 * @var EADC_T::SCTL
<> 149:156823d33999 680 * Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15
<> 149:156823d33999 681 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 682 * |Bits |Field |Descriptions
<> 149:156823d33999 683 * | :----: | :----: | :---- |
<> 149:156823d33999 684 * |[3:0] |CHSEL |A/D Sample Module Channel Selection
<> 149:156823d33999 685 * | | |00H = EADC_CH0.
<> 149:156823d33999 686 * | | |01H = EADC_CH1.
<> 149:156823d33999 687 * | | |02H = EADC_CH2.
<> 149:156823d33999 688 * | | |03H = EADC_CH3.
<> 149:156823d33999 689 * | | |04H = EADC_CH4.
<> 149:156823d33999 690 * | | |05H = EADC_CH5.
<> 149:156823d33999 691 * | | |06H = EADC_CH6.
<> 149:156823d33999 692 * | | |07H = EADC_CH7.
<> 149:156823d33999 693 * | | |08H = EADC_CH8.
<> 149:156823d33999 694 * | | |09H = EADC_CH9.
<> 149:156823d33999 695 * | | |0AH = EADC_CH10.
<> 149:156823d33999 696 * | | |0BH = EADC_CH11.
<> 149:156823d33999 697 * | | |0CH = EADC_CH12.
<> 149:156823d33999 698 * | | |0DH = EADC_CH13.
<> 149:156823d33999 699 * | | |0EH = EADC_CH14.
<> 149:156823d33999 700 * | | |0FH = EADC_CH15.
<> 149:156823d33999 701 * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
<> 149:156823d33999 702 * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
<> 149:156823d33999 703 * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
<> 149:156823d33999 704 * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
<> 149:156823d33999 705 * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
<> 149:156823d33999 706 * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
<> 149:156823d33999 707 * |[7:6] |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
<> 149:156823d33999 708 * | | |Trigger delay clock frequency:
<> 149:156823d33999 709 * | | |00 = ADC_CLK/1.
<> 149:156823d33999 710 * | | |01 = ADC_CLK/2.
<> 149:156823d33999 711 * | | |10 = ADC_CLK/4.
<> 149:156823d33999 712 * | | |11 = ADC_CLK/16.
<> 149:156823d33999 713 * |[15:8] |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
<> 149:156823d33999 714 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
<> 149:156823d33999 715 * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
<> 149:156823d33999 716 * | | |0H = Disable trigger.
<> 149:156823d33999 717 * | | |1H = External trigger from STADC pin input.
<> 149:156823d33999 718 * | | |2H = ADC ADINT0 interrupt EOC pulse trigger.
<> 149:156823d33999 719 * | | |3H = ADC ADINT1 interrupt EOC pulse trigger.
<> 149:156823d33999 720 * | | |4H = Timer0 overflow pulse trigger.
<> 149:156823d33999 721 * | | |5H = Timer1 overflow pulse trigger.
<> 149:156823d33999 722 * | | |6H = Timer2 overflow pulse trigger.
<> 149:156823d33999 723 * | | |7H = Timer3 overflow pulse trigger.
<> 149:156823d33999 724 * | | |8H = PWM0TG0.
<> 149:156823d33999 725 * | | |9H = PWM0TG1.
<> 149:156823d33999 726 * | | |AH = PWM0TG2.
<> 149:156823d33999 727 * | | |BH = PWM0TG3.
<> 149:156823d33999 728 * | | |CH = PWM0TG4.
<> 149:156823d33999 729 * | | |DH = PWM0TG5.
<> 149:156823d33999 730 * | | |EH = PWM1TG0.
<> 149:156823d33999 731 * | | |FH = PWM1TG1.
<> 149:156823d33999 732 * | | |10H = PWM1TG2.
<> 149:156823d33999 733 * | | |11H = PWM1TG3.
<> 149:156823d33999 734 * | | |12H = PWM1TG4.
<> 149:156823d33999 735 * | | |13H = PWM1TG5.
<> 149:156823d33999 736 * | | |other = Reserved.
<> 149:156823d33999 737 * |[22] |INTPOS |Interrupt Flag Position Select
<> 149:156823d33999 738 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
<> 149:156823d33999 739 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
<> 149:156823d33999 740 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
<> 149:156823d33999 741 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
<> 149:156823d33999 742 * | | |The range of start delay time is from 0~255 ADC clock.
<> 149:156823d33999 743 * @var EADC_T::SCTL
<> 149:156823d33999 744 * Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18
<> 149:156823d33999 745 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 746 * |Bits |Field |Descriptions
<> 149:156823d33999 747 * | :----: | :----: | :---- |
<> 149:156823d33999 748 * |[31:24] |EXTSMPT |ADC Sampling Time Extend
<> 149:156823d33999 749 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
<> 149:156823d33999 750 * | | |The range of start delay time is from 0~255 ADC clock.
<> 149:156823d33999 751 * @var EADC_T::INTSRC
<> 149:156823d33999 752 * Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3
<> 149:156823d33999 753 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 754 * |Bits |Field |Descriptions
<> 149:156823d33999 755 * | :----: | :----: | :---- |
<> 149:156823d33999 756 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
<> 149:156823d33999 757 * | | |0 = Sample Module 0 interrupt Disabled.
<> 149:156823d33999 758 * | | |1 = Sample Module 0 interrupt Enabled.
<> 149:156823d33999 759 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
<> 149:156823d33999 760 * | | |0 = Sample Module 1 interrupt Disabled.
<> 149:156823d33999 761 * | | |1 = Sample Module 1 interrupt Enabled.
<> 149:156823d33999 762 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
<> 149:156823d33999 763 * | | |0 = Sample Module 2 interrupt Disabled.
<> 149:156823d33999 764 * | | |1 = Sample Module 2 interrupt Enabled.
<> 149:156823d33999 765 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
<> 149:156823d33999 766 * | | |0 = Sample Module 3 interrupt Disabled.
<> 149:156823d33999 767 * | | |1 = Sample Module 3 interrupt Enabled.
<> 149:156823d33999 768 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
<> 149:156823d33999 769 * | | |0 = Sample Module 4 interrupt Disabled.
<> 149:156823d33999 770 * | | |1 = Sample Module 4 interrupt Enabled.
<> 149:156823d33999 771 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
<> 149:156823d33999 772 * | | |0 = Sample Module 5 interrupt Disabled.
<> 149:156823d33999 773 * | | |1 = Sample Module 5 interrupt Enabled.
<> 149:156823d33999 774 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
<> 149:156823d33999 775 * | | |0 = Sample Module 6 interrupt Disabled.
<> 149:156823d33999 776 * | | |1 = Sample Module 6 interrupt Enabled.
<> 149:156823d33999 777 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
<> 149:156823d33999 778 * | | |0 = Sample Module 7 interrupt Disabled.
<> 149:156823d33999 779 * | | |1 = Sample Module 7 interrupt Enabled.
<> 149:156823d33999 780 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
<> 149:156823d33999 781 * | | |0 = Sample Module 8 interrupt Disabled.
<> 149:156823d33999 782 * | | |1 = Sample Module 8 interrupt Enabled.
<> 149:156823d33999 783 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
<> 149:156823d33999 784 * | | |0 = Sample Module 9 interrupt Disabled.
<> 149:156823d33999 785 * | | |1 = Sample Module 9 interrupt Enabled.
<> 149:156823d33999 786 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
<> 149:156823d33999 787 * | | |0 = Sample Module 10 interrupt Disabled.
<> 149:156823d33999 788 * | | |1 = Sample Module 10 interrupt Enabled.
<> 149:156823d33999 789 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
<> 149:156823d33999 790 * | | |0 = Sample Module 11 interrupt Disabled.
<> 149:156823d33999 791 * | | |1 = Sample Module 11 interrupt Enabled.
<> 149:156823d33999 792 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
<> 149:156823d33999 793 * | | |0 = Sample Module 12 interrupt Disabled.
<> 149:156823d33999 794 * | | |1 = Sample Module 12 interrupt Enabled.
<> 149:156823d33999 795 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
<> 149:156823d33999 796 * | | |0 = Sample Module 13 interrupt Disabled.
<> 149:156823d33999 797 * | | |1 = Sample Module 13 interrupt Enabled.
<> 149:156823d33999 798 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
<> 149:156823d33999 799 * | | |0 = Sample Module 14 interrupt Disabled.
<> 149:156823d33999 800 * | | |1 = Sample Module 14 interrupt Enabled.
<> 149:156823d33999 801 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
<> 149:156823d33999 802 * | | |0 = Sample Module 15 interrupt Disabled.
<> 149:156823d33999 803 * | | |1 = Sample Module 15 interrupt Enabled.
<> 149:156823d33999 804 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
<> 149:156823d33999 805 * | | |0 = Sample Module 16 interrupt Disabled.
<> 149:156823d33999 806 * | | |1 = Sample Module 16 interrupt Enabled.
<> 149:156823d33999 807 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
<> 149:156823d33999 808 * | | |0 = Sample Module 17 interrupt Disabled.
<> 149:156823d33999 809 * | | |1 = Sample Module 17 interrupt Enabled.
<> 149:156823d33999 810 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
<> 149:156823d33999 811 * | | |0 = Sample Module 18 interrupt Disabled.
<> 149:156823d33999 812 * | | |1 = Sample Module 18 interrupt Enabled.
<> 149:156823d33999 813 * @var EADC_T::CMP
<> 149:156823d33999 814 * Offset: 0xEC A/D Result Compare Register n, n=0~3
<> 149:156823d33999 815 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 816 * |Bits |Field |Descriptions
<> 149:156823d33999 817 * | :----: | :----: | :---- |
<> 149:156823d33999 818 * |[0] |ADCMPEN |A/D Result Compare Enable Bit
<> 149:156823d33999 819 * | | |0 = Compare Disabled.
<> 149:156823d33999 820 * | | |1 = Compare Enabled.
<> 149:156823d33999 821 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
<> 149:156823d33999 822 * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
<> 149:156823d33999 823 * | | |0 = Compare function interrupt Disabled.
<> 149:156823d33999 824 * | | |1 = Compare function interrupt Enabled.
<> 149:156823d33999 825 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
<> 149:156823d33999 826 * |[2] |CMPCOND |Compare Condition
<> 149:156823d33999 827 * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
<> 149:156823d33999 828 * | | |[27:16]), the internal match counter will increase one.
<> 149:156823d33999 829 * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
<> 149:156823d33999 830 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
<> 149:156823d33999 831 * |[7:3] |CMPSPL |Compare Sample Module Selection
<> 149:156823d33999 832 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
<> 149:156823d33999 833 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
<> 149:156823d33999 834 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
<> 149:156823d33999 835 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
<> 149:156823d33999 836 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
<> 149:156823d33999 837 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
<> 149:156823d33999 838 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
<> 149:156823d33999 839 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
<> 149:156823d33999 840 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
<> 149:156823d33999 841 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
<> 149:156823d33999 842 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
<> 149:156823d33999 843 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
<> 149:156823d33999 844 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
<> 149:156823d33999 845 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
<> 149:156823d33999 846 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
<> 149:156823d33999 847 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
<> 149:156823d33999 848 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
<> 149:156823d33999 849 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
<> 149:156823d33999 850 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
<> 149:156823d33999 851 * |[11:8] |CMPMCNT |Compare Match Count
<> 149:156823d33999 852 * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
<> 149:156823d33999 853 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
<> 149:156823d33999 854 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
<> 149:156823d33999 855 * |[15] |CMPWEN |Compare Window Mode Enable Bit
<> 149:156823d33999 856 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
<> 149:156823d33999 857 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
<> 149:156823d33999 858 * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
<> 149:156823d33999 859 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
<> 149:156823d33999 860 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
<> 149:156823d33999 861 * |[27:16] |CMPDAT |Comparison Data
<> 149:156823d33999 862 * | | |The 12 bits data is used to compare with conversion result of specified sample module.
<> 149:156823d33999 863 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
<> 149:156823d33999 864 * @var EADC_T::STATUS0
<> 149:156823d33999 865 * Offset: 0xF0 A/D Status Register 0
<> 149:156823d33999 866 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 867 * |Bits |Field |Descriptions
<> 149:156823d33999 868 * | :----: | :----: | :---- |
<> 149:156823d33999 869 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
<> 149:156823d33999 870 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
<> 149:156823d33999 871 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
<> 149:156823d33999 872 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
<> 149:156823d33999 873 * @var EADC_T::STATUS1
<> 149:156823d33999 874 * Offset: 0xF4 A/D Status Register 1
<> 149:156823d33999 875 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 876 * |Bits |Field |Descriptions
<> 149:156823d33999 877 * | :----: | :----: | :---- |
<> 149:156823d33999 878 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
<> 149:156823d33999 879 * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
<> 149:156823d33999 880 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
<> 149:156823d33999 881 * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
<> 149:156823d33999 882 * @var EADC_T::STATUS2
<> 149:156823d33999 883 * Offset: 0xF8 A/D Status Register 2
<> 149:156823d33999 884 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 885 * |Bits |Field |Descriptions
<> 149:156823d33999 886 * | :----: | :----: | :---- |
<> 149:156823d33999 887 * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
<> 149:156823d33999 888 * | | |0 = No ADINT0 interrupt pulse received.
<> 149:156823d33999 889 * | | |1 = ADINT0 interrupt pulse has been received.
<> 149:156823d33999 890 * | | |Note1: This bit is cleared by writing 1 to it.
<> 149:156823d33999 891 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
<> 149:156823d33999 892 * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
<> 149:156823d33999 893 * | | |0 = No ADINT1 interrupt pulse received.
<> 149:156823d33999 894 * | | |1 = ADINT1 interrupt pulse has been received.
<> 149:156823d33999 895 * | | |Note1: This bit is cleared by writing 1 to it.
<> 149:156823d33999 896 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
<> 149:156823d33999 897 * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
<> 149:156823d33999 898 * | | |0 = No ADINT2 interrupt pulse received.
<> 149:156823d33999 899 * | | |1 = ADINT2 interrupt pulse has been received.
<> 149:156823d33999 900 * | | |Note1: This bit is cleared by writing 1 to it.
<> 149:156823d33999 901 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
<> 149:156823d33999 902 * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
<> 149:156823d33999 903 * | | |0 = No ADINT3 interrupt pulse received.
<> 149:156823d33999 904 * | | |1 = ADINT3 interrupt pulse has been received.
<> 149:156823d33999 905 * | | |Note1: This bit is cleared by writing 1 to it.
<> 149:156823d33999 906 * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
<> 149:156823d33999 907 * |[4] |ADCMPF0 |ADC Compare 0 Flag
<> 149:156823d33999 908 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
<> 149:156823d33999 909 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
<> 149:156823d33999 910 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
<> 149:156823d33999 911 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 912 * |[5] |ADCMPF1 |ADC Compare 1 Flag
<> 149:156823d33999 913 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
<> 149:156823d33999 914 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
<> 149:156823d33999 915 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
<> 149:156823d33999 916 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 917 * |[6] |ADCMPF2 |ADC Compare 2 Flag
<> 149:156823d33999 918 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
<> 149:156823d33999 919 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
<> 149:156823d33999 920 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
<> 149:156823d33999 921 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 922 * |[7] |ADCMPF3 |ADC Compare 3 Flag
<> 149:156823d33999 923 * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
<> 149:156823d33999 924 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
<> 149:156823d33999 925 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
<> 149:156823d33999 926 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 927 * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
<> 149:156823d33999 928 * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
<> 149:156823d33999 929 * | | |1 = ADINT0 interrupt flag is overwritten to 1.
<> 149:156823d33999 930 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 931 * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
<> 149:156823d33999 932 * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
<> 149:156823d33999 933 * | | |1 = ADINT1 interrupt flag is overwritten to 1.
<> 149:156823d33999 934 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 935 * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
<> 149:156823d33999 936 * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
<> 149:156823d33999 937 * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
<> 149:156823d33999 938 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 939 * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
<> 149:156823d33999 940 * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
<> 149:156823d33999 941 * | | |1 = ADINT3 interrupt flag is overwritten to 1.
<> 149:156823d33999 942 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 943 * |[12] |ADCMPO0 |ADC Compare 0 Output Status
<> 149:156823d33999 944 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
<> 149:156823d33999 945 * | | |User can use it to monitor the external analog input pin voltage status.
<> 149:156823d33999 946 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
<> 149:156823d33999 947 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
<> 149:156823d33999 948 * | | |setting.
<> 149:156823d33999 949 * |[13] |ADCMPO1 |ADC Compare 1 Output Status
<> 149:156823d33999 950 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
<> 149:156823d33999 951 * | | |User can use it to monitor the external analog input pin voltage status.
<> 149:156823d33999 952 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
<> 149:156823d33999 953 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
<> 149:156823d33999 954 * | | |setting.
<> 149:156823d33999 955 * |[14] |ADCMPO2 |ADC Compare 2 Output Status
<> 149:156823d33999 956 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
<> 149:156823d33999 957 * | | |User can use it to monitor the external analog input pin voltage status.
<> 149:156823d33999 958 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
<> 149:156823d33999 959 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
<> 149:156823d33999 960 * | | |setting.
<> 149:156823d33999 961 * |[15] |ADCMPO3 |ADC Compare 3 Output Status
<> 149:156823d33999 962 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
<> 149:156823d33999 963 * | | |User can use it to monitor the external analog input pin voltage status.
<> 149:156823d33999 964 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
<> 149:156823d33999 965 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
<> 149:156823d33999 966 * | | |setting.
<> 149:156823d33999 967 * |[20:16] |CHANNEL |Current Conversion Channel
<> 149:156823d33999 968 * | | |This filed reflects ADC current conversion channel when BUSY=1.
<> 149:156823d33999 969 * | | |It is read only.
<> 149:156823d33999 970 * | | |00H = EADC_CH0.
<> 149:156823d33999 971 * | | |01H = EADC_CH1.
<> 149:156823d33999 972 * | | |02H = EADC_CH2.
<> 149:156823d33999 973 * | | |03H = EADC_CH3.
<> 149:156823d33999 974 * | | |04H = EADC_CH4.
<> 149:156823d33999 975 * | | |05H = EADC_CH5.
<> 149:156823d33999 976 * | | |06H = EADC_CH6.
<> 149:156823d33999 977 * | | |07H = EADC_CH7.
<> 149:156823d33999 978 * | | |08H = EADC_CH8.
<> 149:156823d33999 979 * | | |09H = EADC_CH9.
<> 149:156823d33999 980 * | | |0AH = EADC_CH10.
<> 149:156823d33999 981 * | | |0BH = EADC_CH11.
<> 149:156823d33999 982 * | | |0CH = EADC_CH12.
<> 149:156823d33999 983 * | | |0DH = EADC_CH13.
<> 149:156823d33999 984 * | | |0EH = EADC_CH14.
<> 149:156823d33999 985 * | | |0FH = EADC_CH15.
<> 149:156823d33999 986 * | | |10H = VBG.
<> 149:156823d33999 987 * | | |11H = VTEMP.
<> 149:156823d33999 988 * | | |12H = VBAT.
<> 149:156823d33999 989 * |[23] |BUSY |Busy/Idle
<> 149:156823d33999 990 * | | |0 = EADC is in idle state.
<> 149:156823d33999 991 * | | |1 = EADC is busy at conversion.
<> 149:156823d33999 992 * | | |Note: This bit is read only.
<> 149:156823d33999 993 * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
<> 149:156823d33999 994 * | | |n=0~3.
<> 149:156823d33999 995 * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
<> 149:156823d33999 996 * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
<> 149:156823d33999 997 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
<> 149:156823d33999 998 * |[25] |STOVF |For All A/D Sample Module Start Of Conversion Overrun Flags Check
<> 149:156823d33999 999 * | | |n=0~18.
<> 149:156823d33999 1000 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
<> 149:156823d33999 1001 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
<> 149:156823d33999 1002 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
<> 149:156823d33999 1003 * |[26] |AVALID |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
<> 149:156823d33999 1004 * | | |n=0~18.
<> 149:156823d33999 1005 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
<> 149:156823d33999 1006 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
<> 149:156823d33999 1007 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
<> 149:156823d33999 1008 * |[27] |AOV |For All Sample Module A/D Result Data Register Overrun Flags Check
<> 149:156823d33999 1009 * | | |n=0~18.
<> 149:156823d33999 1010 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
<> 149:156823d33999 1011 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
<> 149:156823d33999 1012 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
<> 149:156823d33999 1013 * @var EADC_T::STATUS3
<> 149:156823d33999 1014 * Offset: 0xFC A/D Status Register 3
<> 149:156823d33999 1015 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1016 * |Bits |Field |Descriptions
<> 149:156823d33999 1017 * | :----: | :----: | :---- |
<> 149:156823d33999 1018 * |[4:0] |CURSPL |ADC Current Sample Module
<> 149:156823d33999 1019 * | | |This register show the current ADC is controlled by which sample module control logic modules.
<> 149:156823d33999 1020 * | | |If the ADC is Idle, this bit filed will set to 0x1F.
<> 149:156823d33999 1021 * | | |This is a read only register.
<> 149:156823d33999 1022 * @var EADC_T::DDAT
<> 149:156823d33999 1023 * Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3
<> 149:156823d33999 1024 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1025 * |Bits |Field |Descriptions
<> 149:156823d33999 1026 * | :----: | :----: | :---- |
<> 149:156823d33999 1027 * |[15:0] |RESULT |A/D Conversion Results
<> 149:156823d33999 1028 * | | |This field contains 12 bits conversion results.
<> 149:156823d33999 1029 * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
<> 149:156823d33999 1030 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
<> 149:156823d33999 1031 * |[16] |OV |Overrun Flag
<> 149:156823d33999 1032 * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
<> 149:156823d33999 1033 * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
<> 149:156823d33999 1034 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
<> 149:156823d33999 1035 * | | |It is cleared by hardware after EADC_DDAT register is read.
<> 149:156823d33999 1036 * |[17] |VALID |Valid Flag
<> 149:156823d33999 1037 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
<> 149:156823d33999 1038 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
<> 149:156823d33999 1039 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
<> 149:156823d33999 1040 * | | |(n=0~3).
<> 149:156823d33999 1041 */
<> 149:156823d33999 1042
<> 149:156823d33999 1043 __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
<> 149:156823d33999 1044 __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
<> 149:156823d33999 1045 __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
<> 149:156823d33999 1046 __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
<> 149:156823d33999 1047 __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
<> 149:156823d33999 1048 __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
<> 149:156823d33999 1049 __I uint32_t RESERVE0[8];
<> 149:156823d33999 1050 __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
<> 149:156823d33999 1051 __I uint32_t RESERVE1[1];
<> 149:156823d33999 1052 __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
<> 149:156823d33999 1053 __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
<> 149:156823d33999 1054 __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
<> 149:156823d33999 1055 __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
<> 149:156823d33999 1056 __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
<> 149:156823d33999 1057 __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
<> 149:156823d33999 1058 __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
<> 149:156823d33999 1059
<> 149:156823d33999 1060 } EADC_T;
<> 149:156823d33999 1061
<> 149:156823d33999 1062
<> 149:156823d33999 1063
<> 149:156823d33999 1064 /**
<> 149:156823d33999 1065 @addtogroup EADC_CONST EADC Bit Field Definition
<> 149:156823d33999 1066 Constant Definitions for EADC Controller
<> 149:156823d33999 1067 @{ */
<> 149:156823d33999 1068 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
<> 149:156823d33999 1069 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
<> 149:156823d33999 1070
<> 149:156823d33999 1071 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
<> 149:156823d33999 1072 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
<> 149:156823d33999 1073
<> 149:156823d33999 1074 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
<> 149:156823d33999 1075 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
<> 149:156823d33999 1076
<> 149:156823d33999 1077 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
<> 149:156823d33999 1078 #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
<> 149:156823d33999 1079
<> 149:156823d33999 1080 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
<> 149:156823d33999 1081 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
<> 149:156823d33999 1082
<> 149:156823d33999 1083 #define EADC_CTL_ADRST_Pos (1) /*!< EADC_T::CTL: ADRST Position */
<> 149:156823d33999 1084 #define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) /*!< EADC_T::CTL: ADRST Mask */
<> 149:156823d33999 1085
<> 149:156823d33999 1086 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
<> 149:156823d33999 1087 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
<> 149:156823d33999 1088
<> 149:156823d33999 1089 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
<> 149:156823d33999 1090 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
<> 149:156823d33999 1091
<> 149:156823d33999 1092 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
<> 149:156823d33999 1093 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
<> 149:156823d33999 1094
<> 149:156823d33999 1095 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
<> 149:156823d33999 1096 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
<> 149:156823d33999 1097
<> 149:156823d33999 1098 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
<> 149:156823d33999 1099 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
<> 149:156823d33999 1100
<> 149:156823d33999 1101 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
<> 149:156823d33999 1102 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
<> 149:156823d33999 1103
<> 149:156823d33999 1104 #define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
<> 149:156823d33999 1105 #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
<> 149:156823d33999 1106
<> 149:156823d33999 1107 #define EADC_CTL_SMPTSEL_Pos (16) /*!< EADC_T::CTL: SMPTSEL Position */
<> 149:156823d33999 1108 #define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) /*!< EADC_T::CTL: SMPTSEL Mask */
<> 149:156823d33999 1109
<> 149:156823d33999 1110 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
<> 149:156823d33999 1111 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
<> 149:156823d33999 1112
<> 149:156823d33999 1113 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
<> 149:156823d33999 1114 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
<> 149:156823d33999 1115
<> 149:156823d33999 1116 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
<> 149:156823d33999 1117 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
<> 149:156823d33999 1118
<> 149:156823d33999 1119 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
<> 149:156823d33999 1120 #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
<> 149:156823d33999 1121
<> 149:156823d33999 1122 #define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
<> 149:156823d33999 1123 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
<> 149:156823d33999 1124
<> 149:156823d33999 1125 #define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
<> 149:156823d33999 1126 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
<> 149:156823d33999 1127
<> 149:156823d33999 1128 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
<> 149:156823d33999 1129 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
<> 149:156823d33999 1130
<> 149:156823d33999 1131 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
<> 149:156823d33999 1132 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
<> 149:156823d33999 1133
<> 149:156823d33999 1134 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
<> 149:156823d33999 1135 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
<> 149:156823d33999 1136
<> 149:156823d33999 1137 #define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
<> 149:156823d33999 1138 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
<> 149:156823d33999 1139
<> 149:156823d33999 1140 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
<> 149:156823d33999 1141 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
<> 149:156823d33999 1142
<> 149:156823d33999 1143 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
<> 149:156823d33999 1144 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
<> 149:156823d33999 1145
<> 149:156823d33999 1146 #define EADC_INTSRC_SPLIE_Pos (0) /*!< EADC_T::INTSRC: SPLIE Position */
<> 149:156823d33999 1147 #define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) /*!< EADC_T::INTSRC: SPLIE Mask */
<> 149:156823d33999 1148
<> 149:156823d33999 1149 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
<> 149:156823d33999 1150 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
<> 149:156823d33999 1151
<> 149:156823d33999 1152 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
<> 149:156823d33999 1153 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
<> 149:156823d33999 1154
<> 149:156823d33999 1155 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
<> 149:156823d33999 1156 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
<> 149:156823d33999 1157
<> 149:156823d33999 1158 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
<> 149:156823d33999 1159 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
<> 149:156823d33999 1160
<> 149:156823d33999 1161 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
<> 149:156823d33999 1162 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
<> 149:156823d33999 1163
<> 149:156823d33999 1164 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
<> 149:156823d33999 1165 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
<> 149:156823d33999 1166
<> 149:156823d33999 1167 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
<> 149:156823d33999 1168 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
<> 149:156823d33999 1169
<> 149:156823d33999 1170 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
<> 149:156823d33999 1171 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
<> 149:156823d33999 1172
<> 149:156823d33999 1173 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
<> 149:156823d33999 1174 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
<> 149:156823d33999 1175
<> 149:156823d33999 1176 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
<> 149:156823d33999 1177 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
<> 149:156823d33999 1178
<> 149:156823d33999 1179 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
<> 149:156823d33999 1180 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
<> 149:156823d33999 1181
<> 149:156823d33999 1182 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
<> 149:156823d33999 1183 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
<> 149:156823d33999 1184
<> 149:156823d33999 1185 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
<> 149:156823d33999 1186 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
<> 149:156823d33999 1187
<> 149:156823d33999 1188 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
<> 149:156823d33999 1189 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
<> 149:156823d33999 1190
<> 149:156823d33999 1191 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
<> 149:156823d33999 1192 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
<> 149:156823d33999 1193
<> 149:156823d33999 1194 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
<> 149:156823d33999 1195 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
<> 149:156823d33999 1196
<> 149:156823d33999 1197 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
<> 149:156823d33999 1198 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
<> 149:156823d33999 1199
<> 149:156823d33999 1200 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
<> 149:156823d33999 1201 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
<> 149:156823d33999 1202
<> 149:156823d33999 1203 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
<> 149:156823d33999 1204 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
<> 149:156823d33999 1205
<> 149:156823d33999 1206 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
<> 149:156823d33999 1207 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
<> 149:156823d33999 1208
<> 149:156823d33999 1209 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
<> 149:156823d33999 1210 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
<> 149:156823d33999 1211
<> 149:156823d33999 1212 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
<> 149:156823d33999 1213 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
<> 149:156823d33999 1214
<> 149:156823d33999 1215 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
<> 149:156823d33999 1216 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
<> 149:156823d33999 1217
<> 149:156823d33999 1218 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
<> 149:156823d33999 1219 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
<> 149:156823d33999 1220
<> 149:156823d33999 1221 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
<> 149:156823d33999 1222 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
<> 149:156823d33999 1223
<> 149:156823d33999 1224 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
<> 149:156823d33999 1225 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
<> 149:156823d33999 1226
<> 149:156823d33999 1227 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
<> 149:156823d33999 1228 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
<> 149:156823d33999 1229
<> 149:156823d33999 1230 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
<> 149:156823d33999 1231 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
<> 149:156823d33999 1232
<> 149:156823d33999 1233 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
<> 149:156823d33999 1234 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
<> 149:156823d33999 1235
<> 149:156823d33999 1236 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
<> 149:156823d33999 1237 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
<> 149:156823d33999 1238
<> 149:156823d33999 1239 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
<> 149:156823d33999 1240 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
<> 149:156823d33999 1241
<> 149:156823d33999 1242 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
<> 149:156823d33999 1243 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
<> 149:156823d33999 1244
<> 149:156823d33999 1245 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
<> 149:156823d33999 1246 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
<> 149:156823d33999 1247
<> 149:156823d33999 1248 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
<> 149:156823d33999 1249 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
<> 149:156823d33999 1250
<> 149:156823d33999 1251 #define EADC_DDAT_RESULT_Pos (0) /*!< EADC_T::DDAT: RESULT Position */
<> 149:156823d33999 1252 #define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) /*!< EADC_T::DDAT: RESULT Mask */
<> 149:156823d33999 1253
<> 149:156823d33999 1254 #define EADC_DDAT_OV_Pos (16) /*!< EADC_T::DDAT: OV Position */
<> 149:156823d33999 1255 #define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) /*!< EADC_T::DDAT: OV Mask */
<> 149:156823d33999 1256
<> 149:156823d33999 1257 #define EADC_DDAT_VALID_Pos (17) /*!< EADC_T::DDAT: VALID Position */
<> 149:156823d33999 1258 #define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /*!< EADC_T::DDAT: VALID Mask */
<> 149:156823d33999 1259
<> 149:156823d33999 1260
<> 149:156823d33999 1261 /**@}*/ /* EADC_CONST */
<> 149:156823d33999 1262 /**@}*/ /* end of EADC register group */
<> 149:156823d33999 1263
<> 149:156823d33999 1264
<> 149:156823d33999 1265 /*---------------------- Controller Area Network Controller -------------------------*/
<> 149:156823d33999 1266 /**
<> 149:156823d33999 1267 @addtogroup CAN Controller Area Network Controller(CAN)
<> 149:156823d33999 1268 Memory Mapped Structure for CAN Controller
<> 149:156823d33999 1269 @{ */
<> 149:156823d33999 1270
<> 149:156823d33999 1271
<> 149:156823d33999 1272 typedef struct
<> 149:156823d33999 1273 {
<> 149:156823d33999 1274
<> 149:156823d33999 1275
<> 149:156823d33999 1276
<> 149:156823d33999 1277 /**
<> 149:156823d33999 1278 * @var CAN_IF_T::CREQ
<> 149:156823d33999 1279 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
<> 149:156823d33999 1280 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1281 * |Bits |Field |Descriptions
<> 149:156823d33999 1282 * | :----: | :----: | :---- |
<> 149:156823d33999 1283 * |[5:0] |MessageNumber|Message Number
<> 149:156823d33999 1284 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
<> 149:156823d33999 1285 * | | |RAM is selected for data transfer.
<> 149:156823d33999 1286 * | | |0x00: Not a valid Message Number, interpreted as 0x20.
<> 149:156823d33999 1287 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
<> 149:156823d33999 1288 * |[15] |Busy |Busy Flag
<> 149:156823d33999 1289 * | | |0 = Read/write action has finished.
<> 149:156823d33999 1290 * | | |1 = Writing to the IFn Command Request Register is in progress.
<> 149:156823d33999 1291 * | | |This bit can only be read by the software.
<> 149:156823d33999 1292 * @var CAN_IF_T::CMASK
<> 149:156823d33999 1293 * Offset: 0x24, 0x84 IFn Command Mask Register
<> 149:156823d33999 1294 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1295 * |Bits |Field |Descriptions
<> 149:156823d33999 1296 * | :----: | :----: | :---- |
<> 149:156823d33999 1297 * |[0] |DAT_B |Access Data Bytes [7:4]
<> 149:156823d33999 1298 * | | |Write Operation:
<> 149:156823d33999 1299 * | | |0 = Data Bytes [7:4] unchanged.
<> 149:156823d33999 1300 * | | |1 = Transfer Data Bytes [7:4] to Message Object.
<> 149:156823d33999 1301 * | | |Read Operation:
<> 149:156823d33999 1302 * | | |0 = Data Bytes [7:4] unchanged.
<> 149:156823d33999 1303 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
<> 149:156823d33999 1304 * |[1] |DAT_A |Access Data Bytes [3:0]
<> 149:156823d33999 1305 * | | |Write Operation:
<> 149:156823d33999 1306 * | | |0 = Data Bytes [3:0] unchanged.
<> 149:156823d33999 1307 * | | |1 = Transfer Data Bytes [3:0] to Message Object.
<> 149:156823d33999 1308 * | | |Read Operation:
<> 149:156823d33999 1309 * | | |0 = Data Bytes [3:0] unchanged.
<> 149:156823d33999 1310 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
<> 149:156823d33999 1311 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
<> 149:156823d33999 1312 * | | |0 = TxRqst bit unchanged.
<> 149:156823d33999 1313 * | | |1 = Set TxRqst bit.
<> 149:156823d33999 1314 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
<> 149:156823d33999 1315 * | | |Access New Data Bit when Read Operation.
<> 149:156823d33999 1316 * | | |0 = NewDat bit remains unchanged.
<> 149:156823d33999 1317 * | | |1 = Clear NewDat bit in the Message Object.
<> 149:156823d33999 1318 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
<> 149:156823d33999 1319 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
<> 149:156823d33999 1320 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
<> 149:156823d33999 1321 * | | |Write Operation:
<> 149:156823d33999 1322 * | | |When writing to a Message Object, this bit is ignored.
<> 149:156823d33999 1323 * | | |Read Operation:
<> 149:156823d33999 1324 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
<> 149:156823d33999 1325 * | | |1 = Clear IntPnd bit in the Message Object.
<> 149:156823d33999 1326 * |[4] |Control |Control Access Control Bits
<> 149:156823d33999 1327 * | | |Write Operation:
<> 149:156823d33999 1328 * | | |0 = Control Bits unchanged.
<> 149:156823d33999 1329 * | | |1 = Transfer Control Bits to Message Object.
<> 149:156823d33999 1330 * | | |Read Operation:
<> 149:156823d33999 1331 * | | |0 = Control Bits unchanged.
<> 149:156823d33999 1332 * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
<> 149:156823d33999 1333 * |[5] |Arb |Access Arbitration Bits
<> 149:156823d33999 1334 * | | |Write Operation:
<> 149:156823d33999 1335 * | | |0 = Arbitration bits unchanged.
<> 149:156823d33999 1336 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
<> 149:156823d33999 1337 * | | |Read Operation:
<> 149:156823d33999 1338 * | | |0 = Arbitration bits unchanged.
<> 149:156823d33999 1339 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
<> 149:156823d33999 1340 * |[6] |Mask |Access Mask Bits
<> 149:156823d33999 1341 * | | |Write Operation:
<> 149:156823d33999 1342 * | | |0 = Mask bits unchanged.
<> 149:156823d33999 1343 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
<> 149:156823d33999 1344 * | | |Read Operation:
<> 149:156823d33999 1345 * | | |0 = Mask bits unchanged.
<> 149:156823d33999 1346 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
<> 149:156823d33999 1347 * |[7] |WR_RD |Write / Read Mode
<> 149:156823d33999 1348 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
<> 149:156823d33999 1349 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
<> 149:156823d33999 1350 * @var CAN_IF_T::MASK1
<> 149:156823d33999 1351 * Offset: 0x28, 0x88 IFn Mask 1 Register
<> 149:156823d33999 1352 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1353 * |Bits |Field |Descriptions
<> 149:156823d33999 1354 * | :----: | :----: | :---- |
<> 149:156823d33999 1355 * |[15:0] |Msk[15:0] |Identifier Mask 15-0
<> 149:156823d33999 1356 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
<> 149:156823d33999 1357 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
<> 149:156823d33999 1358 * @var CAN_IF_T::MASK2
<> 149:156823d33999 1359 * Offset: 0x2C, 0x8C IFn Mask 2 Register
<> 149:156823d33999 1360 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1361 * |Bits |Field |Descriptions
<> 149:156823d33999 1362 * | :----: | :----: | :---- |
<> 149:156823d33999 1363 * |[12:0] |Msk[28:16]|Identifier Mask 28-16
<> 149:156823d33999 1364 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
<> 149:156823d33999 1365 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
<> 149:156823d33999 1366 * |[14] |MDir |Mask Message Direction
<> 149:156823d33999 1367 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
<> 149:156823d33999 1368 * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
<> 149:156823d33999 1369 * |[15] |MXtd |Mask Extended Identifier
<> 149:156823d33999 1370 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
<> 149:156823d33999 1371 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
<> 149:156823d33999 1372 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
<> 149:156823d33999 1373 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
<> 149:156823d33999 1374 * @var CAN_IF_T::ARB1
<> 149:156823d33999 1375 * Offset: 0x30, 0x90 IFn Arbitration 1 Register
<> 149:156823d33999 1376 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1377 * |Bits |Field |Descriptions
<> 149:156823d33999 1378 * | :----: | :----: | :---- |
<> 149:156823d33999 1379 * |[15:0] |ID[15:0] |Message Identifier 15-0
<> 149:156823d33999 1380 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
<> 149:156823d33999 1381 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
<> 149:156823d33999 1382 * @var CAN_IF_T::ARB2
<> 149:156823d33999 1383 * Offset: 0x34, 0x94 IFn Arbitration 2 Register
<> 149:156823d33999 1384 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1385 * |Bits |Field |Descriptions
<> 149:156823d33999 1386 * | :----: | :----: | :---- |
<> 149:156823d33999 1387 * |[12:0] |ID[28:16] |Message Identifier 28-16
<> 149:156823d33999 1388 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
<> 149:156823d33999 1389 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
<> 149:156823d33999 1390 * |[13] |Dir |Message Direction
<> 149:156823d33999 1391 * | | |0 = Direction is receive.
<> 149:156823d33999 1392 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
<> 149:156823d33999 1393 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
<> 149:156823d33999 1394 * | | |1 = Direction is transmit.
<> 149:156823d33999 1395 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
<> 149:156823d33999 1396 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
<> 149:156823d33999 1397 * |[14] |Xtd |Extended Identifier
<> 149:156823d33999 1398 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
<> 149:156823d33999 1399 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
<> 149:156823d33999 1400 * |[15] |MsgVal |Message Valid
<> 149:156823d33999 1401 * | | |0 = The Message Object is ignored by the Message Handler.
<> 149:156823d33999 1402 * | | |1 = The Message Object is configured and should be considered by the Message Handler.
<> 149:156823d33999 1403 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
<> 149:156823d33999 1404 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
<> 149:156823d33999 1405 * @var CAN_IF_T::MCON
<> 149:156823d33999 1406 * Offset: 0x38, 0x98 IFn Message Control Register
<> 149:156823d33999 1407 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1408 * |Bits |Field |Descriptions
<> 149:156823d33999 1409 * | :----: | :----: | :---- |
<> 149:156823d33999 1410 * |[3:0] |DLC |Data Length Code
<> 149:156823d33999 1411 * | | |0-8: Data Frame has 0-8 data bytes.
<> 149:156823d33999 1412 * | | |9-15: Data Frame has 8 data bytes
<> 149:156823d33999 1413 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
<> 149:156823d33999 1414 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
<> 149:156823d33999 1415 * | | |Data 0: 1st data byte of a CAN Data Frame
<> 149:156823d33999 1416 * | | |Data 1: 2nd data byte of a CAN Data Frame
<> 149:156823d33999 1417 * | | |Data 2: 3rd data byte of a CAN Data Frame
<> 149:156823d33999 1418 * | | |Data 3: 4th data byte of a CAN Data Frame
<> 149:156823d33999 1419 * | | |Data 4: 5th data byte of a CAN Data Frame
<> 149:156823d33999 1420 * | | |Data 5: 6th data byte of a CAN Data Frame
<> 149:156823d33999 1421 * | | |Data 6: 7th data byte of a CAN Data Frame
<> 149:156823d33999 1422 * | | |Data 7 : 8th data byte of a CAN Data Frame
<> 149:156823d33999 1423 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
<> 149:156823d33999 1424 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
<> 149:156823d33999 1425 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
<> 149:156823d33999 1426 * |[7] |EoB |End Of Buffer
<> 149:156823d33999 1427 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
<> 149:156823d33999 1428 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
<> 149:156823d33999 1429 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
<> 149:156823d33999 1430 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
<> 149:156823d33999 1431 * |[8] |TxRqst |Transmit Request
<> 149:156823d33999 1432 * | | |0 = This Message Object is not waiting for transmission.
<> 149:156823d33999 1433 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 149:156823d33999 1434 * |[9] |RmtEn |Remote Enable Control
<> 149:156823d33999 1435 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
<> 149:156823d33999 1436 * | | |1 = At the reception of a Remote Frame, TxRqst is set.
<> 149:156823d33999 1437 * |[10] |RxIE |Receive Interrupt Enable Control
<> 149:156823d33999 1438 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
<> 149:156823d33999 1439 * | | |1 = IntPnd will be set after a successful reception of a frame.
<> 149:156823d33999 1440 * |[11] |TxIE |Transmit Interrupt Enable Control
<> 149:156823d33999 1441 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
<> 149:156823d33999 1442 * | | |1 = IntPnd will be set after a successful transmission of a frame.
<> 149:156823d33999 1443 * |[12] |UMask |Use Acceptance Mask
<> 149:156823d33999 1444 * | | |0 = Mask ignored.
<> 149:156823d33999 1445 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
<> 149:156823d33999 1446 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
<> 149:156823d33999 1447 * |[13] |IntPnd |Interrupt Pending
<> 149:156823d33999 1448 * | | |0 = This message object is not the source of an interrupt.
<> 149:156823d33999 1449 * | | |1 = This message object is the source of an interrupt.
<> 149:156823d33999 1450 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
<> 149:156823d33999 1451 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
<> 149:156823d33999 1452 * | | |0 = No message lost since last time this bit was reset by the CPU.
<> 149:156823d33999 1453 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
<> 149:156823d33999 1454 * |[15] |NewDat |New Data
<> 149:156823d33999 1455 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
<> 149:156823d33999 1456 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 149:156823d33999 1457 * @var CAN_IF_T::DAT_A1
<> 149:156823d33999 1458 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
<> 149:156823d33999 1459 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1460 * |Bits |Field |Descriptions
<> 149:156823d33999 1461 * | :----: | :----: | :---- |
<> 149:156823d33999 1462 * |[7:0] |Data0 |Data Byte 0
<> 149:156823d33999 1463 * | | |1st data byte of a CAN Data Frame
<> 149:156823d33999 1464 * |[15:8] |Data1 |Data Byte 1
<> 149:156823d33999 1465 * | | |2nd data byte of a CAN Data Frame
<> 149:156823d33999 1466 * @var CAN_IF_T::DAT_A2
<> 149:156823d33999 1467 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
<> 149:156823d33999 1468 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1469 * |Bits |Field |Descriptions
<> 149:156823d33999 1470 * | :----: | :----: | :---- |
<> 149:156823d33999 1471 * |[7:0] |Data2 |Data Byte 2
<> 149:156823d33999 1472 * | | |3rd data byte of CAN Data Frame
<> 149:156823d33999 1473 * |[15:8] |Data3 |Data Byte 3
<> 149:156823d33999 1474 * | | |4th data byte of CAN Data Frame
<> 149:156823d33999 1475 * @var CAN_IF_T::DAT_B1
<> 149:156823d33999 1476 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
<> 149:156823d33999 1477 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1478 * |Bits |Field |Descriptions
<> 149:156823d33999 1479 * | :----: | :----: | :---- |
<> 149:156823d33999 1480 * |[7:0] |Data4 |Data Byte 4
<> 149:156823d33999 1481 * | | |5th data byte of CAN Data Frame
<> 149:156823d33999 1482 * |[15:8] |Data5 |Data Byte 5
<> 149:156823d33999 1483 * | | |6th data byte of CAN Data Frame
<> 149:156823d33999 1484 * @var CAN_IF_T::DAT_B2
<> 149:156823d33999 1485 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
<> 149:156823d33999 1486 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1487 * |Bits |Field |Descriptions
<> 149:156823d33999 1488 * | :----: | :----: | :---- |
<> 149:156823d33999 1489 * |[7:0] |Data6 |Data Byte 6
<> 149:156823d33999 1490 * | | |7th data byte of CAN Data Frame.
<> 149:156823d33999 1491 * |[15:8] |Data7 |Data Byte 7
<> 149:156823d33999 1492 * | | |8th data byte of CAN Data Frame.
<> 149:156823d33999 1493 */
<> 149:156823d33999 1494
<> 149:156823d33999 1495 __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
<> 149:156823d33999 1496 __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
<> 149:156823d33999 1497 __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
<> 149:156823d33999 1498 __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
<> 149:156823d33999 1499 __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
<> 149:156823d33999 1500 __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
<> 149:156823d33999 1501 __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
<> 149:156823d33999 1502 __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
<> 149:156823d33999 1503 __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
<> 149:156823d33999 1504 __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
<> 149:156823d33999 1505 __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
<> 149:156823d33999 1506 __I uint32_t RESERVE0[13];
<> 149:156823d33999 1507
<> 149:156823d33999 1508 } CAN_IF_T;
<> 149:156823d33999 1509
<> 149:156823d33999 1510
<> 149:156823d33999 1511
<> 149:156823d33999 1512
<> 149:156823d33999 1513 typedef struct
<> 149:156823d33999 1514 {
<> 149:156823d33999 1515
<> 149:156823d33999 1516
<> 149:156823d33999 1517
<> 149:156823d33999 1518 /**
<> 149:156823d33999 1519 * @var CAN_T::CON
<> 149:156823d33999 1520 * Offset: 0x00 Control Register
<> 149:156823d33999 1521 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1522 * |Bits |Field |Descriptions
<> 149:156823d33999 1523 * | :----: | :----: | :---- |
<> 149:156823d33999 1524 * |[0] |Init |Init Initialization
<> 149:156823d33999 1525 * | | |0 = Normal Operation.
<> 149:156823d33999 1526 * | | |1 = Initialization is started.
<> 149:156823d33999 1527 * |[1] |IE |Module Interrupt Enable Control
<> 149:156823d33999 1528 * | | |0 = Disabled.
<> 149:156823d33999 1529 * | | |1 = Enabled.
<> 149:156823d33999 1530 * |[2] |SIE |Status Change Interrupt Enable Control
<> 149:156823d33999 1531 * | | |0 = Disabled - No Status Change Interrupt will be generated.
<> 149:156823d33999 1532 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
<> 149:156823d33999 1533 * |[3] |EIE |Error Interrupt Enable Control
<> 149:156823d33999 1534 * | | |0 = Disabled - No Error Status Interrupt will be generated.
<> 149:156823d33999 1535 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
<> 149:156823d33999 1536 * |[5] |DAR |Automatic Re-Transmission Disable Control
<> 149:156823d33999 1537 * | | |0 = Automatic Retransmission of disturbed messages enabled.
<> 149:156823d33999 1538 * | | |1 = Automatic Retransmission disabled.
<> 149:156823d33999 1539 * |[6] |CCE |Configuration Change Enable Control
<> 149:156823d33999 1540 * | | |0 = No write access to the Bit Timing Register.
<> 149:156823d33999 1541 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
<> 149:156823d33999 1542 * |[7] |Test |Test Mode Enable Control
<> 149:156823d33999 1543 * | | |0 = Normal Operation.
<> 149:156823d33999 1544 * | | |1 = Test Mode.
<> 149:156823d33999 1545 * @var CAN_T::STATUS
<> 149:156823d33999 1546 * Offset: 0x04 Status Register
<> 149:156823d33999 1547 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1548 * |Bits |Field |Descriptions
<> 149:156823d33999 1549 * | :----: | :----: | :---- |
<> 149:156823d33999 1550 * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
<> 149:156823d33999 1551 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
<> 149:156823d33999 1552 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
<> 149:156823d33999 1553 * | | |The unused code '7' may be written by the CPU to check for updates.
<> 149:156823d33999 1554 * | | |The following table describes the error code.
<> 149:156823d33999 1555 * |[3] |TxOK |Transmitted A Message Successfully
<> 149:156823d33999 1556 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
<> 149:156823d33999 1557 * | | |This bit is never reset by the CAN Core.
<> 149:156823d33999 1558 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
<> 149:156823d33999 1559 * |[4] |RxOK |Received A Message Successfully
<> 149:156823d33999 1560 * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
<> 149:156823d33999 1561 * | | |This bit is never reset by the CAN Core.
<> 149:156823d33999 1562 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
<> 149:156823d33999 1563 * |[5] |EPass |Error Passive (Read Only)
<> 149:156823d33999 1564 * | | |0 = The CAN Core is error active.
<> 149:156823d33999 1565 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
<> 149:156823d33999 1566 * |[6] |EWarn |Error Warning Status (Read Only)
<> 149:156823d33999 1567 * | | |0 = Both error counters are below the error warning limit of 96.
<> 149:156823d33999 1568 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
<> 149:156823d33999 1569 * |[7] |BOff |Bus-Off Status (Read Only)
<> 149:156823d33999 1570 * | | |0 = The CAN module is not in bus-off state.
<> 149:156823d33999 1571 * | | |1 = The CAN module is in bus-off state.
<> 149:156823d33999 1572 * @var CAN_T::ERR
<> 149:156823d33999 1573 * Offset: 0x08 Error Counter Register
<> 149:156823d33999 1574 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1575 * |Bits |Field |Descriptions
<> 149:156823d33999 1576 * | :----: | :----: | :---- |
<> 149:156823d33999 1577 * |[7:0] |TEC |Transmit Error Counter
<> 149:156823d33999 1578 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
<> 149:156823d33999 1579 * |[14:8] |REC |Receive Error Counter
<> 149:156823d33999 1580 * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
<> 149:156823d33999 1581 * |[15] |RP |Receive Error Passive
<> 149:156823d33999 1582 * | | |0 = The Receive Error Counter is below the error passive level.
<> 149:156823d33999 1583 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
<> 149:156823d33999 1584 * @var CAN_T::BTIME
<> 149:156823d33999 1585 * Offset: 0x0C Bit Timing Register
<> 149:156823d33999 1586 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1587 * |Bits |Field |Descriptions
<> 149:156823d33999 1588 * | :----: | :----: | :---- |
<> 149:156823d33999 1589 * |[5:0] |BRP |Baud Rate Prescaler
<> 149:156823d33999 1590 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
<> 149:156823d33999 1591 * | | |The bit time is built up from a multiple of this quanta.
<> 149:156823d33999 1592 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
<> 149:156823d33999 1593 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 149:156823d33999 1594 * |[7:6] |SJW |(Re)Synchronization Jump Width
<> 149:156823d33999 1595 * | | |0x0-0x3: Valid programmed values are [0 ... 3].
<> 149:156823d33999 1596 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 149:156823d33999 1597 * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
<> 149:156823d33999 1598 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
<> 149:156823d33999 1599 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
<> 149:156823d33999 1600 * |[14:12] |TSeg2 |Time Segment After Sample Point
<> 149:156823d33999 1601 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
<> 149:156823d33999 1602 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 149:156823d33999 1603 * @var CAN_T::IIDR
<> 149:156823d33999 1604 * Offset: 0x10 Interrupt Identifier Register
<> 149:156823d33999 1605 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1606 * |Bits |Field |Descriptions
<> 149:156823d33999 1607 * | :----: | :----: | :---- |
<> 149:156823d33999 1608 * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
<> 149:156823d33999 1609 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
<> 149:156823d33999 1610 * | | |An interrupt remains pending until the application software has cleared it.
<> 149:156823d33999 1611 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
<> 149:156823d33999 1612 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
<> 149:156823d33999 1613 * | | |The Status Interrupt has the highest priority.
<> 149:156823d33999 1614 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
<> 149:156823d33999 1615 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
<> 149:156823d33999 1616 * | | |The Status Interrupt is cleared by reading the Status Register.
<> 149:156823d33999 1617 * @var CAN_T::TEST
<> 149:156823d33999 1618 * Offset: 0x14 Test Register (Register Map Note 1)
<> 149:156823d33999 1619 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1620 * |Bits |Field |Descriptions
<> 149:156823d33999 1621 * | :----: | :----: | :---- |
<> 149:156823d33999 1622 * |[1:0] |Res |Reserved
<> 149:156823d33999 1623 * | | |There are reserved bits.
<> 149:156823d33999 1624 * | | |These bits are always read as '0' and must always be written with '0'.
<> 149:156823d33999 1625 * |[2] |Basic |Basic Mode
<> 149:156823d33999 1626 * | | |0 = Basic Mode disabled.
<> 149:156823d33999 1627 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
<> 149:156823d33999 1628 * |[3] |Silent |Silent Mode
<> 149:156823d33999 1629 * | | |0 = Normal operation.
<> 149:156823d33999 1630 * | | |1 = The module is in Silent Mode.
<> 149:156823d33999 1631 * |[4] |LBack |Loop Back Mode Enable Control
<> 149:156823d33999 1632 * | | |0 = Loop Back Mode is disabled.
<> 149:156823d33999 1633 * | | |1 = Loop Back Mode is enabled.
<> 149:156823d33999 1634 * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
<> 149:156823d33999 1635 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
<> 149:156823d33999 1636 * | | |01 = Sample Point can be monitored at CAN_TX pin.
<> 149:156823d33999 1637 * | | |10 = CAN_TX pin drives a dominant ('0') value.
<> 149:156823d33999 1638 * | | |11 = CAN_TX pin drives a recessive ('1') value.
<> 149:156823d33999 1639 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
<> 149:156823d33999 1640 * | | |0 = The CAN bus is dominant (CAN_RX = '0').
<> 149:156823d33999 1641 * | | |1 = The CAN bus is recessive (CAN_RX = '1').
<> 149:156823d33999 1642 * @var CAN_T::BRPE
<> 149:156823d33999 1643 * Offset: 0x18 Baud Rate Prescaler Extension Register
<> 149:156823d33999 1644 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1645 * |Bits |Field |Descriptions
<> 149:156823d33999 1646 * | :----: | :----: | :---- |
<> 149:156823d33999 1647 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
<> 149:156823d33999 1648 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
<> 149:156823d33999 1649 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
<> 149:156823d33999 1650 * @var CAN_T::IF
<> 149:156823d33999 1651 * Offset: 0x20~0xFC CAN Interface Registers
<> 149:156823d33999 1652 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1653 * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
<> 149:156823d33999 1654 *
<> 149:156823d33999 1655 * @var CAN_T::TXREQ1
<> 149:156823d33999 1656 * Offset: 0x100 Transmission Request Register 1
<> 149:156823d33999 1657 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1658 * |Bits |Field |Descriptions
<> 149:156823d33999 1659 * | :----: | :----: | :---- |
<> 149:156823d33999 1660 * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
<> 149:156823d33999 1661 * | | |0 = This Message Object is not waiting for transmission.
<> 149:156823d33999 1662 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 149:156823d33999 1663 * | | |These bits are read only.
<> 149:156823d33999 1664 * @var CAN_T::TXREQ2
<> 149:156823d33999 1665 * Offset: 0x104 Transmission Request Register 2
<> 149:156823d33999 1666 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1667 * |Bits |Field |Descriptions
<> 149:156823d33999 1668 * | :----: | :----: | :---- |
<> 149:156823d33999 1669 * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
<> 149:156823d33999 1670 * | | |0 = This Message Object is not waiting for transmission.
<> 149:156823d33999 1671 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 149:156823d33999 1672 * | | |These bits are read only.
<> 149:156823d33999 1673 * @var CAN_T::NDAT1
<> 149:156823d33999 1674 * Offset: 0x120 New Data Register 1
<> 149:156823d33999 1675 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1676 * |Bits |Field |Descriptions
<> 149:156823d33999 1677 * | :----: | :----: | :---- |
<> 149:156823d33999 1678 * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
<> 149:156823d33999 1679 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
<> 149:156823d33999 1680 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 149:156823d33999 1681 * @var CAN_T::NDAT2
<> 149:156823d33999 1682 * Offset: 0x124 New Data Register 2
<> 149:156823d33999 1683 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1684 * |Bits |Field |Descriptions
<> 149:156823d33999 1685 * | :----: | :----: | :---- |
<> 149:156823d33999 1686 * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
<> 149:156823d33999 1687 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
<> 149:156823d33999 1688 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 149:156823d33999 1689 * @var CAN_T::IPND1
<> 149:156823d33999 1690 * Offset: 0x140 Interrupt Pending Register 1
<> 149:156823d33999 1691 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1692 * |Bits |Field |Descriptions
<> 149:156823d33999 1693 * | :----: | :----: | :---- |
<> 149:156823d33999 1694 * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
<> 149:156823d33999 1695 * | | |0 = This message object is not the source of an interrupt.
<> 149:156823d33999 1696 * | | |1 = This message object is the source of an interrupt.
<> 149:156823d33999 1697 * @var CAN_T::IPND2
<> 149:156823d33999 1698 * Offset: 0x144 Interrupt Pending Register 2
<> 149:156823d33999 1699 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1700 * |Bits |Field |Descriptions
<> 149:156823d33999 1701 * | :----: | :----: | :---- |
<> 149:156823d33999 1702 * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
<> 149:156823d33999 1703 * | | |0 = This message object is not the source of an interrupt.
<> 149:156823d33999 1704 * | | |1 = This message object is the source of an interrupt.
<> 149:156823d33999 1705 * @var CAN_T::MVLD1
<> 149:156823d33999 1706 * Offset: 0x160 Message Valid Register 1
<> 149:156823d33999 1707 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1708 * |Bits |Field |Descriptions
<> 149:156823d33999 1709 * | :----: | :----: | :---- |
<> 149:156823d33999 1710 * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
<> 149:156823d33999 1711 * | | |0 = This Message Object is ignored by the Message Handler.
<> 149:156823d33999 1712 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
<> 149:156823d33999 1713 * | | |Ex.
<> 149:156823d33999 1714 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
<> 149:156823d33999 1715 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
<> 149:156823d33999 1716 * @var CAN_T::MVLD2
<> 149:156823d33999 1717 * Offset: 0x164 Message Valid Register 2
<> 149:156823d33999 1718 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1719 * |Bits |Field |Descriptions
<> 149:156823d33999 1720 * | :----: | :----: | :---- |
<> 149:156823d33999 1721 * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
<> 149:156823d33999 1722 * | | |0 = This Message Object is ignored by the Message Handler.
<> 149:156823d33999 1723 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
<> 149:156823d33999 1724 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
<> 149:156823d33999 1725 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
<> 149:156823d33999 1726 * @var CAN_T::WU_EN
<> 149:156823d33999 1727 * Offset: 0x168 Wake-up Enable Register
<> 149:156823d33999 1728 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1729 * |Bits |Field |Descriptions
<> 149:156823d33999 1730 * | :----: | :----: | :---- |
<> 149:156823d33999 1731 * |[0] |WAKUP_EN |Wake-Up Enable Control
<> 149:156823d33999 1732 * | | |0 = The wake-up function Disabled.
<> 149:156823d33999 1733 * | | |1 = The wake-up function Enabled.
<> 149:156823d33999 1734 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
<> 149:156823d33999 1735 * @var CAN_T::WU_STATUS
<> 149:156823d33999 1736 * Offset: 0x16C Wake-up Status Register
<> 149:156823d33999 1737 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 1738 * |Bits |Field |Descriptions
<> 149:156823d33999 1739 * | :----: | :----: | :---- |
<> 149:156823d33999 1740 * |[0] |WAKUP_STS |Wake-Up Status
<> 149:156823d33999 1741 * | | |0 = No wake-up event occurred.
<> 149:156823d33999 1742 * | | |1 = Wake-up event occurred.
<> 149:156823d33999 1743 * | | |Note: This bit can be cleared by writing '0'.
<> 149:156823d33999 1744 */
<> 149:156823d33999 1745
<> 149:156823d33999 1746 __IO uint32_t CON; /* Offset: 0x00 Control Register */
<> 149:156823d33999 1747 __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
<> 149:156823d33999 1748 __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
<> 149:156823d33999 1749 __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
<> 149:156823d33999 1750 __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
<> 149:156823d33999 1751 __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
<> 149:156823d33999 1752 __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
<> 149:156823d33999 1753 __I uint32_t RESERVE0[1];
<> 149:156823d33999 1754 __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
<> 149:156823d33999 1755 __I uint32_t RESERVE1[8];
<> 149:156823d33999 1756 __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
<> 149:156823d33999 1757 __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
<> 149:156823d33999 1758 __I uint32_t RESERVE3[6];
<> 149:156823d33999 1759 __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
<> 149:156823d33999 1760 __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
<> 149:156823d33999 1761 __I uint32_t RESERVE4[6];
<> 149:156823d33999 1762 __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
<> 149:156823d33999 1763 __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
<> 149:156823d33999 1764 __I uint32_t RESERVE5[6];
<> 149:156823d33999 1765 __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
<> 149:156823d33999 1766 __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
<> 149:156823d33999 1767 __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
<> 149:156823d33999 1768 __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
<> 149:156823d33999 1769
<> 149:156823d33999 1770 } CAN_T;
<> 149:156823d33999 1771
<> 149:156823d33999 1772
<> 149:156823d33999 1773
<> 149:156823d33999 1774 /**
<> 149:156823d33999 1775 @addtogroup CAN_CONST CAN Bit Field Definition
<> 149:156823d33999 1776 Constant Definitions for CAN Controller
<> 149:156823d33999 1777 @{ */
<> 149:156823d33999 1778 /* CAN CON Bit Field Definitions */
<> 149:156823d33999 1779 #define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
<> 149:156823d33999 1780 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
<> 149:156823d33999 1781
<> 149:156823d33999 1782 #define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
<> 149:156823d33999 1783 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
<> 149:156823d33999 1784
<> 149:156823d33999 1785 #define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
<> 149:156823d33999 1786 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
<> 149:156823d33999 1787
<> 149:156823d33999 1788 #define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
<> 149:156823d33999 1789 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
<> 149:156823d33999 1790
<> 149:156823d33999 1791 #define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
<> 149:156823d33999 1792 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
<> 149:156823d33999 1793
<> 149:156823d33999 1794 #define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
<> 149:156823d33999 1795 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
<> 149:156823d33999 1796
<> 149:156823d33999 1797 #define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
<> 149:156823d33999 1798 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
<> 149:156823d33999 1799
<> 149:156823d33999 1800 /* CAN STATUS Bit Field Definitions */
<> 149:156823d33999 1801 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
<> 149:156823d33999 1802 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
<> 149:156823d33999 1803
<> 149:156823d33999 1804 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
<> 149:156823d33999 1805 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
<> 149:156823d33999 1806
<> 149:156823d33999 1807 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
<> 149:156823d33999 1808 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
<> 149:156823d33999 1809
<> 149:156823d33999 1810 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
<> 149:156823d33999 1811 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
<> 149:156823d33999 1812
<> 149:156823d33999 1813 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
<> 149:156823d33999 1814 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
<> 149:156823d33999 1815
<> 149:156823d33999 1816 #define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
<> 149:156823d33999 1817 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
<> 149:156823d33999 1818
<> 149:156823d33999 1819 /* CAN ERR Bit Field Definitions */
<> 149:156823d33999 1820 #define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
<> 149:156823d33999 1821 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
<> 149:156823d33999 1822
<> 149:156823d33999 1823 #define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
<> 149:156823d33999 1824 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
<> 149:156823d33999 1825
<> 149:156823d33999 1826 #define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
<> 149:156823d33999 1827 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
<> 149:156823d33999 1828
<> 149:156823d33999 1829 /* CAN BTIME Bit Field Definitions */
<> 149:156823d33999 1830 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
<> 149:156823d33999 1831 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
<> 149:156823d33999 1832
<> 149:156823d33999 1833 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
<> 149:156823d33999 1834 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
<> 149:156823d33999 1835
<> 149:156823d33999 1836 #define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
<> 149:156823d33999 1837 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
<> 149:156823d33999 1838
<> 149:156823d33999 1839 #define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
<> 149:156823d33999 1840 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
<> 149:156823d33999 1841
<> 149:156823d33999 1842 /* CAN IIDR Bit Field Definitions */
<> 149:156823d33999 1843 #define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
<> 149:156823d33999 1844 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
<> 149:156823d33999 1845
<> 149:156823d33999 1846 /* CAN TEST Bit Field Definitions */
<> 149:156823d33999 1847 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
<> 149:156823d33999 1848 #define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
<> 149:156823d33999 1849
<> 149:156823d33999 1850 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
<> 149:156823d33999 1851 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
<> 149:156823d33999 1852
<> 149:156823d33999 1853 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
<> 149:156823d33999 1854 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
<> 149:156823d33999 1855
<> 149:156823d33999 1856 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
<> 149:156823d33999 1857 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
<> 149:156823d33999 1858
<> 149:156823d33999 1859 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
<> 149:156823d33999 1860 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
<> 149:156823d33999 1861
<> 149:156823d33999 1862 /* CAN BPRE Bit Field Definitions */
<> 149:156823d33999 1863 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
<> 149:156823d33999 1864 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
<> 149:156823d33999 1865
<> 149:156823d33999 1866 /* CAN IFn_CREQ Bit Field Definitions */
<> 149:156823d33999 1867 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
<> 149:156823d33999 1868 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
<> 149:156823d33999 1869
<> 149:156823d33999 1870 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
<> 149:156823d33999 1871 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
<> 149:156823d33999 1872
<> 149:156823d33999 1873 /* CAN IFn_CMASK Bit Field Definitions */
<> 149:156823d33999 1874 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
<> 149:156823d33999 1875 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
<> 149:156823d33999 1876
<> 149:156823d33999 1877 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
<> 149:156823d33999 1878 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
<> 149:156823d33999 1879
<> 149:156823d33999 1880 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
<> 149:156823d33999 1881 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
<> 149:156823d33999 1882
<> 149:156823d33999 1883 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
<> 149:156823d33999 1884 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
<> 149:156823d33999 1885
<> 149:156823d33999 1886 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
<> 149:156823d33999 1887 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
<> 149:156823d33999 1888
<> 149:156823d33999 1889 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
<> 149:156823d33999 1890 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
<> 149:156823d33999 1891
<> 149:156823d33999 1892 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
<> 149:156823d33999 1893 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
<> 149:156823d33999 1894
<> 149:156823d33999 1895 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
<> 149:156823d33999 1896 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
<> 149:156823d33999 1897
<> 149:156823d33999 1898 /* CAN IFn_MASK1 Bit Field Definitions */
<> 149:156823d33999 1899 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
<> 149:156823d33999 1900 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
<> 149:156823d33999 1901
<> 149:156823d33999 1902 /* CAN IFn_MASK2 Bit Field Definitions */
<> 149:156823d33999 1903 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
<> 149:156823d33999 1904 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
<> 149:156823d33999 1905
<> 149:156823d33999 1906 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
<> 149:156823d33999 1907 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
<> 149:156823d33999 1908
<> 149:156823d33999 1909 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
<> 149:156823d33999 1910 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
<> 149:156823d33999 1911
<> 149:156823d33999 1912 /* CAN IFn_ARB1 Bit Field Definitions */
<> 149:156823d33999 1913 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
<> 149:156823d33999 1914 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
<> 149:156823d33999 1915
<> 149:156823d33999 1916 /* CAN IFn_ARB2 Bit Field Definitions */
<> 149:156823d33999 1917 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
<> 149:156823d33999 1918 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
<> 149:156823d33999 1919
<> 149:156823d33999 1920 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
<> 149:156823d33999 1921 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
<> 149:156823d33999 1922
<> 149:156823d33999 1923 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
<> 149:156823d33999 1924 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
<> 149:156823d33999 1925
<> 149:156823d33999 1926 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
<> 149:156823d33999 1927 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
<> 149:156823d33999 1928
<> 149:156823d33999 1929 /* CAN IFn_MCON Bit Field Definitions */
<> 149:156823d33999 1930 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
<> 149:156823d33999 1931 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
<> 149:156823d33999 1932
<> 149:156823d33999 1933 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
<> 149:156823d33999 1934 #define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
<> 149:156823d33999 1935
<> 149:156823d33999 1936 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
<> 149:156823d33999 1937 #define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
<> 149:156823d33999 1938
<> 149:156823d33999 1939 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
<> 149:156823d33999 1940 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
<> 149:156823d33999 1941
<> 149:156823d33999 1942 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
<> 149:156823d33999 1943 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
<> 149:156823d33999 1944
<> 149:156823d33999 1945 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
<> 149:156823d33999 1946 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
<> 149:156823d33999 1947
<> 149:156823d33999 1948 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
<> 149:156823d33999 1949 #define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
<> 149:156823d33999 1950
<> 149:156823d33999 1951 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
<> 149:156823d33999 1952 #define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
<> 149:156823d33999 1953
<> 149:156823d33999 1954 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
<> 149:156823d33999 1955 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
<> 149:156823d33999 1956
<> 149:156823d33999 1957 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
<> 149:156823d33999 1958 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
<> 149:156823d33999 1959
<> 149:156823d33999 1960 /* CAN IFn_DATA_A1 Bit Field Definitions */
<> 149:156823d33999 1961 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
<> 149:156823d33999 1962 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
<> 149:156823d33999 1963
<> 149:156823d33999 1964 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
<> 149:156823d33999 1965 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
<> 149:156823d33999 1966
<> 149:156823d33999 1967 /* CAN IFn_DATA_A2 Bit Field Definitions */
<> 149:156823d33999 1968 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
<> 149:156823d33999 1969 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
<> 149:156823d33999 1970
<> 149:156823d33999 1971 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
<> 149:156823d33999 1972 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
<> 149:156823d33999 1973
<> 149:156823d33999 1974 /* CAN IFn_DATA_B1 Bit Field Definitions */
<> 149:156823d33999 1975 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
<> 149:156823d33999 1976 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
<> 149:156823d33999 1977
<> 149:156823d33999 1978 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
<> 149:156823d33999 1979 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
<> 149:156823d33999 1980
<> 149:156823d33999 1981 /* CAN IFn_DATA_B2 Bit Field Definitions */
<> 149:156823d33999 1982 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
<> 149:156823d33999 1983 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
<> 149:156823d33999 1984
<> 149:156823d33999 1985 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
<> 149:156823d33999 1986 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
<> 149:156823d33999 1987
<> 149:156823d33999 1988 /* CAN IFn_TXRQST1 Bit Field Definitions */
<> 149:156823d33999 1989 #define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
<> 149:156823d33999 1990 #define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
<> 149:156823d33999 1991
<> 149:156823d33999 1992 /* CAN IFn_TXRQST2 Bit Field Definitions */
<> 149:156823d33999 1993 #define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
<> 149:156823d33999 1994 #define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
<> 149:156823d33999 1995
<> 149:156823d33999 1996 /* CAN IFn_NDAT1 Bit Field Definitions */
<> 149:156823d33999 1997 #define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
<> 149:156823d33999 1998 #define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
<> 149:156823d33999 1999
<> 149:156823d33999 2000 /* CAN IFn_NDAT2 Bit Field Definitions */
<> 149:156823d33999 2001 #define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
<> 149:156823d33999 2002 #define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
<> 149:156823d33999 2003
<> 149:156823d33999 2004 /* CAN IFn_IPND1 Bit Field Definitions */
<> 149:156823d33999 2005 #define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
<> 149:156823d33999 2006 #define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
<> 149:156823d33999 2007
<> 149:156823d33999 2008 /* CAN IFn_IPND2 Bit Field Definitions */
<> 149:156823d33999 2009 #define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
<> 149:156823d33999 2010 #define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
<> 149:156823d33999 2011
<> 149:156823d33999 2012 /* CAN IFn_MVLD1 Bit Field Definitions */
<> 149:156823d33999 2013 #define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
<> 149:156823d33999 2014 #define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
<> 149:156823d33999 2015
<> 149:156823d33999 2016 /* CAN IFn_MVLD2 Bit Field Definitions */
<> 149:156823d33999 2017 #define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
<> 149:156823d33999 2018 #define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
<> 149:156823d33999 2019
<> 149:156823d33999 2020 /* CAN WUEN Bit Field Definitions */
<> 149:156823d33999 2021 #define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
<> 149:156823d33999 2022 #define CAN_WUEN_WAKUP_EN_Msk (0x1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
<> 149:156823d33999 2023
<> 149:156823d33999 2024 /* CAN WUSTATUS Bit Field Definitions */
<> 149:156823d33999 2025 #define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
<> 149:156823d33999 2026 #define CAN_WUSTATUS_WAKUP_STS_Msk (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
<> 149:156823d33999 2027
<> 149:156823d33999 2028
<> 149:156823d33999 2029 /**@}*/ /* CAN_CONST */
<> 149:156823d33999 2030 /**@}*/ /* end of CAN register group */
<> 149:156823d33999 2031
<> 149:156823d33999 2032
<> 149:156823d33999 2033 /*---------------------- System Clock Controller -------------------------*/
<> 149:156823d33999 2034 /**
<> 149:156823d33999 2035 @addtogroup CLK System Clock Controller(CLK)
<> 149:156823d33999 2036 Memory Mapped Structure for CLK Controller
<> 149:156823d33999 2037 @{ */
<> 149:156823d33999 2038
<> 149:156823d33999 2039
<> 149:156823d33999 2040 typedef struct
<> 149:156823d33999 2041 {
<> 149:156823d33999 2042
<> 149:156823d33999 2043
<> 149:156823d33999 2044
<> 149:156823d33999 2045
<> 149:156823d33999 2046 /**
<> 149:156823d33999 2047 * @var CLK_T::PWRCTL
<> 149:156823d33999 2048 * Offset: 0x00 System Power-down Control Register
<> 149:156823d33999 2049 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2050 * |Bits |Field |Descriptions
<> 149:156823d33999 2051 * | :----: | :----: | :---- |
<> 149:156823d33999 2052 * |[0] |HXTEN |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
<> 149:156823d33999 2053 * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
<> 149:156823d33999 2054 * | | |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
<> 149:156823d33999 2055 * | | |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
<> 149:156823d33999 2056 * | | |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
<> 149:156823d33999 2057 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2058 * |[1] |LXTEN |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
<> 149:156823d33999 2059 * | | |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
<> 149:156823d33999 2060 * | | |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
<> 149:156823d33999 2061 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2062 * |[2] |HIRCEN |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
<> 149:156823d33999 2063 * | | |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
<> 149:156823d33999 2064 * | | |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
<> 149:156823d33999 2065 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2066 * |[3] |LIRCEN |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
<> 149:156823d33999 2067 * | | |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
<> 149:156823d33999 2068 * | | |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
<> 149:156823d33999 2069 * |[4] |PDWKDLY |Enable The Wake-Up Delay Counter (Write Protect)
<> 149:156823d33999 2070 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
<> 149:156823d33999 2071 * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
<> 149:156823d33999 2072 * | | |0 = Clock cycles delay Disabled.
<> 149:156823d33999 2073 * | | |1 = Clock cycles delay Enabled.
<> 149:156823d33999 2074 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2075 * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
<> 149:156823d33999 2076 * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
<> 149:156823d33999 2077 * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
<> 149:156823d33999 2078 * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
<> 149:156823d33999 2079 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2080 * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
<> 149:156823d33999 2081 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
<> 149:156823d33999 2082 * | | |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
<> 149:156823d33999 2083 * | | |Note1: Write 1 to clear the bit to 0.
<> 149:156823d33999 2084 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
<> 149:156823d33999 2085 * |[7] |PDEN |System Power-Down Enable (Write Protect)
<> 149:156823d33999 2086 * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
<> 149:156823d33999 2087 * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
<> 149:156823d33999 2088 * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
<> 149:156823d33999 2089 * | | |When chip wakes up from Power-down mode, this bit is auto cleared.
<> 149:156823d33999 2090 * | | |Users need to set this bit again for next Power-down.
<> 149:156823d33999 2091 * | | |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
<> 149:156823d33999 2092 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
<> 149:156823d33999 2093 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
<> 149:156823d33999 2094 * | | |0 = Chip operating normally or chip in idle mode because of WFI command.
<> 149:156823d33999 2095 * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
<> 149:156823d33999 2096 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2097 * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
<> 149:156823d33999 2098 * | | |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
<> 149:156823d33999 2099 * | | |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
<> 149:156823d33999 2100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2101 * |[11:10] |HXTGAIN |4~24 MHz High-Speed Crystal Gain Control Bit
<> 149:156823d33999 2102 * | | |(Write Protect)
<> 149:156823d33999 2103 * | | |This is a protected register. Please refer to open lock sequence to program it.
<> 149:156823d33999 2104 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
<> 149:156823d33999 2105 * | | |If gain control is enabled, crystal will consume more power than gain control off.
<> 149:156823d33999 2106 * | | |00 = HXT frequency is lower than from 8 MHz.
<> 149:156823d33999 2107 * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
<> 149:156823d33999 2108 * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
<> 149:156823d33999 2109 * | | |11 = HXT frequency is higher than 16 MHz.
<> 149:156823d33999 2110 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2111 * |[12] |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
<> 149:156823d33999 2112 * | | |This is a protected register. Please refer to open lock sequence to program it.
<> 149:156823d33999 2113 * | | |0 = Select INV type.
<> 149:156823d33999 2114 * | | |1 = Select GM type.
<> 149:156823d33999 2115 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2116 * @var CLK_T::AHBCLK
<> 149:156823d33999 2117 * Offset: 0x04 AHB Devices Clock Enable Control Register
<> 149:156823d33999 2118 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2119 * |Bits |Field |Descriptions
<> 149:156823d33999 2120 * | :----: | :----: | :---- |
<> 149:156823d33999 2121 * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
<> 149:156823d33999 2122 * | | |0 = PDMA peripheral clock Disabled.
<> 149:156823d33999 2123 * | | |1 = PDMA peripheral clock Enabled.
<> 149:156823d33999 2124 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
<> 149:156823d33999 2125 * | | |0 = Flash ISP peripheral clock Disabled.
<> 149:156823d33999 2126 * | | |1 = Flash ISP peripheral clock Enabled.
<> 149:156823d33999 2127 * |[3] |EBICKEN |EBI Controller Clock Enable Bit
<> 149:156823d33999 2128 * | | |0 = EBI peripheral clock Disabled.
<> 149:156823d33999 2129 * | | |1 = EBI peripheral clock Enabled.
<> 149:156823d33999 2130 * |[4] |USBHCKEN |USB HOST Controller Clock Enable Bit
<> 149:156823d33999 2131 * | | |0 = USB HOST peripheral clock Disabled.
<> 149:156823d33999 2132 * | | |1 = USB HOST peripheral clock Enabled.
<> 149:156823d33999 2133 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
<> 149:156823d33999 2134 * | | |0 = CRC peripheral clock Disabled.
<> 149:156823d33999 2135 * | | |1 = CRC peripheral clock Enabled.
<> 149:156823d33999 2136 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit In IDLE Mode
<> 149:156823d33999 2137 * | | |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
<> 149:156823d33999 2138 * | | |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
<> 149:156823d33999 2139 * @var CLK_T::APBCLK0
<> 149:156823d33999 2140 * Offset: 0x08 APB Devices Clock Enable Control Register 0
<> 149:156823d33999 2141 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2142 * |Bits |Field |Descriptions
<> 149:156823d33999 2143 * | :----: | :----: | :---- |
<> 149:156823d33999 2144 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
<> 149:156823d33999 2145 * | | |0 = Watchdog Timer Clock Disabled.
<> 149:156823d33999 2146 * | | |1 = Watchdog Timer Clock Enabled.
<> 149:156823d33999 2147 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2148 * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Bit
<> 149:156823d33999 2149 * | | |This bit is used to control the RTC APB clock only.
<> 149:156823d33999 2150 * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
<> 149:156823d33999 2151 * | | |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
<> 149:156823d33999 2152 * | | |0 = RTC Clock Disabled.
<> 149:156823d33999 2153 * | | |1 = RTC Clock Enabled.
<> 149:156823d33999 2154 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
<> 149:156823d33999 2155 * | | |0 = Timer0 Clock Disabled.
<> 149:156823d33999 2156 * | | |1 = Timer0 Clock Enabled.
<> 149:156823d33999 2157 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
<> 149:156823d33999 2158 * | | |0 = Timer1 Clock Disabled.
<> 149:156823d33999 2159 * | | |1 = Timer1 Clock Enabled.
<> 149:156823d33999 2160 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
<> 149:156823d33999 2161 * | | |0 = Timer2 Clock Disabled.
<> 149:156823d33999 2162 * | | |1 = Timer2 Clock Enabled.
<> 149:156823d33999 2163 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
<> 149:156823d33999 2164 * | | |0 = Timer3 Clock Disabled.
<> 149:156823d33999 2165 * | | |1 = Timer3 Clock Enabled.
<> 149:156823d33999 2166 * |[6] |CLKOCKEN |CLKO Clock Enable Bit
<> 149:156823d33999 2167 * | | |0 = CLKO Clock Disabled.
<> 149:156823d33999 2168 * | | |1 = CLKO Clock Enabled.
<> 149:156823d33999 2169 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
<> 149:156823d33999 2170 * | | |0 = Analog Comparator 0/1 Clock Disabled.
<> 149:156823d33999 2171 * | | |1 = Analog Comparator 0/1 Clock Enabled.
<> 149:156823d33999 2172 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
<> 149:156823d33999 2173 * | | |0 = I2C0 Clock Disabled.
<> 149:156823d33999 2174 * | | |1 = I2C0 Clock Enabled.
<> 149:156823d33999 2175 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
<> 149:156823d33999 2176 * | | |0 = I2C1 Clock Disabled.
<> 149:156823d33999 2177 * | | |1 = I2C1 Clock Enabled.
<> 149:156823d33999 2178 * |[12] |SPI0CKEN |SPI0 Clock Enable Bit
<> 149:156823d33999 2179 * | | |0 = SPI0 Clock Disabled.
<> 149:156823d33999 2180 * | | |1 = SPI0 Clock Enabled.
<> 149:156823d33999 2181 * |[13] |SPI1CKEN |SPI1 Clock Enable Bit
<> 149:156823d33999 2182 * | | |0 = SPI1 Clock Disabled.
<> 149:156823d33999 2183 * | | |1 = SPI1 Clock Enabled.
<> 149:156823d33999 2184 * |[14] |SPI2CKEN |SPI2 Clock Enable Bit
<> 149:156823d33999 2185 * | | |0 = SPI2 Clock Disabled.
<> 149:156823d33999 2186 * | | |1 = SPI2 Clock Enabled.
<> 149:156823d33999 2187 * |[16] |UART0CKEN |UART0 Clock Enable Bit
<> 149:156823d33999 2188 * | | |0 = UART0 clock Disabled.
<> 149:156823d33999 2189 * | | |1 = UART0 clock Enabled.
<> 149:156823d33999 2190 * |[17] |UART1CKEN |UART1 Clock Enable Bit
<> 149:156823d33999 2191 * | | |0 = UART1 clock Disabled.
<> 149:156823d33999 2192 * | | |1 = UART1 clock Enabled.
<> 149:156823d33999 2193 * |[18] |UART2CKEN |UART2 Clock Enable Bit
<> 149:156823d33999 2194 * | | |0 = UART2 clock Disabled.
<> 149:156823d33999 2195 * | | |1 = UART2 clock Enabled.
<> 149:156823d33999 2196 * |[19] |UART3CKEN |UART3 Clock Enable Bit
<> 149:156823d33999 2197 * | | |0 = UART3 clock Disabled.
<> 149:156823d33999 2198 * | | |1 = UART3 clock Enabled.
<> 149:156823d33999 2199 * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
<> 149:156823d33999 2200 * | | |0 = CAN0 clock Disabled.
<> 149:156823d33999 2201 * | | |1 = CAN0 clock Enabled.
<> 149:156823d33999 2202 * |[26] |OTGCKEN |USB OTG Clock Enable Bit
<> 149:156823d33999 2203 * | | |0 = USB OTG clock Disabled.
<> 149:156823d33999 2204 * | | |1 = USB OTG clock Enabled.
<> 149:156823d33999 2205 * |[27] |USBDCKEN |USB Device Clock Enable Bit
<> 149:156823d33999 2206 * | | |0 = USB Device clock Disabled.
<> 149:156823d33999 2207 * | | |1 = USB Device clock Enabled.
<> 149:156823d33999 2208 * |[28] |EADCCKEN |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
<> 149:156823d33999 2209 * | | |0 = EADC clock Disabled.
<> 149:156823d33999 2210 * | | |1 = EADC clock Enabled.
<> 149:156823d33999 2211 * @var CLK_T::APBCLK1
<> 149:156823d33999 2212 * Offset: 0x0C APB Devices Clock Enable Control Register 1
<> 149:156823d33999 2213 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2214 * |Bits |Field |Descriptions
<> 149:156823d33999 2215 * | :----: | :----: | :---- |
<> 149:156823d33999 2216 * |[0] |SC0CKEN |SC0 Clock Enable Bit
<> 149:156823d33999 2217 * | | |0 = SC0 Clock Disabled.
<> 149:156823d33999 2218 * | | |1 = SC0 Clock Enabled.
<> 149:156823d33999 2219 * |[12] |DACCKEN |DAC Clock Enable Bit
<> 149:156823d33999 2220 * | | |0 = DAC Clock Disabled.
<> 149:156823d33999 2221 * | | |1 = DAC Clock Enabled.
<> 149:156823d33999 2222 * |[16] |PWM0CKEN |PWM0 Clock Enable Bit
<> 149:156823d33999 2223 * | | |0 = PWM0 Clock Disabled.
<> 149:156823d33999 2224 * | | |1 = PWM0 Clock Enabled.
<> 149:156823d33999 2225 * |[17] |PWM1CKEN |PWM1 Clock Enable Bit
<> 149:156823d33999 2226 * | | |0 = PWM1 Clock Disabled.
<> 149:156823d33999 2227 * | | |1 = PWM1 Clock Enabled.
<> 149:156823d33999 2228 * |[25] |TKCKEN |Touch Key Clock Enable Bit
<> 149:156823d33999 2229 * | | |0 = Touch Key Clock Disabled.
<> 149:156823d33999 2230 * | | |1 = Touch key Clock Enabled.
<> 149:156823d33999 2231 * @var CLK_T::CLKSEL0
<> 149:156823d33999 2232 * Offset: 0x10 Clock Source Select Control Register 0
<> 149:156823d33999 2233 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2234 * |Bits |Field |Descriptions
<> 149:156823d33999 2235 * | :----: | :----: | :---- |
<> 149:156823d33999 2236 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
<> 149:156823d33999 2237 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
<> 149:156823d33999 2238 * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
<> 149:156823d33999 2239 * | | |Therefore the default value is either 000b or 111b.
<> 149:156823d33999 2240 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2241 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2242 * | | |010 = Clock source from PLL clock.
<> 149:156823d33999 2243 * | | |011 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2244 * | | |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2245 * | | |Other = Reserved.
<> 149:156823d33999 2246 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2247 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
<> 149:156823d33999 2248 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
<> 149:156823d33999 2249 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2250 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2251 * | | |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
<> 149:156823d33999 2252 * | | |011 = Clock source from HCLK/2.
<> 149:156823d33999 2253 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
<> 149:156823d33999 2254 * | | |Note: if SysTick clock source is not from HCLK (i.e.
<> 149:156823d33999 2255 * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
<> 149:156823d33999 2256 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2257 * |[6] |PCLK0SEL |PCLK0 Clock Source Selection (Write Protect)
<> 149:156823d33999 2258 * | | |0 = APB0 BUS clock source from HCLK.
<> 149:156823d33999 2259 * | | |1 = APB0 BUS clock source from HCLK/2.
<> 149:156823d33999 2260 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2261 * |[7] |PCLK1SEL |PCLK1 Clock Source Selection (Write Protect)
<> 149:156823d33999 2262 * | | |0 = APB1 BUS clock source from HCLK.
<> 149:156823d33999 2263 * | | |1 = APB1 BUS clock source from HCLK/2.
<> 149:156823d33999 2264 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 2265 * @var CLK_T::CLKSEL1
<> 149:156823d33999 2266 * Offset: 0x14 Clock Source Select Control Register 1
<> 149:156823d33999 2267 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2268 * |Bits |Field |Descriptions
<> 149:156823d33999 2269 * | :----: | :----: | :---- |
<> 149:156823d33999 2270 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
<> 149:156823d33999 2271 * | | |00 = Reserved.
<> 149:156823d33999 2272 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2273 * | | |10 = Clock source from PCLK0/2048 clock.
<> 149:156823d33999 2274 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2275 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
<> 149:156823d33999 2276 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2277 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2278 * | | |010 = Clock source from PCLK0.
<> 149:156823d33999 2279 * | | |011 = Clock source from external clock T0 pin
<> 149:156823d33999 2280 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2281 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2282 * | | |Others = Reserved.
<> 149:156823d33999 2283 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
<> 149:156823d33999 2284 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2285 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2286 * | | |010 = Clock source from PCLK0.
<> 149:156823d33999 2287 * | | |011 = Clock source from external clock T1 pin
<> 149:156823d33999 2288 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2289 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2290 * | | |Others = Reserved.
<> 149:156823d33999 2291 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
<> 149:156823d33999 2292 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2293 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2294 * | | |010 = Clock source from PCLK1.
<> 149:156823d33999 2295 * | | |011 = Clock source from external clock T2 pin
<> 149:156823d33999 2296 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2297 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2298 * | | |Others = Reserved.
<> 149:156823d33999 2299 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
<> 149:156823d33999 2300 * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2301 * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2302 * | | |010 = Clock source from PCLK1.
<> 149:156823d33999 2303 * | | |011 = Clock source from external clock T3 pin.
<> 149:156823d33999 2304 * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2305 * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2306 * | | |Others = Reserved.
<> 149:156823d33999 2307 * |[25:24] |UARTSEL |UART Clock Source Selection
<> 149:156823d33999 2308 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
<> 149:156823d33999 2309 * | | |01 = Clock source from PLL clock.
<> 149:156823d33999 2310 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
<> 149:156823d33999 2311 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
<> 149:156823d33999 2312 * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
<> 149:156823d33999 2313 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2314 * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
<> 149:156823d33999 2315 * | | |10 = Clock source from HCLK.
<> 149:156823d33999 2316 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2317 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
<> 149:156823d33999 2318 * | | |10 = Clock source from PCLK0/2048 clock.
<> 149:156823d33999 2319 * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
<> 149:156823d33999 2320 * | | |Others = Reserved.
<> 149:156823d33999 2321 * @var CLK_T::CLKSEL2
<> 149:156823d33999 2322 * Offset: 0x18 Clock Source Select Control Register 2
<> 149:156823d33999 2323 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2324 * |Bits |Field |Descriptions
<> 149:156823d33999 2325 * | :----: | :----: | :---- |
<> 149:156823d33999 2326 * |[0] |PWM0SEL |PWM0 Clock Source Selection
<> 149:156823d33999 2327 * | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
<> 149:156823d33999 2328 * | | |0 = Clock source from PLL clock.
<> 149:156823d33999 2329 * | | |1 = Clock source from PCLK0.
<> 149:156823d33999 2330 * |[1] |PWM1SEL |PWM1 Clock Source Selection
<> 149:156823d33999 2331 * | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
<> 149:156823d33999 2332 * | | |0 = Clock source from PLL clock.
<> 149:156823d33999 2333 * | | |1 = Clock source from PCLK1.
<> 149:156823d33999 2334 * |[3:2] |SPI0SEL |SPI0 Clock Source Selection
<> 149:156823d33999 2335 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
<> 149:156823d33999 2336 * | | |01 = Clock source from PLL clock.
<> 149:156823d33999 2337 * | | |10 = Clock source from PCLK0.
<> 149:156823d33999 2338 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
<> 149:156823d33999 2339 * |[5:4] |SPI1SEL |SPI1 Clock Source Selection
<> 149:156823d33999 2340 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
<> 149:156823d33999 2341 * | | |01 = Clock source from PLL clock.
<> 149:156823d33999 2342 * | | |10 = Clock source from PCLK1.
<> 149:156823d33999 2343 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
<> 149:156823d33999 2344 * |[7:6] |SPI2SEL |SPI2 Clock Source Selection
<> 149:156823d33999 2345 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
<> 149:156823d33999 2346 * | | |01 = Clock source from PLL clock.
<> 149:156823d33999 2347 * | | |10 = Clock source from PCLK0.
<> 149:156823d33999 2348 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
<> 149:156823d33999 2349 * @var CLK_T::CLKSEL3
<> 149:156823d33999 2350 * Offset: 0x1C Clock Source Select Control Register 3
<> 149:156823d33999 2351 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2352 * |Bits |Field |Descriptions
<> 149:156823d33999 2353 * | :----: | :----: | :---- |
<> 149:156823d33999 2354 * |[1:0] |SC0SEL |SC0 Clock Source Selection
<> 149:156823d33999 2355 * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
<> 149:156823d33999 2356 * | | |01 = Clock source from PLL clock.
<> 149:156823d33999 2357 * | | |10 = Clock source from PCLK0.
<> 149:156823d33999 2358 * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
<> 149:156823d33999 2359 * |[8] |RTCSEL |RTC Clock Source Selection
<> 149:156823d33999 2360 * | | |0 = Clock source from external 32.768 kHz low-speed oscillator.
<> 149:156823d33999 2361 * | | |1 = Clock source from internal 10 kHz low speed RC oscillator.
<> 149:156823d33999 2362 * @var CLK_T::CLKDIV0
<> 149:156823d33999 2363 * Offset: 0x20 Clock Divider Number Register 0
<> 149:156823d33999 2364 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2365 * |Bits |Field |Descriptions
<> 149:156823d33999 2366 * | :----: | :----: | :---- |
<> 149:156823d33999 2367 * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
<> 149:156823d33999 2368 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
<> 149:156823d33999 2369 * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
<> 149:156823d33999 2370 * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
<> 149:156823d33999 2371 * |[11:8] |UARTDIV |UART Clock Divide Number From UART Clock Source
<> 149:156823d33999 2372 * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
<> 149:156823d33999 2373 * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
<> 149:156823d33999 2374 * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
<> 149:156823d33999 2375 * @var CLK_T::CLKDIV1
<> 149:156823d33999 2376 * Offset: 0x24 Clock Divider Number Register 1
<> 149:156823d33999 2377 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2378 * |Bits |Field |Descriptions
<> 149:156823d33999 2379 * | :----: | :----: | :---- |
<> 149:156823d33999 2380 * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
<> 149:156823d33999 2381 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
<> 149:156823d33999 2382 * @var CLK_T::PLLCTL
<> 149:156823d33999 2383 * Offset: 0x40 PLL Control Register
<> 149:156823d33999 2384 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2385 * |Bits |Field |Descriptions
<> 149:156823d33999 2386 * | :----: | :----: | :---- |
<> 149:156823d33999 2387 * |[8:0] |FBDIV |PLL Feedback Divider Control Pins (Write Protect)
<> 149:156823d33999 2388 * | | |Refer to the formulas below the table.
<> 149:156823d33999 2389 * |[13:9] |INDIV |PLL Input Divider Control Pins (Write Protect)
<> 149:156823d33999 2390 * | | |Refer to the formulas below the table.
<> 149:156823d33999 2391 * |[15:14] |OUTDIV |PLL Output Divider Control Pins (Write Protect)
<> 149:156823d33999 2392 * | | |Refer to the formulas below the table.
<> 149:156823d33999 2393 * |[16] |PD |Power-Down Mode (Write Protect)
<> 149:156823d33999 2394 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
<> 149:156823d33999 2395 * | | |0 = PLL is in normal mode.
<> 149:156823d33999 2396 * | | |1 = PLL is in Power-down mode (default).
<> 149:156823d33999 2397 * |[17] |BP |PLL Bypass Control (Write Protect)
<> 149:156823d33999 2398 * | | |0 = PLL is in normal mode (default).
<> 149:156823d33999 2399 * | | |1 = PLL clock output is same as PLL input clock FIN.
<> 149:156823d33999 2400 * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
<> 149:156823d33999 2401 * | | |0 = PLL FOUT Enabled.
<> 149:156823d33999 2402 * | | |1 = PLL FOUT is fixed low.
<> 149:156823d33999 2403 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
<> 149:156823d33999 2404 * | | |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
<> 149:156823d33999 2405 * | | |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
<> 149:156823d33999 2406 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
<> 149:156823d33999 2407 * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
<> 149:156823d33999 2408 * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
<> 149:156823d33999 2409 * @var CLK_T::STATUS
<> 149:156823d33999 2410 * Offset: 0x50 Clock Status Monitor Register
<> 149:156823d33999 2411 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2412 * |Bits |Field |Descriptions
<> 149:156823d33999 2413 * | :----: | :----: | :---- |
<> 149:156823d33999 2414 * |[0] |HXTSTB |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
<> 149:156823d33999 2415 * | | |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
<> 149:156823d33999 2416 * | | |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
<> 149:156823d33999 2417 * |[1] |LXTSTB |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
<> 149:156823d33999 2418 * | | |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
<> 149:156823d33999 2419 * | | |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
<> 149:156823d33999 2420 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
<> 149:156823d33999 2421 * | | |0 = Internal PLL clock is not stable or disabled.
<> 149:156823d33999 2422 * | | |1 = Internal PLL clock is stable and enabled.
<> 149:156823d33999 2423 * |[3] |LIRCSTB |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
<> 149:156823d33999 2424 * | | |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
<> 149:156823d33999 2425 * | | |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
<> 149:156823d33999 2426 * |[4] |HIRCSTB |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
<> 149:156823d33999 2427 * | | |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
<> 149:156823d33999 2428 * | | |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
<> 149:156823d33999 2429 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
<> 149:156823d33999 2430 * | | |This bit is updated when software switches system clock source.
<> 149:156823d33999 2431 * | | |If switch target clock is stable, this bit will be set to 0.
<> 149:156823d33999 2432 * | | |If switch target clock is not stable, this bit will be set to 1.
<> 149:156823d33999 2433 * | | |0 = Clock switching success.
<> 149:156823d33999 2434 * | | |1 = Clock switching failure.
<> 149:156823d33999 2435 * | | |Note: Write 1 to clear the bit to 0.
<> 149:156823d33999 2436 * @var CLK_T::CLKOCTL
<> 149:156823d33999 2437 * Offset: 0x60 Clock Output Control Register
<> 149:156823d33999 2438 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2439 * |Bits |Field |Descriptions
<> 149:156823d33999 2440 * | :----: | :----: | :---- |
<> 149:156823d33999 2441 * |[3:0] |FREQSEL |Clock Output Frequency Selection
<> 149:156823d33999 2442 * | | |The formula of output frequency is
<> 149:156823d33999 2443 * | | |Fout = Fin/2(N+1).
<> 149:156823d33999 2444 * | | |Fin is the input clock frequency.
<> 149:156823d33999 2445 * | | |Fout is the frequency of divider output clock.
<> 149:156823d33999 2446 * | | |N is the 4-bit value of FREQSEL[3:0].
<> 149:156823d33999 2447 * |[4] |CLKOEN |Clock Output Enable Bit
<> 149:156823d33999 2448 * | | |0 =Clock Output function Disabled.
<> 149:156823d33999 2449 * | | |1 = Clock Output function Enabled.
<> 149:156823d33999 2450 * |[5] |DIV1EN |Clock Output Divide One Enable Bit
<> 149:156823d33999 2451 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
<> 149:156823d33999 2452 * | | |1 = Clock Output will output clock with source frequency.
<> 149:156823d33999 2453 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
<> 149:156823d33999 2454 * | | |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
<> 149:156823d33999 2455 * | | |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
<> 149:156823d33999 2456 * @var CLK_T::CLKDCTL
<> 149:156823d33999 2457 * Offset: 0x70 Clock Fail Detector Control Register
<> 149:156823d33999 2458 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2459 * |Bits |Field |Descriptions
<> 149:156823d33999 2460 * | :----: | :----: | :---- |
<> 149:156823d33999 2461 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
<> 149:156823d33999 2462 * | | |0 = HXT clock Fail detector Disabled.
<> 149:156823d33999 2463 * | | |1 = HXT clock Fail detector Enabled.
<> 149:156823d33999 2464 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
<> 149:156823d33999 2465 * | | |0 = HXT clock Fail interrupt Disabled.
<> 149:156823d33999 2466 * | | |1 = HXT clock Fail interrupt Enabled.
<> 149:156823d33999 2467 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
<> 149:156823d33999 2468 * | | |0 = LXT clock Fail detector Disabled.
<> 149:156823d33999 2469 * | | |1 = LXT clock Fail detector Enabled.
<> 149:156823d33999 2470 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
<> 149:156823d33999 2471 * | | |0 = LXT clock Fail interrupt Disabled.
<> 149:156823d33999 2472 * | | |1 = LXT clock Fail interrupt Enabled.
<> 149:156823d33999 2473 * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit
<> 149:156823d33999 2474 * | | |0 = HXT clock frequency monitor Disabled.
<> 149:156823d33999 2475 * | | |1 = HXT clock frequency monitor Enabled.
<> 149:156823d33999 2476 * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit
<> 149:156823d33999 2477 * | | |0 = HXT clock frequency monitor fail interrupt Disabled.
<> 149:156823d33999 2478 * | | |1 = HXT clock frequency monitor fail interrupt Enabled.
<> 149:156823d33999 2479 * @var CLK_T::CLKDSTS
<> 149:156823d33999 2480 * Offset: 0x74 Clock Fail Detector Status Register
<> 149:156823d33999 2481 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2482 * |Bits |Field |Descriptions
<> 149:156823d33999 2483 * | :----: | :----: | :---- |
<> 149:156823d33999 2484 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
<> 149:156823d33999 2485 * | | |0 = HXT clock normal.
<> 149:156823d33999 2486 * | | |1 = HXT clock stop
<> 149:156823d33999 2487 * | | |Note: Write 1 to clear the bit to 0.
<> 149:156823d33999 2488 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
<> 149:156823d33999 2489 * | | |0 = LXT clock normal.
<> 149:156823d33999 2490 * | | |1 = LXT stop
<> 149:156823d33999 2491 * | | |Note: Write 1 to clear the bit to 0.
<> 149:156823d33999 2492 * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag
<> 149:156823d33999 2493 * | | |0 = HXT clock normal.
<> 149:156823d33999 2494 * | | |1 = HXT clock frequency abnormal
<> 149:156823d33999 2495 * | | |Note: Write 1 to clear the bit to 0.
<> 149:156823d33999 2496 * @var CLK_T::CDUPB
<> 149:156823d33999 2497 * Offset: 0x78 Clock Frequency Detector Upper Boundary Register
<> 149:156823d33999 2498 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2499 * |Bits |Field |Descriptions
<> 149:156823d33999 2500 * | :----: | :----: | :---- |
<> 149:156823d33999 2501 * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary
<> 149:156823d33999 2502 * | | |The bits define the high value of frequency monitor window.
<> 149:156823d33999 2503 * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
<> 149:156823d33999 2504 * @var CLK_T::CDLOWB
<> 149:156823d33999 2505 * Offset: 0x7C Clock Frequency Detector Low Boundary Register
<> 149:156823d33999 2506 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2507 * |Bits |Field |Descriptions
<> 149:156823d33999 2508 * | :----: | :----: | :---- |
<> 149:156823d33999 2509 * |[9:0] |LOWERBD |HXT Clock Frequency Detector Low Boundary
<> 149:156823d33999 2510 * | | |The bits define the low value of frequency monitor window.
<> 149:156823d33999 2511 * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
<> 149:156823d33999 2512 */
<> 149:156823d33999 2513
<> 149:156823d33999 2514 __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
<> 149:156823d33999 2515 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
<> 149:156823d33999 2516 __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
<> 149:156823d33999 2517 __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
<> 149:156823d33999 2518 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
<> 149:156823d33999 2519 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
<> 149:156823d33999 2520 __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
<> 149:156823d33999 2521 __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
<> 149:156823d33999 2522 __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
<> 149:156823d33999 2523 __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
<> 149:156823d33999 2524 __I uint32_t RESERVE0[6];
<> 149:156823d33999 2525 __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
<> 149:156823d33999 2526 __I uint32_t RESERVE1[3];
<> 149:156823d33999 2527 __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
<> 149:156823d33999 2528 __I uint32_t RESERVE2[3];
<> 149:156823d33999 2529 __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
<> 149:156823d33999 2530 __I uint32_t RESERVE3[3];
<> 149:156823d33999 2531 __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
<> 149:156823d33999 2532 __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
<> 149:156823d33999 2533 __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
<> 149:156823d33999 2534 __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
<> 149:156823d33999 2535
<> 149:156823d33999 2536 } CLK_T;
<> 149:156823d33999 2537
<> 149:156823d33999 2538
<> 149:156823d33999 2539
<> 149:156823d33999 2540 /**
<> 149:156823d33999 2541 @addtogroup CLK_CONST CLK Bit Field Definition
<> 149:156823d33999 2542 Constant Definitions for CLK Controller
<> 149:156823d33999 2543 @{ */
<> 149:156823d33999 2544
<> 149:156823d33999 2545 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
<> 149:156823d33999 2546 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
<> 149:156823d33999 2547
<> 149:156823d33999 2548 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
<> 149:156823d33999 2549 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
<> 149:156823d33999 2550
<> 149:156823d33999 2551 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
<> 149:156823d33999 2552 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
<> 149:156823d33999 2553
<> 149:156823d33999 2554 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
<> 149:156823d33999 2555 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
<> 149:156823d33999 2556
<> 149:156823d33999 2557 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
<> 149:156823d33999 2558 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
<> 149:156823d33999 2559
<> 149:156823d33999 2560 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
<> 149:156823d33999 2561 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
<> 149:156823d33999 2562
<> 149:156823d33999 2563 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
<> 149:156823d33999 2564 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
<> 149:156823d33999 2565
<> 149:156823d33999 2566 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
<> 149:156823d33999 2567 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
<> 149:156823d33999 2568
<> 149:156823d33999 2569 #define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK_T::PWRCTL: PDWTCPU Position */
<> 149:156823d33999 2570 #define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK_T::PWRCTL: PDWTCPU Mask */
<> 149:156823d33999 2571
<> 149:156823d33999 2572 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
<> 149:156823d33999 2573 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
<> 149:156823d33999 2574
<> 149:156823d33999 2575 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
<> 149:156823d33999 2576 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
<> 149:156823d33999 2577
<> 149:156823d33999 2578 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
<> 149:156823d33999 2579 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
<> 149:156823d33999 2580
<> 149:156823d33999 2581 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
<> 149:156823d33999 2582 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
<> 149:156823d33999 2583
<> 149:156823d33999 2584 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
<> 149:156823d33999 2585 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
<> 149:156823d33999 2586
<> 149:156823d33999 2587 #define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK_T::AHBCLK: USBHCKEN Position */
<> 149:156823d33999 2588 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
<> 149:156823d33999 2589
<> 149:156823d33999 2590 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
<> 149:156823d33999 2591 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
<> 149:156823d33999 2592
<> 149:156823d33999 2593 #define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
<> 149:156823d33999 2594 #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
<> 149:156823d33999 2595
<> 149:156823d33999 2596 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
<> 149:156823d33999 2597 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
<> 149:156823d33999 2598
<> 149:156823d33999 2599 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
<> 149:156823d33999 2600 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
<> 149:156823d33999 2601
<> 149:156823d33999 2602 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
<> 149:156823d33999 2603 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
<> 149:156823d33999 2604
<> 149:156823d33999 2605 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
<> 149:156823d33999 2606 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
<> 149:156823d33999 2607
<> 149:156823d33999 2608 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
<> 149:156823d33999 2609 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
<> 149:156823d33999 2610
<> 149:156823d33999 2611 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
<> 149:156823d33999 2612 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
<> 149:156823d33999 2613
<> 149:156823d33999 2614 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
<> 149:156823d33999 2615 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
<> 149:156823d33999 2616
<> 149:156823d33999 2617 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
<> 149:156823d33999 2618 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
<> 149:156823d33999 2619
<> 149:156823d33999 2620 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
<> 149:156823d33999 2621 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
<> 149:156823d33999 2622
<> 149:156823d33999 2623 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
<> 149:156823d33999 2624 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
<> 149:156823d33999 2625
<> 149:156823d33999 2626 #define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
<> 149:156823d33999 2627 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
<> 149:156823d33999 2628
<> 149:156823d33999 2629 #define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
<> 149:156823d33999 2630 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
<> 149:156823d33999 2631
<> 149:156823d33999 2632 #define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
<> 149:156823d33999 2633 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
<> 149:156823d33999 2634
<> 149:156823d33999 2635 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
<> 149:156823d33999 2636 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
<> 149:156823d33999 2637
<> 149:156823d33999 2638 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
<> 149:156823d33999 2639 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
<> 149:156823d33999 2640
<> 149:156823d33999 2641 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
<> 149:156823d33999 2642 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
<> 149:156823d33999 2643
<> 149:156823d33999 2644 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
<> 149:156823d33999 2645 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
<> 149:156823d33999 2646
<> 149:156823d33999 2647 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
<> 149:156823d33999 2648 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
<> 149:156823d33999 2649
<> 149:156823d33999 2650 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
<> 149:156823d33999 2651 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
<> 149:156823d33999 2652
<> 149:156823d33999 2653 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
<> 149:156823d33999 2654 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
<> 149:156823d33999 2655
<> 149:156823d33999 2656 #define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
<> 149:156823d33999 2657 #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
<> 149:156823d33999 2658
<> 149:156823d33999 2659 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
<> 149:156823d33999 2660 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
<> 149:156823d33999 2661
<> 149:156823d33999 2662 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
<> 149:156823d33999 2663 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
<> 149:156823d33999 2664
<> 149:156823d33999 2665 #define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
<> 149:156823d33999 2666 #define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
<> 149:156823d33999 2667
<> 149:156823d33999 2668 #define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
<> 149:156823d33999 2669 #define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
<> 149:156823d33999 2670
<> 149:156823d33999 2671 #define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */
<> 149:156823d33999 2672 #define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */
<> 149:156823d33999 2673
<> 149:156823d33999 2674 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
<> 149:156823d33999 2675 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
<> 149:156823d33999 2676
<> 149:156823d33999 2677 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
<> 149:156823d33999 2678 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
<> 149:156823d33999 2679
<> 149:156823d33999 2680 #define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
<> 149:156823d33999 2681 #define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
<> 149:156823d33999 2682
<> 149:156823d33999 2683 #define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
<> 149:156823d33999 2684 #define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
<> 149:156823d33999 2685
<> 149:156823d33999 2686 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
<> 149:156823d33999 2687 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
<> 149:156823d33999 2688
<> 149:156823d33999 2689 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
<> 149:156823d33999 2690 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
<> 149:156823d33999 2691
<> 149:156823d33999 2692 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
<> 149:156823d33999 2693 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
<> 149:156823d33999 2694
<> 149:156823d33999 2695 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
<> 149:156823d33999 2696 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
<> 149:156823d33999 2697
<> 149:156823d33999 2698 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
<> 149:156823d33999 2699 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
<> 149:156823d33999 2700
<> 149:156823d33999 2701 #define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK_T::CLKSEL1: UARTSEL Position */
<> 149:156823d33999 2702 #define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK_T::CLKSEL1: UARTSEL Mask */
<> 149:156823d33999 2703
<> 149:156823d33999 2704 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
<> 149:156823d33999 2705 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
<> 149:156823d33999 2706
<> 149:156823d33999 2707 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
<> 149:156823d33999 2708 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
<> 149:156823d33999 2709
<> 149:156823d33999 2710 #define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
<> 149:156823d33999 2711 #define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
<> 149:156823d33999 2712
<> 149:156823d33999 2713 #define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
<> 149:156823d33999 2714 #define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
<> 149:156823d33999 2715
<> 149:156823d33999 2716 #define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
<> 149:156823d33999 2717 #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
<> 149:156823d33999 2718
<> 149:156823d33999 2719 #define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
<> 149:156823d33999 2720 #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
<> 149:156823d33999 2721
<> 149:156823d33999 2722 #define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
<> 149:156823d33999 2723 #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
<> 149:156823d33999 2724
<> 149:156823d33999 2725 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
<> 149:156823d33999 2726 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
<> 149:156823d33999 2727
<> 149:156823d33999 2728 #define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
<> 149:156823d33999 2729 #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
<> 149:156823d33999 2730
<> 149:156823d33999 2731 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
<> 149:156823d33999 2732 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
<> 149:156823d33999 2733
<> 149:156823d33999 2734 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
<> 149:156823d33999 2735 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
<> 149:156823d33999 2736
<> 149:156823d33999 2737 #define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK_T::CLKDIV0: UARTDIV Position */
<> 149:156823d33999 2738 #define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK_T::CLKDIV0: UARTDIV Mask */
<> 149:156823d33999 2739
<> 149:156823d33999 2740 #define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
<> 149:156823d33999 2741 #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
<> 149:156823d33999 2742
<> 149:156823d33999 2743 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
<> 149:156823d33999 2744 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
<> 149:156823d33999 2745
<> 149:156823d33999 2746 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
<> 149:156823d33999 2747 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
<> 149:156823d33999 2748
<> 149:156823d33999 2749 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
<> 149:156823d33999 2750 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
<> 149:156823d33999 2751
<> 149:156823d33999 2752 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
<> 149:156823d33999 2753 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
<> 149:156823d33999 2754
<> 149:156823d33999 2755 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
<> 149:156823d33999 2756 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
<> 149:156823d33999 2757
<> 149:156823d33999 2758 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
<> 149:156823d33999 2759 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
<> 149:156823d33999 2760
<> 149:156823d33999 2761 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
<> 149:156823d33999 2762 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
<> 149:156823d33999 2763
<> 149:156823d33999 2764 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
<> 149:156823d33999 2765 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
<> 149:156823d33999 2766
<> 149:156823d33999 2767 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
<> 149:156823d33999 2768 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
<> 149:156823d33999 2769
<> 149:156823d33999 2770 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
<> 149:156823d33999 2771 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
<> 149:156823d33999 2772
<> 149:156823d33999 2773 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
<> 149:156823d33999 2774 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
<> 149:156823d33999 2775
<> 149:156823d33999 2776 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
<> 149:156823d33999 2777 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
<> 149:156823d33999 2778
<> 149:156823d33999 2779 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
<> 149:156823d33999 2780 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
<> 149:156823d33999 2781
<> 149:156823d33999 2782 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
<> 149:156823d33999 2783 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
<> 149:156823d33999 2784
<> 149:156823d33999 2785 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
<> 149:156823d33999 2786 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
<> 149:156823d33999 2787
<> 149:156823d33999 2788 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
<> 149:156823d33999 2789 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
<> 149:156823d33999 2790
<> 149:156823d33999 2791 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
<> 149:156823d33999 2792 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
<> 149:156823d33999 2793
<> 149:156823d33999 2794 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
<> 149:156823d33999 2795 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
<> 149:156823d33999 2796
<> 149:156823d33999 2797 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
<> 149:156823d33999 2798 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
<> 149:156823d33999 2799
<> 149:156823d33999 2800 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
<> 149:156823d33999 2801 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
<> 149:156823d33999 2802
<> 149:156823d33999 2803 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
<> 149:156823d33999 2804 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
<> 149:156823d33999 2805
<> 149:156823d33999 2806 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
<> 149:156823d33999 2807 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
<> 149:156823d33999 2808
<> 149:156823d33999 2809 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
<> 149:156823d33999 2810 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
<> 149:156823d33999 2811
<> 149:156823d33999 2812 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
<> 149:156823d33999 2813 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
<> 149:156823d33999 2814
<> 149:156823d33999 2815 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
<> 149:156823d33999 2816 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
<> 149:156823d33999 2817
<> 149:156823d33999 2818 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
<> 149:156823d33999 2819 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
<> 149:156823d33999 2820
<> 149:156823d33999 2821 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
<> 149:156823d33999 2822 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
<> 149:156823d33999 2823
<> 149:156823d33999 2824 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
<> 149:156823d33999 2825 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
<> 149:156823d33999 2826
<> 149:156823d33999 2827 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
<> 149:156823d33999 2828 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
<> 149:156823d33999 2829
<> 149:156823d33999 2830 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
<> 149:156823d33999 2831 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
<> 149:156823d33999 2832
<> 149:156823d33999 2833
<> 149:156823d33999 2834 /**@}*/ /* CLK_CONST */
<> 149:156823d33999 2835 /**@}*/ /* end of CLK register group */
<> 149:156823d33999 2836
<> 149:156823d33999 2837
<> 149:156823d33999 2838
<> 149:156823d33999 2839 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/
<> 149:156823d33999 2840 /**
<> 149:156823d33999 2841 @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
<> 149:156823d33999 2842 Memory Mapped Structure for CRC Controller
<> 149:156823d33999 2843 @{ */
<> 149:156823d33999 2844
<> 149:156823d33999 2845
<> 149:156823d33999 2846 typedef struct
<> 149:156823d33999 2847 {
<> 149:156823d33999 2848
<> 149:156823d33999 2849
<> 149:156823d33999 2850
<> 149:156823d33999 2851
<> 149:156823d33999 2852 /**
<> 149:156823d33999 2853 * @var CRC_T::CTL
<> 149:156823d33999 2854 * Offset: 0x00 CRC Control Register
<> 149:156823d33999 2855 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2856 * |Bits |Field |Descriptions
<> 149:156823d33999 2857 * | :----: | :----: | :---- |
<> 149:156823d33999 2858 * |[0] |CRCEN |CRC Channel Enable Bit
<> 149:156823d33999 2859 * | | |0 = No effect.
<> 149:156823d33999 2860 * | | |1 = CRC operation Enabled.
<> 149:156823d33999 2861 * |[1] |CRCRST |CRC Engine Reset
<> 149:156823d33999 2862 * | | |0 = No effect.
<> 149:156823d33999 2863 * | | |1 = Reset the internal CRC state machine and internal buffer.
<> 149:156823d33999 2864 * | | |The others contents of CRC_CTL register will not be cleared.
<> 149:156823d33999 2865 * | | |Note1: This bit will be cleared automatically.
<> 149:156823d33999 2866 * | | |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
<> 149:156823d33999 2867 * |[24] |DATREV |Write Data Bit Order Reverse
<> 149:156823d33999 2868 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
<> 149:156823d33999 2869 * | | |0 = Bit order reversed for CRC write data in Disabled.
<> 149:156823d33999 2870 * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
<> 149:156823d33999 2871 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
<> 149:156823d33999 2872 * |[25] |CHKSREV |Checksum Bit Order Reverse
<> 149:156823d33999 2873 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
<> 149:156823d33999 2874 * | | |0 = Bit order reverse for CRC checksum Disabled.
<> 149:156823d33999 2875 * | | |1 = Bit order reverse for CRC checksum Enabled.
<> 149:156823d33999 2876 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
<> 149:156823d33999 2877 * |[26] |DATFMT |Write Data 1's Complement
<> 149:156823d33999 2878 * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
<> 149:156823d33999 2879 * | | |0 = 1's complement for CRC writes data in Disabled.
<> 149:156823d33999 2880 * | | |1 = 1's complement for CRC writes data in Enabled.
<> 149:156823d33999 2881 * |[27] |CHKSFMT |Checksum 1's Complement
<> 149:156823d33999 2882 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
<> 149:156823d33999 2883 * | | |0 = 1's complement for CRC checksum Disabled.
<> 149:156823d33999 2884 * | | |1 = 1's complement for CRC checksum Enabled.
<> 149:156823d33999 2885 * |[29:28] |DATLEN |CPU Write Data Length
<> 149:156823d33999 2886 * | | |This field indicates the write data length.
<> 149:156823d33999 2887 * | | |00 = Data length is 8-bit mode.
<> 149:156823d33999 2888 * | | |01 = Data length is 16-bit mode.
<> 149:156823d33999 2889 * | | |1x = Data length is 32-bit mode.
<> 149:156823d33999 2890 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
<> 149:156823d33999 2891 * |[31:30] |CRCMODE |CRC Polynomial Mode
<> 149:156823d33999 2892 * | | |This field indicates the CRC operation polynomial mode.
<> 149:156823d33999 2893 * | | |00 = CRC-CCITT Polynomial mode.
<> 149:156823d33999 2894 * | | |01 = CRC-8 Polynomial mode.
<> 149:156823d33999 2895 * | | |10 = CRC-16 Polynomial mode.
<> 149:156823d33999 2896 * | | |11 = CRC-32 Polynomial mode.
<> 149:156823d33999 2897 * @var CRC_T::DAT
<> 149:156823d33999 2898 * Offset: 0x04 CRC Write Data Register
<> 149:156823d33999 2899 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2900 * |Bits |Field |Descriptions
<> 149:156823d33999 2901 * | :----: | :----: | :---- |
<> 149:156823d33999 2902 * |[31:0] |DATA |CRC Write Data Bits
<> 149:156823d33999 2903 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
<> 149:156823d33999 2904 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
<> 149:156823d33999 2905 * @var CRC_T::SEED
<> 149:156823d33999 2906 * Offset: 0x08 CRC Seed Register
<> 149:156823d33999 2907 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2908 * |Bits |Field |Descriptions
<> 149:156823d33999 2909 * | :----: | :----: | :---- |
<> 149:156823d33999 2910 * |[31:0] |SEED |CRC Seed Value
<> 149:156823d33999 2911 * | | |This field indicates the CRC seed value.
<> 149:156823d33999 2912 * @var CRC_T::CHECKSUM
<> 149:156823d33999 2913 * Offset: 0x0C CRC Checksum Register
<> 149:156823d33999 2914 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2915 * |Bits |Field |Descriptions
<> 149:156823d33999 2916 * | :----: | :----: | :---- |
<> 149:156823d33999 2917 * |[31:0] |CHECKSUM |CRC Checksum Results
<> 149:156823d33999 2918 * | | |This field indicates the CRC checksum result.
<> 149:156823d33999 2919 */
<> 149:156823d33999 2920
<> 149:156823d33999 2921 __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
<> 149:156823d33999 2922 __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
<> 149:156823d33999 2923 __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
<> 149:156823d33999 2924 __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
<> 149:156823d33999 2925
<> 149:156823d33999 2926 } CRC_T;
<> 149:156823d33999 2927
<> 149:156823d33999 2928
<> 149:156823d33999 2929
<> 149:156823d33999 2930 /**
<> 149:156823d33999 2931 @addtogroup CRC_CONST CRC Bit Field Definition
<> 149:156823d33999 2932 Constant Definitions for CRC Controller
<> 149:156823d33999 2933 @{ */
<> 149:156823d33999 2934
<> 149:156823d33999 2935 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
<> 149:156823d33999 2936 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
<> 149:156823d33999 2937
<> 149:156823d33999 2938 #define CRC_CTL_CRCRST_Pos (1) /*!< CRC_T::CTL: CRCRST Position */
<> 149:156823d33999 2939 #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC_T::CTL: CRCRST Mask */
<> 149:156823d33999 2940
<> 149:156823d33999 2941 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
<> 149:156823d33999 2942 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
<> 149:156823d33999 2943
<> 149:156823d33999 2944 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
<> 149:156823d33999 2945 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
<> 149:156823d33999 2946
<> 149:156823d33999 2947 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
<> 149:156823d33999 2948 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
<> 149:156823d33999 2949
<> 149:156823d33999 2950 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
<> 149:156823d33999 2951 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
<> 149:156823d33999 2952
<> 149:156823d33999 2953 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
<> 149:156823d33999 2954 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
<> 149:156823d33999 2955
<> 149:156823d33999 2956 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
<> 149:156823d33999 2957 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
<> 149:156823d33999 2958
<> 149:156823d33999 2959 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
<> 149:156823d33999 2960 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
<> 149:156823d33999 2961
<> 149:156823d33999 2962 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
<> 149:156823d33999 2963 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
<> 149:156823d33999 2964
<> 149:156823d33999 2965 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
<> 149:156823d33999 2966 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
<> 149:156823d33999 2967
<> 149:156823d33999 2968 /**@}*/ /* CRC_CONST */
<> 149:156823d33999 2969 /**@}*/ /* end of CRC register group */
<> 149:156823d33999 2970
<> 149:156823d33999 2971
<> 149:156823d33999 2972 /*---------------------- Digital to Analog Converter -------------------------*/
<> 149:156823d33999 2973 /**
<> 149:156823d33999 2974 @addtogroup DAC Digital to Analog Converter(DAC)
<> 149:156823d33999 2975 Memory Mapped Structure for DAC Controller
<> 149:156823d33999 2976 @{ */
<> 149:156823d33999 2977
<> 149:156823d33999 2978
<> 149:156823d33999 2979 typedef struct
<> 149:156823d33999 2980 {
<> 149:156823d33999 2981
<> 149:156823d33999 2982
<> 149:156823d33999 2983
<> 149:156823d33999 2984 /**
<> 149:156823d33999 2985 * @var DAC_T::CTL
<> 149:156823d33999 2986 * Offset: 0x00 DAC Control Register
<> 149:156823d33999 2987 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 2988 * |Bits |Field |Descriptions
<> 149:156823d33999 2989 * | :----: | :----: | :---- |
<> 149:156823d33999 2990 * |[0] |DACEN |DAC Enable Bit
<> 149:156823d33999 2991 * | | |0 = DAC is Disabled.
<> 149:156823d33999 2992 * | | |1 = DAC is Enabled.
<> 149:156823d33999 2993 * |[1] |DACIEN |DAC Interrupt Enable Bit
<> 149:156823d33999 2994 * | | |0 = Interrupt is Disabled.
<> 149:156823d33999 2995 * | | |1 = Interrupt is Enabled.
<> 149:156823d33999 2996 * |[2] |DMAEN |DMA Mode Enable Bit
<> 149:156823d33999 2997 * | | |0 = DMA mode Disabled.
<> 149:156823d33999 2998 * | | |1 = DMA mode Enabled.
<> 149:156823d33999 2999 * |[3] |DMAURIEN |DMA Under-Run Interrupt Enable Bit
<> 149:156823d33999 3000 * | | |0 = DMA under run interrupt Disabled.
<> 149:156823d33999 3001 * | | |1 = DMA under run interrupt Enabled.
<> 149:156823d33999 3002 * |[4] |TRGEN |Trigger Mode Enable Bit
<> 149:156823d33999 3003 * | | |0 = DAC event trigger mode Disabled.
<> 149:156823d33999 3004 * | | |1 = DAC event trigger mode Enabled.
<> 149:156823d33999 3005 * |[7:5] |TRGSEL |Trigger Source Selection
<> 149:156823d33999 3006 * | | |000 = Software trigger.
<> 149:156823d33999 3007 * | | |001 = External pin STDAC trigger.
<> 149:156823d33999 3008 * | | |010 = Timer 0 trigger.
<> 149:156823d33999 3009 * | | |011 = Timer 1 trigger.
<> 149:156823d33999 3010 * | | |100 = Timer 2 trigger.
<> 149:156823d33999 3011 * | | |101 = Timer 3 trigger.
<> 149:156823d33999 3012 * | | |110 = PWM0 trigger.
<> 149:156823d33999 3013 * | | |111 = PWM1 trigger.
<> 149:156823d33999 3014 * |[8] |BYPASS |Bypass Buffer Mode
<> 149:156823d33999 3015 * | | |0 = Output voltage buffer Enabled.
<> 149:156823d33999 3016 * | | |1 = Output voltage buffer Disabled.
<> 149:156823d33999 3017 * |[10] |LALIGN |DAC Data Left-Aligned Enabled Control
<> 149:156823d33999 3018 * | | |0 = Right alignment.
<> 149:156823d33999 3019 * | | |1 = Left alignment.
<> 149:156823d33999 3020 * |[13:12] |ETRGSEL |External Pin Trigger Selection
<> 149:156823d33999 3021 * | | |00 = Low level trigger.
<> 149:156823d33999 3022 * | | |01 = High level trigger.
<> 149:156823d33999 3023 * | | |10 = Falling edge trigger.
<> 149:156823d33999 3024 * | | |11 = Rising edge trigger.
<> 149:156823d33999 3025 * @var DAC_T::SWTRG
<> 149:156823d33999 3026 * Offset: 0x04 DAC Software Trigger Control Register
<> 149:156823d33999 3027 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3028 * |Bits |Field |Descriptions
<> 149:156823d33999 3029 * | :----: | :----: | :---- |
<> 149:156823d33999 3030 * |[0] |SWTRG |Software Trigger
<> 149:156823d33999 3031 * | | |0 = Software trigger Disabled.
<> 149:156823d33999 3032 * | | |1 = Software trigger Enabled.
<> 149:156823d33999 3033 * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
<> 149:156823d33999 3034 * @var DAC_T::DAT
<> 149:156823d33999 3035 * Offset: 0x08 DAC Data Holding Register
<> 149:156823d33999 3036 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3037 * |Bits |Field |Descriptions
<> 149:156823d33999 3038 * | :----: | :----: | :---- |
<> 149:156823d33999 3039 * |[15:0] |DAC_DAT |DAC 12-Bit Holding Data
<> 149:156823d33999 3040 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
<> 149:156823d33999 3041 * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
<> 149:156823d33999 3042 * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
<> 149:156823d33999 3043 * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
<> 149:156823d33999 3044 * @var DAC_T::DATOUT
<> 149:156823d33999 3045 * Offset: 0x0C DAC Data Output Register
<> 149:156823d33999 3046 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3047 * |Bits |Field |Descriptions
<> 149:156823d33999 3048 * | :----: | :----: | :---- |
<> 149:156823d33999 3049 * |[11:0] |DATOUT |DAC 12-Bit Output Data
<> 149:156823d33999 3050 * | | |These bits are current digital data for DAC output conversion.
<> 149:156823d33999 3051 * | | |It is loaded from DAC_DAT register and user cannot write it directly.
<> 149:156823d33999 3052 * @var DAC_T::STATUS
<> 149:156823d33999 3053 * Offset: 0x10 DAC Status Register
<> 149:156823d33999 3054 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3055 * |Bits |Field |Descriptions
<> 149:156823d33999 3056 * | :----: | :----: | :---- |
<> 149:156823d33999 3057 * |[0] |FINISH |DAC Conversion Complete Finish Flag
<> 149:156823d33999 3058 * | | |0 = DAC is in conversion state.
<> 149:156823d33999 3059 * | | |1 = DAC conversion finish.
<> 149:156823d33999 3060 * | | |This bit set to 1 when conversion time counter counts to SETTLET.
<> 149:156823d33999 3061 * | | |It is cleared to 0 when DAC starts a new conversion.
<> 149:156823d33999 3062 * | | |User writes 1 to clear this bit to 0.
<> 149:156823d33999 3063 * |[1] |DMAUDR |DMA Under Run Interrupt Flag
<> 149:156823d33999 3064 * | | |0 = No DMA under-run error condition occurred.
<> 149:156823d33999 3065 * | | |1 = DMA under-run error condition occurred.
<> 149:156823d33999 3066 * | | |User writes 1 to clear this bit.
<> 149:156823d33999 3067 * |[8] |BUSY |DAC Busy Flag (Read Only)
<> 149:156823d33999 3068 * | | |0 = DAC is ready for next conversion.
<> 149:156823d33999 3069 * | | |1 = DAC is busy in conversion.
<> 149:156823d33999 3070 * | | |This is read only bit.
<> 149:156823d33999 3071 * @var DAC_T::TCTL
<> 149:156823d33999 3072 * Offset: 0x14 DAC Timing Control Register
<> 149:156823d33999 3073 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3074 * |Bits |Field |Descriptions
<> 149:156823d33999 3075 * | :----: | :----: | :---- |
<> 149:156823d33999 3076 * |[9:0] |SETTLET |DAC Output Settling Time
<> 149:156823d33999 3077 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
<> 149:156823d33999 3078 * | | |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
<> 149:156823d33999 3079 */
<> 149:156823d33999 3080
<> 149:156823d33999 3081 __IO uint32_t CTL; /* Offset: 0x00 DAC Control Register */
<> 149:156823d33999 3082 __IO uint32_t SWTRG; /* Offset: 0x04 DAC Software Trigger Control Register */
<> 149:156823d33999 3083 __IO uint32_t DAT; /* Offset: 0x08 DAC Data Holding Register */
<> 149:156823d33999 3084 __I uint32_t DATOUT; /* Offset: 0x0C DAC Data Output Register */
<> 149:156823d33999 3085 __IO uint32_t STATUS; /* Offset: 0x10 DAC Status Register */
<> 149:156823d33999 3086 __IO uint32_t TCTL; /* Offset: 0x14 DAC Timing Control Register */
<> 149:156823d33999 3087
<> 149:156823d33999 3088 } DAC_T;
<> 149:156823d33999 3089
<> 149:156823d33999 3090
<> 149:156823d33999 3091
<> 149:156823d33999 3092 /**
<> 149:156823d33999 3093 @addtogroup DAC_CONST DAC Bit Field Definition
<> 149:156823d33999 3094 Constant Definitions for DAC Controller
<> 149:156823d33999 3095 @{ */
<> 149:156823d33999 3096
<> 149:156823d33999 3097 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
<> 149:156823d33999 3098 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
<> 149:156823d33999 3099
<> 149:156823d33999 3100 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
<> 149:156823d33999 3101 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
<> 149:156823d33999 3102
<> 149:156823d33999 3103 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
<> 149:156823d33999 3104 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
<> 149:156823d33999 3105
<> 149:156823d33999 3106 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
<> 149:156823d33999 3107 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
<> 149:156823d33999 3108
<> 149:156823d33999 3109 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
<> 149:156823d33999 3110 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
<> 149:156823d33999 3111
<> 149:156823d33999 3112 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
<> 149:156823d33999 3113 #define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
<> 149:156823d33999 3114
<> 149:156823d33999 3115 #define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
<> 149:156823d33999 3116 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
<> 149:156823d33999 3117
<> 149:156823d33999 3118 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
<> 149:156823d33999 3119 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
<> 149:156823d33999 3120
<> 149:156823d33999 3121 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
<> 149:156823d33999 3122 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
<> 149:156823d33999 3123
<> 149:156823d33999 3124 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
<> 149:156823d33999 3125 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
<> 149:156823d33999 3126
<> 149:156823d33999 3127 #define DAC_DAT_DAC_DAT_Pos (0) /*!< DAC_T::DAT: DAC_DAT Position */
<> 149:156823d33999 3128 #define DAC_DAT_DAC_DAT_Msk (0xfffful << DAC_DAT_DAC_DAT_Pos) /*!< DAC_T::DAT: DAC_DAT Mask */
<> 149:156823d33999 3129
<> 149:156823d33999 3130 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
<> 149:156823d33999 3131 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
<> 149:156823d33999 3132
<> 149:156823d33999 3133 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
<> 149:156823d33999 3134 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
<> 149:156823d33999 3135
<> 149:156823d33999 3136 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
<> 149:156823d33999 3137 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
<> 149:156823d33999 3138
<> 149:156823d33999 3139 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
<> 149:156823d33999 3140 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
<> 149:156823d33999 3141
<> 149:156823d33999 3142 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
<> 149:156823d33999 3143 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
<> 149:156823d33999 3144
<> 149:156823d33999 3145 /**@}*/ /* DAC_CONST */
<> 149:156823d33999 3146 /**@}*/ /* end of DAC register group */
<> 149:156823d33999 3147
<> 149:156823d33999 3148
<> 149:156823d33999 3149 /*---------------------- External Bus Interface Controller -------------------------*/
<> 149:156823d33999 3150 /**
<> 149:156823d33999 3151 @addtogroup EBI External Bus Interface Controller(EBI)
<> 149:156823d33999 3152 Memory Mapped Structure for EBI Controller
<> 149:156823d33999 3153 @{ */
<> 149:156823d33999 3154
<> 149:156823d33999 3155
<> 149:156823d33999 3156 typedef struct
<> 149:156823d33999 3157 {
<> 149:156823d33999 3158
<> 149:156823d33999 3159
<> 149:156823d33999 3160
<> 149:156823d33999 3161
<> 149:156823d33999 3162 /**
<> 149:156823d33999 3163 * @var EBI_T::CTL0
<> 149:156823d33999 3164 * Offset: 0x00 External Bus Interface Bank0 Control Register
<> 149:156823d33999 3165 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3166 * |Bits |Field |Descriptions
<> 149:156823d33999 3167 * | :----: | :----: | :---- |
<> 149:156823d33999 3168 * |[0] |EN |EBI Enable Bit
<> 149:156823d33999 3169 * | | |This bit is the functional enable bit for EBI.
<> 149:156823d33999 3170 * | | |0 = EBI function Disabled.
<> 149:156823d33999 3171 * | | |1 = EBI function Enabled.
<> 149:156823d33999 3172 * |[1] |DW16 |EBI Data Width 16-Bit Select
<> 149:156823d33999 3173 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
<> 149:156823d33999 3174 * | | |0 = EBI data width is 8-bit.
<> 149:156823d33999 3175 * | | |1 = EBI data width is 16-bit.
<> 149:156823d33999 3176 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
<> 149:156823d33999 3177 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
<> 149:156823d33999 3178 * | | |0 = Chip select pin (EBI_nCS) is active low.
<> 149:156823d33999 3179 * | | |1 = Chip select pin (EBI_nCS) is active high.
<> 149:156823d33999 3180 * |[10:8] |MCLKDIV |External Output Clock Divider
<> 149:156823d33999 3181 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
<> 149:156823d33999 3182 * | | |000 = HCLK/1.
<> 149:156823d33999 3183 * | | |001 = HCLK/2.
<> 149:156823d33999 3184 * | | |010 = HCLK/4.
<> 149:156823d33999 3185 * | | |011 = HCLK/8.
<> 149:156823d33999 3186 * | | |100 = HCLK/16.
<> 149:156823d33999 3187 * | | |101 = HCLK/32.
<> 149:156823d33999 3188 * | | |110 = Reserved.
<> 149:156823d33999 3189 * | | |111 = Reserved.
<> 149:156823d33999 3190 * |[18:16] |TALE |Extend Time Of ALE
<> 149:156823d33999 3191 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
<> 149:156823d33999 3192 * | | |tALE = (TALE+1)*EBI_MCLK.
<> 149:156823d33999 3193 * | | |Note: This field only available in EBI_CTL0 register
<> 149:156823d33999 3194 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
<> 149:156823d33999 3195 * | | |0 = EBI write buffer Disabled.
<> 149:156823d33999 3196 * | | |1 = EBI write buffer Enabled.
<> 149:156823d33999 3197 * | | |Note: This bit only available in EBI_CTL0 register
<> 149:156823d33999 3198 * @var EBI_T::TCTL0
<> 149:156823d33999 3199 * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
<> 149:156823d33999 3200 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3201 * |Bits |Field |Descriptions
<> 149:156823d33999 3202 * | :----: | :----: | :---- |
<> 149:156823d33999 3203 * |[7:3] |TACC |EBI Data Access Time
<> 149:156823d33999 3204 * | | |TACC define data access time (tACC).
<> 149:156823d33999 3205 * | | |tACC = (TACC +1) * EBI_MCLK.
<> 149:156823d33999 3206 * |[10:8] |TAHD |EBI Data Access Hold Time
<> 149:156823d33999 3207 * | | |TAHD define data access hold time (tAHD).
<> 149:156823d33999 3208 * | | |tAHD = (TAHD +1) * EBI_MCLK.
<> 149:156823d33999 3209 * |[15:12] |W2X |Idle Cycle After Write
<> 149:156823d33999 3210 * | | |This field defines the number of W2X idle cycle.
<> 149:156823d33999 3211 * | | |W2X idle cycle = (W2X * EBI_MCLK).
<> 149:156823d33999 3212 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
<> 149:156823d33999 3213 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
<> 149:156823d33999 3214 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
<> 149:156823d33999 3215 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
<> 149:156823d33999 3216 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
<> 149:156823d33999 3217 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
<> 149:156823d33999 3218 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
<> 149:156823d33999 3219 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
<> 149:156823d33999 3220 * | | |This field defines the number of R2R idle cycle.
<> 149:156823d33999 3221 * | | |R2R idle cycle = (R2R * EBI_MCLK).
<> 149:156823d33999 3222 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
<> 149:156823d33999 3223 * @var EBI_T::CTL1
<> 149:156823d33999 3224 * Offset: 0x10 External Bus Interface Bank1 Control Register
<> 149:156823d33999 3225 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3226 * |Bits |Field |Descriptions
<> 149:156823d33999 3227 * | :----: | :----: | :---- |
<> 149:156823d33999 3228 * |[0] |EN |EBI Enable Bit
<> 149:156823d33999 3229 * | | |This bit is the functional enable bit for EBI.
<> 149:156823d33999 3230 * | | |0 = EBI function Disabled.
<> 149:156823d33999 3231 * | | |1 = EBI function Enabled.
<> 149:156823d33999 3232 * |[1] |DW16 |EBI Data Width 16-Bit Select
<> 149:156823d33999 3233 * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
<> 149:156823d33999 3234 * | | |0 = EBI data width is 8-bit.
<> 149:156823d33999 3235 * | | |1 = EBI data width is 16-bit.
<> 149:156823d33999 3236 * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
<> 149:156823d33999 3237 * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
<> 149:156823d33999 3238 * | | |0 = Chip select pin (EBI_nCS) is active low.
<> 149:156823d33999 3239 * | | |1 = Chip select pin (EBI_nCS) is active high.
<> 149:156823d33999 3240 * |[10:8] |MCLKDIV |External Output Clock Divider
<> 149:156823d33999 3241 * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
<> 149:156823d33999 3242 * | | |000 = HCLK/1.
<> 149:156823d33999 3243 * | | |001 = HCLK/2.
<> 149:156823d33999 3244 * | | |010 = HCLK/4.
<> 149:156823d33999 3245 * | | |011 = HCLK/8.
<> 149:156823d33999 3246 * | | |100 = HCLK/16.
<> 149:156823d33999 3247 * | | |101 = HCLK/32.
<> 149:156823d33999 3248 * | | |110 = Reserved.
<> 149:156823d33999 3249 * | | |111 = Reserved.
<> 149:156823d33999 3250 * |[18:16] |TALE |Extend Time Of ALE
<> 149:156823d33999 3251 * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
<> 149:156823d33999 3252 * | | |tALE = (TALE+1)*EBI_MCLK.
<> 149:156823d33999 3253 * | | |Note: This field only available in EBI_CTL0 register
<> 149:156823d33999 3254 * |[24] |WBUFEN |EBI Write Buffer Enable Bit
<> 149:156823d33999 3255 * | | |0 = EBI write buffer Disabled.
<> 149:156823d33999 3256 * | | |1 = EBI write buffer Enabled.
<> 149:156823d33999 3257 * | | |Note: This bit only available in EBI_CTL0 register
<> 149:156823d33999 3258 * @var EBI_T::TCTL1
<> 149:156823d33999 3259 * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
<> 149:156823d33999 3260 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3261 * |Bits |Field |Descriptions
<> 149:156823d33999 3262 * | :----: | :----: | :---- |
<> 149:156823d33999 3263 * |[7:3] |TACC |EBI Data Access Time
<> 149:156823d33999 3264 * | | |TACC define data access time (tACC).
<> 149:156823d33999 3265 * | | |tACC = (TACC +1) * EBI_MCLK.
<> 149:156823d33999 3266 * |[10:8] |TAHD |EBI Data Access Hold Time
<> 149:156823d33999 3267 * | | |TAHD define data access hold time (tAHD).
<> 149:156823d33999 3268 * | | |tAHD = (TAHD +1) * EBI_MCLK.
<> 149:156823d33999 3269 * |[15:12] |W2X |Idle Cycle After Write
<> 149:156823d33999 3270 * | | |This field defines the number of W2X idle cycle.
<> 149:156823d33999 3271 * | | |W2X idle cycle = (W2X * EBI_MCLK).
<> 149:156823d33999 3272 * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
<> 149:156823d33999 3273 * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
<> 149:156823d33999 3274 * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
<> 149:156823d33999 3275 * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
<> 149:156823d33999 3276 * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
<> 149:156823d33999 3277 * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
<> 149:156823d33999 3278 * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
<> 149:156823d33999 3279 * |[27:24] |R2R |Idle Cycle Between Read-To-Read
<> 149:156823d33999 3280 * | | |This field defines the number of R2R idle cycle.
<> 149:156823d33999 3281 * | | |R2R idle cycle = (R2R * EBI_MCLK).
<> 149:156823d33999 3282 * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
<> 149:156823d33999 3283 */
<> 149:156823d33999 3284
<> 149:156823d33999 3285 __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
<> 149:156823d33999 3286 __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
<> 149:156823d33999 3287 __I uint32_t RESERVE0[2];
<> 149:156823d33999 3288 __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
<> 149:156823d33999 3289 __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
<> 149:156823d33999 3290
<> 149:156823d33999 3291 } EBI_T;
<> 149:156823d33999 3292
<> 149:156823d33999 3293
<> 149:156823d33999 3294
<> 149:156823d33999 3295 /**
<> 149:156823d33999 3296 @addtogroup EBI_CONST EBI Bit Field Definition
<> 149:156823d33999 3297 Constant Definitions for EBI Controller
<> 149:156823d33999 3298 @{ */
<> 149:156823d33999 3299
<> 149:156823d33999 3300 #define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
<> 149:156823d33999 3301 #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
<> 149:156823d33999 3302
<> 149:156823d33999 3303 #define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
<> 149:156823d33999 3304 #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
<> 149:156823d33999 3305
<> 149:156823d33999 3306 #define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
<> 149:156823d33999 3307 #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
<> 149:156823d33999 3308
<> 149:156823d33999 3309 #define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
<> 149:156823d33999 3310 #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
<> 149:156823d33999 3311
<> 149:156823d33999 3312 #define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
<> 149:156823d33999 3313 #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
<> 149:156823d33999 3314
<> 149:156823d33999 3315 #define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
<> 149:156823d33999 3316 #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
<> 149:156823d33999 3317
<> 149:156823d33999 3318 #define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
<> 149:156823d33999 3319 #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
<> 149:156823d33999 3320
<> 149:156823d33999 3321 #define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
<> 149:156823d33999 3322 #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
<> 149:156823d33999 3323
<> 149:156823d33999 3324 #define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
<> 149:156823d33999 3325 #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
<> 149:156823d33999 3326
<> 149:156823d33999 3327 #define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
<> 149:156823d33999 3328 #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
<> 149:156823d33999 3329
<> 149:156823d33999 3330 #define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
<> 149:156823d33999 3331 #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
<> 149:156823d33999 3332
<> 149:156823d33999 3333 #define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
<> 149:156823d33999 3334 #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
<> 149:156823d33999 3335
<> 149:156823d33999 3336 #define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
<> 149:156823d33999 3337 #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
<> 149:156823d33999 3338
<> 149:156823d33999 3339 #define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
<> 149:156823d33999 3340 #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
<> 149:156823d33999 3341
<> 149:156823d33999 3342 #define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
<> 149:156823d33999 3343 #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
<> 149:156823d33999 3344
<> 149:156823d33999 3345 #define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
<> 149:156823d33999 3346 #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
<> 149:156823d33999 3347
<> 149:156823d33999 3348 #define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
<> 149:156823d33999 3349 #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
<> 149:156823d33999 3350
<> 149:156823d33999 3351 #define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
<> 149:156823d33999 3352 #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
<> 149:156823d33999 3353
<> 149:156823d33999 3354 #define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
<> 149:156823d33999 3355 #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
<> 149:156823d33999 3356
<> 149:156823d33999 3357 #define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
<> 149:156823d33999 3358 #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
<> 149:156823d33999 3359
<> 149:156823d33999 3360 #define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
<> 149:156823d33999 3361 #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
<> 149:156823d33999 3362
<> 149:156823d33999 3363 #define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
<> 149:156823d33999 3364 #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
<> 149:156823d33999 3365
<> 149:156823d33999 3366 #define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
<> 149:156823d33999 3367 #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
<> 149:156823d33999 3368
<> 149:156823d33999 3369 #define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
<> 149:156823d33999 3370 #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
<> 149:156823d33999 3371
<> 149:156823d33999 3372 /**@}*/ /* EBI_CONST */
<> 149:156823d33999 3373 /**@}*/ /* end of EBI register group */
<> 149:156823d33999 3374
<> 149:156823d33999 3375
<> 149:156823d33999 3376 /*---------------------- Flash Memory Controller -------------------------*/
<> 149:156823d33999 3377 /**
<> 149:156823d33999 3378 @addtogroup FMC Flash Memory Controller(FMC)
<> 149:156823d33999 3379 Memory Mapped Structure for FMC Controller
<> 149:156823d33999 3380 @{ */
<> 149:156823d33999 3381
<> 149:156823d33999 3382
<> 149:156823d33999 3383 typedef struct
<> 149:156823d33999 3384 {
<> 149:156823d33999 3385
<> 149:156823d33999 3386
<> 149:156823d33999 3387
<> 149:156823d33999 3388
<> 149:156823d33999 3389 /**
<> 149:156823d33999 3390 * @var FMC_T::ISPCTL
<> 149:156823d33999 3391 * Offset: 0x00 ISP Control Register
<> 149:156823d33999 3392 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3393 * |Bits |Field |Descriptions
<> 149:156823d33999 3394 * | :----: | :----: | :---- |
<> 149:156823d33999 3395 * |[0] |ISPEN |ISP Enable Bit (Write Protect)
<> 149:156823d33999 3396 * | | |ISP function enable bit. Set this bit to enable ISP function.
<> 149:156823d33999 3397 * | | |0 = ISP function Disabled.
<> 149:156823d33999 3398 * | | |1 = ISP function Enabled.
<> 149:156823d33999 3399 * |[1] |BS |Boot Select (Write Protect)
<> 149:156823d33999 3400 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
<> 149:156823d33999 3401 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
<> 149:156823d33999 3402 * | | |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
<> 149:156823d33999 3403 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
<> 149:156823d33999 3404 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
<> 149:156823d33999 3405 * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
<> 149:156823d33999 3406 * | | |0 = APROM cannot be updated when the chip runs in APROM.
<> 149:156823d33999 3407 * | | |1 = APROM can be updated when the chip runs in APROM.
<> 149:156823d33999 3408 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
<> 149:156823d33999 3409 * | | |0 = CONFIG cannot be updated.
<> 149:156823d33999 3410 * | | |1 = CONFIG can be updated.
<> 149:156823d33999 3411 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
<> 149:156823d33999 3412 * | | |LDROM update enable bit.
<> 149:156823d33999 3413 * | | |0 = LDROM cannot be updated.
<> 149:156823d33999 3414 * | | |1 = LDROM can be updated.
<> 149:156823d33999 3415 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
<> 149:156823d33999 3416 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
<> 149:156823d33999 3417 * | | |This bit needs to be cleared by writing 1 to it.
<> 149:156823d33999 3418 * | | |(1) APROM writes to itself if APUEN is set to 0.
<> 149:156823d33999 3419 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
<> 149:156823d33999 3420 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
<> 149:156823d33999 3421 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
<> 149:156823d33999 3422 * | | |(5) SPROM is programmed at SPROM secured mode.
<> 149:156823d33999 3423 * | | |(6) Page Erase command at LOCK mode with ICE connection
<> 149:156823d33999 3424 * | | |(7) Erase or Program command at brown-out detected
<> 149:156823d33999 3425 * | | |(8) Destination address is illegal, such as over an available range.
<> 149:156823d33999 3426 * | | |(9) Invalid ISP commands
<> 149:156823d33999 3427 * |[16] |BL |Boot Loader Booting (Write Protect)
<> 149:156823d33999 3428 * | | |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
<> 149:156823d33999 3429 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
<> 149:156823d33999 3430 * | | |This bit is used to check chip boot from Boot Loader or not.
<> 149:156823d33999 3431 * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
<> 149:156823d33999 3432 * | | |0 = Booting from APROM or LDROM.
<> 149:156823d33999 3433 * | | |1 = Booting from Boot Loader.
<> 149:156823d33999 3434 * @var FMC_T::ISPADDR
<> 149:156823d33999 3435 * Offset: 0x04 ISP Address Register
<> 149:156823d33999 3436 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3437 * |Bits |Field |Descriptions
<> 149:156823d33999 3438 * | :----: | :----: | :---- |
<> 149:156823d33999 3439 * |[31:0] |ISPADDR |ISP Address
<> 149:156823d33999 3440 * | | |The NuMicro M451 series is equipped with embedded flash.
<> 149:156823d33999 3441 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
<> 149:156823d33999 3442 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
<> 149:156823d33999 3443 * | | |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
<> 149:156823d33999 3444 * @var FMC_T::ISPDAT
<> 149:156823d33999 3445 * Offset: 0x08 ISP Data Register
<> 149:156823d33999 3446 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3447 * |Bits |Field |Descriptions
<> 149:156823d33999 3448 * | :----: | :----: | :---- |
<> 149:156823d33999 3449 * |[31:0] |ISPDAT |ISP Data
<> 149:156823d33999 3450 * | | |Write data to this register before ISP program operation.
<> 149:156823d33999 3451 * | | |Read data from this register after ISP read operation.
<> 149:156823d33999 3452 * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
<> 149:156823d33999 3453 * | | |For ISP Read Checksum command, ISPDAT is the checksum result.
<> 149:156823d33999 3454 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
<> 149:156823d33999 3455 * @var FMC_T::ISPCMD
<> 149:156823d33999 3456 * Offset: 0x0C ISP CMD Register
<> 149:156823d33999 3457 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3458 * |Bits |Field |Descriptions
<> 149:156823d33999 3459 * | :----: | :----: | :---- |
<> 149:156823d33999 3460 * |[6:0] |CMD |ISP CMD
<> 149:156823d33999 3461 * | | |ISP command table is shown below:
<> 149:156823d33999 3462 * | | |0x00= FLASH Read.
<> 149:156823d33999 3463 * | | |0x04= Read Unique ID.
<> 149:156823d33999 3464 * | | |0x0B= Read Company ID.
<> 149:156823d33999 3465 * | | |0x0C= Read Device ID.
<> 149:156823d33999 3466 * | | |0x0D= Read Checksum.
<> 149:156823d33999 3467 * | | |0x21= FLASH 32-bit Program.
<> 149:156823d33999 3468 * | | |0x22= FLASH Page Erase.
<> 149:156823d33999 3469 * | | |0x27= FLASH Multi-Word Program.
<> 149:156823d33999 3470 * | | |0x2D= Run Checksum Calculation.
<> 149:156823d33999 3471 * | | |0x2E= Vector Remap.
<> 149:156823d33999 3472 * | | |0x61= FLASH 64-bit Program.
<> 149:156823d33999 3473 * | | |The other commands are invalid.
<> 149:156823d33999 3474 * @var FMC_T::ISPTRG
<> 149:156823d33999 3475 * Offset: 0x10 ISP Trigger Control Register
<> 149:156823d33999 3476 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3477 * |Bits |Field |Descriptions
<> 149:156823d33999 3478 * | :----: | :----: | :---- |
<> 149:156823d33999 3479 * |[0] |ISPGO |ISP Start Trigger (Write Protect)
<> 149:156823d33999 3480 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
<> 149:156823d33999 3481 * | | |0 = ISP operation is finished.
<> 149:156823d33999 3482 * | | |1 = ISP is progressed.
<> 149:156823d33999 3483 * @var FMC_T::DFBA
<> 149:156823d33999 3484 * Offset: 0x14 Data Flash Base Address
<> 149:156823d33999 3485 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3486 * |Bits |Field |Descriptions
<> 149:156823d33999 3487 * | :----: | :----: | :---- |
<> 149:156823d33999 3488 * |[31:0] |DFBA |Data Flash Base Address
<> 149:156823d33999 3489 * | | |This register indicates Data Flash start address. It is a read only register.
<> 149:156823d33999 3490 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
<> 149:156823d33999 3491 * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
<> 149:156823d33999 3492 * @var FMC_T::FTCTL
<> 149:156823d33999 3493 * Offset: 0x18 Flash Access Time Control Register
<> 149:156823d33999 3494 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3495 * |Bits |Field |Descriptions
<> 149:156823d33999 3496 * | :----: | :----: | :---- |
<> 149:156823d33999 3497 * |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
<> 149:156823d33999 3498 * | | |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
<> 149:156823d33999 3499 * | | |001 = Frequency <= 12MHz.
<> 149:156823d33999 3500 * | | |010 = Frequency <= 36MHz.
<> 149:156823d33999 3501 * | | |100 = Frequency <= 60MHz.
<> 149:156823d33999 3502 * | | |Others = Frequency <= 72MHz.
<> 149:156823d33999 3503 * @var FMC_T::ISPSTS
<> 149:156823d33999 3504 * Offset: 0x40 ISP Status Register
<> 149:156823d33999 3505 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3506 * |Bits |Field |Descriptions
<> 149:156823d33999 3507 * | :----: | :----: | :---- |
<> 149:156823d33999 3508 * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
<> 149:156823d33999 3509 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
<> 149:156823d33999 3510 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
<> 149:156823d33999 3511 * | | |0 = ISP operation is finished.
<> 149:156823d33999 3512 * | | |1 = ISP is progressed.
<> 149:156823d33999 3513 * |[2:1] |CBS |Boot Selection Of CONFIG (Read Only)
<> 149:156823d33999 3514 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
<> 149:156823d33999 3515 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
<> 149:156823d33999 3516 * | | |00 = LDROM with IAP mode.
<> 149:156823d33999 3517 * | | |01 = LDROM without IAP mode.
<> 149:156823d33999 3518 * | | |10 = APROM with IAP mode.
<> 149:156823d33999 3519 * | | |11 = APROM without IAP mode.
<> 149:156823d33999 3520 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
<> 149:156823d33999 3521 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
<> 149:156823d33999 3522 * | | |0 = Booting from Boot Loader.
<> 149:156823d33999 3523 * | | |1 = Booting
<> 149:156823d33999 3524 * | | |from LDROM/APROM.(see CBS bit setting)
<> 149:156823d33999 3525 * |[5] |PGFF |Flash Program With Fast Verification Flag (Read Only)
<> 149:156823d33999 3526 * | | |This bit is set if data is mismatched at ISP programming verification.
<> 149:156823d33999 3527 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation.
<> 149:156823d33999 3528 * | | |0 = Flash Program is success.
<> 149:156823d33999 3529 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
<> 149:156823d33999 3530 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
<> 149:156823d33999 3531 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
<> 149:156823d33999 3532 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
<> 149:156823d33999 3533 * | | |(1) APROM writes to itself if APUEN is set to 0.
<> 149:156823d33999 3534 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
<> 149:156823d33999 3535 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
<> 149:156823d33999 3536 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
<> 149:156823d33999 3537 * | | |(5) SPROM is programmed at SPROM secured mode.
<> 149:156823d33999 3538 * | | |(6) Page Erase command at LOCK mode with ICE connection
<> 149:156823d33999 3539 * | | |(7) Erase or Program command at brown-out detected
<> 149:156823d33999 3540 * | | |(8) Destination address is illegal, such as over an available range.
<> 149:156823d33999 3541 * | | |(9) Invalid ISP commands
<> 149:156823d33999 3542 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
<> 149:156823d33999 3543 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
<> 149:156823d33999 3544 * @var FMC_T::MPDAT0
<> 149:156823d33999 3545 * Offset: 0x80 ISP Data0 Register
<> 149:156823d33999 3546 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3547 * |Bits |Field |Descriptions
<> 149:156823d33999 3548 * | :----: | :----: | :---- |
<> 149:156823d33999 3549 * |[31:0] |ISPDAT0 |ISP Data 0
<> 149:156823d33999 3550 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
<> 149:156823d33999 3551 * @var FMC_T::MPDAT1
<> 149:156823d33999 3552 * Offset: 0x84 ISP Data1 Register
<> 149:156823d33999 3553 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3554 * |Bits |Field |Descriptions
<> 149:156823d33999 3555 * | :----: | :----: | :---- |
<> 149:156823d33999 3556 * |[31:0] |ISPDAT1 |ISP Data 1
<> 149:156823d33999 3557 * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
<> 149:156823d33999 3558 * @var FMC_T::MPDAT2
<> 149:156823d33999 3559 * Offset: 0x88 ISP Data2 Register
<> 149:156823d33999 3560 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3561 * |Bits |Field |Descriptions
<> 149:156823d33999 3562 * | :----: | :----: | :---- |
<> 149:156823d33999 3563 * |[31:0] |ISPDAT2 |ISP Data 2
<> 149:156823d33999 3564 * | | |This register is the third 32-bit data for multi-word programming.
<> 149:156823d33999 3565 * @var FMC_T::MPDAT3
<> 149:156823d33999 3566 * Offset: 0x8C ISP Data3 Register
<> 149:156823d33999 3567 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3568 * |Bits |Field |Descriptions
<> 149:156823d33999 3569 * | :----: | :----: | :---- |
<> 149:156823d33999 3570 * |[31:0] |ISPDAT3 |ISP Data 3
<> 149:156823d33999 3571 * | | |This register is the fourth 32-bit data for multi-word programming.
<> 149:156823d33999 3572 * @var FMC_T::MPSTS
<> 149:156823d33999 3573 * Offset: 0xC0 ISP Multi-Program Status Register
<> 149:156823d33999 3574 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3575 * |Bits |Field |Descriptions
<> 149:156823d33999 3576 * | :----: | :----: | :---- |
<> 149:156823d33999 3577 * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
<> 149:156823d33999 3578 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
<> 149:156823d33999 3579 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
<> 149:156823d33999 3580 * | | |0 = ISP Multi-Word program operation is finished.
<> 149:156823d33999 3581 * | | |1 = ISP Multi-Word program operation
<> 149:156823d33999 3582 * | | |is progressed.
<> 149:156823d33999 3583 * |[1] |PPGO |ISP Multi-Program Status (Read Only)
<> 149:156823d33999 3584 * | | |0 = ISP multi-word program operation is not active.
<> 149:156823d33999 3585 * | | |1 = ISP multi-word program operation is in progress.
<> 149:156823d33999 3586 * |[2] |ISPFF |ISP Fail Flag (Read Only)
<> 149:156823d33999 3587 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
<> 149:156823d33999 3588 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
<> 149:156823d33999 3589 * | | |(1) APROM writes to itself if APUEN is set to 0.
<> 149:156823d33999 3590 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
<> 149:156823d33999 3591 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
<> 149:156823d33999 3592 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
<> 149:156823d33999 3593 * | | |(5) SPROM is programmed at SPROM secured mode.
<> 149:156823d33999 3594 * | | |(6) Page Erase command at LOCK mode with ICE connection
<> 149:156823d33999 3595 * | | |(7) Erase or Program command at brown-out detected
<> 149:156823d33999 3596 * | | |(8) Destination address is illegal, such as over an available range.
<> 149:156823d33999 3597 * | | |(9) Invalid ISP commands
<> 149:156823d33999 3598 * |[4] |D0 |ISP DATA 0 Flag (Read Only)
<> 149:156823d33999 3599 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
<> 149:156823d33999 3600 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
<> 149:156823d33999 3601 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
<> 149:156823d33999 3602 * |[5] |D1 |ISP DATA 1 Flag (Read Only)
<> 149:156823d33999 3603 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
<> 149:156823d33999 3604 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
<> 149:156823d33999 3605 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
<> 149:156823d33999 3606 * |[6] |D2 |ISP DATA 2 Flag (Read Only)
<> 149:156823d33999 3607 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
<> 149:156823d33999 3608 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
<> 149:156823d33999 3609 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
<> 149:156823d33999 3610 * |[7] |D3 |ISP DATA 3 Flag (Read Only)
<> 149:156823d33999 3611 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
<> 149:156823d33999 3612 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
<> 149:156823d33999 3613 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
<> 149:156823d33999 3614 * @var FMC_T::MPADDR
<> 149:156823d33999 3615 * Offset: 0xC4 ISP Multi-Program Address Register
<> 149:156823d33999 3616 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3617 * |Bits |Field |Descriptions
<> 149:156823d33999 3618 * | :----: | :----: | :---- |
<> 149:156823d33999 3619 * |[31:0] |MPADDR |ISP Multi-Word Program Address
<> 149:156823d33999 3620 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
<> 149:156823d33999 3621 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
<> 149:156823d33999 3622 */
<> 149:156823d33999 3623
<> 149:156823d33999 3624 __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
<> 149:156823d33999 3625 __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
<> 149:156823d33999 3626 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
<> 149:156823d33999 3627 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
<> 149:156823d33999 3628 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
<> 149:156823d33999 3629 __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
<> 149:156823d33999 3630 __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
<> 149:156823d33999 3631 __I uint32_t RESERVE0[9];
<> 149:156823d33999 3632 __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
<> 149:156823d33999 3633 __I uint32_t RESERVE1[15];
<> 149:156823d33999 3634 __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
<> 149:156823d33999 3635 __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
<> 149:156823d33999 3636 __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
<> 149:156823d33999 3637 __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
<> 149:156823d33999 3638 __I uint32_t RESERVE2[12];
<> 149:156823d33999 3639 __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
<> 149:156823d33999 3640 __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
<> 149:156823d33999 3641
<> 149:156823d33999 3642 } FMC_T;
<> 149:156823d33999 3643
<> 149:156823d33999 3644
<> 149:156823d33999 3645
<> 149:156823d33999 3646
<> 149:156823d33999 3647 /**
<> 149:156823d33999 3648 @addtogroup FMC_CONST FMC Bit Field Definition
<> 149:156823d33999 3649 Constant Definitions for FMC Controller
<> 149:156823d33999 3650 @{ */
<> 149:156823d33999 3651
<> 149:156823d33999 3652 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
<> 149:156823d33999 3653 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
<> 149:156823d33999 3654
<> 149:156823d33999 3655 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
<> 149:156823d33999 3656 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
<> 149:156823d33999 3657
<> 149:156823d33999 3658 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
<> 149:156823d33999 3659 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
<> 149:156823d33999 3660
<> 149:156823d33999 3661 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
<> 149:156823d33999 3662 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
<> 149:156823d33999 3663
<> 149:156823d33999 3664 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
<> 149:156823d33999 3665 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
<> 149:156823d33999 3666
<> 149:156823d33999 3667 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
<> 149:156823d33999 3668 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
<> 149:156823d33999 3669
<> 149:156823d33999 3670 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
<> 149:156823d33999 3671 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
<> 149:156823d33999 3672
<> 149:156823d33999 3673 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
<> 149:156823d33999 3674 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
<> 149:156823d33999 3675
<> 149:156823d33999 3676 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
<> 149:156823d33999 3677 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
<> 149:156823d33999 3678
<> 149:156823d33999 3679 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
<> 149:156823d33999 3680 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
<> 149:156823d33999 3681
<> 149:156823d33999 3682 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
<> 149:156823d33999 3683 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
<> 149:156823d33999 3684
<> 149:156823d33999 3685 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
<> 149:156823d33999 3686 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
<> 149:156823d33999 3687
<> 149:156823d33999 3688 #define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
<> 149:156823d33999 3689 #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
<> 149:156823d33999 3690
<> 149:156823d33999 3691 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
<> 149:156823d33999 3692 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
<> 149:156823d33999 3693
<> 149:156823d33999 3694 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
<> 149:156823d33999 3695 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
<> 149:156823d33999 3696
<> 149:156823d33999 3697 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
<> 149:156823d33999 3698 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
<> 149:156823d33999 3699
<> 149:156823d33999 3700 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
<> 149:156823d33999 3701 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
<> 149:156823d33999 3702
<> 149:156823d33999 3703 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
<> 149:156823d33999 3704 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
<> 149:156823d33999 3705
<> 149:156823d33999 3706 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
<> 149:156823d33999 3707 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
<> 149:156823d33999 3708
<> 149:156823d33999 3709 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
<> 149:156823d33999 3710 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
<> 149:156823d33999 3711
<> 149:156823d33999 3712 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
<> 149:156823d33999 3713 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
<> 149:156823d33999 3714
<> 149:156823d33999 3715 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
<> 149:156823d33999 3716 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
<> 149:156823d33999 3717
<> 149:156823d33999 3718 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
<> 149:156823d33999 3719 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
<> 149:156823d33999 3720
<> 149:156823d33999 3721 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
<> 149:156823d33999 3722 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
<> 149:156823d33999 3723
<> 149:156823d33999 3724 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
<> 149:156823d33999 3725 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
<> 149:156823d33999 3726
<> 149:156823d33999 3727 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
<> 149:156823d33999 3728 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
<> 149:156823d33999 3729
<> 149:156823d33999 3730 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
<> 149:156823d33999 3731 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
<> 149:156823d33999 3732
<> 149:156823d33999 3733 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
<> 149:156823d33999 3734 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
<> 149:156823d33999 3735
<> 149:156823d33999 3736 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
<> 149:156823d33999 3737 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
<> 149:156823d33999 3738
<> 149:156823d33999 3739 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
<> 149:156823d33999 3740 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
<> 149:156823d33999 3741
<> 149:156823d33999 3742 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
<> 149:156823d33999 3743 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
<> 149:156823d33999 3744
<> 149:156823d33999 3745 /**@}*/ /* FMC_CONST */
<> 149:156823d33999 3746 /**@}*/ /* end of FMC register group */
<> 149:156823d33999 3747
<> 149:156823d33999 3748
<> 149:156823d33999 3749 /*---------------------- General Purpose Input/Output Controller -------------------------*/
<> 149:156823d33999 3750 /**
<> 149:156823d33999 3751 @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
<> 149:156823d33999 3752 Memory Mapped Structure for GPIO Controller
<> 149:156823d33999 3753 @{ */
<> 149:156823d33999 3754
<> 149:156823d33999 3755
<> 149:156823d33999 3756 typedef struct
<> 149:156823d33999 3757 {
<> 149:156823d33999 3758
<> 149:156823d33999 3759
<> 149:156823d33999 3760
<> 149:156823d33999 3761 /**
<> 149:156823d33999 3762 * @var GPIO_T::MODE
<> 149:156823d33999 3763 * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
<> 149:156823d33999 3764 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3765 * |Bits |Field |Descriptions
<> 149:156823d33999 3766 * | :----: | :----: | :---- |
<> 149:156823d33999 3767 * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
<> 149:156823d33999 3768 * | | |Determine each I/O mode of Px.n pins.
<> 149:156823d33999 3769 * | | |00 = Px.n is in Input mode.
<> 149:156823d33999 3770 * | | |01 = Px.n is in Push-pull Output mode.
<> 149:156823d33999 3771 * | | |10 = Px.n is in Open-drain Output mode.
<> 149:156823d33999 3772 * | | |11 = Px.n is in Quasi-bidirectional mode.
<> 149:156823d33999 3773 * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
<> 149:156823d33999 3774 * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
<> 149:156823d33999 3775 * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
<> 149:156823d33999 3776 * | | |input mode after chip powered on.
<> 149:156823d33999 3777 * | | |Note2:
<> 149:156823d33999 3778 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3779 * | | |n=0~14 for port E.
<> 149:156823d33999 3780 * | | |n=0~7 for port F.
<> 149:156823d33999 3781 * @var GPIO_T::DINOFF
<> 149:156823d33999 3782 * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
<> 149:156823d33999 3783 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3784 * |Bits |Field |Descriptions
<> 149:156823d33999 3785 * | :----: | :----: | :---- |
<> 149:156823d33999 3786 * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Control
<> 149:156823d33999 3787 * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
<> 149:156823d33999 3788 * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
<> 149:156823d33999 3789 * | | |0 = Px.n digital input path Enabled.
<> 149:156823d33999 3790 * | | |1 = Px.n digital input path Disabled (digital input tied to low).
<> 149:156823d33999 3791 * | | |Note:
<> 149:156823d33999 3792 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3793 * | | |n=0~14 for port E.
<> 149:156823d33999 3794 * | | |n=0~7 for port F.
<> 149:156823d33999 3795 * @var GPIO_T::DOUT
<> 149:156823d33999 3796 * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
<> 149:156823d33999 3797 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3798 * |Bits |Field |Descriptions
<> 149:156823d33999 3799 * | :----: | :----: | :---- |
<> 149:156823d33999 3800 * |[n] |DOUTn |Port A-F Pin[n] Output Value
<> 149:156823d33999 3801 * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
<> 149:156823d33999 3802 * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
<> 149:156823d33999 3803 * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
<> 149:156823d33999 3804 * | | |Note:
<> 149:156823d33999 3805 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3806 * | | |n=0~14 for port E.
<> 149:156823d33999 3807 * | | |n=0~7 for port F.
<> 149:156823d33999 3808 * @var GPIO_T::DATMSK
<> 149:156823d33999 3809 * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
<> 149:156823d33999 3810 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3811 * |Bits |Field |Descriptions
<> 149:156823d33999 3812 * | :----: | :----: | :---- |
<> 149:156823d33999 3813 * |[n] |DMASKn |Port A-F Pin[n] Data Output Write Mask
<> 149:156823d33999 3814 * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
<> 149:156823d33999 3815 * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
<> 149:156823d33999 3816 * | | |If the write signal is masked, writing data to the protect bit is ignored.
<> 149:156823d33999 3817 * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
<> 149:156823d33999 3818 * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
<> 149:156823d33999 3819 * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
<> 149:156823d33999 3820 * | | |Note2:
<> 149:156823d33999 3821 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3822 * | | |n=0~14 for port E.
<> 149:156823d33999 3823 * | | |n=0~7 for port F.
<> 149:156823d33999 3824 * @var GPIO_T::PIN
<> 149:156823d33999 3825 * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value
<> 149:156823d33999 3826 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3827 * |Bits |Field |Descriptions
<> 149:156823d33999 3828 * | :----: | :----: | :---- |
<> 149:156823d33999 3829 * |[n] |PINn |Port A-F Pin[n] Pin Value
<> 149:156823d33999 3830 * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
<> 149:156823d33999 3831 * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
<> 149:156823d33999 3832 * | | |Note:
<> 149:156823d33999 3833 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3834 * | | |n=0~14 for port E.
<> 149:156823d33999 3835 * | | |n=0~7 for port F.
<> 149:156823d33999 3836 * @var GPIO_T::DBEN
<> 149:156823d33999 3837 * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
<> 149:156823d33999 3838 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3839 * |Bits |Field |Descriptions
<> 149:156823d33999 3840 * | :----: | :----: | :---- |
<> 149:156823d33999 3841 * |[n] |DBENn |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
<> 149:156823d33999 3842 * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
<> 149:156823d33999 3843 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 149:156823d33999 3844 * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
<> 149:156823d33999 3845 * | | |0 = Px.n de-bounce function Disabled.
<> 149:156823d33999 3846 * | | |1 = Px.n de-bounce function Enabled.
<> 149:156823d33999 3847 * | | |The de-bounce function is valid only for edge triggered interrupt.
<> 149:156823d33999 3848 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 149:156823d33999 3849 * | | |Note:
<> 149:156823d33999 3850 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3851 * | | |n=0~14 for port E.
<> 149:156823d33999 3852 * | | |n=0~7 for port F.
<> 149:156823d33999 3853 * @var GPIO_T::INTTYPE
<> 149:156823d33999 3854 * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
<> 149:156823d33999 3855 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3856 * |Bits |Field |Descriptions
<> 149:156823d33999 3857 * | :----: | :----: | :---- |
<> 149:156823d33999 3858 * |[n] |TYPEn |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
<> 149:156823d33999 3859 * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
<> 149:156823d33999 3860 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 149:156823d33999 3861 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
<> 149:156823d33999 3862 * | | |0 = Edge trigger interrupt.
<> 149:156823d33999 3863 * | | |1 = Level trigger interrupt.
<> 149:156823d33999 3864 * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
<> 149:156823d33999 3865 * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
<> 149:156823d33999 3866 * | | |The de-bounce function is valid only for edge triggered interrupt.
<> 149:156823d33999 3867 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 149:156823d33999 3868 * | | |Note:
<> 149:156823d33999 3869 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3870 * | | |n=0~14 for port E.
<> 149:156823d33999 3871 * | | |n=0~7 for port F.
<> 149:156823d33999 3872 * @var GPIO_T::INTEN
<> 149:156823d33999 3873 * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
<> 149:156823d33999 3874 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3875 * |Bits |Field |Descriptions
<> 149:156823d33999 3876 * | :----: | :----: | :---- |
<> 149:156823d33999 3877 * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
<> 149:156823d33999 3878 * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
<> 149:156823d33999 3879 * | | |Set bit to 1 also enable the pin wake-up function.
<> 149:156823d33999 3880 * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
<> 149:156823d33999 3881 * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
<> 149:156823d33999 3882 * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
<> 149:156823d33999 3883 * | | |0 = Px.n level low or high to low interrupt Disabled.
<> 149:156823d33999 3884 * | | |1 = Px.n level low or high to low interrupt Enabled.
<> 149:156823d33999 3885 * | | |Note:
<> 149:156823d33999 3886 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3887 * | | |n=0~14 for port E.
<> 149:156823d33999 3888 * | | |n=0~7 for port F.
<> 149:156823d33999 3889 * @var GPIO_T::INTSRC
<> 149:156823d33999 3890 * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
<> 149:156823d33999 3891 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3892 * |Bits |Field |Descriptions
<> 149:156823d33999 3893 * | :----: | :----: | :---- |
<> 149:156823d33999 3894 * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
<> 149:156823d33999 3895 * | | |Write Operation :
<> 149:156823d33999 3896 * | | |0 = No action.
<> 149:156823d33999 3897 * | | |1 = Clear the corresponding pending interrupt.
<> 149:156823d33999 3898 * | | |Read Operation :
<> 149:156823d33999 3899 * | | |0 = No interrupt at Px.n.
<> 149:156823d33999 3900 * | | |1 = Px.n generates an interrupt.
<> 149:156823d33999 3901 * | | |Note:
<> 149:156823d33999 3902 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3903 * | | |n=0~14 for port E.
<> 149:156823d33999 3904 * | | |n=0~7 for port F.
<> 149:156823d33999 3905 * @var GPIO_T::SMTEN
<> 149:156823d33999 3906 * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
<> 149:156823d33999 3907 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3908 * |Bits |Field |Descriptions
<> 149:156823d33999 3909 * | :----: | :----: | :---- |
<> 149:156823d33999 3910 * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
<> 149:156823d33999 3911 * | | |0 = Px.n input Schmitt trigger function Disabled.
<> 149:156823d33999 3912 * | | |1 = Px.n input Schmitt trigger function Enabled.
<> 149:156823d33999 3913 * | | |Note:
<> 149:156823d33999 3914 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3915 * | | |n=0~14 for port E.
<> 149:156823d33999 3916 * | | |n=0~7 for port F.
<> 149:156823d33999 3917 * @var GPIO_T::SLEWCTL
<> 149:156823d33999 3918 * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
<> 149:156823d33999 3919 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3920 * |Bits |Field |Descriptions
<> 149:156823d33999 3921 * | :----: | :----: | :---- |
<> 149:156823d33999 3922 * |[n] |HSRENn |Port A-F Pin[n] High Slew Rate Control
<> 149:156823d33999 3923 * | | |0 = Px.n output with basic slew rate.
<> 149:156823d33999 3924 * | | |1 = Px.n output with higher slew rate.
<> 149:156823d33999 3925 * | | |Note:
<> 149:156823d33999 3926 * | | |n=0~15 for port A/B/C/D.
<> 149:156823d33999 3927 * | | |n=0~14 for port E.
<> 149:156823d33999 3928 * | | |n=0~7 for port F.
<> 149:156823d33999 3929 * @var GPIO_T::DRVCTL
<> 149:156823d33999 3930 * Offset: 0x2C Port E High Drive Strength Control Register
<> 149:156823d33999 3931 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3932 * |Bits |Field |Descriptions
<> 149:156823d33999 3933 * | :----: | :----: | :---- |
<> 149:156823d33999 3934 * |[n] |HDRVENn |Port E Pin[n] Driving Strength Control
<> 149:156823d33999 3935 * | | |0 = Px.n output with basic driving strength.
<> 149:156823d33999 3936 * | | |1 = Px.n output with high driving strength.
<> 149:156823d33999 3937 * | | |Note:
<> 149:156823d33999 3938 * | | |n=8,9..13 for port E.
<> 149:156823d33999 3939 */
<> 149:156823d33999 3940
<> 149:156823d33999 3941 __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
<> 149:156823d33999 3942 __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
<> 149:156823d33999 3943 __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
<> 149:156823d33999 3944 __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
<> 149:156823d33999 3945 __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
<> 149:156823d33999 3946 __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
<> 149:156823d33999 3947 __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
<> 149:156823d33999 3948 __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
<> 149:156823d33999 3949 __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
<> 149:156823d33999 3950 __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
<> 149:156823d33999 3951 __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
<> 149:156823d33999 3952 __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
<> 149:156823d33999 3953
<> 149:156823d33999 3954 } GPIO_T;
<> 149:156823d33999 3955
<> 149:156823d33999 3956
<> 149:156823d33999 3957
<> 149:156823d33999 3958
<> 149:156823d33999 3959 typedef struct
<> 149:156823d33999 3960 {
<> 149:156823d33999 3961
<> 149:156823d33999 3962
<> 149:156823d33999 3963
<> 149:156823d33999 3964 /**
<> 149:156823d33999 3965 * @var GPIO_DBCTL_T::DBCTL
<> 149:156823d33999 3966 * Offset: 0x440 Interrupt De-bounce Control Register
<> 149:156823d33999 3967 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 3968 * |Bits |Field |Descriptions
<> 149:156823d33999 3969 * | :----: | :----: | :---- |
<> 149:156823d33999 3970 * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
<> 149:156823d33999 3971 * | | |0000 = Sample interrupt input once per 1 clocks.
<> 149:156823d33999 3972 * | | |0001 = Sample interrupt input once per 2 clocks.
<> 149:156823d33999 3973 * | | |0010 = Sample interrupt input once per 4 clocks.
<> 149:156823d33999 3974 * | | |0011 = Sample interrupt input once per 8 clocks.
<> 149:156823d33999 3975 * | | |0100 = Sample interrupt input once per 16 clocks.
<> 149:156823d33999 3976 * | | |0101 = Sample interrupt input once per 32 clocks.
<> 149:156823d33999 3977 * | | |0110 = Sample interrupt input once per 64 clocks.
<> 149:156823d33999 3978 * | | |0111 = Sample interrupt input once per 128 clocks.
<> 149:156823d33999 3979 * | | |1000 = Sample interrupt input once per 256 clocks.
<> 149:156823d33999 3980 * | | |1001 = Sample interrupt input once per 2*256 clocks.
<> 149:156823d33999 3981 * | | |1010 = Sample interrupt input once per 4*256 clocks.
<> 149:156823d33999 3982 * | | |1011 = Sample interrupt input once per 8*256 clocks.
<> 149:156823d33999 3983 * | | |1100 = Sample interrupt input once per 16*256 clocks.
<> 149:156823d33999 3984 * | | |1101 = Sample interrupt input once per 32*256 clocks.
<> 149:156823d33999 3985 * | | |1110 = Sample interrupt input once per 64*256 clocks.
<> 149:156823d33999 3986 * | | |1111 = Sample interrupt input once per 128*256 clocks.
<> 149:156823d33999 3987 * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
<> 149:156823d33999 3988 * | | |0 = De-bounce counter clock source is the HCLK.
<> 149:156823d33999 3989 * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
<> 149:156823d33999 3990 * |[5] |ICLKON |Interrupt Clock On Mode
<> 149:156823d33999 3991 * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
<> 149:156823d33999 3992 * | | |1 = All I/O pins edge detection circuit is always active after reset.
<> 149:156823d33999 3993 * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
<> 149:156823d33999 3994 */
<> 149:156823d33999 3995
<> 149:156823d33999 3996 __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
<> 149:156823d33999 3997
<> 149:156823d33999 3998 } GPIO_DBCTL_T;
<> 149:156823d33999 3999
<> 149:156823d33999 4000
<> 149:156823d33999 4001
<> 149:156823d33999 4002
<> 149:156823d33999 4003 /**
<> 149:156823d33999 4004 @addtogroup GPIO_CONST GPIO Bit Field Definition
<> 149:156823d33999 4005 Constant Definitions for GPIO Controller
<> 149:156823d33999 4006 @{ */
<> 149:156823d33999 4007
<> 149:156823d33999 4008 #define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
<> 149:156823d33999 4009 #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
<> 149:156823d33999 4010
<> 149:156823d33999 4011 #define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
<> 149:156823d33999 4012 #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
<> 149:156823d33999 4013
<> 149:156823d33999 4014 #define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
<> 149:156823d33999 4015 #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
<> 149:156823d33999 4016
<> 149:156823d33999 4017 #define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
<> 149:156823d33999 4018 #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
<> 149:156823d33999 4019
<> 149:156823d33999 4020 #define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
<> 149:156823d33999 4021 #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
<> 149:156823d33999 4022
<> 149:156823d33999 4023 #define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
<> 149:156823d33999 4024 #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
<> 149:156823d33999 4025
<> 149:156823d33999 4026 #define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
<> 149:156823d33999 4027 #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
<> 149:156823d33999 4028
<> 149:156823d33999 4029 #define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
<> 149:156823d33999 4030 #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
<> 149:156823d33999 4031
<> 149:156823d33999 4032 #define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
<> 149:156823d33999 4033 #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
<> 149:156823d33999 4034
<> 149:156823d33999 4035 #define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
<> 149:156823d33999 4036 #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
<> 149:156823d33999 4037
<> 149:156823d33999 4038 #define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
<> 149:156823d33999 4039 #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
<> 149:156823d33999 4040
<> 149:156823d33999 4041 #define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
<> 149:156823d33999 4042 #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
<> 149:156823d33999 4043
<> 149:156823d33999 4044 #define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
<> 149:156823d33999 4045 #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
<> 149:156823d33999 4046
<> 149:156823d33999 4047 #define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
<> 149:156823d33999 4048 #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
<> 149:156823d33999 4049
<> 149:156823d33999 4050 #define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
<> 149:156823d33999 4051 #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
<> 149:156823d33999 4052
<> 149:156823d33999 4053 #define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
<> 149:156823d33999 4054 #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
<> 149:156823d33999 4055
<> 149:156823d33999 4056 #define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
<> 149:156823d33999 4057 #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
<> 149:156823d33999 4058
<> 149:156823d33999 4059 #define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
<> 149:156823d33999 4060 #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
<> 149:156823d33999 4061
<> 149:156823d33999 4062 #define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
<> 149:156823d33999 4063 #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
<> 149:156823d33999 4064
<> 149:156823d33999 4065 #define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
<> 149:156823d33999 4066 #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
<> 149:156823d33999 4067
<> 149:156823d33999 4068 #define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
<> 149:156823d33999 4069 #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
<> 149:156823d33999 4070
<> 149:156823d33999 4071 #define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
<> 149:156823d33999 4072 #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
<> 149:156823d33999 4073
<> 149:156823d33999 4074 #define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
<> 149:156823d33999 4075 #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
<> 149:156823d33999 4076
<> 149:156823d33999 4077 #define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
<> 149:156823d33999 4078 #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
<> 149:156823d33999 4079
<> 149:156823d33999 4080 #define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
<> 149:156823d33999 4081 #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
<> 149:156823d33999 4082
<> 149:156823d33999 4083 #define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
<> 149:156823d33999 4084 #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
<> 149:156823d33999 4085
<> 149:156823d33999 4086 #define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
<> 149:156823d33999 4087 #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
<> 149:156823d33999 4088
<> 149:156823d33999 4089 #define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
<> 149:156823d33999 4090 #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
<> 149:156823d33999 4091
<> 149:156823d33999 4092 #define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
<> 149:156823d33999 4093 #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
<> 149:156823d33999 4094
<> 149:156823d33999 4095 #define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
<> 149:156823d33999 4096 #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
<> 149:156823d33999 4097
<> 149:156823d33999 4098 #define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
<> 149:156823d33999 4099 #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
<> 149:156823d33999 4100
<> 149:156823d33999 4101 #define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
<> 149:156823d33999 4102 #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
<> 149:156823d33999 4103
<> 149:156823d33999 4104 #define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
<> 149:156823d33999 4105 #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
<> 149:156823d33999 4106
<> 149:156823d33999 4107 #define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
<> 149:156823d33999 4108 #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
<> 149:156823d33999 4109
<> 149:156823d33999 4110 #define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
<> 149:156823d33999 4111 #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
<> 149:156823d33999 4112
<> 149:156823d33999 4113 #define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
<> 149:156823d33999 4114 #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
<> 149:156823d33999 4115
<> 149:156823d33999 4116 #define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
<> 149:156823d33999 4117 #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
<> 149:156823d33999 4118
<> 149:156823d33999 4119 #define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
<> 149:156823d33999 4120 #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
<> 149:156823d33999 4121
<> 149:156823d33999 4122 #define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
<> 149:156823d33999 4123 #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
<> 149:156823d33999 4124
<> 149:156823d33999 4125 #define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
<> 149:156823d33999 4126 #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
<> 149:156823d33999 4127
<> 149:156823d33999 4128 #define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
<> 149:156823d33999 4129 #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
<> 149:156823d33999 4130
<> 149:156823d33999 4131 #define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
<> 149:156823d33999 4132 #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
<> 149:156823d33999 4133
<> 149:156823d33999 4134 #define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
<> 149:156823d33999 4135 #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
<> 149:156823d33999 4136
<> 149:156823d33999 4137 #define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
<> 149:156823d33999 4138 #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
<> 149:156823d33999 4139
<> 149:156823d33999 4140 #define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
<> 149:156823d33999 4141 #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
<> 149:156823d33999 4142
<> 149:156823d33999 4143 #define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
<> 149:156823d33999 4144 #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
<> 149:156823d33999 4145
<> 149:156823d33999 4146 #define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
<> 149:156823d33999 4147 #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
<> 149:156823d33999 4148
<> 149:156823d33999 4149 #define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
<> 149:156823d33999 4150 #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
<> 149:156823d33999 4151
<> 149:156823d33999 4152 #define GPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */
<> 149:156823d33999 4153 #define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */
<> 149:156823d33999 4154
<> 149:156823d33999 4155 #define GPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */
<> 149:156823d33999 4156 #define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */
<> 149:156823d33999 4157
<> 149:156823d33999 4158 #define GPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */
<> 149:156823d33999 4159 #define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */
<> 149:156823d33999 4160
<> 149:156823d33999 4161 #define GPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */
<> 149:156823d33999 4162 #define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */
<> 149:156823d33999 4163
<> 149:156823d33999 4164 #define GPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */
<> 149:156823d33999 4165 #define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */
<> 149:156823d33999 4166
<> 149:156823d33999 4167 #define GPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */
<> 149:156823d33999 4168 #define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */
<> 149:156823d33999 4169
<> 149:156823d33999 4170 #define GPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */
<> 149:156823d33999 4171 #define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */
<> 149:156823d33999 4172
<> 149:156823d33999 4173 #define GPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */
<> 149:156823d33999 4174 #define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */
<> 149:156823d33999 4175
<> 149:156823d33999 4176 #define GPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */
<> 149:156823d33999 4177 #define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */
<> 149:156823d33999 4178
<> 149:156823d33999 4179 #define GPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */
<> 149:156823d33999 4180 #define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */
<> 149:156823d33999 4181
<> 149:156823d33999 4182 #define GPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */
<> 149:156823d33999 4183 #define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */
<> 149:156823d33999 4184
<> 149:156823d33999 4185 #define GPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */
<> 149:156823d33999 4186 #define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */
<> 149:156823d33999 4187
<> 149:156823d33999 4188 #define GPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */
<> 149:156823d33999 4189 #define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */
<> 149:156823d33999 4190
<> 149:156823d33999 4191 #define GPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */
<> 149:156823d33999 4192 #define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */
<> 149:156823d33999 4193
<> 149:156823d33999 4194 #define GPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */
<> 149:156823d33999 4195 #define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */
<> 149:156823d33999 4196
<> 149:156823d33999 4197 #define GPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */
<> 149:156823d33999 4198 #define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */
<> 149:156823d33999 4199
<> 149:156823d33999 4200 #define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
<> 149:156823d33999 4201 #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
<> 149:156823d33999 4202
<> 149:156823d33999 4203 #define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
<> 149:156823d33999 4204 #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
<> 149:156823d33999 4205
<> 149:156823d33999 4206 #define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
<> 149:156823d33999 4207 #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
<> 149:156823d33999 4208
<> 149:156823d33999 4209 #define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
<> 149:156823d33999 4210 #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
<> 149:156823d33999 4211
<> 149:156823d33999 4212 #define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
<> 149:156823d33999 4213 #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
<> 149:156823d33999 4214
<> 149:156823d33999 4215 #define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
<> 149:156823d33999 4216 #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
<> 149:156823d33999 4217
<> 149:156823d33999 4218 #define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
<> 149:156823d33999 4219 #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
<> 149:156823d33999 4220
<> 149:156823d33999 4221 #define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
<> 149:156823d33999 4222 #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
<> 149:156823d33999 4223
<> 149:156823d33999 4224 #define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
<> 149:156823d33999 4225 #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
<> 149:156823d33999 4226
<> 149:156823d33999 4227 #define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
<> 149:156823d33999 4228 #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
<> 149:156823d33999 4229
<> 149:156823d33999 4230 #define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
<> 149:156823d33999 4231 #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
<> 149:156823d33999 4232
<> 149:156823d33999 4233 #define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
<> 149:156823d33999 4234 #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
<> 149:156823d33999 4235
<> 149:156823d33999 4236 #define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
<> 149:156823d33999 4237 #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
<> 149:156823d33999 4238
<> 149:156823d33999 4239 #define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
<> 149:156823d33999 4240 #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
<> 149:156823d33999 4241
<> 149:156823d33999 4242 #define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
<> 149:156823d33999 4243 #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
<> 149:156823d33999 4244
<> 149:156823d33999 4245 #define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
<> 149:156823d33999 4246 #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
<> 149:156823d33999 4247
<> 149:156823d33999 4248 #define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
<> 149:156823d33999 4249 #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
<> 149:156823d33999 4250
<> 149:156823d33999 4251 #define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
<> 149:156823d33999 4252 #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
<> 149:156823d33999 4253
<> 149:156823d33999 4254 #define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
<> 149:156823d33999 4255 #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
<> 149:156823d33999 4256
<> 149:156823d33999 4257 #define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
<> 149:156823d33999 4258 #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
<> 149:156823d33999 4259
<> 149:156823d33999 4260 #define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
<> 149:156823d33999 4261 #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
<> 149:156823d33999 4262
<> 149:156823d33999 4263 #define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
<> 149:156823d33999 4264 #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
<> 149:156823d33999 4265
<> 149:156823d33999 4266 #define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
<> 149:156823d33999 4267 #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
<> 149:156823d33999 4268
<> 149:156823d33999 4269 #define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
<> 149:156823d33999 4270 #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
<> 149:156823d33999 4271
<> 149:156823d33999 4272 #define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
<> 149:156823d33999 4273 #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
<> 149:156823d33999 4274
<> 149:156823d33999 4275 #define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
<> 149:156823d33999 4276 #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
<> 149:156823d33999 4277
<> 149:156823d33999 4278 #define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
<> 149:156823d33999 4279 #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
<> 149:156823d33999 4280
<> 149:156823d33999 4281 #define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
<> 149:156823d33999 4282 #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
<> 149:156823d33999 4283
<> 149:156823d33999 4284 #define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
<> 149:156823d33999 4285 #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
<> 149:156823d33999 4286
<> 149:156823d33999 4287 #define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
<> 149:156823d33999 4288 #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
<> 149:156823d33999 4289
<> 149:156823d33999 4290 #define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
<> 149:156823d33999 4291 #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
<> 149:156823d33999 4292
<> 149:156823d33999 4293 #define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
<> 149:156823d33999 4294 #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
<> 149:156823d33999 4295
<> 149:156823d33999 4296 #define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
<> 149:156823d33999 4297 #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
<> 149:156823d33999 4298
<> 149:156823d33999 4299 #define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
<> 149:156823d33999 4300 #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
<> 149:156823d33999 4301
<> 149:156823d33999 4302 #define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
<> 149:156823d33999 4303 #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
<> 149:156823d33999 4304
<> 149:156823d33999 4305 #define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
<> 149:156823d33999 4306 #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
<> 149:156823d33999 4307
<> 149:156823d33999 4308 #define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
<> 149:156823d33999 4309 #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
<> 149:156823d33999 4310
<> 149:156823d33999 4311 #define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
<> 149:156823d33999 4312 #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
<> 149:156823d33999 4313
<> 149:156823d33999 4314 #define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
<> 149:156823d33999 4315 #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
<> 149:156823d33999 4316
<> 149:156823d33999 4317 #define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
<> 149:156823d33999 4318 #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
<> 149:156823d33999 4319
<> 149:156823d33999 4320 #define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
<> 149:156823d33999 4321 #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
<> 149:156823d33999 4322
<> 149:156823d33999 4323 #define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
<> 149:156823d33999 4324 #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
<> 149:156823d33999 4325
<> 149:156823d33999 4326 #define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
<> 149:156823d33999 4327 #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
<> 149:156823d33999 4328
<> 149:156823d33999 4329 #define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
<> 149:156823d33999 4330 #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
<> 149:156823d33999 4331
<> 149:156823d33999 4332 #define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
<> 149:156823d33999 4333 #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
<> 149:156823d33999 4334
<> 149:156823d33999 4335 #define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
<> 149:156823d33999 4336 #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
<> 149:156823d33999 4337
<> 149:156823d33999 4338 #define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
<> 149:156823d33999 4339 #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
<> 149:156823d33999 4340
<> 149:156823d33999 4341 #define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
<> 149:156823d33999 4342 #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
<> 149:156823d33999 4343
<> 149:156823d33999 4344 #define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
<> 149:156823d33999 4345 #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
<> 149:156823d33999 4346
<> 149:156823d33999 4347 #define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
<> 149:156823d33999 4348 #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
<> 149:156823d33999 4349
<> 149:156823d33999 4350 #define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
<> 149:156823d33999 4351 #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
<> 149:156823d33999 4352
<> 149:156823d33999 4353 #define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
<> 149:156823d33999 4354 #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
<> 149:156823d33999 4355
<> 149:156823d33999 4356 #define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
<> 149:156823d33999 4357 #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
<> 149:156823d33999 4358
<> 149:156823d33999 4359 #define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
<> 149:156823d33999 4360 #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
<> 149:156823d33999 4361
<> 149:156823d33999 4362 #define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
<> 149:156823d33999 4363 #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
<> 149:156823d33999 4364
<> 149:156823d33999 4365 #define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
<> 149:156823d33999 4366 #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
<> 149:156823d33999 4367
<> 149:156823d33999 4368 #define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
<> 149:156823d33999 4369 #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
<> 149:156823d33999 4370
<> 149:156823d33999 4371 #define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
<> 149:156823d33999 4372 #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
<> 149:156823d33999 4373
<> 149:156823d33999 4374 #define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
<> 149:156823d33999 4375 #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
<> 149:156823d33999 4376
<> 149:156823d33999 4377 #define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
<> 149:156823d33999 4378 #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
<> 149:156823d33999 4379
<> 149:156823d33999 4380 #define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
<> 149:156823d33999 4381 #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
<> 149:156823d33999 4382
<> 149:156823d33999 4383 #define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
<> 149:156823d33999 4384 #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
<> 149:156823d33999 4385
<> 149:156823d33999 4386 #define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
<> 149:156823d33999 4387 #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
<> 149:156823d33999 4388
<> 149:156823d33999 4389 #define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
<> 149:156823d33999 4390 #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
<> 149:156823d33999 4391
<> 149:156823d33999 4392 #define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
<> 149:156823d33999 4393 #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
<> 149:156823d33999 4394
<> 149:156823d33999 4395 #define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
<> 149:156823d33999 4396 #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
<> 149:156823d33999 4397
<> 149:156823d33999 4398 #define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
<> 149:156823d33999 4399 #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
<> 149:156823d33999 4400
<> 149:156823d33999 4401 #define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
<> 149:156823d33999 4402 #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
<> 149:156823d33999 4403
<> 149:156823d33999 4404 #define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
<> 149:156823d33999 4405 #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
<> 149:156823d33999 4406
<> 149:156823d33999 4407 #define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
<> 149:156823d33999 4408 #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
<> 149:156823d33999 4409
<> 149:156823d33999 4410 #define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
<> 149:156823d33999 4411 #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
<> 149:156823d33999 4412
<> 149:156823d33999 4413 #define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
<> 149:156823d33999 4414 #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
<> 149:156823d33999 4415
<> 149:156823d33999 4416 #define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
<> 149:156823d33999 4417 #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
<> 149:156823d33999 4418
<> 149:156823d33999 4419 #define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
<> 149:156823d33999 4420 #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
<> 149:156823d33999 4421
<> 149:156823d33999 4422 #define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
<> 149:156823d33999 4423 #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
<> 149:156823d33999 4424
<> 149:156823d33999 4425 #define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
<> 149:156823d33999 4426 #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
<> 149:156823d33999 4427
<> 149:156823d33999 4428 #define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
<> 149:156823d33999 4429 #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
<> 149:156823d33999 4430
<> 149:156823d33999 4431 #define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
<> 149:156823d33999 4432 #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
<> 149:156823d33999 4433
<> 149:156823d33999 4434 #define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
<> 149:156823d33999 4435 #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
<> 149:156823d33999 4436
<> 149:156823d33999 4437 #define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
<> 149:156823d33999 4438 #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
<> 149:156823d33999 4439
<> 149:156823d33999 4440 #define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
<> 149:156823d33999 4441 #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
<> 149:156823d33999 4442
<> 149:156823d33999 4443 #define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
<> 149:156823d33999 4444 #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
<> 149:156823d33999 4445
<> 149:156823d33999 4446 #define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
<> 149:156823d33999 4447 #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
<> 149:156823d33999 4448
<> 149:156823d33999 4449 #define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
<> 149:156823d33999 4450 #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
<> 149:156823d33999 4451
<> 149:156823d33999 4452 #define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
<> 149:156823d33999 4453 #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
<> 149:156823d33999 4454
<> 149:156823d33999 4455 #define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
<> 149:156823d33999 4456 #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
<> 149:156823d33999 4457
<> 149:156823d33999 4458 #define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
<> 149:156823d33999 4459 #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
<> 149:156823d33999 4460
<> 149:156823d33999 4461 #define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
<> 149:156823d33999 4462 #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
<> 149:156823d33999 4463
<> 149:156823d33999 4464 #define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
<> 149:156823d33999 4465 #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
<> 149:156823d33999 4466
<> 149:156823d33999 4467 #define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
<> 149:156823d33999 4468 #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
<> 149:156823d33999 4469
<> 149:156823d33999 4470 #define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
<> 149:156823d33999 4471 #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
<> 149:156823d33999 4472
<> 149:156823d33999 4473 #define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
<> 149:156823d33999 4474 #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
<> 149:156823d33999 4475
<> 149:156823d33999 4476 #define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
<> 149:156823d33999 4477 #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
<> 149:156823d33999 4478
<> 149:156823d33999 4479 #define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
<> 149:156823d33999 4480 #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
<> 149:156823d33999 4481
<> 149:156823d33999 4482 #define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
<> 149:156823d33999 4483 #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
<> 149:156823d33999 4484
<> 149:156823d33999 4485 #define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
<> 149:156823d33999 4486 #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
<> 149:156823d33999 4487
<> 149:156823d33999 4488 #define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
<> 149:156823d33999 4489 #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
<> 149:156823d33999 4490
<> 149:156823d33999 4491 #define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
<> 149:156823d33999 4492 #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
<> 149:156823d33999 4493
<> 149:156823d33999 4494 #define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
<> 149:156823d33999 4495 #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
<> 149:156823d33999 4496
<> 149:156823d33999 4497 #define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
<> 149:156823d33999 4498 #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
<> 149:156823d33999 4499
<> 149:156823d33999 4500 #define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
<> 149:156823d33999 4501 #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
<> 149:156823d33999 4502
<> 149:156823d33999 4503 #define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
<> 149:156823d33999 4504 #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
<> 149:156823d33999 4505
<> 149:156823d33999 4506 #define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
<> 149:156823d33999 4507 #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
<> 149:156823d33999 4508
<> 149:156823d33999 4509 #define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
<> 149:156823d33999 4510 #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
<> 149:156823d33999 4511
<> 149:156823d33999 4512 #define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
<> 149:156823d33999 4513 #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
<> 149:156823d33999 4514
<> 149:156823d33999 4515 #define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
<> 149:156823d33999 4516 #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
<> 149:156823d33999 4517
<> 149:156823d33999 4518 #define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
<> 149:156823d33999 4519 #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
<> 149:156823d33999 4520
<> 149:156823d33999 4521 #define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
<> 149:156823d33999 4522 #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
<> 149:156823d33999 4523
<> 149:156823d33999 4524 #define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
<> 149:156823d33999 4525 #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
<> 149:156823d33999 4526
<> 149:156823d33999 4527 #define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
<> 149:156823d33999 4528 #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
<> 149:156823d33999 4529
<> 149:156823d33999 4530 #define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
<> 149:156823d33999 4531 #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
<> 149:156823d33999 4532
<> 149:156823d33999 4533 #define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
<> 149:156823d33999 4534 #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
<> 149:156823d33999 4535
<> 149:156823d33999 4536 #define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
<> 149:156823d33999 4537 #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
<> 149:156823d33999 4538
<> 149:156823d33999 4539 #define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
<> 149:156823d33999 4540 #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
<> 149:156823d33999 4541
<> 149:156823d33999 4542 #define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
<> 149:156823d33999 4543 #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
<> 149:156823d33999 4544
<> 149:156823d33999 4545 #define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
<> 149:156823d33999 4546 #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
<> 149:156823d33999 4547
<> 149:156823d33999 4548 #define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
<> 149:156823d33999 4549 #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
<> 149:156823d33999 4550
<> 149:156823d33999 4551 #define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
<> 149:156823d33999 4552 #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
<> 149:156823d33999 4553
<> 149:156823d33999 4554 #define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
<> 149:156823d33999 4555 #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
<> 149:156823d33999 4556
<> 149:156823d33999 4557 #define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
<> 149:156823d33999 4558 #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
<> 149:156823d33999 4559
<> 149:156823d33999 4560 #define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
<> 149:156823d33999 4561 #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
<> 149:156823d33999 4562
<> 149:156823d33999 4563 #define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
<> 149:156823d33999 4564 #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
<> 149:156823d33999 4565
<> 149:156823d33999 4566 #define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
<> 149:156823d33999 4567 #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
<> 149:156823d33999 4568
<> 149:156823d33999 4569 #define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
<> 149:156823d33999 4570 #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
<> 149:156823d33999 4571
<> 149:156823d33999 4572 #define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
<> 149:156823d33999 4573 #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
<> 149:156823d33999 4574
<> 149:156823d33999 4575 #define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
<> 149:156823d33999 4576 #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
<> 149:156823d33999 4577
<> 149:156823d33999 4578 #define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
<> 149:156823d33999 4579 #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
<> 149:156823d33999 4580
<> 149:156823d33999 4581 #define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
<> 149:156823d33999 4582 #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
<> 149:156823d33999 4583
<> 149:156823d33999 4584 #define GPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */
<> 149:156823d33999 4585 #define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */
<> 149:156823d33999 4586
<> 149:156823d33999 4587 #define GPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */
<> 149:156823d33999 4588 #define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */
<> 149:156823d33999 4589
<> 149:156823d33999 4590 #define GPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */
<> 149:156823d33999 4591 #define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */
<> 149:156823d33999 4592
<> 149:156823d33999 4593 #define GPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */
<> 149:156823d33999 4594 #define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */
<> 149:156823d33999 4595
<> 149:156823d33999 4596 #define GPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */
<> 149:156823d33999 4597 #define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */
<> 149:156823d33999 4598
<> 149:156823d33999 4599 #define GPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */
<> 149:156823d33999 4600 #define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */
<> 149:156823d33999 4601
<> 149:156823d33999 4602 #define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
<> 149:156823d33999 4603 #define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
<> 149:156823d33999 4604
<> 149:156823d33999 4605 #define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
<> 149:156823d33999 4606 #define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
<> 149:156823d33999 4607
<> 149:156823d33999 4608 #define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
<> 149:156823d33999 4609 #define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
<> 149:156823d33999 4610
<> 149:156823d33999 4611
<> 149:156823d33999 4612 /**@}*/ /* GPIO_CONST */
<> 149:156823d33999 4613 /**@}*/ /* end of GPIO register group */
<> 149:156823d33999 4614
<> 149:156823d33999 4615
<> 149:156823d33999 4616 /*---------------------- Inter-IC Bus Controller -------------------------*/
<> 149:156823d33999 4617 /**
<> 149:156823d33999 4618 @addtogroup I2C Inter-IC Bus Controller(I2C)
<> 149:156823d33999 4619 Memory Mapped Structure for I2C Controller
<> 149:156823d33999 4620 @{ */
<> 149:156823d33999 4621
<> 149:156823d33999 4622
<> 149:156823d33999 4623 typedef struct
<> 149:156823d33999 4624 {
<> 149:156823d33999 4625
<> 149:156823d33999 4626
<> 149:156823d33999 4627
<> 149:156823d33999 4628
<> 149:156823d33999 4629 /**
<> 149:156823d33999 4630 * @var I2C_T::CTL
<> 149:156823d33999 4631 * Offset: 0x00 I2C Control Register
<> 149:156823d33999 4632 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4633 * |Bits |Field |Descriptions
<> 149:156823d33999 4634 * | :----: | :----: | :---- |
<> 149:156823d33999 4635 * |[2] |AA |Assert Acknowledge Control
<> 149:156823d33999 4636 * | | |When AA =1 prior to address or data is received,
<> 149:156823d33999 4637 * | | |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
<> 149:156823d33999 4638 * | | |1. A slave is acknowledging the address sent from master.
<> 149:156823d33999 4639 * | | |2. The receiver devices are acknowledging the data sent by transmitter.
<> 149:156823d33999 4640 * | | |When AA=0 prior to address or data received,
<> 149:156823d33999 4641 * | | |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
<> 149:156823d33999 4642 * |[3] |SI |I2C Interrupt Flag
<> 149:156823d33999 4643 * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
<> 149:156823d33999 4644 * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
<> 149:156823d33999 4645 * | | |SI must be cleared by software.
<> 149:156823d33999 4646 * | | |Clear SI by writing 1 to this bit.
<> 149:156823d33999 4647 * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
<> 149:156823d33999 4648 * |[4] |STO |I2C STOP Control
<> 149:156823d33999 4649 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
<> 149:156823d33999 4650 * | | |This bit will be cleared by hardware automatically.
<> 149:156823d33999 4651 * |[5] |STA |I2C START Control
<> 149:156823d33999 4652 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
<> 149:156823d33999 4653 * |[6] |I2CEN |I2C Controller Enable Bit
<> 149:156823d33999 4654 * | | |Set to enable I2C serial function controller.
<> 149:156823d33999 4655 * | | |When I2CEN=1 the I2C serial function enable.
<> 149:156823d33999 4656 * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
<> 149:156823d33999 4657 * | | |0 = Disabled.
<> 149:156823d33999 4658 * | | |1 = Enabled.
<> 149:156823d33999 4659 * |[7] |INTEN |Enable Interrupt
<> 149:156823d33999 4660 * | | |0 = I2C interrupt Disabled.
<> 149:156823d33999 4661 * | | |1 = I2C interrupt Enabled.
<> 149:156823d33999 4662 * @var I2C_T::ADDR0
<> 149:156823d33999 4663 * Offset: 0x04 I2C Slave Address Register0
<> 149:156823d33999 4664 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4665 * |Bits |Field |Descriptions
<> 149:156823d33999 4666 * | :----: | :----: | :---- |
<> 149:156823d33999 4667 * |[0] |GC |General Call Function
<> 149:156823d33999 4668 * | | |0 = General Call Function Disabled.
<> 149:156823d33999 4669 * | | |1 = General Call Function Enabled.
<> 149:156823d33999 4670 * |[7:1] |ADDR |I2C Address
<> 149:156823d33999 4671 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 149:156823d33999 4672 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 149:156823d33999 4673 * | | |The I2C hardware will react if either of the address is matched.
<> 149:156823d33999 4674 * @var I2C_T::DAT
<> 149:156823d33999 4675 * Offset: 0x08 I2C Data Register
<> 149:156823d33999 4676 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4677 * |Bits |Field |Descriptions
<> 149:156823d33999 4678 * | :----: | :----: | :---- |
<> 149:156823d33999 4679 * |[7:0] |DAT |I2C Data
<> 149:156823d33999 4680 * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
<> 149:156823d33999 4681 * @var I2C_T::STATUS
<> 149:156823d33999 4682 * Offset: 0x0C I2C Status Register
<> 149:156823d33999 4683 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4684 * |Bits |Field |Descriptions
<> 149:156823d33999 4685 * | :----: | :----: | :---- |
<> 149:156823d33999 4686 * |[7:0] |STATUS |I2C Status
<> 149:156823d33999 4687 * | | |The three least significant bits are always 0.
<> 149:156823d33999 4688 * | | |The five most significant bits contain the status code.
<> 149:156823d33999 4689 * | | |There are 28 possible status codes.
<> 149:156823d33999 4690 * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
<> 149:156823d33999 4691 * | | |Others I2C_STATUS values correspond to defined I2C states.
<> 149:156823d33999 4692 * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
<> 149:156823d33999 4693 * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
<> 149:156823d33999 4694 * | | |In addition, states 00H stands for a Bus Error.
<> 149:156823d33999 4695 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
<> 149:156823d33999 4696 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
<> 149:156823d33999 4697 * | | |Note:
<> 149:156823d33999 4698 * | | |1.
<> 149:156823d33999 4699 * | | |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
<> 149:156823d33999 4700 * | | |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
<> 149:156823d33999 4701 * | | |2.
<> 149:156823d33999 4702 * | | |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
<> 149:156823d33999 4703 * @var I2C_T::CLKDIV
<> 149:156823d33999 4704 * Offset: 0x10 I2C Clock Divided Register
<> 149:156823d33999 4705 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4706 * |Bits |Field |Descriptions
<> 149:156823d33999 4707 * | :----: | :----: | :---- |
<> 149:156823d33999 4708 * |[7:0] |DIVIDER |I2C Clock Divided
<> 149:156823d33999 4709 * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
<> 149:156823d33999 4710 * | | |Note: The minimum value of I2C_CLKDIV is 4.
<> 149:156823d33999 4711 * @var I2C_T::TOCTL
<> 149:156823d33999 4712 * Offset: 0x14 I2C Time-out Control Register
<> 149:156823d33999 4713 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4714 * |Bits |Field |Descriptions
<> 149:156823d33999 4715 * | :----: | :----: | :---- |
<> 149:156823d33999 4716 * |[0] |TOIF |Time-Out Flag
<> 149:156823d33999 4717 * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
<> 149:156823d33999 4718 * | | |Note: Software can write 1 to clear this bit.
<> 149:156823d33999 4719 * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
<> 149:156823d33999 4720 * | | |When Enabled, The time-out period is extend 4 times.
<> 149:156823d33999 4721 * | | |0 = Disabled.
<> 149:156823d33999 4722 * | | |1 = Enabled.
<> 149:156823d33999 4723 * |[2] |TOCEN |Time-Out Counter Enable Bit
<> 149:156823d33999 4724 * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
<> 149:156823d33999 4725 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
<> 149:156823d33999 4726 * | | |0 = Disabled.
<> 149:156823d33999 4727 * | | |1 = Enabled.
<> 149:156823d33999 4728 * @var I2C_T::ADDR1
<> 149:156823d33999 4729 * Offset: 0x18 I2C Slave Address Register1
<> 149:156823d33999 4730 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4731 * |Bits |Field |Descriptions
<> 149:156823d33999 4732 * | :----: | :----: | :---- |
<> 149:156823d33999 4733 * |[0] |GC |General Call Function
<> 149:156823d33999 4734 * | | |0 = General Call Function Disabled.
<> 149:156823d33999 4735 * | | |1 = General Call Function Enabled.
<> 149:156823d33999 4736 * |[7:1] |ADDR |I2C Address
<> 149:156823d33999 4737 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 149:156823d33999 4738 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 149:156823d33999 4739 * | | |The I2C hardware will react if either of the address is matched.
<> 149:156823d33999 4740 * @var I2C_T::ADDR2
<> 149:156823d33999 4741 * Offset: 0x1C I2C Slave Address Register2
<> 149:156823d33999 4742 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4743 * |Bits |Field |Descriptions
<> 149:156823d33999 4744 * | :----: | :----: | :---- |
<> 149:156823d33999 4745 * |[0] |GC |General Call Function
<> 149:156823d33999 4746 * | | |0 = General Call Function Disabled.
<> 149:156823d33999 4747 * | | |1 = General Call Function Enabled.
<> 149:156823d33999 4748 * |[7:1] |ADDR |I2C Address
<> 149:156823d33999 4749 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 149:156823d33999 4750 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 149:156823d33999 4751 * | | |The I2C hardware will react if either of the address is matched.
<> 149:156823d33999 4752 * @var I2C_T::ADDR3
<> 149:156823d33999 4753 * Offset: 0x20 I2C Slave Address Register3
<> 149:156823d33999 4754 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4755 * |Bits |Field |Descriptions
<> 149:156823d33999 4756 * | :----: | :----: | :---- |
<> 149:156823d33999 4757 * |[0] |GC |General Call Function
<> 149:156823d33999 4758 * | | |0 = General Call Function Disabled.
<> 149:156823d33999 4759 * | | |1 = General Call Function Enabled.
<> 149:156823d33999 4760 * |[7:1] |ADDR |I2C Address
<> 149:156823d33999 4761 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 149:156823d33999 4762 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 149:156823d33999 4763 * | | |The I2C hardware will react if either of the address is matched.
<> 149:156823d33999 4764 * @var I2C_T::ADDRMSK0
<> 149:156823d33999 4765 * Offset: 0x24 I2C Slave Address Mask Register0
<> 149:156823d33999 4766 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4767 * |Bits |Field |Descriptions
<> 149:156823d33999 4768 * | :----: | :----: | :---- |
<> 149:156823d33999 4769 * |[7:1] |ADDRMSK |I2C Address Mask
<> 149:156823d33999 4770 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 149:156823d33999 4771 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 149:156823d33999 4772 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 149:156823d33999 4773 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 149:156823d33999 4774 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 149:156823d33999 4775 * @var I2C_T::ADDRMSK1
<> 149:156823d33999 4776 * Offset: 0x28 I2C Slave Address Mask Register1
<> 149:156823d33999 4777 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4778 * |Bits |Field |Descriptions
<> 149:156823d33999 4779 * | :----: | :----: | :---- |
<> 149:156823d33999 4780 * |[7:1] |ADDRMSK |I2C Address Mask
<> 149:156823d33999 4781 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 149:156823d33999 4782 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 149:156823d33999 4783 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 149:156823d33999 4784 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 149:156823d33999 4785 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 149:156823d33999 4786 * @var I2C_T::ADDRMSK2
<> 149:156823d33999 4787 * Offset: 0x2C I2C Slave Address Mask Register2
<> 149:156823d33999 4788 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4789 * |Bits |Field |Descriptions
<> 149:156823d33999 4790 * | :----: | :----: | :---- |
<> 149:156823d33999 4791 * |[7:1] |ADDRMSK |I2C Address Mask
<> 149:156823d33999 4792 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 149:156823d33999 4793 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 149:156823d33999 4794 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 149:156823d33999 4795 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 149:156823d33999 4796 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 149:156823d33999 4797 * @var I2C_T::ADDRMSK3
<> 149:156823d33999 4798 * Offset: 0x30 I2C Slave Address Mask Register3
<> 149:156823d33999 4799 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4800 * |Bits |Field |Descriptions
<> 149:156823d33999 4801 * | :----: | :----: | :---- |
<> 149:156823d33999 4802 * |[7:1] |ADDRMSK |I2C Address Mask
<> 149:156823d33999 4803 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 149:156823d33999 4804 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 149:156823d33999 4805 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 149:156823d33999 4806 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 149:156823d33999 4807 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 149:156823d33999 4808 * @var I2C_T::WKCTL
<> 149:156823d33999 4809 * Offset: 0x3C I2C Wake-up Control Register
<> 149:156823d33999 4810 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4811 * |Bits |Field |Descriptions
<> 149:156823d33999 4812 * | :----: | :----: | :---- |
<> 149:156823d33999 4813 * |[0] |WKEN |I2C Wake-Up Enable Bit
<> 149:156823d33999 4814 * | | |0 = I2C wake-up function Disabled.
<> 149:156823d33999 4815 * | | |1= I2C wake-up function Enabled.
<> 149:156823d33999 4816 * @var I2C_T::WKSTS
<> 149:156823d33999 4817 * Offset: 0x40 I2C Wake-up Status Register
<> 149:156823d33999 4818 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4819 * |Bits |Field |Descriptions
<> 149:156823d33999 4820 * | :----: | :----: | :---- |
<> 149:156823d33999 4821 * |[0] |WKIF |I2C Wake-Up Flag
<> 149:156823d33999 4822 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
<> 149:156823d33999 4823 * | | |Software can write 1 to clear this bit.
<> 149:156823d33999 4824 * @var I2C_T::BUSCTL
<> 149:156823d33999 4825 * Offset: 0x44 I2C Bus Management Control Register
<> 149:156823d33999 4826 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4827 * |Bits |Field |Descriptions
<> 149:156823d33999 4828 * | :----: | :----: | :---- |
<> 149:156823d33999 4829 * |[0] |ACKMEN |Acknowledge Control By Manual
<> 149:156823d33999 4830 * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
<> 149:156823d33999 4831 * | | |0 = Slave byte control Disabled.
<> 149:156823d33999 4832 * | | |1 = Slave byte control Enabled.
<> 149:156823d33999 4833 * | | |The 9th bit can response the ACK or NACK according the received data by user.
<> 149:156823d33999 4834 * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
<> 149:156823d33999 4835 * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
<> 149:156823d33999 4836 * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
<> 149:156823d33999 4837 * | | |0 = Packet Error Checking Calculation Disabled.
<> 149:156823d33999 4838 * | | |1 = Packet Error Checking Calculation Enabled.
<> 149:156823d33999 4839 * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
<> 149:156823d33999 4840 * | | |0 = Device default address Disable.
<> 149:156823d33999 4841 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
<> 149:156823d33999 4842 * | | |1 = Device default address Enabled.
<> 149:156823d33999 4843 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
<> 149:156823d33999 4844 * |[3] |BMHEN |Bus Management Host Enable Bit
<> 149:156823d33999 4845 * | | |0 = Host function Disabled.
<> 149:156823d33999 4846 * | | |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
<> 149:156823d33999 4847 * |[4] |ALERTEN |Bus Management Alert Enable Bit
<> 149:156823d33999 4848 * | | |Device Mode (BMHEN =0).
<> 149:156823d33999 4849 * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
<> 149:156823d33999 4850 * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
<> 149:156823d33999 4851 * | | |Host Mode (BMHEN =1).
<> 149:156823d33999 4852 * | | |0 = BM_ALERT pin not supported.
<> 149:156823d33999 4853 * | | |1 = BM_ALERT pin supported.
<> 149:156823d33999 4854 * |[5] |SCTLOSTS |Suspend/Control Data Output Status
<> 149:156823d33999 4855 * | | |0 = The output of SUSCON pin is low.
<> 149:156823d33999 4856 * | | |1 = The output of SUSCON pin is high.
<> 149:156823d33999 4857 * |[6] |SCTLOEN |Suspend Or Control Pin Output Enable Bit
<> 149:156823d33999 4858 * | | |0 = The SUSCON pin in input.
<> 149:156823d33999 4859 * | | |1 = The output enable is active on the SUSCON pin.
<> 149:156823d33999 4860 * |[7] |BUSEN |BUS Enable Bit
<> 149:156823d33999 4861 * | | |0 = The system management function is Disabled.
<> 149:156823d33999 4862 * | | |1 = The system management function is Enable.
<> 149:156823d33999 4863 * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
<> 149:156823d33999 4864 * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
<> 149:156823d33999 4865 * | | |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
<> 149:156823d33999 4866 * | | |0 = No PEC transfer.
<> 149:156823d33999 4867 * | | |1 = PEC transmission/reception is requested.
<> 149:156823d33999 4868 * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
<> 149:156823d33999 4869 * |[9] |TIDLE |Timer Check In Idle State
<> 149:156823d33999 4870 * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
<> 149:156823d33999 4871 * | | |This bit is used to define which condition is enabled.
<> 149:156823d33999 4872 * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
<> 149:156823d33999 4873 * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
<> 149:156823d33999 4874 * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
<> 149:156823d33999 4875 * |[10] |PECCLR |PEC Clear At Repeat Start
<> 149:156823d33999 4876 * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
<> 149:156823d33999 4877 * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
<> 149:156823d33999 4878 * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
<> 149:156823d33999 4879 * | | |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
<> 149:156823d33999 4880 * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
<> 149:156823d33999 4881 * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
<> 149:156823d33999 4882 * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
<> 149:156823d33999 4883 * @var I2C_T::BUSTCTL
<> 149:156823d33999 4884 * Offset: 0x48 I2C Bus Management Timer Control Register
<> 149:156823d33999 4885 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4886 * |Bits |Field |Descriptions
<> 149:156823d33999 4887 * | :----: | :----: | :---- |
<> 149:156823d33999 4888 * |[0] |BUSTOEN |Bus Time Out Enable Bit
<> 149:156823d33999 4889 * | | |0 = Indicates the bus clock low time-out detection is Disabled.
<> 149:156823d33999 4890 * | | |1 = Indicates the bus clock low time-out detection is Enabled
<> 149:156823d33999 4891 * | | |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
<> 149:156823d33999 4892 * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
<> 149:156823d33999 4893 * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
<> 149:156823d33999 4894 * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
<> 149:156823d33999 4895 * | | |For Master, it calculates the period from START to ACK
<> 149:156823d33999 4896 * | | |For Slave, it calculates the period from START to STOP
<> 149:156823d33999 4897 * |[2] |BUSTOIEN |Time-Out Interrupt Enable Bit
<> 149:156823d33999 4898 * | | |BUSY =1.
<> 149:156823d33999 4899 * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
<> 149:156823d33999 4900 * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
<> 149:156823d33999 4901 * | | |BUSY =0.
<> 149:156823d33999 4902 * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
<> 149:156823d33999 4903 * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
<> 149:156823d33999 4904 * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
<> 149:156823d33999 4905 * | | |0 = Indicates the time extended interrupt is Disabled.
<> 149:156823d33999 4906 * | | |1 = Indicates the time extended interrupt is Enabled.
<> 149:156823d33999 4907 * |[4] |TORSTEN |Time Out Reset Enable Bit
<> 149:156823d33999 4908 * | | |0 = Indicates the I2C state machine reset is Disable.
<> 149:156823d33999 4909 * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
<> 149:156823d33999 4910 * |[5] |PECIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
<> 149:156823d33999 4911 * | | |0 = Indicates the byte count done interrupt is Disabled.
<> 149:156823d33999 4912 * | | |1 = Indicates the byte count done interrupt is Enabled.
<> 149:156823d33999 4913 * | | |Note: This bit is used in PECEN =1.
<> 149:156823d33999 4914 * @var I2C_T::BUSSTS
<> 149:156823d33999 4915 * Offset: 0x4C I2C Bus Management Status Register
<> 149:156823d33999 4916 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4917 * |Bits |Field |Descriptions
<> 149:156823d33999 4918 * | :----: | :----: | :---- |
<> 149:156823d33999 4919 * |[0] |BUSY |Bus Busy
<> 149:156823d33999 4920 * | | |Indicates that a communication is in progress on the bus.
<> 149:156823d33999 4921 * | | |It is set by hardware when a START condition is detected.
<> 149:156823d33999 4922 * | | |It is cleared by hardware when a STOP condition is detected.
<> 149:156823d33999 4923 * | | |0 = The bus is IDLE (both SCLK and SDA High).
<> 149:156823d33999 4924 * | | |1 = The bus is busy.
<> 149:156823d33999 4925 * |[1] |BCDONE |Byte Count Transmission/Receive Done
<> 149:156823d33999 4926 * | | |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
<> 149:156823d33999 4927 * | | |1 = Indicates the transmission/ receive is finished when the PECEN is set.
<> 149:156823d33999 4928 * | | |Note: Software can write 1 to clear this bit.
<> 149:156823d33999 4929 * |[2] |PECERR |PEC Error In Reception
<> 149:156823d33999 4930 * | | |0 = Indicates the PEC value equal the received PEC data packet.
<> 149:156823d33999 4931 * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
<> 149:156823d33999 4932 * | | |Note: Software can write 1 to clear this bit.
<> 149:156823d33999 4933 * |[3] |ALERT |SMBus Alert Status
<> 149:156823d33999 4934 * | | |Device Mode (BMHEN =0).
<> 149:156823d33999 4935 * | | |0 = Indicates SMALERT pin state is low.
<> 149:156823d33999 4936 * | | |1 = Indicates SMALERT pin state is high
<> 149:156823d33999 4937 * | | |Host Mode (BMHEN =1).
<> 149:156823d33999 4938 * | | |0 = No SMBALERT event.
<> 149:156823d33999 4939 * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
<> 149:156823d33999 4940 * | | |Note: 1.
<> 149:156823d33999 4941 * | | |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
<> 149:156823d33999 4942 * | | |2.
<> 149:156823d33999 4943 * | | |Software can write 1 to clear this bit.
<> 149:156823d33999 4944 * |[4] |SCTLDIN |Bus Suspend Or Control Signal Input Status
<> 149:156823d33999 4945 * | | |0 = The input status of SUSCON pin is 0.
<> 149:156823d33999 4946 * | | |1 = The input status of SUSCON pin is 1.
<> 149:156823d33999 4947 * |[5] |BUSTO |Bus Time-out Status
<> 149:156823d33999 4948 * | | |0 = Indicates that there is no any time-out or external clock time-out.
<> 149:156823d33999 4949 * | | |1 = Indicates that a time-out or external clock time-out occurred.
<> 149:156823d33999 4950 * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
<> 149:156823d33999 4951 * | | |Note: Software can write 1 to clear this bit.
<> 149:156823d33999 4952 * |[6] |CLKTO |Clock Low Cumulate Time-out Status
<> 149:156823d33999 4953 * | | |0 = Indicates that the cumulative clock low is no any time-out.
<> 149:156823d33999 4954 * | | |1 = Indicates that the cumulative clock low time-out occurred.
<> 149:156823d33999 4955 * | | |Note: Software can write 1 to clear this bit.
<> 149:156823d33999 4956 * @var I2C_T::PKTSIZE
<> 149:156823d33999 4957 * Offset: 0x50 I2C Packet Error Checking Byte Number Register
<> 149:156823d33999 4958 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4959 * |Bits |Field |Descriptions
<> 149:156823d33999 4960 * | :----: | :----: | :---- |
<> 149:156823d33999 4961 * |[7:0] |PLDSIZE |Transfer Byte Number
<> 149:156823d33999 4962 * | | |The transmission or receive byte number in one transaction when the PECEN is set.
<> 149:156823d33999 4963 * | | |The maximum transaction or receive byte is 255 Bytes.
<> 149:156823d33999 4964 * @var I2C_T::PKTCRC
<> 149:156823d33999 4965 * Offset: 0x54 I2C Packet Error Checking Byte Value Register
<> 149:156823d33999 4966 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4967 * |Bits |Field |Descriptions
<> 149:156823d33999 4968 * | :----: | :----: | :---- |
<> 149:156823d33999 4969 * |[7:0] |PECCRC |Packet Error Checking Byte Value
<> 149:156823d33999 4970 * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
<> 149:156823d33999 4971 * | | |I t is read only.
<> 149:156823d33999 4972 * @var I2C_T::BUSTOUT
<> 149:156823d33999 4973 * Offset: 0x58 I2C Bus Management Timer Register
<> 149:156823d33999 4974 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4975 * |Bits |Field |Descriptions
<> 149:156823d33999 4976 * | :----: | :----: | :---- |
<> 149:156823d33999 4977 * |[7:0] |BUSTO |Bus Management Time-out Value
<> 149:156823d33999 4978 * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
<> 149:156823d33999 4979 * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
<> 149:156823d33999 4980 * @var I2C_T::CLKTOUT
<> 149:156823d33999 4981 * Offset: 0x5C I2C Bus Management Clock Low Timer Register
<> 149:156823d33999 4982 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 4983 * |Bits |Field |Descriptions
<> 149:156823d33999 4984 * | :----: | :----: | :---- |
<> 149:156823d33999 4985 * |[7:0] |CLKTO |Bus Clock Low Timer
<> 149:156823d33999 4986 * | | |The field is used to configure the cumulative clock extension time-out.
<> 149:156823d33999 4987 * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
<> 149:156823d33999 4988 */
<> 149:156823d33999 4989
<> 149:156823d33999 4990 __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
<> 149:156823d33999 4991 __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
<> 149:156823d33999 4992 __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
<> 149:156823d33999 4993 __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
<> 149:156823d33999 4994 __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
<> 149:156823d33999 4995 __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
<> 149:156823d33999 4996 __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
<> 149:156823d33999 4997 __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
<> 149:156823d33999 4998 __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
<> 149:156823d33999 4999 __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
<> 149:156823d33999 5000 __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
<> 149:156823d33999 5001 __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
<> 149:156823d33999 5002 __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
<> 149:156823d33999 5003 __I uint32_t RESERVE0[2];
<> 149:156823d33999 5004 __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
<> 149:156823d33999 5005 __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
<> 149:156823d33999 5006 __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
<> 149:156823d33999 5007 __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
<> 149:156823d33999 5008 __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
<> 149:156823d33999 5009 __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
<> 149:156823d33999 5010 __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
<> 149:156823d33999 5011 __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
<> 149:156823d33999 5012 __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
<> 149:156823d33999 5013
<> 149:156823d33999 5014 } I2C_T;
<> 149:156823d33999 5015
<> 149:156823d33999 5016
<> 149:156823d33999 5017
<> 149:156823d33999 5018 /**
<> 149:156823d33999 5019 @addtogroup I2C_CONST I2C Bit Field Definition
<> 149:156823d33999 5020 Constant Definitions for I2C Controller
<> 149:156823d33999 5021 @{ */
<> 149:156823d33999 5022
<> 149:156823d33999 5023 #define I2C_CTL_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
<> 149:156823d33999 5024 #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C_T::CTL: AA Mask */
<> 149:156823d33999 5025
<> 149:156823d33999 5026 #define I2C_CTL_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
<> 149:156823d33999 5027 #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C_T::CTL: SI Mask */
<> 149:156823d33999 5028
<> 149:156823d33999 5029 #define I2C_CTL_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
<> 149:156823d33999 5030 #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C_T::CTL: STO Mask */
<> 149:156823d33999 5031
<> 149:156823d33999 5032 #define I2C_CTL_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
<> 149:156823d33999 5033 #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C_T::CTL: STA Mask */
<> 149:156823d33999 5034
<> 149:156823d33999 5035 #define I2C_CTL_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
<> 149:156823d33999 5036 #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
<> 149:156823d33999 5037
<> 149:156823d33999 5038 #define I2C_CTL_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
<> 149:156823d33999 5039 #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
<> 149:156823d33999 5040
<> 149:156823d33999 5041 #define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
<> 149:156823d33999 5042 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
<> 149:156823d33999 5043
<> 149:156823d33999 5044 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
<> 149:156823d33999 5045 #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
<> 149:156823d33999 5046
<> 149:156823d33999 5047 #define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
<> 149:156823d33999 5048 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
<> 149:156823d33999 5049
<> 149:156823d33999 5050 #define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
<> 149:156823d33999 5051 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
<> 149:156823d33999 5052
<> 149:156823d33999 5053 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
<> 149:156823d33999 5054 #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
<> 149:156823d33999 5055
<> 149:156823d33999 5056 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
<> 149:156823d33999 5057 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
<> 149:156823d33999 5058
<> 149:156823d33999 5059 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
<> 149:156823d33999 5060 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
<> 149:156823d33999 5061
<> 149:156823d33999 5062 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
<> 149:156823d33999 5063 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
<> 149:156823d33999 5064
<> 149:156823d33999 5065 #define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
<> 149:156823d33999 5066 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
<> 149:156823d33999 5067
<> 149:156823d33999 5068 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
<> 149:156823d33999 5069 #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
<> 149:156823d33999 5070
<> 149:156823d33999 5071 #define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
<> 149:156823d33999 5072 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
<> 149:156823d33999 5073
<> 149:156823d33999 5074 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
<> 149:156823d33999 5075 #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
<> 149:156823d33999 5076
<> 149:156823d33999 5077 #define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
<> 149:156823d33999 5078 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
<> 149:156823d33999 5079
<> 149:156823d33999 5080 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
<> 149:156823d33999 5081 #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
<> 149:156823d33999 5082
<> 149:156823d33999 5083 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
<> 149:156823d33999 5084 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
<> 149:156823d33999 5085
<> 149:156823d33999 5086 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
<> 149:156823d33999 5087 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
<> 149:156823d33999 5088
<> 149:156823d33999 5089 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
<> 149:156823d33999 5090 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
<> 149:156823d33999 5091
<> 149:156823d33999 5092 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
<> 149:156823d33999 5093 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
<> 149:156823d33999 5094
<> 149:156823d33999 5095 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
<> 149:156823d33999 5096 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
<> 149:156823d33999 5097
<> 149:156823d33999 5098 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
<> 149:156823d33999 5099 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
<> 149:156823d33999 5100
<> 149:156823d33999 5101 #define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
<> 149:156823d33999 5102 #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
<> 149:156823d33999 5103
<> 149:156823d33999 5104 #define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
<> 149:156823d33999 5105 #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
<> 149:156823d33999 5106
<> 149:156823d33999 5107 #define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
<> 149:156823d33999 5108 #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
<> 149:156823d33999 5109
<> 149:156823d33999 5110 #define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
<> 149:156823d33999 5111 #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
<> 149:156823d33999 5112
<> 149:156823d33999 5113 #define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
<> 149:156823d33999 5114 #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
<> 149:156823d33999 5115
<> 149:156823d33999 5116 #define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
<> 149:156823d33999 5117 #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
<> 149:156823d33999 5118
<> 149:156823d33999 5119 #define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
<> 149:156823d33999 5120 #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
<> 149:156823d33999 5121
<> 149:156823d33999 5122 #define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
<> 149:156823d33999 5123 #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
<> 149:156823d33999 5124
<> 149:156823d33999 5125 #define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
<> 149:156823d33999 5126 #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
<> 149:156823d33999 5127
<> 149:156823d33999 5128 #define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
<> 149:156823d33999 5129 #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
<> 149:156823d33999 5130
<> 149:156823d33999 5131 #define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
<> 149:156823d33999 5132 #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
<> 149:156823d33999 5133
<> 149:156823d33999 5134 #define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
<> 149:156823d33999 5135 #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
<> 149:156823d33999 5136
<> 149:156823d33999 5137 #define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
<> 149:156823d33999 5138 #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
<> 149:156823d33999 5139
<> 149:156823d33999 5140 #define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
<> 149:156823d33999 5141 #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
<> 149:156823d33999 5142
<> 149:156823d33999 5143 #define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
<> 149:156823d33999 5144 #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
<> 149:156823d33999 5145
<> 149:156823d33999 5146 #define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
<> 149:156823d33999 5147 #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
<> 149:156823d33999 5148
<> 149:156823d33999 5149 #define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
<> 149:156823d33999 5150 #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
<> 149:156823d33999 5151
<> 149:156823d33999 5152 #define I2C_BUSTCTL_PECIEN_Pos (5) /*!< I2C_T::BUSTCTL: PECIEN Position */
<> 149:156823d33999 5153 #define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) /*!< I2C_T::BUSTCTL: PECIEN Mask */
<> 149:156823d33999 5154
<> 149:156823d33999 5155 #define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
<> 149:156823d33999 5156 #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
<> 149:156823d33999 5157
<> 149:156823d33999 5158 #define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
<> 149:156823d33999 5159 #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
<> 149:156823d33999 5160
<> 149:156823d33999 5161 #define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
<> 149:156823d33999 5162 #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
<> 149:156823d33999 5163
<> 149:156823d33999 5164 #define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
<> 149:156823d33999 5165 #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
<> 149:156823d33999 5166
<> 149:156823d33999 5167 #define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
<> 149:156823d33999 5168 #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
<> 149:156823d33999 5169
<> 149:156823d33999 5170 #define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
<> 149:156823d33999 5171 #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
<> 149:156823d33999 5172
<> 149:156823d33999 5173 #define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
<> 149:156823d33999 5174 #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
<> 149:156823d33999 5175
<> 149:156823d33999 5176 #define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
<> 149:156823d33999 5177 #define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
<> 149:156823d33999 5178
<> 149:156823d33999 5179 #define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
<> 149:156823d33999 5180 #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
<> 149:156823d33999 5181
<> 149:156823d33999 5182 #define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
<> 149:156823d33999 5183 #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
<> 149:156823d33999 5184
<> 149:156823d33999 5185 #define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
<> 149:156823d33999 5186 #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
<> 149:156823d33999 5187
<> 149:156823d33999 5188
<> 149:156823d33999 5189 /**@}*/ /* I2C_CONST */
<> 149:156823d33999 5190 /**@}*/ /* end of I2C register group */
<> 149:156823d33999 5191
<> 149:156823d33999 5192 /*---------------------- USB On-The-Go Controller -------------------------*/
<> 149:156823d33999 5193 /**
<> 149:156823d33999 5194 @addtogroup OTG USB On-The-Go Controller(OTG)
<> 149:156823d33999 5195 Memory Mapped Structure for OTG Controller
<> 149:156823d33999 5196 @{ */
<> 149:156823d33999 5197
<> 149:156823d33999 5198
<> 149:156823d33999 5199 typedef struct
<> 149:156823d33999 5200 {
<> 149:156823d33999 5201
<> 149:156823d33999 5202
<> 149:156823d33999 5203 /**
<> 149:156823d33999 5204 * @var OTG_T::CTL
<> 149:156823d33999 5205 * Offset: 0x00 OTG Control Register
<> 149:156823d33999 5206 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5207 * |Bits |Field |Descriptions
<> 149:156823d33999 5208 * | :----: | :----: | :---- |
<> 149:156823d33999 5209 * |[0] |VBUSDROP |Drop VBUS Control
<> 149:156823d33999 5210 * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
<> 149:156823d33999 5211 * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
<> 149:156823d33999 5212 * | | |0 = Not drop the VBUS.
<> 149:156823d33999 5213 * | | |1 = Drop the VBUS.
<> 149:156823d33999 5214 * |[1] |BUSREQ |OTG Bus Request
<> 149:156823d33999 5215 * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
<> 149:156823d33999 5216 * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
<> 149:156823d33999 5217 * | | |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
<> 149:156823d33999 5218 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
<> 149:156823d33999 5219 * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
<> 149:156823d33999 5220 * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
<> 149:156823d33999 5221 * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
<> 149:156823d33999 5222 * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
<> 149:156823d33999 5223 * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
<> 149:156823d33999 5224 * |[2] |HNPREQEN |OTG HNP Request Enable Bit
<> 149:156823d33999 5225 * | | |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
<> 149:156823d33999 5226 * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
<> 149:156823d33999 5227 * | | |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
<> 149:156823d33999 5228 * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
<> 149:156823d33999 5229 * | | |0 = HNP request Disabled.
<> 149:156823d33999 5230 * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
<> 149:156823d33999 5231 * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
<> 149:156823d33999 5232 * |[4] |OTGEN |OTG Function Enable Bit
<> 149:156823d33999 5233 * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
<> 149:156823d33999 5234 * | | |When USB frame not configured as OTG device, this bit is must be low.
<> 149:156823d33999 5235 * | | |0 = OTG function Disabled.
<> 149:156823d33999 5236 * | | |1 = OTG function Enabled.
<> 149:156823d33999 5237 * |[5] |WKEN |OTG ID Pin Wake-Up Enable Bit
<> 149:156823d33999 5238 * | | |0 = OTG ID pin status change wake-up function Disabled.
<> 149:156823d33999 5239 * | | |1 = OTG ID pin status change wake-up function Enabled.
<> 149:156823d33999 5240 * @var OTG_T::PHYCTL
<> 149:156823d33999 5241 * Offset: 0x04 OTG PHY Control Register
<> 149:156823d33999 5242 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5243 * |Bits |Field |Descriptions
<> 149:156823d33999 5244 * | :----: | :----: | :---- |
<> 149:156823d33999 5245 * |[0] |OTGPHYEN |OTG PHY Enable
<> 149:156823d33999 5246 * | | |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
<> 149:156823d33999 5247 * | | |If device is not configured as OTG-device, this bit is "don't care".
<> 149:156823d33999 5248 * | | |0 = OTG PHY Disabled.
<> 149:156823d33999 5249 * | | |1 = OTG PHY Enabled.
<> 149:156823d33999 5250 * |[1] |IDDETEN |ID Detection Enable Bit
<> 149:156823d33999 5251 * | | |0 = Detect ID pin status Disabled.
<> 149:156823d33999 5252 * | | |1 = Detect ID pin status Enabled.
<> 149:156823d33999 5253 * |[4] |VBENPOL |Off-Chip USB VBUS Power Switch Enable Polarity
<> 149:156823d33999 5254 * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
<> 149:156823d33999 5255 * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
<> 149:156823d33999 5256 * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
<> 149:156823d33999 5257 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
<> 149:156823d33999 5258 * | | |0 = The off-chip USB VBUS power switch enable is active high.
<> 149:156823d33999 5259 * | | |1 = The off-chip USB VBUS power switch enable is active low.
<> 149:156823d33999 5260 * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Switch Status Polarity
<> 149:156823d33999 5261 * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
<> 149:156823d33999 5262 * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
<> 149:156823d33999 5263 * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
<> 149:156823d33999 5264 * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
<> 149:156823d33999 5265 * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
<> 149:156823d33999 5266 * @var OTG_T::INTEN
<> 149:156823d33999 5267 * Offset: 0x08 OTG Interrupt Enable Register
<> 149:156823d33999 5268 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5269 * |Bits |Field |Descriptions
<> 149:156823d33999 5270 * | :----: | :----: | :---- |
<> 149:156823d33999 5271 * |[0] |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
<> 149:156823d33999 5272 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5273 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5274 * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
<> 149:156823d33999 5275 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5276 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5277 * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
<> 149:156823d33999 5278 * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
<> 149:156823d33999 5279 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5280 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5281 * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
<> 149:156823d33999 5282 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5283 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5284 * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
<> 149:156823d33999 5285 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5286 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5287 * | | |Note: Going to idle state means going to a_idle or b_idle state.
<> 149:156823d33999 5288 * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
<> 149:156823d33999 5289 * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
<> 149:156823d33999 5290 * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
<> 149:156823d33999 5291 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5292 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5293 * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
<> 149:156823d33999 5294 * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
<> 149:156823d33999 5295 * | | |0 = This device as a peripheral interrupt Disabled.
<> 149:156823d33999 5296 * | | |1 = This device as a peripheral interrupt Enabled.
<> 149:156823d33999 5297 * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
<> 149:156823d33999 5298 * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
<> 149:156823d33999 5299 * | | |0 = This device as a host interrupt Disabled.
<> 149:156823d33999 5300 * | | |1 = This device as a host interrupt Enabled.
<> 149:156823d33999 5301 * |[8] |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
<> 149:156823d33999 5302 * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
<> 149:156823d33999 5303 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5304 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5305 * |[9] |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
<> 149:156823d33999 5306 * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
<> 149:156823d33999 5307 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5308 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5309 * |[10] |VBCHGIEN |VBUSVLD Status Changed
<> 149:156823d33999 5310 * | | |Interrupt Enable Bit
<> 149:156823d33999 5311 * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
<> 149:156823d33999 5312 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5313 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5314 * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
<> 149:156823d33999 5315 * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
<> 149:156823d33999 5316 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5317 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5318 * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
<> 149:156823d33999 5319 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 5320 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 5321 * @var OTG_T::INTSTS
<> 149:156823d33999 5322 * Offset: 0x0C OTG Interrupt Status Register
<> 149:156823d33999 5323 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5324 * |Bits |Field |Descriptions
<> 149:156823d33999 5325 * | :----: | :----: | :---- |
<> 149:156823d33999 5326 * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
<> 149:156823d33999 5327 * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
<> 149:156823d33999 5328 * | | |0 = OTG device role not changed.
<> 149:156823d33999 5329 * | | |1 = OTG device role changed.
<> 149:156823d33999 5330 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5331 * |[1] |VBEIF |VBUS Error Interrupt Status
<> 149:156823d33999 5332 * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
<> 149:156823d33999 5333 * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
<> 149:156823d33999 5334 * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
<> 149:156823d33999 5335 * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
<> 149:156823d33999 5336 * |[2] |SRPFIF |SRP Fail Interrupt Status
<> 149:156823d33999 5337 * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
<> 149:156823d33999 5338 * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
<> 149:156823d33999 5339 * | | |0 = OTG B-device gets VBUS high before this interval.
<> 149:156823d33999 5340 * | | |1 = OTG B-device does not get VBUS high before this interval.
<> 149:156823d33999 5341 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5342 * |[3] |HNPFIF |HNP Fail Interrupt Status
<> 149:156823d33999 5343 * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
<> 149:156823d33999 5344 * | | |0 = A-device connects to B-device before specified interval expires.
<> 149:156823d33999 5345 * | | |1 = A-device does not connect to B-device before specified interval expires.
<> 149:156823d33999 5346 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5347 * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
<> 149:156823d33999 5348 * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
<> 149:156823d33999 5349 * | | |The OTG device will be neither a host nor a peripheral.
<> 149:156823d33999 5350 * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
<> 149:156823d33999 5351 * | | |1 = OTG device goes back to idle state (a_idle or b_idle).
<> 149:156823d33999 5352 * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
<> 149:156823d33999 5353 * | | |Note 2: Write 1 to clear this flag.
<> 149:156823d33999 5354 * |[5] |IDCHGIF |ID State Change Interrupt Status
<> 149:156823d33999 5355 * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
<> 149:156823d33999 5356 * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
<> 149:156823d33999 5357 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5358 * |[6] |PDEVIF |Act As Peripheral Interrupt Status
<> 149:156823d33999 5359 * | | |0 = This device does not act as a peripheral.
<> 149:156823d33999 5360 * | | |1 = This device acts as a peripheral.
<> 149:156823d33999 5361 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5362 * |[7] |HOSTIF |Act As Host Interrupt Status
<> 149:156823d33999 5363 * | | |0 = This device does not act as a host.
<> 149:156823d33999 5364 * | | |1 = This device acts as a host.
<> 149:156823d33999 5365 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5366 * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
<> 149:156823d33999 5367 * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
<> 149:156823d33999 5368 * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
<> 149:156823d33999 5369 * | | |Note: Write 1 to clear this status.
<> 149:156823d33999 5370 * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
<> 149:156823d33999 5371 * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
<> 149:156823d33999 5372 * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
<> 149:156823d33999 5373 * | | |Note: Write 1 to clear this status.
<> 149:156823d33999 5374 * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
<> 149:156823d33999 5375 * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
<> 149:156823d33999 5376 * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
<> 149:156823d33999 5377 * | | |Note: Write 1 to clear this status.
<> 149:156823d33999 5378 * |[11] |SECHGIF |SESSEND State Change Interrupt Status
<> 149:156823d33999 5379 * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
<> 149:156823d33999 5380 * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
<> 149:156823d33999 5381 * | | |Note: Write 1 to clear this flag.
<> 149:156823d33999 5382 * |[13] |SRPDETIF |SRP Detected Interrupt Status
<> 149:156823d33999 5383 * | | |0 = SRP not detected.
<> 149:156823d33999 5384 * | | |1 = SRP detected.
<> 149:156823d33999 5385 * | | |Note: Write 1 to clear this status.
<> 149:156823d33999 5386 * @var OTG_T::STATUS
<> 149:156823d33999 5387 * Offset: 0x10 OTG Status Register
<> 149:156823d33999 5388 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5389 * |Bits |Field |Descriptions
<> 149:156823d33999 5390 * | :----: | :----: | :---- |
<> 149:156823d33999 5391 * |[0] |OVERCUR |Over Current Condition
<> 149:156823d33999 5392 * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
<> 149:156823d33999 5393 * | | |0 = OTG A-device drives VBUS successfully.
<> 149:156823d33999 5394 * | | |1 = OTG A-device cannot drives VBUS high in this interval.
<> 149:156823d33999 5395 * |[1] |IDSTS |USB_ID Pin State Of Mini-B/Micro-Plug
<> 149:156823d33999 5396 * | | |0 = Mini-A/Micro-A plug is attached.
<> 149:156823d33999 5397 * | | |1 = Mini-B/Micro-B plug is attached.
<> 149:156823d33999 5398 * |[2] |SESSEND |Session End Status
<> 149:156823d33999 5399 * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
<> 149:156823d33999 5400 * | | |Session end means no meaningful power on VBUS.
<> 149:156823d33999 5401 * | | |0 = Session is not end.
<> 149:156823d33999 5402 * | | |1 = Session is end.
<> 149:156823d33999 5403 * |[3] |BVLD |B-Device Session Valid Status
<> 149:156823d33999 5404 * | | |0 = B-device session is not valid.
<> 149:156823d33999 5405 * | | |1 = B-device session is valid.
<> 149:156823d33999 5406 * |[4] |AVLD |A-Device Session Valid Status
<> 149:156823d33999 5407 * | | |0 = A-device session is not valid.
<> 149:156823d33999 5408 * | | |1 = A-device session is valid.
<> 149:156823d33999 5409 * |[5] |VBUSVLD |VBUS Valid Status
<> 149:156823d33999 5410 * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
<> 149:156823d33999 5411 * | | |0 = VBUS is not valid.
<> 149:156823d33999 5412 * | | |1 = VBUS is valid.
<> 149:156823d33999 5413 */
<> 149:156823d33999 5414
<> 149:156823d33999 5415 __IO uint32_t CTL; /* Offset: 0x00 OTG Control Register */
<> 149:156823d33999 5416 __IO uint32_t PHYCTL; /* Offset: 0x04 OTG PHY Control Register */
<> 149:156823d33999 5417 __IO uint32_t INTEN; /* Offset: 0x08 OTG Interrupt Enable Register */
<> 149:156823d33999 5418 __IO uint32_t INTSTS; /* Offset: 0x0C OTG Interrupt Status Register */
<> 149:156823d33999 5419 __I uint32_t STATUS; /* Offset: 0x10 OTG Status Register */
<> 149:156823d33999 5420
<> 149:156823d33999 5421 } OTG_T;
<> 149:156823d33999 5422
<> 149:156823d33999 5423
<> 149:156823d33999 5424
<> 149:156823d33999 5425 /**
<> 149:156823d33999 5426 @addtogroup OTG_CONST OTG Bit Field Definition
<> 149:156823d33999 5427 Constant Definitions for OTG Controller
<> 149:156823d33999 5428 @{ */
<> 149:156823d33999 5429
<> 149:156823d33999 5430 #define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
<> 149:156823d33999 5431 #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
<> 149:156823d33999 5432
<> 149:156823d33999 5433 #define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
<> 149:156823d33999 5434 #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
<> 149:156823d33999 5435
<> 149:156823d33999 5436 #define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
<> 149:156823d33999 5437 #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
<> 149:156823d33999 5438
<> 149:156823d33999 5439 #define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
<> 149:156823d33999 5440 #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
<> 149:156823d33999 5441
<> 149:156823d33999 5442 #define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
<> 149:156823d33999 5443 #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
<> 149:156823d33999 5444
<> 149:156823d33999 5445 #define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
<> 149:156823d33999 5446 #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
<> 149:156823d33999 5447
<> 149:156823d33999 5448 #define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
<> 149:156823d33999 5449 #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
<> 149:156823d33999 5450
<> 149:156823d33999 5451 #define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
<> 149:156823d33999 5452 #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
<> 149:156823d33999 5453
<> 149:156823d33999 5454 #define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
<> 149:156823d33999 5455 #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
<> 149:156823d33999 5456
<> 149:156823d33999 5457 #define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
<> 149:156823d33999 5458 #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
<> 149:156823d33999 5459
<> 149:156823d33999 5460 #define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
<> 149:156823d33999 5461 #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
<> 149:156823d33999 5462
<> 149:156823d33999 5463 #define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
<> 149:156823d33999 5464 #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
<> 149:156823d33999 5465
<> 149:156823d33999 5466 #define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
<> 149:156823d33999 5467 #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
<> 149:156823d33999 5468
<> 149:156823d33999 5469 #define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
<> 149:156823d33999 5470 #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
<> 149:156823d33999 5471
<> 149:156823d33999 5472 #define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
<> 149:156823d33999 5473 #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
<> 149:156823d33999 5474
<> 149:156823d33999 5475 #define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
<> 149:156823d33999 5476 #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
<> 149:156823d33999 5477
<> 149:156823d33999 5478 #define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
<> 149:156823d33999 5479 #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
<> 149:156823d33999 5480
<> 149:156823d33999 5481 #define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
<> 149:156823d33999 5482 #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
<> 149:156823d33999 5483
<> 149:156823d33999 5484 #define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
<> 149:156823d33999 5485 #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
<> 149:156823d33999 5486
<> 149:156823d33999 5487 #define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
<> 149:156823d33999 5488 #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
<> 149:156823d33999 5489
<> 149:156823d33999 5490 #define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
<> 149:156823d33999 5491 #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
<> 149:156823d33999 5492
<> 149:156823d33999 5493 #define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
<> 149:156823d33999 5494 #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
<> 149:156823d33999 5495
<> 149:156823d33999 5496 #define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
<> 149:156823d33999 5497 #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
<> 149:156823d33999 5498
<> 149:156823d33999 5499 #define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
<> 149:156823d33999 5500 #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
<> 149:156823d33999 5501
<> 149:156823d33999 5502 #define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
<> 149:156823d33999 5503 #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
<> 149:156823d33999 5504
<> 149:156823d33999 5505 #define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
<> 149:156823d33999 5506 #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
<> 149:156823d33999 5507
<> 149:156823d33999 5508 #define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
<> 149:156823d33999 5509 #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
<> 149:156823d33999 5510
<> 149:156823d33999 5511 #define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
<> 149:156823d33999 5512 #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
<> 149:156823d33999 5513
<> 149:156823d33999 5514 #define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
<> 149:156823d33999 5515 #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
<> 149:156823d33999 5516
<> 149:156823d33999 5517 #define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
<> 149:156823d33999 5518 #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
<> 149:156823d33999 5519
<> 149:156823d33999 5520 #define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
<> 149:156823d33999 5521 #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
<> 149:156823d33999 5522
<> 149:156823d33999 5523 #define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
<> 149:156823d33999 5524 #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
<> 149:156823d33999 5525
<> 149:156823d33999 5526 #define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
<> 149:156823d33999 5527 #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
<> 149:156823d33999 5528
<> 149:156823d33999 5529 #define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
<> 149:156823d33999 5530 #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
<> 149:156823d33999 5531
<> 149:156823d33999 5532 #define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
<> 149:156823d33999 5533 #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
<> 149:156823d33999 5534
<> 149:156823d33999 5535 #define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
<> 149:156823d33999 5536 #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
<> 149:156823d33999 5537
<> 149:156823d33999 5538 #define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
<> 149:156823d33999 5539 #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
<> 149:156823d33999 5540
<> 149:156823d33999 5541 #define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
<> 149:156823d33999 5542 #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
<> 149:156823d33999 5543
<> 149:156823d33999 5544 #define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
<> 149:156823d33999 5545 #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
<> 149:156823d33999 5546
<> 149:156823d33999 5547 #define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
<> 149:156823d33999 5548 #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
<> 149:156823d33999 5549
<> 149:156823d33999 5550 #define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
<> 149:156823d33999 5551 #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
<> 149:156823d33999 5552
<> 149:156823d33999 5553 /**@}*/ /* OTG_CONST */
<> 149:156823d33999 5554 /**@}*/ /* end of OTG register group */
<> 149:156823d33999 5555
<> 149:156823d33999 5556
<> 149:156823d33999 5557 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
<> 149:156823d33999 5558 /**
<> 149:156823d33999 5559 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
<> 149:156823d33999 5560 Memory Mapped Structure for PDMA Controller
<> 149:156823d33999 5561 @{ */
<> 149:156823d33999 5562
<> 149:156823d33999 5563
<> 149:156823d33999 5564 typedef struct
<> 149:156823d33999 5565 {
<> 149:156823d33999 5566
<> 149:156823d33999 5567
<> 149:156823d33999 5568 /**
<> 149:156823d33999 5569 * @var DSCT_T::CTL
<> 149:156823d33999 5570 * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11
<> 149:156823d33999 5571 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5572 * |Bits |Field |Descriptions
<> 149:156823d33999 5573 * | :----: | :----: | :---- |
<> 149:156823d33999 5574 * |[1:0] |OPMODE |PDMA Operation Mode Selection
<> 149:156823d33999 5575 * | | |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
<> 149:156823d33999 5576 * | | |1 = Basic mode: The descriptor table only has one task.
<> 149:156823d33999 5577 * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
<> 149:156823d33999 5578 * | | |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
<> 149:156823d33999 5579 * | | |3 = Reserved.
<> 149:156823d33999 5580 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
<> 149:156823d33999 5581 * |[2] |TXTYPE |Transfer Type
<> 149:156823d33999 5582 * | | |0 = Burst transfer type.
<> 149:156823d33999 5583 * | | |1 = Single transfer type.
<> 149:156823d33999 5584 * |[6:4] |BURSIZE |Burst Size
<> 149:156823d33999 5585 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
<> 149:156823d33999 5586 * | | |000 = 128 Transfers.
<> 149:156823d33999 5587 * | | |001 = 64 Transfers.
<> 149:156823d33999 5588 * | | |010 = 32 Transfers.
<> 149:156823d33999 5589 * | | |011 = 16 Transfers.
<> 149:156823d33999 5590 * | | |100 = 8 Transfers.
<> 149:156823d33999 5591 * | | |101 = 4 Transfers.
<> 149:156823d33999 5592 * | | |110 = 2 Transfers.
<> 149:156823d33999 5593 * | | |111 = 1 Transfers.
<> 149:156823d33999 5594 * | | |Note: This field is only useful in burst transfer type.
<> 149:156823d33999 5595 * |[7] |TBINTDIS |Table Interrupt Disable
<> 149:156823d33999 5596 * | | |This field can be used to decide whether to enable table interrupt or not.
<> 149:156823d33999 5597 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
<> 149:156823d33999 5598 * | | |0 = Table interrupt Enabled.
<> 149:156823d33999 5599 * | | |1 = Table interrupt Disabled.
<> 149:156823d33999 5600 * | | |Note: If this bit set to '1', the TEMPTYF will not be set.
<> 149:156823d33999 5601 * |[9:8] |SAINC |Source Address Increment
<> 149:156823d33999 5602 * | | |This field is used to set the source address increment size.
<> 149:156823d33999 5603 * | | |11 = No increment (fixed address).
<> 149:156823d33999 5604 * | | |Others = Increment and size is depended on TXWIDTH selection.
<> 149:156823d33999 5605 * |[11:10] |DAINC |Destination Address Increment
<> 149:156823d33999 5606 * | | |This field is used to set the destination address increment size.
<> 149:156823d33999 5607 * | | |11 = No increment (fixed address).
<> 149:156823d33999 5608 * | | |Others = Increment and size is depended on TXWIDTH selection.
<> 149:156823d33999 5609 * |[13:12] |TXWIDTH |Transfer Width Selection
<> 149:156823d33999 5610 * | | |This field is used for transfer width.
<> 149:156823d33999 5611 * | | |00 = One byte (8 bit) is transferred for every operation.
<> 149:156823d33999 5612 * | | |01= One half-word (16 bit) is transferred for every operation.
<> 149:156823d33999 5613 * | | |10 = One word (32-bit) is transferred for every operation.
<> 149:156823d33999 5614 * | | |11 = Reserved.
<> 149:156823d33999 5615 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
<> 149:156823d33999 5616 * |[29:16] |TXCNT |Transfer Count
<> 149:156823d33999 5617 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
<> 149:156823d33999 5618 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
<> 149:156823d33999 5619 * @var DSCT_T::SA
<> 149:156823d33999 5620 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11
<> 149:156823d33999 5621 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5622 * |Bits |Field |Descriptions
<> 149:156823d33999 5623 * | :----: | :----: | :---- |
<> 149:156823d33999 5624 * |[31:0] |SA |PDMA Transfer Source Address Register
<> 149:156823d33999 5625 * | | |This field indicates a 32-bit source address of PDMA controller.
<> 149:156823d33999 5626 * @var DSCT_T::DA
<> 149:156823d33999 5627 * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11
<> 149:156823d33999 5628 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5629 * |Bits |Field |Descriptions
<> 149:156823d33999 5630 * | :----: | :----: | :---- |
<> 149:156823d33999 5631 * |[31:0] |DA |PDMA Transfer Destination Address Register
<> 149:156823d33999 5632 * | | |This field indicates a 32-bit destination address of PDMA controller.
<> 149:156823d33999 5633 * @var DSCT_T::NEXT
<> 149:156823d33999 5634 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
<> 149:156823d33999 5635 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5636 * |Bits |Field |Descriptions
<> 149:156823d33999 5637 * | :----: | :----: | :---- |
<> 149:156823d33999 5638 * |[15:2] |NEXT |PDMA Next Descriptor Table Offset Address Register
<> 149:156823d33999 5639 * | | |This field indicates the offset of next descriptor table address in system memory.
<> 149:156823d33999 5640 * | | |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
<> 149:156823d33999 5641 * | | |Note1: The next descriptor table address must be word boundary.
<> 149:156823d33999 5642 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
<> 149:156823d33999 5643 */
<> 149:156823d33999 5644
<> 149:156823d33999 5645 __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
<> 149:156823d33999 5646 __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
<> 149:156823d33999 5647 __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
<> 149:156823d33999 5648 __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
<> 149:156823d33999 5649
<> 149:156823d33999 5650 } DSCT_T;
<> 149:156823d33999 5651
<> 149:156823d33999 5652
<> 149:156823d33999 5653
<> 149:156823d33999 5654
<> 149:156823d33999 5655 typedef struct
<> 149:156823d33999 5656 {
<> 149:156823d33999 5657
<> 149:156823d33999 5658
<> 149:156823d33999 5659 /**
<> 149:156823d33999 5660 * @var PDMA_T::DSCT
<> 149:156823d33999 5661 * Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11
<> 149:156823d33999 5662 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5663 * @var PDMA_T::CURSCAT
<> 149:156823d33999 5664 * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
<> 149:156823d33999 5665 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5666 * |Bits |Field |Descriptions
<> 149:156823d33999 5667 * | :----: | :----: | :---- |
<> 149:156823d33999 5668 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
<> 149:156823d33999 5669 * | | |This field indicates a 32-bit current external description address of PDMA controller.
<> 149:156823d33999 5670 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
<> 149:156823d33999 5671 * @var PDMA_T::CHCTL
<> 149:156823d33999 5672 * Offset: 0x400 PDMA Channel Control Register
<> 149:156823d33999 5673 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5674 * |Bits |Field |Descriptions
<> 149:156823d33999 5675 * | :----: | :----: | :---- |
<> 149:156823d33999 5676 * |[11:0] |CHENn |PDMA Channel Enable Bit
<> 149:156823d33999 5677 * | | |Set this bit to 1 to enable PDMAn operation.
<> 149:156823d33999 5678 * | | |If each channel is not set as enabled, each channel cannot be active.
<> 149:156823d33999 5679 * | | |0 = PDMA channel [n] Disabled.
<> 149:156823d33999 5680 * | | |1 = PDMA channel [n] Enabled.
<> 149:156823d33999 5681 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
<> 149:156823d33999 5682 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
<> 149:156823d33999 5683 * @var PDMA_T::STOP
<> 149:156823d33999 5684 * Offset: 0x404 PDMA Transfer Stop Control Register
<> 149:156823d33999 5685 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5686 * |Bits |Field |Descriptions
<> 149:156823d33999 5687 * | :----: | :----: | :---- |
<> 149:156823d33999 5688 * |[11:0] |STOPn |PDMA Transfer Stop Control Register (Write Only)
<> 149:156823d33999 5689 * | | |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
<> 149:156823d33999 5690 * | | |By bit field:
<> 149:156823d33999 5691 * | | |0 = No effect.
<> 149:156823d33999 5692 * | | |1 = Stop PDMA transfer[n].
<> 149:156823d33999 5693 * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
<> 149:156823d33999 5694 * | | |By write 0xFFFF_FFFF to PDMA_STOP:
<> 149:156823d33999 5695 * | | |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
<> 149:156823d33999 5696 * | | |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
<> 149:156823d33999 5697 * | | |Note: User can poll channel enable bit to know if the on-going transfer is finished.
<> 149:156823d33999 5698 * @var PDMA_T::SWREQ
<> 149:156823d33999 5699 * Offset: 0x408 PDMA Software Request Register
<> 149:156823d33999 5700 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5701 * |Bits |Field |Descriptions
<> 149:156823d33999 5702 * | :----: | :----: | :---- |
<> 149:156823d33999 5703 * |[11:0] |SWREQn |PDMA Software Request Register (Write Only)
<> 149:156823d33999 5704 * | | |Set this bit to 1 to generate a software request to PDMA [n].
<> 149:156823d33999 5705 * | | |0 = No effect.
<> 149:156823d33999 5706 * | | |1 = Generate a software request.
<> 149:156823d33999 5707 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
<> 149:156823d33999 5708 * | | |Active flag may be triggered by software request or peripheral request.
<> 149:156823d33999 5709 * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
<> 149:156823d33999 5710 * @var PDMA_T::TRGSTS
<> 149:156823d33999 5711 * Offset: 0x40C PDMA Channel Request Status Register
<> 149:156823d33999 5712 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5713 * |Bits |Field |Descriptions
<> 149:156823d33999 5714 * | :----: | :----: | :---- |
<> 149:156823d33999 5715 * |[11:0] |REQSTSn |PDMA Channel Request Status (Read Only)
<> 149:156823d33999 5716 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
<> 149:156823d33999 5717 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
<> 149:156823d33999 5718 * | | |0 = PDMA Channel n has no request.
<> 149:156823d33999 5719 * | | |1 = PDMA Channel n has a request.
<> 149:156823d33999 5720 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
<> 149:156823d33999 5721 * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
<> 149:156823d33999 5722 * @var PDMA_T::PRISET
<> 149:156823d33999 5723 * Offset: 0x410 PDMA Fixed Priority Setting Register
<> 149:156823d33999 5724 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5725 * |Bits |Field |Descriptions
<> 149:156823d33999 5726 * | :----: | :----: | :---- |
<> 149:156823d33999 5727 * |[11:0] |FPRISETn |PDMA Fixed Priority Setting Register
<> 149:156823d33999 5728 * | | |Set this bit to 1 to enable fixed priority level.
<> 149:156823d33999 5729 * | | |Write Operation:
<> 149:156823d33999 5730 * | | |0 = No effect.
<> 149:156823d33999 5731 * | | |1 = Set PDMA channel [n] to fixed priority channel.
<> 149:156823d33999 5732 * | | |Read Operation:
<> 149:156823d33999 5733 * | | |0 = Corresponding PDMA channel is round-robin priority.
<> 149:156823d33999 5734 * | | |1 = Corresponding PDMA channel is fixed priority.
<> 149:156823d33999 5735 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
<> 149:156823d33999 5736 * @var PDMA_T::PRICLR
<> 149:156823d33999 5737 * Offset: 0x414 PDMA Fixed Priority Clear Register
<> 149:156823d33999 5738 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5739 * |Bits |Field |Descriptions
<> 149:156823d33999 5740 * | :----: | :----: | :---- |
<> 149:156823d33999 5741 * |[11:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
<> 149:156823d33999 5742 * | | |Set this bit to 1 to clear fixed priority level.
<> 149:156823d33999 5743 * | | |0 = No effect.
<> 149:156823d33999 5744 * | | |1 = Clear PDMA channel [n] fixed priority setting.
<> 149:156823d33999 5745 * | | |Note: User can read PDMA_PRISET register to know the channel priority.
<> 149:156823d33999 5746 * @var PDMA_T::INTEN
<> 149:156823d33999 5747 * Offset: 0x418 PDMA Interrupt Enable Register
<> 149:156823d33999 5748 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5749 * |Bits |Field |Descriptions
<> 149:156823d33999 5750 * | :----: | :----: | :---- |
<> 149:156823d33999 5751 * |[11:0] |INTENn |PDMA Interrupt Enable Register
<> 149:156823d33999 5752 * | | |This field is used for enabling PDMA channel[n] interrupt.
<> 149:156823d33999 5753 * | | |0 = PDMA channel n interrupt Disabled.
<> 149:156823d33999 5754 * | | |1 = PDMA channel n interrupt Enabled.
<> 149:156823d33999 5755 * |[31:12] |Reserved |should be keep 0.
<> 149:156823d33999 5756 * @var PDMA_T::INTSTS
<> 149:156823d33999 5757 * Offset: 0x41C PDMA Interrupt Status Register
<> 149:156823d33999 5758 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5759 * |Bits |Field |Descriptions
<> 149:156823d33999 5760 * | :----: | :----: | :---- |
<> 149:156823d33999 5761 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
<> 149:156823d33999 5762 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
<> 149:156823d33999 5763 * | | |0 = No AHB bus ERROR response received.
<> 149:156823d33999 5764 * | | |1 = AHB bus ERROR response received.
<> 149:156823d33999 5765 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
<> 149:156823d33999 5766 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
<> 149:156823d33999 5767 * | | |0 = Not finished yet.
<> 149:156823d33999 5768 * | | |1 = PDMA channel has finished transmission.
<> 149:156823d33999 5769 * |[2] |TEIF |Table Empty Interrupt Flag (Read Only)
<> 149:156823d33999 5770 * | | |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
<> 149:156823d33999 5771 * | | |User can read TEIF register to indicate which channel finished transfer.
<> 149:156823d33999 5772 * | | |0 = PDMA channel transfer is not finished.
<> 149:156823d33999 5773 * | | |1 = PDMA channel transfer is finished and the operation is in idle state.
<> 149:156823d33999 5774 * |[8:15] |REQTOFn |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
<> 149:156823d33999 5775 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
<> 149:156823d33999 5776 * | | |0 = No request time-out.
<> 149:156823d33999 5777 * | | |1 = Peripheral request time-out.
<> 149:156823d33999 5778 * @var PDMA_T::ABTSTS
<> 149:156823d33999 5779 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
<> 149:156823d33999 5780 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5781 * |Bits |Field |Descriptions
<> 149:156823d33999 5782 * | :----: | :----: | :---- |
<> 149:156823d33999 5783 * |[11:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
<> 149:156823d33999 5784 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
<> 149:156823d33999 5785 * | | |0 = No AHB bus ERROR response received when channel n transfer.
<> 149:156823d33999 5786 * | | |1 = AHB bus ERROR response received when channel n transfer.
<> 149:156823d33999 5787 * @var PDMA_T::TDSTS
<> 149:156823d33999 5788 * Offset: 0x424 PDMA Channel Transfer Done Flag Register
<> 149:156823d33999 5789 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5790 * |Bits |Field |Descriptions
<> 149:156823d33999 5791 * | :----: | :----: | :---- |
<> 149:156823d33999 5792 * |[11:0] |TDIFn |Transfer Done Flag Register
<> 149:156823d33999 5793 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
<> 149:156823d33999 5794 * | | |0 = PDMA channel transfer has not finished.
<> 149:156823d33999 5795 * | | |1 = PDMA channel has finished transmission.
<> 149:156823d33999 5796 * @var PDMA_T::SCATSTS
<> 149:156823d33999 5797 * Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register
<> 149:156823d33999 5798 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5799 * |Bits |Field |Descriptions
<> 149:156823d33999 5800 * | :----: | :----: | :---- |
<> 149:156823d33999 5801 * |[11:0] |TEMPTYFn |Scatter-Gather Table Empty Flag Register
<> 149:156823d33999 5802 * | | |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
<> 149:156823d33999 5803 * | | |User can write 1 to clear these bits.
<> 149:156823d33999 5804 * | | |0 = PDMA channel scatter-gather table is not empty.
<> 149:156823d33999 5805 * | | |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
<> 149:156823d33999 5806 * @var PDMA_T::TACTSTS
<> 149:156823d33999 5807 * Offset: 0x42C PDMA Transfer Active Flag Register
<> 149:156823d33999 5808 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5809 * |Bits |Field |Descriptions
<> 149:156823d33999 5810 * | :----: | :----: | :---- |
<> 149:156823d33999 5811 * |[11:0] |TXACTFn |Transfer On Active Flag Register (Read Only)
<> 149:156823d33999 5812 * | | |This bit indicates which PDMA channel is in active.
<> 149:156823d33999 5813 * | | |0 = PDMA channel is not finished.
<> 149:156823d33999 5814 * | | |1 = PDMA channel is active.
<> 149:156823d33999 5815 * @var PDMA_T::TOUTEN
<> 149:156823d33999 5816 * Offset: 0x434 PDMA Time-out Enable register
<> 149:156823d33999 5817 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5818 * |Bits |Field |Descriptions
<> 149:156823d33999 5819 * | :----: | :----: | :---- |
<> 149:156823d33999 5820 * |[7:0] |TOUTENn |PDMA Time-Out Enable Bits
<> 149:156823d33999 5821 * | | |0 = PDMA Channel n time-out function Disable.
<> 149:156823d33999 5822 * | | |1 = PDMA Channel n time-out function Enable.
<> 149:156823d33999 5823 * @var PDMA_T::TOUTIEN
<> 149:156823d33999 5824 * Offset: 0x438 PDMA Time-out Interrupt Enable register
<> 149:156823d33999 5825 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5826 * |Bits |Field |Descriptions
<> 149:156823d33999 5827 * | :----: | :----: | :---- |
<> 149:156823d33999 5828 * |[7:0] |TOUTIENn |PDMA Time-Out Interrupt Enable Bits
<> 149:156823d33999 5829 * | | |0 = PDMA Channel n time-out interrupt Disable.
<> 149:156823d33999 5830 * | | |1 = PDMA Channel n time-out interrupt Enable.
<> 149:156823d33999 5831 * @var PDMA_T::SCATBA
<> 149:156823d33999 5832 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
<> 149:156823d33999 5833 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5834 * |Bits |Field |Descriptions
<> 149:156823d33999 5835 * | :----: | :----: | :---- |
<> 149:156823d33999 5836 * |[31:16] |SCATBA |PDMA Scatter-Gather Descriptor Table Address Register
<> 149:156823d33999 5837 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
<> 149:156823d33999 5838 * | | |The next link address equation is.
<> 149:156823d33999 5839 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
<> 149:156823d33999 5840 * | | |Note: Only useful in Scatter-Gather mode.
<> 149:156823d33999 5841 * @var PDMA_T::TOC0_1
<> 149:156823d33999 5842 * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
<> 149:156823d33999 5843 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5844 * |Bits |Field |Descriptions
<> 149:156823d33999 5845 * | :----: | :----: | :---- |
<> 149:156823d33999 5846 * |[31:16] |TOC1 |Time-Out Counter For Channel 1
<> 149:156823d33999 5847 * | | |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5848 * |[15:0] |TOC0 |Time-Out Counter For Channel 0
<> 149:156823d33999 5849 * | | |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5850 * @var PDMA_T::TOC2_3
<> 149:156823d33999 5851 * Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register
<> 149:156823d33999 5852 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5853 * |Bits |Field |Descriptions
<> 149:156823d33999 5854 * | :----: | :----: | :---- |
<> 149:156823d33999 5855 * |[31:16] |TOC3 |Time-Out Counter For Channel 3
<> 149:156823d33999 5856 * | | |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5857 * |[15:0] |TOC2 |Time-Out Counter For Channel 2
<> 149:156823d33999 5858 * | | |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5859 * @var PDMA_T::TOC4_5
<> 149:156823d33999 5860 * Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register
<> 149:156823d33999 5861 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5862 * |Bits |Field |Descriptions
<> 149:156823d33999 5863 * | :----: | :----: | :---- |
<> 149:156823d33999 5864 * |[31:16] |TOC5 |Time-Out Counter For Channel 5
<> 149:156823d33999 5865 * | | |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5866 * |[15:0] |TOC4 |Time-Out Counter For Channel 4
<> 149:156823d33999 5867 * | | |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5868 * @var PDMA_T::TOC6_7
<> 149:156823d33999 5869 * Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register
<> 149:156823d33999 5870 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5871 * |Bits |Field |Descriptions
<> 149:156823d33999 5872 * | :----: | :----: | :---- |
<> 149:156823d33999 5873 * |[31:16] |TOC7 |Time-Out Counter For Channel 7
<> 149:156823d33999 5874 * | | |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5875 * |[15:0] |TOC6 |Time-Out Counter For Channel 6
<> 149:156823d33999 5876 * | | |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
<> 149:156823d33999 5877 * @var PDMA_T::REQSEL0_3
<> 149:156823d33999 5878 * Offset: 0x480 PDMA Request Source Select Register 0
<> 149:156823d33999 5879 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5880 * |Bits |Field |Descriptions
<> 149:156823d33999 5881 * | :----: | :----: | :---- |
<> 149:156823d33999 5882 * |[4:0] |REQSRC0 |Channel 0 Request Source Selection
<> 149:156823d33999 5883 * | | |This filed defines which peripheral is connected to PDMA channel 0.
<> 149:156823d33999 5884 * | | |User can configure the peripheral by setting REQSRC0.
<> 149:156823d33999 5885 * | | |1 = Channel connects to SPI0_TX.
<> 149:156823d33999 5886 * | | |2 = Channel connects to SPI1_TX.
<> 149:156823d33999 5887 * | | |3 = Channel connects to SPI2_TX.
<> 149:156823d33999 5888 * | | |4 = Channel connects to UART0_TX.
<> 149:156823d33999 5889 * | | |5 = Channel connects to UART1_TX.
<> 149:156823d33999 5890 * | | |6 = Channel connects to UART2_TX.
<> 149:156823d33999 5891 * | | |7 = Channel connects to UART3_TX.
<> 149:156823d33999 5892 * | | |8 = Channel connects to DAC_TX.
<> 149:156823d33999 5893 * | | |9 = Channel connects to ADC_RX.
<> 149:156823d33999 5894 * | | |11 = Channel connects to PWM0_P1_RX.
<> 149:156823d33999 5895 * | | |12 = Channel connects to PWM0_P2_RX.
<> 149:156823d33999 5896 * | | |13 = Channel connects to PWM0_P3_RX.
<> 149:156823d33999 5897 * | | |14 = Channel connects to PWM1_P1_RX.
<> 149:156823d33999 5898 * | | |15 = Channel connects to PWM1_P2_RX.
<> 149:156823d33999 5899 * | | |16 = Channel connects to PWM1_P3_RX.
<> 149:156823d33999 5900 * | | |17 = Channel connects to SPI0_RX.
<> 149:156823d33999 5901 * | | |18 = Channel connects to SPI1_RX.
<> 149:156823d33999 5902 * | | |19 = Channel connects to SPI2_RX.
<> 149:156823d33999 5903 * | | |20 = Channel connects to UART0_RX.
<> 149:156823d33999 5904 * | | |21 = Channel connects to UART1_RX.
<> 149:156823d33999 5905 * | | |22 = Channel connects to UART2_RX.
<> 149:156823d33999 5906 * | | |23 = Channel connects to UART3_RX.
<> 149:156823d33999 5907 * | | |31 = Disable PDMA.
<> 149:156823d33999 5908 * | | |Others = Reserved.
<> 149:156823d33999 5909 * | | |Note 1: A peripheral can't assign to two channels at the same time.
<> 149:156823d33999 5910 * | | |Note 2: This field is useless when transfer between memory and memory.
<> 149:156823d33999 5911 * |[12:8] |REQSRC1 |Channel 1 Request Source Selection
<> 149:156823d33999 5912 * | | |This filed defines which peripheral is connected to PDMA channel 1.
<> 149:156823d33999 5913 * | | |User can configure the peripheral setting by REQSRC1.
<> 149:156823d33999 5914 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5915 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5916 * |[20:16] |REQSRC2 |Channel 2 Request Source Selection
<> 149:156823d33999 5917 * | | |This filed defines which peripheral is connected to PDMA channel 2.
<> 149:156823d33999 5918 * | | |User can configure the peripheral setting by REQSRC2.
<> 149:156823d33999 5919 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5920 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5921 * |[28:24] |REQSRC3 |Channel 3 Request Source Selection
<> 149:156823d33999 5922 * | | |This filed defines which peripheral is connected to PDMA channel 3.
<> 149:156823d33999 5923 * | | |User can configure the peripheral setting by REQSRC3.
<> 149:156823d33999 5924 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5925 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5926 * @var PDMA_T::REQSEL4_7
<> 149:156823d33999 5927 * Offset: 0x484 PDMA Request Source Select Register 1
<> 149:156823d33999 5928 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5929 * |Bits |Field |Descriptions
<> 149:156823d33999 5930 * | :----: | :----: | :---- |
<> 149:156823d33999 5931 * |[4:0] |REQSRC4 |Channel 4 Request Source Selection
<> 149:156823d33999 5932 * | | |This filed defines which peripheral is connected to PDMA channel 4.
<> 149:156823d33999 5933 * | | |User can configure the peripheral setting by REQSRC4.
<> 149:156823d33999 5934 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5935 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5936 * |[12:8] |REQSRC5 |Channel 5 Request Source Selection
<> 149:156823d33999 5937 * | | |This filed defines which peripheral is connected to PDMA channel 5.
<> 149:156823d33999 5938 * | | |User can configure the peripheral setting by REQSRC5.
<> 149:156823d33999 5939 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5940 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5941 * |[20:16] |REQSRC6 |Channel 6 Request Source Selection
<> 149:156823d33999 5942 * | | |This filed defines which peripheral is connected to PDMA channel 6.
<> 149:156823d33999 5943 * | | |User can configure the peripheral setting by REQSRC6.
<> 149:156823d33999 5944 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5945 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5946 * |[28:24] |REQSRC7 |Channel 7 Request Source Selection
<> 149:156823d33999 5947 * | | |This filed defines which peripheral is connected to PDMA channel 7.
<> 149:156823d33999 5948 * | | |User can configure the peripheral setting by REQSRC7.
<> 149:156823d33999 5949 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5950 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5951 * @var PDMA_T::REQSEL8_11
<> 149:156823d33999 5952 * Offset: 0x488 PDMA Request Source Select Register 2
<> 149:156823d33999 5953 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 5954 * |Bits |Field |Descriptions
<> 149:156823d33999 5955 * | :----: | :----: | :---- |
<> 149:156823d33999 5956 * |[4:0] |REQSRC8 |Channel 8 Request Source Selection
<> 149:156823d33999 5957 * | | |This filed defines which peripheral is connected to PDMA channel 8.
<> 149:156823d33999 5958 * | | |User can configure the peripheral setting by REQSRC8.
<> 149:156823d33999 5959 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5960 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5961 * |[12:8] |REQSRC9 |Channel 9 Request Source Selection
<> 149:156823d33999 5962 * | | |This filed defines which peripheral is connected to PDMA channel 9.
<> 149:156823d33999 5963 * | | |User can configure the peripheral setting by REQSRC9.
<> 149:156823d33999 5964 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5965 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5966 * |[20:16] |REQSRC10 |Channel 10 Request Source Selection
<> 149:156823d33999 5967 * | | |This filed defines which peripheral is connected to PDMA channel 10.
<> 149:156823d33999 5968 * | | |User can configure the peripheral setting by REQSRC10.
<> 149:156823d33999 5969 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5970 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5971 * |[28:24] |REQSRC11 |Channel 11 Request Source Selection
<> 149:156823d33999 5972 * | | |This filed defines which peripheral is connected to PDMA channel 11.
<> 149:156823d33999 5973 * | | |User can configure the peripheral setting by REQSRC11.
<> 149:156823d33999 5974 * | | |Note: The channel configuration is the same as REQSRC0 field.
<> 149:156823d33999 5975 * | | |Please refer to the explanation of REQSRC0.
<> 149:156823d33999 5976 */
<> 149:156823d33999 5977
<> 149:156823d33999 5978 DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
<> 149:156823d33999 5979 __I uint32_t CURSCAT[12];
<> 149:156823d33999 5980 __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
<> 149:156823d33999 5981 __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
<> 149:156823d33999 5982 __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
<> 149:156823d33999 5983 __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
<> 149:156823d33999 5984 __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
<> 149:156823d33999 5985 __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
<> 149:156823d33999 5986 __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
<> 149:156823d33999 5987 __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
<> 149:156823d33999 5988 __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
<> 149:156823d33999 5989 __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
<> 149:156823d33999 5990 __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
<> 149:156823d33999 5991 __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
<> 149:156823d33999 5992 __I uint32_t TACTSTS;
<> 149:156823d33999 5993 __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
<> 149:156823d33999 5994 __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
<> 149:156823d33999 5995 __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
<> 149:156823d33999 5996 __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
<> 149:156823d33999 5997 __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
<> 149:156823d33999 5998 __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
<> 149:156823d33999 5999 __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
<> 149:156823d33999 6000 __IO uint32_t TOC6_7;
<> 149:156823d33999 6001 __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
<> 149:156823d33999 6002 __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
<> 149:156823d33999 6003 __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
<> 149:156823d33999 6004 __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
<> 149:156823d33999 6005
<> 149:156823d33999 6006 } PDMA_T;
<> 149:156823d33999 6007
<> 149:156823d33999 6008
<> 149:156823d33999 6009
<> 149:156823d33999 6010 /**
<> 149:156823d33999 6011 @addtogroup PDMA_CONST PDMA Bit Field Definition
<> 149:156823d33999 6012 Constant Definitions for PDMA Controller
<> 149:156823d33999 6013 @{ */
<> 149:156823d33999 6014
<> 149:156823d33999 6015 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
<> 149:156823d33999 6016 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
<> 149:156823d33999 6017
<> 149:156823d33999 6018 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
<> 149:156823d33999 6019 #define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
<> 149:156823d33999 6020
<> 149:156823d33999 6021 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
<> 149:156823d33999 6022 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
<> 149:156823d33999 6023
<> 149:156823d33999 6024 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
<> 149:156823d33999 6025 #define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
<> 149:156823d33999 6026
<> 149:156823d33999 6027 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
<> 149:156823d33999 6028 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
<> 149:156823d33999 6029
<> 149:156823d33999 6030 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
<> 149:156823d33999 6031 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
<> 149:156823d33999 6032
<> 149:156823d33999 6033 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
<> 149:156823d33999 6034 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
<> 149:156823d33999 6035
<> 149:156823d33999 6036 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
<> 149:156823d33999 6037 #define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
<> 149:156823d33999 6038
<> 149:156823d33999 6039 #define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
<> 149:156823d33999 6040 #define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
<> 149:156823d33999 6041
<> 149:156823d33999 6042 #define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
<> 149:156823d33999 6043 #define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
<> 149:156823d33999 6044
<> 149:156823d33999 6045 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
<> 149:156823d33999 6046 #define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
<> 149:156823d33999 6047
<> 149:156823d33999 6048 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
<> 149:156823d33999 6049 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
<> 149:156823d33999 6050
<> 149:156823d33999 6051 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
<> 149:156823d33999 6052 #define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
<> 149:156823d33999 6053
<> 149:156823d33999 6054 #define PDMA_STOP_STOPn_Pos (0) /*!< PDMA_T::STOP: STOPn Position */
<> 149:156823d33999 6055 #define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) /*!< PDMA_T::STOP: STOPn Mask */
<> 149:156823d33999 6056
<> 149:156823d33999 6057 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
<> 149:156823d33999 6058 #define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
<> 149:156823d33999 6059
<> 149:156823d33999 6060 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
<> 149:156823d33999 6061 #define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
<> 149:156823d33999 6062
<> 149:156823d33999 6063 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
<> 149:156823d33999 6064 #define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
<> 149:156823d33999 6065
<> 149:156823d33999 6066 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
<> 149:156823d33999 6067 #define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
<> 149:156823d33999 6068
<> 149:156823d33999 6069 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
<> 149:156823d33999 6070 #define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
<> 149:156823d33999 6071
<> 149:156823d33999 6072 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
<> 149:156823d33999 6073 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
<> 149:156823d33999 6074
<> 149:156823d33999 6075 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
<> 149:156823d33999 6076 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
<> 149:156823d33999 6077
<> 149:156823d33999 6078 #define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA_T::INTSTS: TEIF Position */
<> 149:156823d33999 6079 #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA_T::INTSTS: TEIF Mask */
<> 149:156823d33999 6080
<> 149:156823d33999 6081 #define PDMA_INTSTS_REQTOFn_Pos (8) /*!< PDMA_T::INTSTS: REQTOFn Position */
<> 149:156823d33999 6082 #define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) /*!< PDMA_T::INTSTS: REQTOFn Mask */
<> 149:156823d33999 6083
<> 149:156823d33999 6084 #define PDMA_ABTSTS_ABTIFn_Pos (0) /*!< PDMA_T::ABTSTS: ABTIFn Position */
<> 149:156823d33999 6085 #define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) /*!< PDMA_T::ABTSTS: ABTIFn Mask */
<> 149:156823d33999 6086
<> 149:156823d33999 6087 #define PDMA_TDSTS_TDIFn_Pos (0) /*!< PDMA_T::TDSTS: TDIFn Position */
<> 149:156823d33999 6088 #define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) /*!< PDMA_T::TDSTS: TDIFn Mask */
<> 149:156823d33999 6089
<> 149:156823d33999 6090 #define PDMA_SCATSTS_TEMPTYFn_Pos (0) /*!< PDMA_T::SCATSTS: TEMPTYFn Position */
<> 149:156823d33999 6091 #define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) /*!< PDMA_T::SCATSTS: TEMPTYFn Mask */
<> 149:156823d33999 6092
<> 149:156823d33999 6093 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
<> 149:156823d33999 6094 #define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
<> 149:156823d33999 6095
<> 149:156823d33999 6096 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
<> 149:156823d33999 6097 #define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
<> 149:156823d33999 6098
<> 149:156823d33999 6099 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
<> 149:156823d33999 6100 #define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
<> 149:156823d33999 6101
<> 149:156823d33999 6102 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
<> 149:156823d33999 6103 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
<> 149:156823d33999 6104
<> 149:156823d33999 6105 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
<> 149:156823d33999 6106 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
<> 149:156823d33999 6107
<> 149:156823d33999 6108 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
<> 149:156823d33999 6109 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
<> 149:156823d33999 6110
<> 149:156823d33999 6111 #define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */
<> 149:156823d33999 6112 #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */
<> 149:156823d33999 6113
<> 149:156823d33999 6114 #define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */
<> 149:156823d33999 6115 #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */
<> 149:156823d33999 6116
<> 149:156823d33999 6117 #define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */
<> 149:156823d33999 6118 #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */
<> 149:156823d33999 6119
<> 149:156823d33999 6120 #define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */
<> 149:156823d33999 6121 #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */
<> 149:156823d33999 6122
<> 149:156823d33999 6123 #define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */
<> 149:156823d33999 6124 #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */
<> 149:156823d33999 6125
<> 149:156823d33999 6126 #define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */
<> 149:156823d33999 6127 #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */
<> 149:156823d33999 6128
<> 149:156823d33999 6129 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
<> 149:156823d33999 6130 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
<> 149:156823d33999 6131
<> 149:156823d33999 6132 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
<> 149:156823d33999 6133 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
<> 149:156823d33999 6134
<> 149:156823d33999 6135 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
<> 149:156823d33999 6136 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
<> 149:156823d33999 6137
<> 149:156823d33999 6138 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
<> 149:156823d33999 6139 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
<> 149:156823d33999 6140
<> 149:156823d33999 6141 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
<> 149:156823d33999 6142 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
<> 149:156823d33999 6143
<> 149:156823d33999 6144 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
<> 149:156823d33999 6145 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
<> 149:156823d33999 6146
<> 149:156823d33999 6147 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
<> 149:156823d33999 6148 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
<> 149:156823d33999 6149
<> 149:156823d33999 6150 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
<> 149:156823d33999 6151 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
<> 149:156823d33999 6152
<> 149:156823d33999 6153 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
<> 149:156823d33999 6154 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
<> 149:156823d33999 6155
<> 149:156823d33999 6156 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
<> 149:156823d33999 6157 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
<> 149:156823d33999 6158
<> 149:156823d33999 6159 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
<> 149:156823d33999 6160 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
<> 149:156823d33999 6161
<> 149:156823d33999 6162 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
<> 149:156823d33999 6163 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
<> 149:156823d33999 6164
<> 149:156823d33999 6165 /**@}*/ /* PDMA_CONST */
<> 149:156823d33999 6166 /**@}*/ /* end of PDMA register group */
<> 149:156823d33999 6167
<> 149:156823d33999 6168
<> 149:156823d33999 6169 /*---------------------- Pulse Width Modulation Controller -------------------------*/
<> 149:156823d33999 6170 /**
<> 149:156823d33999 6171 @addtogroup PWM Pulse Width Modulation Controller(PWM)
<> 149:156823d33999 6172 Memory Mapped Structure for PWM Controller
<> 149:156823d33999 6173 @{ */
<> 149:156823d33999 6174
<> 149:156823d33999 6175
<> 149:156823d33999 6176 typedef struct
<> 149:156823d33999 6177 {
<> 149:156823d33999 6178
<> 149:156823d33999 6179
<> 149:156823d33999 6180 /**
<> 149:156823d33999 6181 * @var PWM_T::CTL0
<> 149:156823d33999 6182 * Offset: 0x00 PWM Control Register 0
<> 149:156823d33999 6183 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6184 * |Bits |Field |Descriptions
<> 149:156823d33999 6185 * | :----: | :----: | :---- |
<> 149:156823d33999 6186 * |[5:0] |CTRLDn |Center Re-Load
<> 149:156823d33999 6187 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6188 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
<> 149:156823d33999 6189 * | | |CMPDAT will load to CMPBUF at the center point of a period.
<> 149:156823d33999 6190 * |[13:8] |WINLDENn |Window Load Enable
<> 149:156823d33999 6191 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6192 * | | |0 = PERIOD will load to PBUF at the end point of each period.
<> 149:156823d33999 6193 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
<> 149:156823d33999 6194 * | | |1 = PERIOD will load to PBUF at the end point of each period.
<> 149:156823d33999 6195 * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
<> 149:156823d33999 6196 * | | |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
<> 149:156823d33999 6197 * |[21:16] |IMMLDENn |Immediately Load Enable
<> 149:156823d33999 6198 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6199 * | | |0 = PERIOD will load to PBUF at the end point of each period.
<> 149:156823d33999 6200 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
<> 149:156823d33999 6201 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
<> 149:156823d33999 6202 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
<> 149:156823d33999 6203 * |[24] |GROUPEN |Group Function Enable
<> 149:156823d33999 6204 * | | |0 = The output waveform of each PWM channel are independent.
<> 149:156823d33999 6205 * | | |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
<> 149:156823d33999 6206 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
<> 149:156823d33999 6207 * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
<> 149:156823d33999 6208 * | | |0 = ICE debug mode counter halt disable.
<> 149:156823d33999 6209 * | | |1 = ICE debug mode counter halt enable.
<> 149:156823d33999 6210 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6211 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
<> 149:156823d33999 6212 * | | |0 = ICE debug mode acknowledgement effects PWM output.
<> 149:156823d33999 6213 * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
<> 149:156823d33999 6214 * | | |1 = ICE debug mode acknowledgement disabled.
<> 149:156823d33999 6215 * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
<> 149:156823d33999 6216 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6217 * @var PWM_T::CTL1
<> 149:156823d33999 6218 * Offset: 0x04 PWM Control Register 1
<> 149:156823d33999 6219 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6220 * |Bits |Field |Descriptions
<> 149:156823d33999 6221 * | :----: | :----: | :---- |
<> 149:156823d33999 6222 * |[11:0] |CNTTYPEn |PWM Counter Behavior Type
<> 149:156823d33999 6223 * | | |Each bit n controls corresponding PWM channel n.
<> 149:156823d33999 6224 * | | |00 = Up counter type (supports in capture mode).
<> 149:156823d33999 6225 * | | |01 = Down count type (supports in capture mode).
<> 149:156823d33999 6226 * | | |10 = Up-down counter type.
<> 149:156823d33999 6227 * | | |11 = Reserved.
<> 149:156823d33999 6228 * |[21:16] |CNTMODEn |PWM Counter Mode
<> 149:156823d33999 6229 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6230 * | | |0 = Auto-reload mode.
<> 149:156823d33999 6231 * | | |1 = One-shot mode.
<> 149:156823d33999 6232 * |[26:24] |OUTMODEn |PWM Output Mode
<> 149:156823d33999 6233 * | | |Each bit n controls the
<> 149:156823d33999 6234 * | | |output mode of
<> 149:156823d33999 6235 * | | |corresponding PWM channel n.
<> 149:156823d33999 6236 * | | |0 = PWM independent mode.
<> 149:156823d33999 6237 * | | |1 = PWM complementary mode.
<> 149:156823d33999 6238 * | | |Note: When operating in group function, these bits must all set to the same mode.
<> 149:156823d33999 6239 * @var PWM_T::SYNC
<> 149:156823d33999 6240 * Offset: 0x08 PWM Synchronization Register
<> 149:156823d33999 6241 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6242 * |Bits |Field |Descriptions
<> 149:156823d33999 6243 * | :----: | :----: | :---- |
<> 149:156823d33999 6244 * |[2:0] |PHSENn |SYNC Phase Enable
<> 149:156823d33999 6245 * | | |Each bit n controls corresponding PWM channel n.
<> 149:156823d33999 6246 * | | |0 = PWM counter disable to load PHS value.
<> 149:156823d33999 6247 * | | |1 = PWM counter enable to load PHS value.
<> 149:156823d33999 6248 * |[13:8] |SINSRCn |PWM_SYNC_IN Source Selection
<> 149:156823d33999 6249 * | | |Each bit n controls corresponding PWM channel n.
<> 149:156823d33999 6250 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
<> 149:156823d33999 6251 * | | |01 = Counter equal to 0.
<> 149:156823d33999 6252 * | | |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
<> 149:156823d33999 6253 * | | |11 = SYNC_OUT will not be generated.
<> 149:156823d33999 6254 * |[16] |SNFLTEN |PWM_SYNC_IN Noise Filter Enable
<> 149:156823d33999 6255 * | | |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
<> 149:156823d33999 6256 * | | |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
<> 149:156823d33999 6257 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
<> 149:156823d33999 6258 * | | |000 = Filter clock = HCLK.
<> 149:156823d33999 6259 * | | |001 = Filter clock = HCLK/2.
<> 149:156823d33999 6260 * | | |010 = Filter clock = HCLK/4.
<> 149:156823d33999 6261 * | | |011 = Filter clock = HCLK/8.
<> 149:156823d33999 6262 * | | |100 = Filter clock = HCLK/16.
<> 149:156823d33999 6263 * | | |101 = Filter clock = HCLK/32.
<> 149:156823d33999 6264 * | | |110 = Filter clock = HCLK/64.
<> 149:156823d33999 6265 * | | |111 = Filter clock = HCLK/128.
<> 149:156823d33999 6266 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
<> 149:156823d33999 6267 * | | |The register bits control the counter number of edge detector.
<> 149:156823d33999 6268 * |[23] |SINPINV |SYNC Input Pin Inverse
<> 149:156823d33999 6269 * | | |0 = The state of pin SYNC is passed to the negative edge detector.
<> 149:156823d33999 6270 * | | |1 = The inverted state of pin SYNC is passed to the negative edge detector.
<> 149:156823d33999 6271 * |[26:24] |PHSDIRn |PWM Phase Direction Control
<> 149:156823d33999 6272 * | | |Each bit n controls corresponding PWM channel n.
<> 149:156823d33999 6273 * | | |0 = Control PWM counter count decrement after synchronizing.
<> 149:156823d33999 6274 * | | |1 = Control PWM counter count increment after synchronizing.
<> 149:156823d33999 6275 * @var PWM_T::SWSYNC
<> 149:156823d33999 6276 * Offset: 0x0C PWM Software Control Synchronization Register
<> 149:156823d33999 6277 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6278 * |Bits |Field |Descriptions
<> 149:156823d33999 6279 * | :----: | :----: | :---- |
<> 149:156823d33999 6280 * |[2:0] |SWSYNCn |Software SYNC Function
<> 149:156823d33999 6281 * | | |Each bit n controls corresponding PWM channel n.
<> 149:156823d33999 6282 * | | |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
<> 149:156823d33999 6283 * @var PWM_T::CLKSRC
<> 149:156823d33999 6284 * Offset: 0x10 PWM Clock Source Register
<> 149:156823d33999 6285 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6286 * |Bits |Field |Descriptions
<> 149:156823d33999 6287 * | :----: | :----: | :---- |
<> 149:156823d33999 6288 * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select
<> 149:156823d33999 6289 * | | |000 = PWMx_CLK, x denotes 0 or 1.
<> 149:156823d33999 6290 * | | |001 = TIMER0 overflow.
<> 149:156823d33999 6291 * | | |010 = TIMER1 overflow.
<> 149:156823d33999 6292 * | | |011 = TIMER2 overflow.
<> 149:156823d33999 6293 * | | |100 = TIMER3 overflow.
<> 149:156823d33999 6294 * | | |Others = Reserved.
<> 149:156823d33999 6295 * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select
<> 149:156823d33999 6296 * | | |000 = PWMx_CLK, x denotes 0 or 1.
<> 149:156823d33999 6297 * | | |001 = TIMER0 overflow.
<> 149:156823d33999 6298 * | | |010 = TIMER1 overflow.
<> 149:156823d33999 6299 * | | |011 = TIMER2 overflow.
<> 149:156823d33999 6300 * | | |100 = TIMER3 overflow.
<> 149:156823d33999 6301 * | | |Others = Reserved.
<> 149:156823d33999 6302 * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select
<> 149:156823d33999 6303 * | | |000 = PWMx_CLK, x denotes 0 or 1.
<> 149:156823d33999 6304 * | | |001 = TIMER0 overflow.
<> 149:156823d33999 6305 * | | |010 = TIMER1 overflow.
<> 149:156823d33999 6306 * | | |011 = TIMER2 overflow.
<> 149:156823d33999 6307 * | | |100 = TIMER3 overflow.
<> 149:156823d33999 6308 * | | |Others = Reserved.
<> 149:156823d33999 6309 * @var PWM_T::CLKPSC0_1
<> 149:156823d33999 6310 * Offset: 0x14 PWM Clock Pre-scale Register 0
<> 149:156823d33999 6311 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6312 * |Bits |Field |Descriptions
<> 149:156823d33999 6313 * | :----: | :----: | :---- |
<> 149:156823d33999 6314 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
<> 149:156823d33999 6315 * | | |The clock of PWM counter is decided by clock prescaler.
<> 149:156823d33999 6316 * | | |Each PWM pair share one PWM counter clock prescaler.
<> 149:156823d33999 6317 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
<> 149:156823d33999 6318 * @var PWM_T::CLKPSC2_3
<> 149:156823d33999 6319 * Offset: 0x18 PWM Clock Pre-scale Register 2
<> 149:156823d33999 6320 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6321 * |Bits |Field |Descriptions
<> 149:156823d33999 6322 * | :----: | :----: | :---- |
<> 149:156823d33999 6323 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
<> 149:156823d33999 6324 * | | |The clock of PWM counter is decided by clock prescaler.
<> 149:156823d33999 6325 * | | |Each PWM pair share one PWM counter clock prescaler.
<> 149:156823d33999 6326 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
<> 149:156823d33999 6327 * @var PWM_T::CLKPSC4_5
<> 149:156823d33999 6328 * Offset: 0x1C PWM Clock Pre-scale Register 4
<> 149:156823d33999 6329 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6330 * |Bits |Field |Descriptions
<> 149:156823d33999 6331 * | :----: | :----: | :---- |
<> 149:156823d33999 6332 * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
<> 149:156823d33999 6333 * | | |The clock of PWM counter is decided by clock prescaler.
<> 149:156823d33999 6334 * | | |Each PWM pair share one PWM counter clock prescaler.
<> 149:156823d33999 6335 * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
<> 149:156823d33999 6336 * @var PWM_T::CNTEN
<> 149:156823d33999 6337 * Offset: 0x20 PWM Counter Enable Register
<> 149:156823d33999 6338 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6339 * |Bits |Field |Descriptions
<> 149:156823d33999 6340 * | :----: | :----: | :---- |
<> 149:156823d33999 6341 * |[5:0] |CNTENn |PWM Counter Enable
<> 149:156823d33999 6342 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6343 * | | |0 = PWM Counter and clock prescaler Stop Running.
<> 149:156823d33999 6344 * | | |1 = PWM Counter and clock prescaler Start Running.
<> 149:156823d33999 6345 * @var PWM_T::CNTCLR
<> 149:156823d33999 6346 * Offset: 0x24 PWM Clear Counter Register
<> 149:156823d33999 6347 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6348 * |Bits |Field |Descriptions
<> 149:156823d33999 6349 * | :----: | :----: | :---- |
<> 149:156823d33999 6350 * |[5:0] |CNTCLRn |Clear PWM Counter Control Bit
<> 149:156823d33999 6351 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6352 * | | |0 = No effect.
<> 149:156823d33999 6353 * | | |1 = Clear 16-bit PWM counter to 0000H.
<> 149:156823d33999 6354 * @var PWM_T::LOAD
<> 149:156823d33999 6355 * Offset: 0x28 PWM Load Register
<> 149:156823d33999 6356 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6357 * |Bits |Field |Descriptions
<> 149:156823d33999 6358 * | :----: | :----: | :---- |
<> 149:156823d33999 6359 * |[5:0] |LOADn |Re-Load PWM Comparator Register (CMPDAT) Control Bit
<> 149:156823d33999 6360 * | | |This bit is software write, hardware clear when current PWM period end.
<> 149:156823d33999 6361 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6362 * | | |Write Operation:
<> 149:156823d33999 6363 * | | |0 = No effect.
<> 149:156823d33999 6364 * | | |1 = Set load window of window loading mode.
<> 149:156823d33999 6365 * | | |Read Operation:
<> 149:156823d33999 6366 * | | |0 = No load window is set.
<> 149:156823d33999 6367 * | | |1 = Load window is set.
<> 149:156823d33999 6368 * | | |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
<> 149:156823d33999 6369 * @var PWM_T::PERIOD
<> 149:156823d33999 6370 * Offset: 0x30~0x44 PWM Period Register 0~5
<> 149:156823d33999 6371 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6372 * |Bits |Field |Descriptions
<> 149:156823d33999 6373 * | :----: | :----: | :---- |
<> 149:156823d33999 6374 * |[15:0] |PERIOD |PWM Period Register
<> 149:156823d33999 6375 * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
<> 149:156823d33999 6376 * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
<> 149:156823d33999 6377 * | | |PWM period time = (PERIOD+1) * PWM_CLK period.
<> 149:156823d33999 6378 * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
<> 149:156823d33999 6379 * | | |PWM period time = 2 * PERIOD * PWM_CLK period.
<> 149:156823d33999 6380 * @var PWM_T::CMPDAT
<> 149:156823d33999 6381 * Offset: 0x50~0x64 PWM Comparator Register 0~5
<> 149:156823d33999 6382 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6383 * |Bits |Field |Descriptions
<> 149:156823d33999 6384 * | :----: | :----: | :---- |
<> 149:156823d33999 6385 * |[15:0] |CMP |PWM Comparator Register
<> 149:156823d33999 6386 * | | |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
<> 149:156823d33999 6387 * | | |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
<> 149:156823d33999 6388 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
<> 149:156823d33999 6389 * @var PWM_T::DTCTL0_1
<> 149:156823d33999 6390 * Offset: 0x70 PWM Dead-Time Control Register 0
<> 149:156823d33999 6391 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6392 * |Bits |Field |Descriptions
<> 149:156823d33999 6393 * | :----: | :----: | :---- |
<> 149:156823d33999 6394 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
<> 149:156823d33999 6395 * | | |The dead-time can be calculated from the following formula:
<> 149:156823d33999 6396 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
<> 149:156823d33999 6397 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6398 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
<> 149:156823d33999 6399 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 149:156823d33999 6400 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 149:156823d33999 6401 * | | |0 = Dead-time insertion Disabled on the pin pair.
<> 149:156823d33999 6402 * | | |1 = Dead-time insertion Enabled on the pin pair.
<> 149:156823d33999 6403 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6404 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
<> 149:156823d33999 6405 * | | |0 = Dead-time clock source from PWM_CLK.
<> 149:156823d33999 6406 * | | |1 = Dead-time clock source from prescaler output.
<> 149:156823d33999 6407 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6408 * @var PWM_T::DTCTL2_3
<> 149:156823d33999 6409 * Offset: 0x74 PWM Dead-Time Control Register 2
<> 149:156823d33999 6410 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6411 * |Bits |Field |Descriptions
<> 149:156823d33999 6412 * | :----: | :----: | :---- |
<> 149:156823d33999 6413 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
<> 149:156823d33999 6414 * | | |The dead-time can be calculated from the following formula:
<> 149:156823d33999 6415 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
<> 149:156823d33999 6416 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6417 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
<> 149:156823d33999 6418 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 149:156823d33999 6419 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 149:156823d33999 6420 * | | |0 = Dead-time insertion Disabled on the pin pair.
<> 149:156823d33999 6421 * | | |1 = Dead-time insertion Enabled on the pin pair.
<> 149:156823d33999 6422 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6423 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
<> 149:156823d33999 6424 * | | |0 = Dead-time clock source from PWM_CLK.
<> 149:156823d33999 6425 * | | |1 = Dead-time clock source from prescaler output.
<> 149:156823d33999 6426 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6427 * @var PWM_T::DTCTL4_5
<> 149:156823d33999 6428 * Offset: 0x78 PWM Dead-Time Control Register 4
<> 149:156823d33999 6429 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6430 * |Bits |Field |Descriptions
<> 149:156823d33999 6431 * | :----: | :----: | :---- |
<> 149:156823d33999 6432 * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
<> 149:156823d33999 6433 * | | |The dead-time can be calculated from the following formula:
<> 149:156823d33999 6434 * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
<> 149:156823d33999 6435 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6436 * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
<> 149:156823d33999 6437 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 149:156823d33999 6438 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 149:156823d33999 6439 * | | |0 = Dead-time insertion Disabled on the pin pair.
<> 149:156823d33999 6440 * | | |1 = Dead-time insertion Enabled on the pin pair.
<> 149:156823d33999 6441 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6442 * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
<> 149:156823d33999 6443 * | | |0 = Dead-time clock source from PWM_CLK.
<> 149:156823d33999 6444 * | | |1 = Dead-time clock source from prescaler output.
<> 149:156823d33999 6445 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6446 * @var PWM_T::PHS0_1
<> 149:156823d33999 6447 * Offset: 0x80 PWM Counter Phase Register 0
<> 149:156823d33999 6448 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6449 * |Bits |Field |Descriptions
<> 149:156823d33999 6450 * | :----: | :----: | :---- |
<> 149:156823d33999 6451 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
<> 149:156823d33999 6452 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
<> 149:156823d33999 6453 * @var PWM_T::PHS2_3
<> 149:156823d33999 6454 * Offset: 0x84 PWM Counter Phase Register 2
<> 149:156823d33999 6455 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6456 * |Bits |Field |Descriptions
<> 149:156823d33999 6457 * | :----: | :----: | :---- |
<> 149:156823d33999 6458 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
<> 149:156823d33999 6459 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
<> 149:156823d33999 6460 * @var PWM_T::PHS4_5
<> 149:156823d33999 6461 * Offset: 0x88 PWM Counter Phase Register 4
<> 149:156823d33999 6462 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6463 * |Bits |Field |Descriptions
<> 149:156823d33999 6464 * | :----: | :----: | :---- |
<> 149:156823d33999 6465 * |[15:0] |PHS |PWM Synchronous Start Phase Bits
<> 149:156823d33999 6466 * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
<> 149:156823d33999 6467 * @var PWM_T::CNT
<> 149:156823d33999 6468 * Offset: 0x90~0xA4 PWM Counter Register 0~5
<> 149:156823d33999 6469 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6470 * |Bits |Field |Descriptions
<> 149:156823d33999 6471 * | :----: | :----: | :---- |
<> 149:156823d33999 6472 * |[15:0] |CNT |PWM Data Register (Read Only)
<> 149:156823d33999 6473 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
<> 149:156823d33999 6474 * |[16] |DIRF |PWM Direction Indicator Flag (Read Only)
<> 149:156823d33999 6475 * | | |0 = Counter is Down count.
<> 149:156823d33999 6476 * | | |1 = Counter is UP count.
<> 149:156823d33999 6477 * @var PWM_T::WGCTL0
<> 149:156823d33999 6478 * Offset: 0xB0 PWM Generation Register 0
<> 149:156823d33999 6479 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6480 * |Bits |Field |Descriptions
<> 149:156823d33999 6481 * | :----: | :----: | :---- |
<> 149:156823d33999 6482 * |[11:0] |ZPCTLn |PWM Zero Point Control
<> 149:156823d33999 6483 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6484 * | | |00 = Do nothing.
<> 149:156823d33999 6485 * | | |01 = PWM zero point output Low.
<> 149:156823d33999 6486 * | | |10 = PWM zero point output High.
<> 149:156823d33999 6487 * | | |11 = PWM zero point output Toggle.
<> 149:156823d33999 6488 * | | |PWM can control output level when PWM counter count to zero.
<> 149:156823d33999 6489 * |[27:16] |PRDPCTLn |PWM Period (Center) Point Control
<> 149:156823d33999 6490 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6491 * | | |00 = Do nothing.
<> 149:156823d33999 6492 * | | |01 = PWM period (center) point output Low.
<> 149:156823d33999 6493 * | | |10 = PWM period (center) point output High.
<> 149:156823d33999 6494 * | | |11 = PWM period (center) point output Toggle.
<> 149:156823d33999 6495 * | | |PWM can control output level when PWM counter count to (PERIODn+1).
<> 149:156823d33999 6496 * | | |Note: This bit is center point control when PWM counter operating in up-down counter type.
<> 149:156823d33999 6497 * @var PWM_T::WGCTL1
<> 149:156823d33999 6498 * Offset: 0xB4 PWM Generation Register 1
<> 149:156823d33999 6499 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6500 * |Bits |Field |Descriptions
<> 149:156823d33999 6501 * | :----: | :----: | :---- |
<> 149:156823d33999 6502 * |[11:0] |CMPUCTLn |PWM Compare Up Point Control
<> 149:156823d33999 6503 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6504 * | | |00 = Do nothing.
<> 149:156823d33999 6505 * | | |01 = PWM compare up point output Low.
<> 149:156823d33999 6506 * | | |10 = PWM compare up point output High.
<> 149:156823d33999 6507 * | | |11 = PWM compare up point output Toggle.
<> 149:156823d33999 6508 * | | |PWM can control output level when PWM counter up count to CMPDAT.
<> 149:156823d33999 6509 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
<> 149:156823d33999 6510 * |[27:16] |CMPDCTLn |PWM Compare Down Point Control
<> 149:156823d33999 6511 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6512 * | | |00 = Do nothing.
<> 149:156823d33999 6513 * | | |01 = PWM compare down point output Low.
<> 149:156823d33999 6514 * | | |10 = PWM compare down point output High.
<> 149:156823d33999 6515 * | | |11 = PWM compare down point output Toggle.
<> 149:156823d33999 6516 * | | |PWM can control output level when PWM counter down count to CMPDAT.
<> 149:156823d33999 6517 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
<> 149:156823d33999 6518 * @var PWM_T::MSKEN
<> 149:156823d33999 6519 * Offset: 0xB8 PWM Mask Enable Register
<> 149:156823d33999 6520 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6521 * |Bits |Field |Descriptions
<> 149:156823d33999 6522 * | :----: | :----: | :---- |
<> 149:156823d33999 6523 * |[5:0] |MSKENn |PWM Mask Enable
<> 149:156823d33999 6524 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6525 * | | |The PWM output signal will be masked when this bit is enabled.
<> 149:156823d33999 6526 * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
<> 149:156823d33999 6527 * | | |0 = PWM output signal is non-masked.
<> 149:156823d33999 6528 * | | |1 = PWM output signal is masked and output MSKDATn data.
<> 149:156823d33999 6529 * @var PWM_T::MSK
<> 149:156823d33999 6530 * Offset: 0xBC PWM Mask Data Register
<> 149:156823d33999 6531 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6532 * |Bits |Field |Descriptions
<> 149:156823d33999 6533 * | :----: | :----: | :---- |
<> 149:156823d33999 6534 * |[5:0] |MSKDATn |PWM Mask Data Bit
<> 149:156823d33999 6535 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
<> 149:156823d33999 6536 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6537 * | | |0 = Output logic low to PWMn.
<> 149:156823d33999 6538 * | | |1 = Output logic high to PWMn.
<> 149:156823d33999 6539 * @var PWM_T::BNF
<> 149:156823d33999 6540 * Offset: 0xC0 PWM Brake Noise Filter Register
<> 149:156823d33999 6541 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6542 * |Bits |Field |Descriptions
<> 149:156823d33999 6543 * | :----: | :----: | :---- |
<> 149:156823d33999 6544 * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable
<> 149:156823d33999 6545 * | | |0 = Noise filter of PWM Brake 0 Disabled.
<> 149:156823d33999 6546 * | | |1 = Noise filter of PWM Brake 0 Enabled.
<> 149:156823d33999 6547 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
<> 149:156823d33999 6548 * | | |000 = Filter clock = HCLK.
<> 149:156823d33999 6549 * | | |001 = Filter clock = HCLK/2.
<> 149:156823d33999 6550 * | | |010 = Filter clock = HCLK/4.
<> 149:156823d33999 6551 * | | |011 = Filter clock = HCLK/8.
<> 149:156823d33999 6552 * | | |100 = Filter clock = HCLK/16.
<> 149:156823d33999 6553 * | | |101 = Filter clock = HCLK/32.
<> 149:156823d33999 6554 * | | |110 = Filter clock = HCLK/64.
<> 149:156823d33999 6555 * | | |111 = Filter clock = HCLK/128.
<> 149:156823d33999 6556 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
<> 149:156823d33999 6557 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
<> 149:156823d33999 6558 * |[7] |BRK0PINV |Brake 0 Pin Inverse
<> 149:156823d33999 6559 * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
<> 149:156823d33999 6560 * | | |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
<> 149:156823d33999 6561 * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable
<> 149:156823d33999 6562 * | | |0 = Noise filter of PWM Brake 1 Disabled.
<> 149:156823d33999 6563 * | | |1 = Noise filter of PWM Brake 1 Enabled.
<> 149:156823d33999 6564 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
<> 149:156823d33999 6565 * | | |000 = Filter clock = HCLK.
<> 149:156823d33999 6566 * | | |001 = Filter clock = HCLK/2.
<> 149:156823d33999 6567 * | | |010 = Filter clock = HCLK/4.
<> 149:156823d33999 6568 * | | |011 = Filter clock = HCLK/8.
<> 149:156823d33999 6569 * | | |100 = Filter clock = HCLK/16.
<> 149:156823d33999 6570 * | | |101 = Filter clock = HCLK/32.
<> 149:156823d33999 6571 * | | |110 = Filter clock = HCLK/64.
<> 149:156823d33999 6572 * | | |111 = Filter clock = HCLK/128.
<> 149:156823d33999 6573 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
<> 149:156823d33999 6574 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
<> 149:156823d33999 6575 * |[15] |BRK1PINV |Brake 1 Pin Inverse
<> 149:156823d33999 6576 * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
<> 149:156823d33999 6577 * | | |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
<> 149:156823d33999 6578 * |[16] |BK0SRC |Brake 0 Pin Source Select (M45xD/M45xC Only)
<> 149:156823d33999 6579 * | | |For PWM0 setting:
<> 149:156823d33999 6580 * | | |0 = Brake 0 pin source come from PWM0_BRAKE0.
<> 149:156823d33999 6581 * | | |1 = Brake 0 pin source come from PWM1_BRAKE0.
<> 149:156823d33999 6582 * | | |For PWM1 setting:
<> 149:156823d33999 6583 * | | |0 = Brake 0 pin source come from PWM1_BRAKE0.
<> 149:156823d33999 6584 * | | |1 = Brake 0 pin source come from PWM0_BRAKE0.
<> 149:156823d33999 6585 * |[24] |BK1SRC |Brake 1 Pin Source Select (M45xD/M45xC Only)
<> 149:156823d33999 6586 * | | |For PWM0 setting:
<> 149:156823d33999 6587 * | | |0 = Brake 1 pin source come from PWM0_BRAKE1.
<> 149:156823d33999 6588 * | | |1 = Brake 1 pin source come from PWM1_BRAKE1.
<> 149:156823d33999 6589 * | | |For PWM1 setting:
<> 149:156823d33999 6590 * | | |0 = Brake 1 pin source come from PWM1_BRAKE1.
<> 149:156823d33999 6591 * | | |1 = Brake 1 pin source come from PWM0_BRAKE1.
<> 149:156823d33999 6592 * @var PWM_T::FAILBRK
<> 149:156823d33999 6593 * Offset: 0xC4 PWM System Fail Brake Control Register
<> 149:156823d33999 6594 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6595 * |Bits |Field |Descriptions
<> 149:156823d33999 6596 * | :----: | :----: | :---- |
<> 149:156823d33999 6597 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable
<> 149:156823d33999 6598 * | | |0 = Brake Function triggered by CSS detection Disabled.
<> 149:156823d33999 6599 * | | |1 = Brake Function triggered by CSS detection Enabled.
<> 149:156823d33999 6600 * |[1] |BODBRKEN |Brown-Out Detection Trigger PWM Brake Function 0 Enable
<> 149:156823d33999 6601 * | | |0 = Brake Function triggered by BOD Disabled.
<> 149:156823d33999 6602 * | | |1 = Brake Function triggered by BOD Enabled.
<> 149:156823d33999 6603 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
<> 149:156823d33999 6604 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
<> 149:156823d33999 6605 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
<> 149:156823d33999 6606 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable
<> 149:156823d33999 6607 * | | |0 = Brake Function triggered by Core lockup detection Disabled.
<> 149:156823d33999 6608 * | | |1 = Brake Function triggered by Core lockup detection Enabled.
<> 149:156823d33999 6609 * @var PWM_T::BRKCTL0_1
<> 149:156823d33999 6610 * Offset: 0xC8 PWM Brake Edge Detect Control Register 0
<> 149:156823d33999 6611 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6612 * |Bits |Field |Descriptions
<> 149:156823d33999 6613 * | :----: | :----: | :---- |
<> 149:156823d33999 6614 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6615 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
<> 149:156823d33999 6616 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
<> 149:156823d33999 6617 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6618 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6619 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
<> 149:156823d33999 6620 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
<> 149:156823d33999 6621 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6622 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6623 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6624 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6625 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6626 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6627 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6628 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6629 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6630 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6631 * | | |0 = System Fail condition as edge-detect brake source Disabled.
<> 149:156823d33999 6632 * | | |1 = System Fail condition as edge-detect brake source Enabled.
<> 149:156823d33999 6633 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6634 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6635 * | | |0 = ACMP0_O as level-detect brake source Disabled.
<> 149:156823d33999 6636 * | | |1 = ACMP0_O as level-detect brake source Enabled.
<> 149:156823d33999 6637 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6638 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6639 * | | |0 = ACMP1_O as level-detect brake source Disabled.
<> 149:156823d33999 6640 * | | |1 = ACMP1_O as level-detect brake source Enabled.
<> 149:156823d33999 6641 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6642 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6643 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
<> 149:156823d33999 6644 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
<> 149:156823d33999 6645 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6646 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6647 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
<> 149:156823d33999 6648 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
<> 149:156823d33999 6649 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6650 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6651 * | | |0 = System Fail condition as level-detect brake source Disabled.
<> 149:156823d33999 6652 * | | |1 = System Fail condition as level-detect brake source Enabled.
<> 149:156823d33999 6653 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6654 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
<> 149:156823d33999 6655 * | | |00 = PWM even channel level-detect brake function not affect channel output.
<> 149:156823d33999 6656 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6657 * | | |10 = PWM even channel output low level when level-detect brake happened.
<> 149:156823d33999 6658 * | | |11 = PWM even channel output high level when level-detect brake happened.
<> 149:156823d33999 6659 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6660 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
<> 149:156823d33999 6661 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
<> 149:156823d33999 6662 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6663 * | | |10 = PWM odd channel output low level when level-detect brake happened.
<> 149:156823d33999 6664 * | | |11 = PWM odd channel output high level when level-detect brake happened.
<> 149:156823d33999 6665 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6666 * @var PWM_T::BRKCTL2_3
<> 149:156823d33999 6667 * Offset: 0xCC PWM Brake Edge Detect Control Register 2
<> 149:156823d33999 6668 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6669 * |Bits |Field |Descriptions
<> 149:156823d33999 6670 * | :----: | :----: | :---- |
<> 149:156823d33999 6671 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6672 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
<> 149:156823d33999 6673 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
<> 149:156823d33999 6674 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6675 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6676 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
<> 149:156823d33999 6677 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
<> 149:156823d33999 6678 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6679 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6680 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6681 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6682 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6683 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6684 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6685 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6686 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6687 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6688 * | | |0 = System Fail condition as edge-detect brake source Disabled.
<> 149:156823d33999 6689 * | | |1 = System Fail condition as edge-detect brake source Enabled.
<> 149:156823d33999 6690 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6691 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6692 * | | |0 = ACMP0_O as level-detect brake source Disabled.
<> 149:156823d33999 6693 * | | |1 = ACMP0_O as level-detect brake source Enabled.
<> 149:156823d33999 6694 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6695 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6696 * | | |0 = ACMP1_O as level-detect brake source Disabled.
<> 149:156823d33999 6697 * | | |1 = ACMP1_O as level-detect brake source Enabled.
<> 149:156823d33999 6698 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6699 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6700 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
<> 149:156823d33999 6701 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
<> 149:156823d33999 6702 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6703 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6704 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
<> 149:156823d33999 6705 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
<> 149:156823d33999 6706 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6707 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6708 * | | |0 = System Fail condition as level-detect brake source Disabled.
<> 149:156823d33999 6709 * | | |1 = System Fail condition as level-detect brake source Enabled.
<> 149:156823d33999 6710 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6711 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
<> 149:156823d33999 6712 * | | |00 = PWM even channel level-detect brake function not affect channel output.
<> 149:156823d33999 6713 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6714 * | | |10 = PWM even channel output low level when level-detect brake happened.
<> 149:156823d33999 6715 * | | |11 = PWM even channel output high level when level-detect brake happened.
<> 149:156823d33999 6716 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6717 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
<> 149:156823d33999 6718 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
<> 149:156823d33999 6719 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6720 * | | |10 = PWM odd channel output low level when level-detect brake happened.
<> 149:156823d33999 6721 * | | |11 = PWM odd channel output high level when level-detect brake happened.
<> 149:156823d33999 6722 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6723 * @var PWM_T::BRKCTL4_5
<> 149:156823d33999 6724 * Offset: 0xD0 PWM Brake Edge Detect Control Register 4
<> 149:156823d33999 6725 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6726 * |Bits |Field |Descriptions
<> 149:156823d33999 6727 * | :----: | :----: | :---- |
<> 149:156823d33999 6728 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6729 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
<> 149:156823d33999 6730 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
<> 149:156823d33999 6731 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6732 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6733 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
<> 149:156823d33999 6734 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
<> 149:156823d33999 6735 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6736 * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6737 * | | |0 = BKP0 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6738 * | | |1 = BKP0 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6739 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6740 * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6741 * | | |0 = BKP1 pin as edge-detect brake source Disabled.
<> 149:156823d33999 6742 * | | |1 = BKP1 pin as edge-detect brake source Enabled.
<> 149:156823d33999 6743 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6744 * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
<> 149:156823d33999 6745 * | | |0 = System Fail condition as edge-detect brake source Disabled.
<> 149:156823d33999 6746 * | | |1 = System Fail condition as edge-detect brake source Enabled.
<> 149:156823d33999 6747 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6748 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6749 * | | |0 = ACMP0_O as level-detect brake source Disabled.
<> 149:156823d33999 6750 * | | |1 = ACMP0_O as level-detect brake source Enabled.
<> 149:156823d33999 6751 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6752 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6753 * | | |0 = ACMP1_O as level-detect brake source Disabled.
<> 149:156823d33999 6754 * | | |1 = ACMP1_O as level-detect brake source Enabled.
<> 149:156823d33999 6755 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6756 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6757 * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
<> 149:156823d33999 6758 * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
<> 149:156823d33999 6759 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6760 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6761 * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
<> 149:156823d33999 6762 * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
<> 149:156823d33999 6763 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6764 * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
<> 149:156823d33999 6765 * | | |0 = System Fail condition as level-detect brake source Disabled.
<> 149:156823d33999 6766 * | | |1 = System Fail condition as level-detect brake source Enabled.
<> 149:156823d33999 6767 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6768 * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
<> 149:156823d33999 6769 * | | |00 = PWM even channel level-detect brake function not affect channel output.
<> 149:156823d33999 6770 * | | |01 = PWM even channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6771 * | | |10 = PWM even channel output low level when level-detect brake happened.
<> 149:156823d33999 6772 * | | |11 = PWM even channel output high level when level-detect brake happened.
<> 149:156823d33999 6773 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6774 * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
<> 149:156823d33999 6775 * | | |00 = PWM odd channel level-detect brake function not affect channel output.
<> 149:156823d33999 6776 * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
<> 149:156823d33999 6777 * | | |10 = PWM odd channel output low level when level-detect brake happened.
<> 149:156823d33999 6778 * | | |11 = PWM odd channel output high level when level-detect brake happened.
<> 149:156823d33999 6779 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6780 * @var PWM_T::POLCTL
<> 149:156823d33999 6781 * Offset: 0xD4 PWM Pin Polar Inverse Register
<> 149:156823d33999 6782 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6783 * |Bits |Field |Descriptions
<> 149:156823d33999 6784 * | :----: | :----: | :---- |
<> 149:156823d33999 6785 * |[5:0] |PINVn |PWM PIN Polar Inverse Control
<> 149:156823d33999 6786 * | | |The register controls polarity state of PWM output.
<> 149:156823d33999 6787 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6788 * | | |0 = PWM output polar inverse Disabled.
<> 149:156823d33999 6789 * | | |1 = PWM output polar inverse Enabled.
<> 149:156823d33999 6790 * @var PWM_T::POEN
<> 149:156823d33999 6791 * Offset: 0xD8 PWM Output Enable Register
<> 149:156823d33999 6792 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6793 * |Bits |Field |Descriptions
<> 149:156823d33999 6794 * | :----: | :----: | :---- |
<> 149:156823d33999 6795 * |[5:0] |POENn |PWM Pin Output Enable
<> 149:156823d33999 6796 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6797 * | | |0 = PWM pin at tri-state.
<> 149:156823d33999 6798 * | | |1 = PWM pin in output mode.
<> 149:156823d33999 6799 * @var PWM_T::SWBRK
<> 149:156823d33999 6800 * Offset: 0xDC PWM Software Brake Control Register
<> 149:156823d33999 6801 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6802 * |Bits |Field |Descriptions
<> 149:156823d33999 6803 * | :----: | :----: | :---- |
<> 149:156823d33999 6804 * |[2:0] |BRKETRGn |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
<> 149:156823d33999 6805 * | | |Each bit n controls the corresponding PWM pair n.
<> 149:156823d33999 6806 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
<> 149:156823d33999 6807 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6808 * |[10:8] |BRKLTRGn |PWM Level Brake Software Trigger (Write Only) (Write Protect)
<> 149:156823d33999 6809 * | | |Each bit n controls the corresponding PWM pair n.
<> 149:156823d33999 6810 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
<> 149:156823d33999 6811 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6812 * @var PWM_T::INTEN0
<> 149:156823d33999 6813 * Offset: 0xE0 PWM Interrupt Enable Register 0
<> 149:156823d33999 6814 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6815 * |Bits |Field |Descriptions
<> 149:156823d33999 6816 * | :----: | :----: | :---- |
<> 149:156823d33999 6817 * |[5:0] |ZIENn |PWM Zero Point Interrupt Enable
<> 149:156823d33999 6818 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6819 * | | |0 = Zero point interrupt Disabled.
<> 149:156823d33999 6820 * | | |1 = Zero point interrupt Enabled.
<> 149:156823d33999 6821 * | | |Note: Odd channels will read always 0 at complementary mode.
<> 149:156823d33999 6822 * |[7] |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
<> 149:156823d33999 6823 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
<> 149:156823d33999 6824 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
<> 149:156823d33999 6825 * |[13:8] |PIENn |PWM Period Point Interrupt Enable
<> 149:156823d33999 6826 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6827 * | | |0 = Period point interrupt Disabled.
<> 149:156823d33999 6828 * | | |1 = Period point interrupt Enabled.
<> 149:156823d33999 6829 * | | |Note1: When up-down counter type period point means center point.
<> 149:156823d33999 6830 * | | |Note2: Odd channels will read always 0 at complementary mode.
<> 149:156823d33999 6831 * |[15] |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
<> 149:156823d33999 6832 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
<> 149:156823d33999 6833 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
<> 149:156823d33999 6834 * |[21:16] |CMPUIENn |PWM Compare Up Count Interrupt Enable
<> 149:156823d33999 6835 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6836 * | | |0 = Compare up count interrupt Disabled.
<> 149:156823d33999 6837 * | | |1 = Compare up count interrupt Enabled.
<> 149:156823d33999 6838 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
<> 149:156823d33999 6839 * |[23] |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
<> 149:156823d33999 6840 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
<> 149:156823d33999 6841 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
<> 149:156823d33999 6842 * |[29:24] |CMPDIENn |PWM Compare Down Count Interrupt Enable
<> 149:156823d33999 6843 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6844 * | | |0 = Compare down count interrupt Disabled.
<> 149:156823d33999 6845 * | | |1 = Compare down count interrupt Enabled.
<> 149:156823d33999 6846 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
<> 149:156823d33999 6847 * @var PWM_T::INTEN1
<> 149:156823d33999 6848 * Offset: 0xE4 PWM Interrupt Enable Register 1
<> 149:156823d33999 6849 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6850 * |Bits |Field |Descriptions
<> 149:156823d33999 6851 * | :----: | :----: | :---- |
<> 149:156823d33999 6852 * |[0] |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
<> 149:156823d33999 6853 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
<> 149:156823d33999 6854 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
<> 149:156823d33999 6855 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6856 * |[1] |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
<> 149:156823d33999 6857 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
<> 149:156823d33999 6858 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
<> 149:156823d33999 6859 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6860 * |[2] |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
<> 149:156823d33999 6861 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
<> 149:156823d33999 6862 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
<> 149:156823d33999 6863 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6864 * |[8] |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
<> 149:156823d33999 6865 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
<> 149:156823d33999 6866 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
<> 149:156823d33999 6867 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6868 * |[9] |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
<> 149:156823d33999 6869 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
<> 149:156823d33999 6870 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
<> 149:156823d33999 6871 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6872 * |[10] |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
<> 149:156823d33999 6873 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
<> 149:156823d33999 6874 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
<> 149:156823d33999 6875 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6876 * @var PWM_T::INTSTS0
<> 149:156823d33999 6877 * Offset: 0xE8 PWM Interrupt Flag Register 0
<> 149:156823d33999 6878 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6879 * |Bits |Field |Descriptions
<> 149:156823d33999 6880 * | :----: | :----: | :---- |
<> 149:156823d33999 6881 * |[5:0] |ZIFn |PWM Zero Point Interrupt Flag
<> 149:156823d33999 6882 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6883 * | | |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
<> 149:156823d33999 6884 * |[7] |IFAIF0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
<> 149:156823d33999 6885 * | | |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
<> 149:156823d33999 6886 * |[13:8] |PIFn |PWM Period Point Interrupt Flag
<> 149:156823d33999 6887 * | | |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
<> 149:156823d33999 6888 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6889 * |[15] |IFAIF2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
<> 149:156823d33999 6890 * | | |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
<> 149:156823d33999 6891 * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag
<> 149:156823d33999 6892 * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
<> 149:156823d33999 6893 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6894 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
<> 149:156823d33999 6895 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
<> 149:156823d33999 6896 * |[23] |IFAIF4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
<> 149:156823d33999 6897 * | | |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
<> 149:156823d33999 6898 * |[29:24] |CMPDIFn |PWM Compare Down Count Interrupt Flag
<> 149:156823d33999 6899 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 6900 * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
<> 149:156823d33999 6901 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
<> 149:156823d33999 6902 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
<> 149:156823d33999 6903 * @var PWM_T::INTSTS1
<> 149:156823d33999 6904 * Offset: 0xEC PWM Interrupt Flag Register 1
<> 149:156823d33999 6905 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 6906 * |Bits |Field |Descriptions
<> 149:156823d33999 6907 * | :----: | :----: | :---- |
<> 149:156823d33999 6908 * |[0] |BRKEIF0 |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6909 * | | |0 = PWM channel0 edge-detect brake event do not happened.
<> 149:156823d33999 6910 * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6911 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6912 * |[1] |BRKEIF1 |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6913 * | | |0 = PWM channel1 edge-detect brake event do not happened.
<> 149:156823d33999 6914 * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6915 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6916 * |[2] |BRKEIF2 |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6917 * | | |0 = PWM channel2 edge-detect brake event do not happened.
<> 149:156823d33999 6918 * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6919 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6920 * |[3] |BRKEIF3 |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6921 * | | |0 = PWM channel3 edge-detect brake event do not happened.
<> 149:156823d33999 6922 * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6923 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6924 * |[4] |BRKEIF4 |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6925 * | | |0 = PWM channel4 edge-detect brake event do not happened.
<> 149:156823d33999 6926 * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6927 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6928 * |[5] |BRKEIF5 |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6929 * | | |0 = PWM channel5 edge-detect brake event do not happened.
<> 149:156823d33999 6930 * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6931 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6932 * |[8] |BRKLIF0 |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6933 * | | |0 = PWM channel0 level-detect brake event do not happened.
<> 149:156823d33999 6934 * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6935 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6936 * |[9] |BRKLIF1 |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6937 * | | |0 = PWM channel1 level-detect brake event do not happened.
<> 149:156823d33999 6938 * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6939 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6940 * |[10] |BRKLIF2 |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6941 * | | |0 = PWM channel2 level-detect brake event do not happened.
<> 149:156823d33999 6942 * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6943 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6944 * |[11] |BRKLIF3 |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6945 * | | |0 = PWM channel3 level-detect brake event do not happened.
<> 149:156823d33999 6946 * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6947 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6948 * |[12] |BRKLIF4 |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6949 * | | |0 = PWM channel4 level-detect brake event do not happened.
<> 149:156823d33999 6950 * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6951 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6952 * |[13] |BRKLIF5 |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
<> 149:156823d33999 6953 * | | |0 = PWM channel5 level-detect brake event do not happened.
<> 149:156823d33999 6954 * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
<> 149:156823d33999 6955 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
<> 149:156823d33999 6956 * |[16] |BRKESTS0 |PWM Channel0 Edge-Detect Brake Status
<> 149:156823d33999 6957 * | | |0 = PWM channel0 edge-detect brake state is released.
<> 149:156823d33999 6958 * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
<> 149:156823d33999 6959 * |[17] |BRKESTS1 |PWM Channel1 Edge-Detect Brake Status
<> 149:156823d33999 6960 * | | |0 = PWM channel1 edge-detect brake state is released.
<> 149:156823d33999 6961 * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
<> 149:156823d33999 6962 * |[18] |BRKESTS2 |PWM Channel2 Edge-Detect Brake Status
<> 149:156823d33999 6963 * | | |0 = PWM channel2 edge-detect brake state is released.
<> 149:156823d33999 6964 * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
<> 149:156823d33999 6965 * |[19] |BRKESTS3 |PWM Channel3 Edge-Detect Brake Status
<> 149:156823d33999 6966 * | | |0 = PWM channel3 edge-detect brake state is released.
<> 149:156823d33999 6967 * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
<> 149:156823d33999 6968 * |[20] |BRKESTS4 |PWM Channel4 Edge-Detect Brake Status
<> 149:156823d33999 6969 * | | |0 = PWM channel4 edge-detect brake state is released.
<> 149:156823d33999 6970 * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
<> 149:156823d33999 6971 * |[21] |BRKESTS5 |PWM Channel5 Edge-Detect Brake Status
<> 149:156823d33999 6972 * | | |0 = PWM channel5 edge-detect brake state is released.
<> 149:156823d33999 6973 * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
<> 149:156823d33999 6974 * |[24] |BRKLSTS0 |PWM Channel0 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 6975 * | | |0 = PWM channel0 level-detect brake state is released.
<> 149:156823d33999 6976 * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
<> 149:156823d33999 6977 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 6978 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 6979 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 6980 * |[25] |BRKLSTS1 |PWM Channel1 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 6981 * | | |0 = PWM channel1 level-detect brake state is released.
<> 149:156823d33999 6982 * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
<> 149:156823d33999 6983 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 6984 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 6985 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 6986 * |[26] |BRKLSTS2 |PWM Channel2 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 6987 * | | |0 = PWM channel2 level-detect brake state is released.
<> 149:156823d33999 6988 * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
<> 149:156823d33999 6989 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 6990 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 6991 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 6992 * |[27] |BRKLSTS3 |PWM Channel3 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 6993 * | | |0 = PWM channel3 level-detect brake state is released.
<> 149:156823d33999 6994 * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
<> 149:156823d33999 6995 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 6996 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 6997 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 6998 * |[28] |BRKLSTS4 |PWM Channel4 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 6999 * | | |0 = PWM channel4 level-detect brake state is released.
<> 149:156823d33999 7000 * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
<> 149:156823d33999 7001 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 7002 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 7003 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 7004 * |[29] |BRKLSTS5 |PWM Channel5 Level-Detect Brake Status (Read Only)
<> 149:156823d33999 7005 * | | |0 = PWM channel5 level-detect brake state is released.
<> 149:156823d33999 7006 * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
<> 149:156823d33999 7007 * | | |Note: This bit is read only and auto cleared by hardware.
<> 149:156823d33999 7008 * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
<> 149:156823d33999 7009 * | | |The PWM waveform will start output from next full PWM period.
<> 149:156823d33999 7010 * @var PWM_T::IFA
<> 149:156823d33999 7011 * Offset: 0xF0 PWM Interrupt Flag Accumulator Register
<> 149:156823d33999 7012 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7013 * |Bits |Field |Descriptions
<> 149:156823d33999 7014 * | :----: | :----: | :---- |
<> 149:156823d33999 7015 * |[3:0] |IFCNT0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
<> 149:156823d33999 7016 * | | |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
<> 149:156823d33999 7017 * | | |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
<> 149:156823d33999 7018 * |[6:4] |IFSEL0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
<> 149:156823d33999 7019 * | | |000 = CNT equal to Zero in channel 0.
<> 149:156823d33999 7020 * | | |001 = CNT equal to PERIOD in channel 0.
<> 149:156823d33999 7021 * | | |010 = CNT equal to CMPU in channel 0.
<> 149:156823d33999 7022 * | | |011 = CNT equal to CMPD in channel 0.
<> 149:156823d33999 7023 * | | |100 = CNT equal to Zero in channel 1.
<> 149:156823d33999 7024 * | | |101 = CNT equal to PERIOD in channel 1.
<> 149:156823d33999 7025 * | | |110 = CNT equal to CMPU in channel 1.
<> 149:156823d33999 7026 * | | |111 = CNT equal to CMPD in channel 1.
<> 149:156823d33999 7027 * |[7] |IFAEN0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
<> 149:156823d33999 7028 * | | |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
<> 149:156823d33999 7029 * | | |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
<> 149:156823d33999 7030 * |[11:8] |IFCNT2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
<> 149:156823d33999 7031 * | | |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
<> 149:156823d33999 7032 * | | |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
<> 149:156823d33999 7033 * |[14:12] |IFSEL2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
<> 149:156823d33999 7034 * | | |000 = CNT equal to Zero in channel 2.
<> 149:156823d33999 7035 * | | |001 = CNT equal to PERIOD in channel 2.
<> 149:156823d33999 7036 * | | |010 = CNT equal to CMPU in channel 2.
<> 149:156823d33999 7037 * | | |011 = CNT equal to CMPD in channel 2.
<> 149:156823d33999 7038 * | | |100 = CNT equal to Zero in channel 3.
<> 149:156823d33999 7039 * | | |101 = CNT equal to PERIOD in channel 3.
<> 149:156823d33999 7040 * | | |110 = CNT equal to CMPU in channel 3.
<> 149:156823d33999 7041 * | | |111 = CNT equal to CMPD in channel 3.
<> 149:156823d33999 7042 * |[15] |IFAEN2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
<> 149:156823d33999 7043 * | | |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
<> 149:156823d33999 7044 * | | |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
<> 149:156823d33999 7045 * |[19:16] |IFCNT4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
<> 149:156823d33999 7046 * | | |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
<> 149:156823d33999 7047 * | | |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
<> 149:156823d33999 7048 * |[22:20] |IFSEL4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
<> 149:156823d33999 7049 * | | |000 = CNT equal to Zero in channel 4.
<> 149:156823d33999 7050 * | | |001 = CNT equal to PERIOD in channel 4.
<> 149:156823d33999 7051 * | | |010 = CNT equal to CMPU in channel 4.
<> 149:156823d33999 7052 * | | |011 = CNT equal to CMPD in channel 4.
<> 149:156823d33999 7053 * | | |100 = CNT equal to Zero in channel 5.
<> 149:156823d33999 7054 * | | |101 = CNT equal to PERIOD in channel 5.
<> 149:156823d33999 7055 * | | |110 = CNT equal to CMPU in channel 5.
<> 149:156823d33999 7056 * | | |111 = CNT equal to CMPD in channel 5.
<> 149:156823d33999 7057 * |[23] |IFAEN4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
<> 149:156823d33999 7058 * | | |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
<> 149:156823d33999 7059 * | | |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
<> 149:156823d33999 7060 * @var PWM_T::DACTRGEN
<> 149:156823d33999 7061 * Offset: 0xF4 PWM Trigger DAC Enable Register
<> 149:156823d33999 7062 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7063 * |Bits |Field |Descriptions
<> 149:156823d33999 7064 * | :----: | :----: | :---- |
<> 149:156823d33999 7065 * |[5:0] |ZTEn |PWM Zero Point Trigger DAC Enable
<> 149:156823d33999 7066 * | | |0 = PWM period point trigger DAC function Disabled.
<> 149:156823d33999 7067 * | | |1 = PWM period point trigger DAC function Enabled.
<> 149:156823d33999 7068 * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
<> 149:156823d33999 7069 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7070 * |[13:8] |PTEn |PWM Period Point Trigger DAC Enable
<> 149:156823d33999 7071 * | | |0 = PWM period point trigger DAC function Disabled.
<> 149:156823d33999 7072 * | | |1 = PWM period point trigger DAC function Enabled.
<> 149:156823d33999 7073 * | | |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
<> 149:156823d33999 7074 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7075 * |[21:16] |CUTRGEn |PWM Compare Up Count Point Trigger DAC Enable
<> 149:156823d33999 7076 * | | |0 = PWM Compare Up point trigger DAC function Disabled.
<> 149:156823d33999 7077 * | | |1 = PWM Compare Up point trigger DAC function Enabled.
<> 149:156823d33999 7078 * | | |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
<> 149:156823d33999 7079 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7080 * | | |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
<> 149:156823d33999 7081 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
<> 149:156823d33999 7082 * |[29:24] |CDTRGEn |PWM Compare Down Count Point Trigger DAC Enable
<> 149:156823d33999 7083 * | | |0 = PWM Compare Down count point trigger DAC function Disabled.
<> 149:156823d33999 7084 * | | |1 = PWM Compare Down count point trigger DAC function Enabled.
<> 149:156823d33999 7085 * | | |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
<> 149:156823d33999 7086 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7087 * | | |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
<> 149:156823d33999 7088 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
<> 149:156823d33999 7089 * @var PWM_T::EADCTS0
<> 149:156823d33999 7090 * Offset: 0xF8 PWM Trigger EADC Source Select Register 0
<> 149:156823d33999 7091 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7092 * |Bits |Field |Descriptions
<> 149:156823d33999 7093 * | :----: | :----: | :---- |
<> 149:156823d33999 7094 * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select
<> 149:156823d33999 7095 * | | |0000 = PWM_CH0 zero point.
<> 149:156823d33999 7096 * | | |0001 = PWM_CH0 period point.
<> 149:156823d33999 7097 * | | |0010 = PWM_CH0 zero or period point.
<> 149:156823d33999 7098 * | | |0011 = PWM_CH0 up-count CMPDAT point.
<> 149:156823d33999 7099 * | | |0100 = PWM_CH0 down-count CMPDAT point.
<> 149:156823d33999 7100 * | | |0101 = PWM_CH1 zero point.
<> 149:156823d33999 7101 * | | |0110 = PWM_CH1 period point.
<> 149:156823d33999 7102 * | | |0111 = PWM_CH1 zero or period point.
<> 149:156823d33999 7103 * | | |1000 = PWM_CH1 up-count CMPDAT point.
<> 149:156823d33999 7104 * | | |1001 = PWM_CH1 down-count CMPDAT point.
<> 149:156823d33999 7105 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7106 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7107 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7108 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7109 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7110 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7111 * |[7] |TRGEN0 |PWM_CH0 Trigger EADC enable bit
<> 149:156823d33999 7112 * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select
<> 149:156823d33999 7113 * | | |0000 = PWM_CH0 zero point.
<> 149:156823d33999 7114 * | | |0001 = PWM_CH0 period point.
<> 149:156823d33999 7115 * | | |0010 = PWM_CH0 zero or period point.
<> 149:156823d33999 7116 * | | |0011 = PWM_CH0 up-count CMPDAT point.
<> 149:156823d33999 7117 * | | |0100 = PWM_CH0 down-count CMPDAT point.
<> 149:156823d33999 7118 * | | |0101 = PWM_CH1 zero point.
<> 149:156823d33999 7119 * | | |0110 = PWM_CH1 period point.
<> 149:156823d33999 7120 * | | |0111 = PWM_CH1 zero or period point.
<> 149:156823d33999 7121 * | | |1000 = PWM_CH1 up-count CMPDAT point.
<> 149:156823d33999 7122 * | | |1001 = PWM_CH1 down-count CMPDAT point.
<> 149:156823d33999 7123 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7124 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7125 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7126 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7127 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7128 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7129 * |[15] |TRGEN1 |PWM_CH1 Trigger EADC enable bit
<> 149:156823d33999 7130 * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select
<> 149:156823d33999 7131 * | | |0000 = PWM_CH2 zero point.
<> 149:156823d33999 7132 * | | |0001 = PWM_CH2 period point.
<> 149:156823d33999 7133 * | | |0010 = PWM_CH2 zero or period point.
<> 149:156823d33999 7134 * | | |0011 = PWM_CH2 up-count CMPDAT point.
<> 149:156823d33999 7135 * | | |0100 = PWM_CH2 down-count CMPDAT point.
<> 149:156823d33999 7136 * | | |0101 = PWM_CH3 zero point.
<> 149:156823d33999 7137 * | | |0110 = PWM_CH3 period point.
<> 149:156823d33999 7138 * | | |0111 = PWM_CH3 zero or period point.
<> 149:156823d33999 7139 * | | |1000 = PWM_CH3 up-count CMPDAT point.
<> 149:156823d33999 7140 * | | |1001 = PWM_CH3 down-count CMPDAT point.
<> 149:156823d33999 7141 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7142 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7143 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7144 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7145 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7146 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7147 * |[23] |TRGEN2 |PWM_CH2 Trigger EADC enable bit
<> 149:156823d33999 7148 * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select
<> 149:156823d33999 7149 * | | |0000 = PWM_CH2 zero point.
<> 149:156823d33999 7150 * | | |0001 = PWM_CH2 period point.
<> 149:156823d33999 7151 * | | |0010 = PWM_CH2 zero or period point.
<> 149:156823d33999 7152 * | | |0011 = PWM_CH2 up-count CMPDAT point.
<> 149:156823d33999 7153 * | | |0100 = PWM_CH2 down-count CMPDAT point.
<> 149:156823d33999 7154 * | | |0101 = PWM_CH3 zero point.
<> 149:156823d33999 7155 * | | |0110 = PWM_CH3 period point.
<> 149:156823d33999 7156 * | | |0111 = PWM_CH3 zero or period point.
<> 149:156823d33999 7157 * | | |1000 = PWM_CH3 up-count CMPDAT point.
<> 149:156823d33999 7158 * | | |1001 = PWM_CH3 down-count CMPDAT point.
<> 149:156823d33999 7159 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7160 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7161 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7162 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7163 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7164 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7165 * |[31] |TRGEN3 |PWM_CH3 Trigger EADC enable bit
<> 149:156823d33999 7166 * @var PWM_T::EADCTS1
<> 149:156823d33999 7167 * Offset: 0xFC PWM Trigger EADC Source Select Register 1
<> 149:156823d33999 7168 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7169 * |Bits |Field |Descriptions
<> 149:156823d33999 7170 * | :----: | :----: | :---- |
<> 149:156823d33999 7171 * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select
<> 149:156823d33999 7172 * | | |0000 = PWM_CH4 zero point.
<> 149:156823d33999 7173 * | | |0001 = PWM_CH4 period point.
<> 149:156823d33999 7174 * | | |0010 = PWM_CH4 zero or period point.
<> 149:156823d33999 7175 * | | |0011 = PWM_CH4 up-count CMPDAT point.
<> 149:156823d33999 7176 * | | |0100 = PWM_CH4 down-count CMPDAT point.
<> 149:156823d33999 7177 * | | |0101 = PWM_CH5 zero point.
<> 149:156823d33999 7178 * | | |0110 = PWM_CH5 period point.
<> 149:156823d33999 7179 * | | |0111 = PWM_CH5 zero or period point.
<> 149:156823d33999 7180 * | | |1000 = PWM_CH5 up-count CMPDAT point.
<> 149:156823d33999 7181 * | | |1001 = PWM_CH5 down-count CMPDAT point.
<> 149:156823d33999 7182 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7183 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7184 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7185 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7186 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7187 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7188 * |[7] |TRGEN4 |PWM_CH4 Trigger EADC enable bit
<> 149:156823d33999 7189 * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select
<> 149:156823d33999 7190 * | | |0000 = PWM_CH4 zero point.
<> 149:156823d33999 7191 * | | |0001 = PWM_CH4 period point.
<> 149:156823d33999 7192 * | | |0010 = PWM_CH4 zero or period point.
<> 149:156823d33999 7193 * | | |0011 = PWM_CH4 up-count CMPDAT point.
<> 149:156823d33999 7194 * | | |0100 = PWM_CH4 down-count CMPDAT point.
<> 149:156823d33999 7195 * | | |0101 = PWM_CH5 zero point.
<> 149:156823d33999 7196 * | | |0110 = PWM_CH5 period point.
<> 149:156823d33999 7197 * | | |0111 = PWM_CH5 zero or period point.
<> 149:156823d33999 7198 * | | |1000 = PWM_CH5 up-count CMPDAT point.
<> 149:156823d33999 7199 * | | |1001 = PWM_CH5 down-count CMPDAT point.
<> 149:156823d33999 7200 * | | |1010 = PWM_CH0 up-count free CMPDAT point.
<> 149:156823d33999 7201 * | | |1011 = PWM_CH0 down-count free CMPDAT point.
<> 149:156823d33999 7202 * | | |1100 = PWM_CH2 up-count free CMPDAT point.
<> 149:156823d33999 7203 * | | |1101 = PWM_CH2 down-count free CMPDAT point.
<> 149:156823d33999 7204 * | | |1110 = PWM_CH4 up-count free CMPDAT point.
<> 149:156823d33999 7205 * | | |1111 = PWM_CH4 down-count free CMPDAT point.
<> 149:156823d33999 7206 * |[15] |TRGEN5 |PWM_CH5 Trigger EADC enable bit
<> 149:156823d33999 7207 * @var PWM_T::FTCMPDAT0_1
<> 149:156823d33999 7208 * Offset: 0x100 PWM Free Trigger Compare Register 0
<> 149:156823d33999 7209 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7210 * |Bits |Field |Descriptions
<> 149:156823d33999 7211 * | :----: | :----: | :---- |
<> 149:156823d33999 7212 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
<> 149:156823d33999 7213 * | | |FTCMP use to compare with even CNTR to trigger EADC.
<> 149:156823d33999 7214 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
<> 149:156823d33999 7215 * @var PWM_T::FTCMPDAT2_3
<> 149:156823d33999 7216 * Offset: 0x104 PWM Free Trigger Compare Register 2
<> 149:156823d33999 7217 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7218 * |Bits |Field |Descriptions
<> 149:156823d33999 7219 * | :----: | :----: | :---- |
<> 149:156823d33999 7220 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
<> 149:156823d33999 7221 * | | |FTCMP use to compare with even CNTR to trigger EADC.
<> 149:156823d33999 7222 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
<> 149:156823d33999 7223 * @var PWM_T::FTCMPDAT4_5
<> 149:156823d33999 7224 * Offset: 0x108 PWM Free Trigger Compare Register 4
<> 149:156823d33999 7225 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7226 * |Bits |Field |Descriptions
<> 149:156823d33999 7227 * | :----: | :----: | :---- |
<> 149:156823d33999 7228 * |[15:0] |FTCMP |PWM Free Trigger Compare Register
<> 149:156823d33999 7229 * | | |FTCMP use to compare with even CNTR to trigger EADC.
<> 149:156823d33999 7230 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
<> 149:156823d33999 7231 * @var PWM_T::SSCTL
<> 149:156823d33999 7232 * Offset: 0x110 PWM Synchronous Start Control Register
<> 149:156823d33999 7233 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7234 * |Bits |Field |Descriptions
<> 149:156823d33999 7235 * | :----: | :----: | :---- |
<> 149:156823d33999 7236 * |[5:0] |SSENn |PWM Synchronous Start Function Enable
<> 149:156823d33999 7237 * | | |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
<> 149:156823d33999 7238 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7239 * | | |0 = PWM synchronous start function Disabled.
<> 149:156823d33999 7240 * | | |1 = PWM synchronous start function Enabled.
<> 149:156823d33999 7241 * @var PWM_T::SSTRG
<> 149:156823d33999 7242 * Offset: 0x114 PWM Synchronous Start Trigger Register
<> 149:156823d33999 7243 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7244 * |Bits |Field |Descriptions
<> 149:156823d33999 7245 * | :----: | :----: | :---- |
<> 149:156823d33999 7246 * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only)
<> 149:156823d33999 7247 * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
<> 149:156823d33999 7248 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
<> 149:156823d33999 7249 * | | |Note: This bit only present in PWM0_BA.
<> 149:156823d33999 7250 * @var PWM_T::STATUS
<> 149:156823d33999 7251 * Offset: 0x120 PWM Status Register
<> 149:156823d33999 7252 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7253 * |Bits |Field |Descriptions
<> 149:156823d33999 7254 * | :----: | :----: | :---- |
<> 149:156823d33999 7255 * |[5:0] |CNTMAXFn |Time-Base Counter Equal To 0xFFFF Latched Flag
<> 149:156823d33999 7256 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7257 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
<> 149:156823d33999 7258 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
<> 149:156823d33999 7259 * |[10:8] |SYNCINFn |Input Synchronization Latched Flag
<> 149:156823d33999 7260 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7261 * | | |0 = Indicates no SYNC_IN event has occurred.
<> 149:156823d33999 7262 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
<> 149:156823d33999 7263 * |[21:16] |ADCTRGFn |EADC Start Of Conversion Flag
<> 149:156823d33999 7264 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7265 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
<> 149:156823d33999 7266 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
<> 149:156823d33999 7267 * |[24] |DACTRGF |DAC Start Of Conversion Flag
<> 149:156823d33999 7268 * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
<> 149:156823d33999 7269 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
<> 149:156823d33999 7270 * @var PWM_T::CAPINEN
<> 149:156823d33999 7271 * Offset: 0x200 PWM Capture Input Enable Register
<> 149:156823d33999 7272 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7273 * |Bits |Field |Descriptions
<> 149:156823d33999 7274 * | :----: | :----: | :---- |
<> 149:156823d33999 7275 * |[5:0] |CAPINENn |Capture Input Enable
<> 149:156823d33999 7276 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7277 * | | |0 = PWM Channel capture input path Disabled.
<> 149:156823d33999 7278 * | | |The input of PWM channel capture function is always regarded as 0.
<> 149:156823d33999 7279 * | | |1 = PWM Channel capture input path Enabled.
<> 149:156823d33999 7280 * | | |The input of PWM channel capture function comes from correlative multifunction pin.
<> 149:156823d33999 7281 * @var PWM_T::CAPCTL
<> 149:156823d33999 7282 * Offset: 0x204 PWM Capture Control Register
<> 149:156823d33999 7283 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7284 * |Bits |Field |Descriptions
<> 149:156823d33999 7285 * | :----: | :----: | :---- |
<> 149:156823d33999 7286 * |[5:0] |CAPENn |Capture Function Enable
<> 149:156823d33999 7287 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7288 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
<> 149:156823d33999 7289 * | | |1 = Capture function Enabled.
<> 149:156823d33999 7290 * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
<> 149:156823d33999 7291 * |[13:8] |CAPINVn |Capture Inverter Enable
<> 149:156823d33999 7292 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7293 * | | |0 = Capture source inverter Disabled.
<> 149:156823d33999 7294 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
<> 149:156823d33999 7295 * |[21:16] |RCRLDENn |Rising Capture Reload Enable
<> 149:156823d33999 7296 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7297 * | | |0 = Rising capture reload counter Disabled.
<> 149:156823d33999 7298 * | | |1 = Rising capture reload counter Enabled.
<> 149:156823d33999 7299 * |[29:24] |FCRLDENn |Falling Capture Reload Enable
<> 149:156823d33999 7300 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7301 * | | |0 = Falling capture reload counter Disabled.
<> 149:156823d33999 7302 * | | |1 = Falling capture reload counter Enabled.
<> 149:156823d33999 7303 * @var PWM_T::CAPSTS
<> 149:156823d33999 7304 * Offset: 0x208 PWM Capture Status Register
<> 149:156823d33999 7305 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7306 * |Bits |Field |Descriptions
<> 149:156823d33999 7307 * | :----: | :----: | :---- |
<> 149:156823d33999 7308 * |[5:0] |CRLIFOVn |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
<> 149:156823d33999 7309 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
<> 149:156823d33999 7310 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7311 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
<> 149:156823d33999 7312 * |[13:8] |CFLIFOVn |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
<> 149:156823d33999 7313 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
<> 149:156823d33999 7314 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7315 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
<> 149:156823d33999 7316 * @var PWM_T::RCAPDAT0
<> 149:156823d33999 7317 * Offset: 0x20C PWM Rising Capture Data Register 0
<> 149:156823d33999 7318 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7319 * |Bits |Field |Descriptions
<> 149:156823d33999 7320 * | :----: | :----: | :---- |
<> 149:156823d33999 7321 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7322 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7323 * @var PWM_T::FCAPDAT0
<> 149:156823d33999 7324 * Offset: 0x210 PWM Falling Capture Data Register 0
<> 149:156823d33999 7325 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7326 * |Bits |Field |Descriptions
<> 149:156823d33999 7327 * | :----: | :----: | :---- |
<> 149:156823d33999 7328 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7329 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7330 * @var PWM_T::RCAPDAT1
<> 149:156823d33999 7331 * Offset: 0x214 PWM Rising Capture Data Register 1
<> 149:156823d33999 7332 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7333 * |Bits |Field |Descriptions
<> 149:156823d33999 7334 * | :----: | :----: | :---- |
<> 149:156823d33999 7335 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7336 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7337 * @var PWM_T::FCAPDAT1
<> 149:156823d33999 7338 * Offset: 0x218 PWM Falling Capture Data Register 1
<> 149:156823d33999 7339 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7340 * |Bits |Field |Descriptions
<> 149:156823d33999 7341 * | :----: | :----: | :---- |
<> 149:156823d33999 7342 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7343 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7344 * @var PWM_T::RCAPDAT2
<> 149:156823d33999 7345 * Offset: 0x21C PWM Rising Capture Data Register 2
<> 149:156823d33999 7346 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7347 * |Bits |Field |Descriptions
<> 149:156823d33999 7348 * | :----: | :----: | :---- |
<> 149:156823d33999 7349 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7350 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7351 * @var PWM_T::FCAPDAT2
<> 149:156823d33999 7352 * Offset: 0x220 PWM Falling Capture Data Register 2
<> 149:156823d33999 7353 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7354 * |Bits |Field |Descriptions
<> 149:156823d33999 7355 * | :----: | :----: | :---- |
<> 149:156823d33999 7356 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7357 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7358 * @var PWM_T::RCAPDAT3
<> 149:156823d33999 7359 * Offset: 0x224 PWM Rising Capture Data Register 3
<> 149:156823d33999 7360 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7361 * |Bits |Field |Descriptions
<> 149:156823d33999 7362 * | :----: | :----: | :---- |
<> 149:156823d33999 7363 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7364 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7365 * @var PWM_T::FCAPDAT3
<> 149:156823d33999 7366 * Offset: 0x228 PWM Falling Capture Data Register 3
<> 149:156823d33999 7367 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7368 * |Bits |Field |Descriptions
<> 149:156823d33999 7369 * | :----: | :----: | :---- |
<> 149:156823d33999 7370 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7371 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7372 * @var PWM_T::RCAPDAT4
<> 149:156823d33999 7373 * Offset: 0x22C PWM Rising Capture Data Register 4
<> 149:156823d33999 7374 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7375 * |Bits |Field |Descriptions
<> 149:156823d33999 7376 * | :----: | :----: | :---- |
<> 149:156823d33999 7377 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7378 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7379 * @var PWM_T::FCAPDAT4
<> 149:156823d33999 7380 * Offset: 0x230 PWM Falling Capture Data Register 4
<> 149:156823d33999 7381 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7382 * |Bits |Field |Descriptions
<> 149:156823d33999 7383 * | :----: | :----: | :---- |
<> 149:156823d33999 7384 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7385 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7386 * @var PWM_T::RCAPDAT5
<> 149:156823d33999 7387 * Offset: 0x234 PWM Rising Capture Data Register 5
<> 149:156823d33999 7388 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7389 * |Bits |Field |Descriptions
<> 149:156823d33999 7390 * | :----: | :----: | :---- |
<> 149:156823d33999 7391 * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
<> 149:156823d33999 7392 * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7393 * @var PWM_T::FCAPDAT5
<> 149:156823d33999 7394 * Offset: 0x238 PWM Falling Capture Data Register 5
<> 149:156823d33999 7395 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7396 * |Bits |Field |Descriptions
<> 149:156823d33999 7397 * | :----: | :----: | :---- |
<> 149:156823d33999 7398 * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
<> 149:156823d33999 7399 * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
<> 149:156823d33999 7400 * @var PWM_T::PDMACTL
<> 149:156823d33999 7401 * Offset: 0x23C PWM PDMA Control Register
<> 149:156823d33999 7402 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7403 * |Bits |Field |Descriptions
<> 149:156823d33999 7404 * | :----: | :----: | :---- |
<> 149:156823d33999 7405 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
<> 149:156823d33999 7406 * | | |0 = Channel 0/1 PDMA function Disabled.
<> 149:156823d33999 7407 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
<> 149:156823d33999 7408 * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
<> 149:156823d33999 7409 * | | |00 = Reserved.
<> 149:156823d33999 7410 * | | |01 = PWM_RCAPDAT0/1.
<> 149:156823d33999 7411 * | | |10 = PWM_FCAPDAT0/1.
<> 149:156823d33999 7412 * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
<> 149:156823d33999 7413 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
<> 149:156823d33999 7414 * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
<> 149:156823d33999 7415 * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
<> 149:156823d33999 7416 * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
<> 149:156823d33999 7417 * |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer
<> 149:156823d33999 7418 * | | |0 = Channel0.
<> 149:156823d33999 7419 * | | |1 = Channel1.
<> 149:156823d33999 7420 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
<> 149:156823d33999 7421 * | | |0 = Channel 2/3 PDMA function Disabled.
<> 149:156823d33999 7422 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
<> 149:156823d33999 7423 * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
<> 149:156823d33999 7424 * | | |00 = Reserved.
<> 149:156823d33999 7425 * | | |01 = PWM_RCAPDAT2/3.
<> 149:156823d33999 7426 * | | |10 = PWM_FCAPDAT2/3.
<> 149:156823d33999 7427 * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
<> 149:156823d33999 7428 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
<> 149:156823d33999 7429 * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
<> 149:156823d33999 7430 * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
<> 149:156823d33999 7431 * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
<> 149:156823d33999 7432 * |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer
<> 149:156823d33999 7433 * | | |0 = Channel2.
<> 149:156823d33999 7434 * | | |1 = Channel3.
<> 149:156823d33999 7435 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
<> 149:156823d33999 7436 * | | |0 = Channel 4/5 PDMA function Disabled.
<> 149:156823d33999 7437 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
<> 149:156823d33999 7438 * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
<> 149:156823d33999 7439 * | | |00 = Reserved.
<> 149:156823d33999 7440 * | | |01 = PWM_RCAPDAT4/5.
<> 149:156823d33999 7441 * | | |10 = PWM_FCAPDAT4/5.
<> 149:156823d33999 7442 * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
<> 149:156823d33999 7443 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
<> 149:156823d33999 7444 * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
<> 149:156823d33999 7445 * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
<> 149:156823d33999 7446 * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
<> 149:156823d33999 7447 * |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer
<> 149:156823d33999 7448 * | | |0 = Channel4.
<> 149:156823d33999 7449 * | | |1 = Channel5.
<> 149:156823d33999 7450 * @var PWM_T::PDMACAP0_1
<> 149:156823d33999 7451 * Offset: 0x240 PWM Capture Channel 01 PDMA Register
<> 149:156823d33999 7452 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7453 * |Bits |Field |Descriptions
<> 149:156823d33999 7454 * | :----: | :----: | :---- |
<> 149:156823d33999 7455 * |[15:0] |CAPBUF |PWM Capture PDMA Register
<> 149:156823d33999 7456 * | | |(Read Only)
<> 149:156823d33999 7457 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
<> 149:156823d33999 7458 * @var PWM_T::PDMACAP2_3
<> 149:156823d33999 7459 * Offset: 0x244 PWM Capture Channel 23 PDMA Register
<> 149:156823d33999 7460 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7461 * |Bits |Field |Descriptions
<> 149:156823d33999 7462 * | :----: | :----: | :---- |
<> 149:156823d33999 7463 * |[15:0] |CAPBUF |PWM Capture PDMA Register
<> 149:156823d33999 7464 * | | |(Read Only)
<> 149:156823d33999 7465 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
<> 149:156823d33999 7466 * @var PWM_T::PDMACAP4_5
<> 149:156823d33999 7467 * Offset: 0x248 PWM Capture Channel 45 PDMA Register
<> 149:156823d33999 7468 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7469 * |Bits |Field |Descriptions
<> 149:156823d33999 7470 * | :----: | :----: | :---- |
<> 149:156823d33999 7471 * |[15:0] |CAPBUF |PWM Capture PDMA Register
<> 149:156823d33999 7472 * | | |(Read Only)
<> 149:156823d33999 7473 * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
<> 149:156823d33999 7474 * @var PWM_T::CAPIEN
<> 149:156823d33999 7475 * Offset: 0x250 PWM Capture Interrupt Enable Register
<> 149:156823d33999 7476 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7477 * |Bits |Field |Descriptions
<> 149:156823d33999 7478 * | :----: | :----: | :---- |
<> 149:156823d33999 7479 * |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable
<> 149:156823d33999 7480 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7481 * | | |0 = Capture rising edge latch interrupt Disabled.
<> 149:156823d33999 7482 * | | |1 = Capture rising edge latch interrupt Enabled.
<> 149:156823d33999 7483 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
<> 149:156823d33999 7484 * |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable
<> 149:156823d33999 7485 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7486 * | | |0 = Capture falling edge latch interrupt Disabled.
<> 149:156823d33999 7487 * | | |1 = Capture falling edge latch interrupt Enabled.
<> 149:156823d33999 7488 * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
<> 149:156823d33999 7489 * @var PWM_T::CAPIF
<> 149:156823d33999 7490 * Offset: 0x254 PWM Capture Interrupt Flag Register
<> 149:156823d33999 7491 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7492 * |Bits |Field |Descriptions
<> 149:156823d33999 7493 * | :----: | :----: | :---- |
<> 149:156823d33999 7494 * |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag
<> 149:156823d33999 7495 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7496 * | | |0 = No capture rising latch condition happened.
<> 149:156823d33999 7497 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
<> 149:156823d33999 7498 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
<> 149:156823d33999 7499 * |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag
<> 149:156823d33999 7500 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7501 * | | |0 = No capture falling latch condition happened.
<> 149:156823d33999 7502 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
<> 149:156823d33999 7503 * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
<> 149:156823d33999 7504 * @var PWM_T::PBUF
<> 149:156823d33999 7505 * Offset: 0x304~0x318 PWM PERIOD0~5 Buffer
<> 149:156823d33999 7506 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7507 * |Bits |Field |Descriptions
<> 149:156823d33999 7508 * | :----: | :----: | :---- |
<> 149:156823d33999 7509 * |[15:0] |PBUF |PWM Period Register Buffer
<> 149:156823d33999 7510 * | | |(Read Only)
<> 149:156823d33999 7511 * | | |Used as PERIOD active register.
<> 149:156823d33999 7512 * @var PWM_T::CMPBUF
<> 149:156823d33999 7513 * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer
<> 149:156823d33999 7514 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7515 * |Bits |Field |Descriptions
<> 149:156823d33999 7516 * | :----: | :----: | :---- |
<> 149:156823d33999 7517 * |[15:0] |CMPBUF |PWM Comparator Register Buffer
<> 149:156823d33999 7518 * | | |(Read Only)
<> 149:156823d33999 7519 * | | |Used as CMP active register.
<> 149:156823d33999 7520 * @var PWM_T::FTCBUF0_1
<> 149:156823d33999 7521 * Offset: 0x340 PWM FTCMPDAT0_1 Buffer
<> 149:156823d33999 7522 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7523 * |Bits |Field |Descriptions
<> 149:156823d33999 7524 * | :----: | :----: | :---- |
<> 149:156823d33999 7525 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
<> 149:156823d33999 7526 * | | |Used as FTCMPDAT active register.
<> 149:156823d33999 7527 * @var PWM_T::FTCBUF2_3
<> 149:156823d33999 7528 * Offset: 0x344 PWM FTCMPDAT2_3 Buffer
<> 149:156823d33999 7529 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7530 * |Bits |Field |Descriptions
<> 149:156823d33999 7531 * | :----: | :----: | :---- |
<> 149:156823d33999 7532 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
<> 149:156823d33999 7533 * | | |Used as FTCMPDAT active register.
<> 149:156823d33999 7534 * @var PWM_T::FTCBUF4_5
<> 149:156823d33999 7535 * Offset: 0x348 PWM FTCMPDAT4_5 Buffer
<> 149:156823d33999 7536 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7537 * |Bits |Field |Descriptions
<> 149:156823d33999 7538 * | :----: | :----: | :---- |
<> 149:156823d33999 7539 * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
<> 149:156823d33999 7540 * | | |Used as FTCMPDAT active register.
<> 149:156823d33999 7541 * @var PWM_T::FTCI
<> 149:156823d33999 7542 * Offset: 0x34C PWM FTCMPDAT Indicator Register
<> 149:156823d33999 7543 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 7544 * |Bits |Field |Descriptions
<> 149:156823d33999 7545 * | :----: | :----: | :---- |
<> 149:156823d33999 7546 * |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator
<> 149:156823d33999 7547 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
<> 149:156823d33999 7548 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7549 * |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator
<> 149:156823d33999 7550 * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
<> 149:156823d33999 7551 * | | |Each bit n controls the corresponding PWM channel n.
<> 149:156823d33999 7552 */
<> 149:156823d33999 7553
<> 149:156823d33999 7554 __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
<> 149:156823d33999 7555 __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
<> 149:156823d33999 7556 __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
<> 149:156823d33999 7557 __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
<> 149:156823d33999 7558 __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
<> 149:156823d33999 7559 __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
<> 149:156823d33999 7560 __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
<> 149:156823d33999 7561 __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
<> 149:156823d33999 7562 __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
<> 149:156823d33999 7563 __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
<> 149:156823d33999 7564 __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
<> 149:156823d33999 7565 __I uint32_t RESERVE0[1];
<> 149:156823d33999 7566 __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
<> 149:156823d33999 7567 __I uint32_t RESERVE1[2];
<> 149:156823d33999 7568 __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
<> 149:156823d33999 7569 __I uint32_t RESERVE2[2];
<> 149:156823d33999 7570 __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
<> 149:156823d33999 7571 __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
<> 149:156823d33999 7572 __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
<> 149:156823d33999 7573 __I uint32_t RESERVE3[1];
<> 149:156823d33999 7574 __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
<> 149:156823d33999 7575 __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
<> 149:156823d33999 7576 __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
<> 149:156823d33999 7577 __I uint32_t RESERVE4[1];
<> 149:156823d33999 7578 __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
<> 149:156823d33999 7579 __I uint32_t RESERVE5[2];
<> 149:156823d33999 7580 __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
<> 149:156823d33999 7581 __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
<> 149:156823d33999 7582 __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
<> 149:156823d33999 7583 __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
<> 149:156823d33999 7584 __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
<> 149:156823d33999 7585 __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
<> 149:156823d33999 7586 __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
<> 149:156823d33999 7587 __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
<> 149:156823d33999 7588 __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
<> 149:156823d33999 7589 __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
<> 149:156823d33999 7590 __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
<> 149:156823d33999 7591 __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
<> 149:156823d33999 7592 __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
<> 149:156823d33999 7593 __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
<> 149:156823d33999 7594 __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
<> 149:156823d33999 7595 __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
<> 149:156823d33999 7596 __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
<> 149:156823d33999 7597 __IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */
<> 149:156823d33999 7598 __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
<> 149:156823d33999 7599 __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
<> 149:156823d33999 7600 __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
<> 149:156823d33999 7601 __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
<> 149:156823d33999 7602 __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
<> 149:156823d33999 7603 __I uint32_t RESERVE6[1];
<> 149:156823d33999 7604 __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
<> 149:156823d33999 7605 __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
<> 149:156823d33999 7606 __I uint32_t RESERVE7[2];
<> 149:156823d33999 7607 __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
<> 149:156823d33999 7608 __I uint32_t RESERVE8[55];
<> 149:156823d33999 7609 __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
<> 149:156823d33999 7610 __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
<> 149:156823d33999 7611 __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
<> 149:156823d33999 7612 __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
<> 149:156823d33999 7613 __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
<> 149:156823d33999 7614 __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
<> 149:156823d33999 7615 __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
<> 149:156823d33999 7616 __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
<> 149:156823d33999 7617 __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
<> 149:156823d33999 7618 __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
<> 149:156823d33999 7619 __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
<> 149:156823d33999 7620 __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
<> 149:156823d33999 7621 __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
<> 149:156823d33999 7622 __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
<> 149:156823d33999 7623 __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
<> 149:156823d33999 7624 __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
<> 149:156823d33999 7625 __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
<> 149:156823d33999 7626 __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
<> 149:156823d33999 7627 __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
<> 149:156823d33999 7628 __I uint32_t RESERVE9[1];
<> 149:156823d33999 7629 __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
<> 149:156823d33999 7630 __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
<> 149:156823d33999 7631 __I uint32_t RESERVE10[43];
<> 149:156823d33999 7632 __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
<> 149:156823d33999 7633 __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
<> 149:156823d33999 7634 __I uint32_t RESERVE11[3];
<> 149:156823d33999 7635 __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
<> 149:156823d33999 7636 __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
<> 149:156823d33999 7637 __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
<> 149:156823d33999 7638 __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
<> 149:156823d33999 7639
<> 149:156823d33999 7640 } PWM_T;
<> 149:156823d33999 7641
<> 149:156823d33999 7642
<> 149:156823d33999 7643
<> 149:156823d33999 7644 /**
<> 149:156823d33999 7645 @addtogroup PWM_CONST PWM Bit Field Definition
<> 149:156823d33999 7646 Constant Definitions for PWM Controller
<> 149:156823d33999 7647 @{ */
<> 149:156823d33999 7648
<> 149:156823d33999 7649 #define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */
<> 149:156823d33999 7650 #define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */
<> 149:156823d33999 7651
<> 149:156823d33999 7652 #define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */
<> 149:156823d33999 7653 #define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */
<> 149:156823d33999 7654
<> 149:156823d33999 7655 #define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */
<> 149:156823d33999 7656 #define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */
<> 149:156823d33999 7657
<> 149:156823d33999 7658 #define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */
<> 149:156823d33999 7659 #define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */
<> 149:156823d33999 7660
<> 149:156823d33999 7661 #define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */
<> 149:156823d33999 7662 #define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */
<> 149:156823d33999 7663
<> 149:156823d33999 7664 #define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */
<> 149:156823d33999 7665 #define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */
<> 149:156823d33999 7666
<> 149:156823d33999 7667 #define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */
<> 149:156823d33999 7668 #define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */
<> 149:156823d33999 7669
<> 149:156823d33999 7670 #define PWM_CTL0_WINLDENn_Pos (8) /*!< PWM_T::CTL0: WINLDENn Position */
<> 149:156823d33999 7671 #define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) /*!< PWM_T::CTL0: WINLDENn Mask */
<> 149:156823d33999 7672
<> 149:156823d33999 7673 #define PWM_CTL0_WINLDEN0_Pos (8) /*!< PWM_T::CTL0: WINLDEN0 Position */
<> 149:156823d33999 7674 #define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) /*!< PWM_T::CTL0: WINLDEN0 Mask */
<> 149:156823d33999 7675
<> 149:156823d33999 7676 #define PWM_CTL0_WINLDEN1_Pos (9) /*!< PWM_T::CTL0: WINLDEN1 Position */
<> 149:156823d33999 7677 #define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) /*!< PWM_T::CTL0: WINLDEN1 Mask */
<> 149:156823d33999 7678
<> 149:156823d33999 7679 #define PWM_CTL0_WINLDEN2_Pos (10) /*!< PWM_T::CTL0: WINLDEN2 Position */
<> 149:156823d33999 7680 #define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) /*!< PWM_T::CTL0: WINLDEN2 Mask */
<> 149:156823d33999 7681
<> 149:156823d33999 7682 #define PWM_CTL0_WINLDEN3_Pos (11) /*!< PWM_T::CTL0: WINLDEN3 Position */
<> 149:156823d33999 7683 #define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) /*!< PWM_T::CTL0: WINLDEN3 Mask */
<> 149:156823d33999 7684
<> 149:156823d33999 7685 #define PWM_CTL0_WINLDEN4_Pos (12) /*!< PWM_T::CTL0: WINLDEN4 Position */
<> 149:156823d33999 7686 #define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) /*!< PWM_T::CTL0: WINLDEN4 Mask */
<> 149:156823d33999 7687
<> 149:156823d33999 7688 #define PWM_CTL0_WINLDEN5_Pos (13) /*!< PWM_T::CTL0: WINLDEN5 Position */
<> 149:156823d33999 7689 #define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) /*!< PWM_T::CTL0: WINLDEN5 Mask */
<> 149:156823d33999 7690
<> 149:156823d33999 7691 #define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */
<> 149:156823d33999 7692 #define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */
<> 149:156823d33999 7693
<> 149:156823d33999 7694 #define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */
<> 149:156823d33999 7695 #define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */
<> 149:156823d33999 7696
<> 149:156823d33999 7697 #define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */
<> 149:156823d33999 7698 #define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */
<> 149:156823d33999 7699
<> 149:156823d33999 7700 #define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */
<> 149:156823d33999 7701 #define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */
<> 149:156823d33999 7702
<> 149:156823d33999 7703 #define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */
<> 149:156823d33999 7704 #define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */
<> 149:156823d33999 7705
<> 149:156823d33999 7706 #define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */
<> 149:156823d33999 7707 #define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */
<> 149:156823d33999 7708
<> 149:156823d33999 7709 #define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */
<> 149:156823d33999 7710 #define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */
<> 149:156823d33999 7711
<> 149:156823d33999 7712 #define PWM_CTL0_GROUPEN_Pos (24) /*!< PWM_T::CTL0: GROUPEN Position */
<> 149:156823d33999 7713 #define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) /*!< PWM_T::CTL0: GROUPEN Mask */
<> 149:156823d33999 7714
<> 149:156823d33999 7715 #define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */
<> 149:156823d33999 7716 #define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */
<> 149:156823d33999 7717
<> 149:156823d33999 7718 #define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */
<> 149:156823d33999 7719 #define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */
<> 149:156823d33999 7720
<> 149:156823d33999 7721 #define PWM_CTL1_CNTTYPEn_Pos (0) /*!< PWM_T::CTL1: CNTTYPEn Position */
<> 149:156823d33999 7722 #define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) /*!< PWM_T::CTL1: CNTTYPEn Mask */
<> 149:156823d33999 7723
<> 149:156823d33999 7724 #define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */
<> 149:156823d33999 7725 #define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */
<> 149:156823d33999 7726
<> 149:156823d33999 7727 #define PWM_CTL1_CNTTYPE1_Pos (2) /*!< PWM_T::CTL1: CNTTYPE1 Position */
<> 149:156823d33999 7728 #define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) /*!< PWM_T::CTL1: CNTTYPE1 Mask */
<> 149:156823d33999 7729
<> 149:156823d33999 7730 #define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */
<> 149:156823d33999 7731 #define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */
<> 149:156823d33999 7732
<> 149:156823d33999 7733 #define PWM_CTL1_CNTTYPE3_Pos (6) /*!< PWM_T::CTL1: CNTTYPE3 Position */
<> 149:156823d33999 7734 #define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) /*!< PWM_T::CTL1: CNTTYPE3 Mask */
<> 149:156823d33999 7735
<> 149:156823d33999 7736 #define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */
<> 149:156823d33999 7737 #define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */
<> 149:156823d33999 7738
<> 149:156823d33999 7739 #define PWM_CTL1_CNTTYPE5_Pos (10) /*!< PWM_T::CTL1: CNTTYPE5 Position */
<> 149:156823d33999 7740 #define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) /*!< PWM_T::CTL1: CNTTYPE5 Mask */
<> 149:156823d33999 7741
<> 149:156823d33999 7742 #define PWM_CTL1_CNTMODEn_Pos (16) /*!< PWM_T::CTL1: CNTMODEn Position */
<> 149:156823d33999 7743 #define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) /*!< PWM_T::CTL1: CNTMODEn Mask */
<> 149:156823d33999 7744
<> 149:156823d33999 7745 #define PWM_CTL1_CNTMODE0_Pos (16) /*!< PWM_T::CTL1: CNTMODE0 Position */
<> 149:156823d33999 7746 #define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) /*!< PWM_T::CTL1: CNTMODE0 Mask */
<> 149:156823d33999 7747
<> 149:156823d33999 7748 #define PWM_CTL1_CNTMODE1_Pos (17) /*!< PWM_T::CTL1: CNTMODE1 Position */
<> 149:156823d33999 7749 #define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) /*!< PWM_T::CTL1: CNTMODE1 Mask */
<> 149:156823d33999 7750
<> 149:156823d33999 7751 #define PWM_CTL1_CNTMODE2_Pos (18) /*!< PWM_T::CTL1: CNTMODE2 Position */
<> 149:156823d33999 7752 #define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) /*!< PWM_T::CTL1: CNTMODE2 Mask */
<> 149:156823d33999 7753
<> 149:156823d33999 7754 #define PWM_CTL1_CNTMODE3_Pos (19) /*!< PWM_T::CTL1: CNTMODE3 Position */
<> 149:156823d33999 7755 #define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) /*!< PWM_T::CTL1: CNTMODE3 Mask */
<> 149:156823d33999 7756
<> 149:156823d33999 7757 #define PWM_CTL1_CNTMODE4_Pos (20) /*!< PWM_T::CTL1: CNTMODE4 Position */
<> 149:156823d33999 7758 #define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) /*!< PWM_T::CTL1: CNTMODE4 Mask */
<> 149:156823d33999 7759
<> 149:156823d33999 7760 #define PWM_CTL1_CNTMODE5_Pos (21) /*!< PWM_T::CTL1: CNTMODE5 Position */
<> 149:156823d33999 7761 #define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) /*!< PWM_T::CTL1: CNTMODE5 Mask */
<> 149:156823d33999 7762
<> 149:156823d33999 7763 #define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */
<> 149:156823d33999 7764 #define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */
<> 149:156823d33999 7765
<> 149:156823d33999 7766 #define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */
<> 149:156823d33999 7767 #define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */
<> 149:156823d33999 7768
<> 149:156823d33999 7769 #define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */
<> 149:156823d33999 7770 #define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */
<> 149:156823d33999 7771
<> 149:156823d33999 7772 #define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */
<> 149:156823d33999 7773 #define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */
<> 149:156823d33999 7774
<> 149:156823d33999 7775 #define PWM_SYNC_PHSENn_Pos (0) /*!< PWM_T::SYNC: PHSENn Position */
<> 149:156823d33999 7776 #define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) /*!< PWM_T::SYNC: PHSENn Mask */
<> 149:156823d33999 7777
<> 149:156823d33999 7778 #define PWM_SYNC_PHSEN0_Pos (0) /*!< PWM_T::SYNC: PHSEN0 Position */
<> 149:156823d33999 7779 #define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) /*!< PWM_T::SYNC: PHSEN0 Mask */
<> 149:156823d33999 7780
<> 149:156823d33999 7781 #define PWM_SYNC_PHSEN2_Pos (1) /*!< PWM_T::SYNC: PHSEN2 Position */
<> 149:156823d33999 7782 #define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) /*!< PWM_T::SYNC: PHSEN2 Mask */
<> 149:156823d33999 7783
<> 149:156823d33999 7784 #define PWM_SYNC_PHSEN4_Pos (2) /*!< PWM_T::SYNC: PHSEN4 Position */
<> 149:156823d33999 7785 #define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) /*!< PWM_T::SYNC: PHSEN4 Mask */
<> 149:156823d33999 7786
<> 149:156823d33999 7787 #define PWM_SYNC_SINSRCn_Pos (8) /*!< PWM_T::SYNC: SINSRCn Position */
<> 149:156823d33999 7788 #define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) /*!< PWM_T::SYNC: SINSRCn Mask */
<> 149:156823d33999 7789
<> 149:156823d33999 7790 #define PWM_SYNC_SINSRC0_Pos (8) /*!< PWM_T::SYNC: SINSRC0 Position */
<> 149:156823d33999 7791 #define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) /*!< PWM_T::SYNC: SINSRC0 Mask */
<> 149:156823d33999 7792
<> 149:156823d33999 7793 #define PWM_SYNC_SINSRC2_Pos (10) /*!< PWM_T::SYNC: SINSRC2 Position */
<> 149:156823d33999 7794 #define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) /*!< PWM_T::SYNC: SINSRC2 Mask */
<> 149:156823d33999 7795
<> 149:156823d33999 7796 #define PWM_SYNC_SINSRC4_Pos (12) /*!< PWM_T::SYNC: SINSRC4 Position */
<> 149:156823d33999 7797 #define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) /*!< PWM_T::SYNC: SINSRC4 Mask */
<> 149:156823d33999 7798
<> 149:156823d33999 7799 #define PWM_SYNC_SNFLTEN_Pos (16) /*!< PWM_T::SYNC: SNFLTEN Position */
<> 149:156823d33999 7800 #define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) /*!< PWM_T::SYNC: SNFLTEN Mask */
<> 149:156823d33999 7801
<> 149:156823d33999 7802 #define PWM_SYNC_SFLTCSEL_Pos (17) /*!< PWM_T::SYNC: SFLTCSEL Position */
<> 149:156823d33999 7803 #define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) /*!< PWM_T::SYNC: SFLTCSEL Mask */
<> 149:156823d33999 7804
<> 149:156823d33999 7805 #define PWM_SYNC_SFLTCNT_Pos (20) /*!< PWM_T::SYNC: SFLTCNT Position */
<> 149:156823d33999 7806 #define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) /*!< PWM_T::SYNC: SFLTCNT Mask */
<> 149:156823d33999 7807
<> 149:156823d33999 7808 #define PWM_SYNC_SINPINV_Pos (23) /*!< PWM_T::SYNC: SINPINV Position */
<> 149:156823d33999 7809 #define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) /*!< PWM_T::SYNC: SINPINV Mask */
<> 149:156823d33999 7810
<> 149:156823d33999 7811 #define PWM_SYNC_PHSDIRn_Pos (24) /*!< PWM_T::SYNC: PHSDIRn Position */
<> 149:156823d33999 7812 #define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) /*!< PWM_T::SYNC: PHSDIRn Mask */
<> 149:156823d33999 7813
<> 149:156823d33999 7814 #define PWM_SYNC_PHSDIR0_Pos (24) /*!< PWM_T::SYNC: PHSDIR0 Position */
<> 149:156823d33999 7815 #define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) /*!< PWM_T::SYNC: PHSDIR0 Mask */
<> 149:156823d33999 7816
<> 149:156823d33999 7817 #define PWM_SYNC_PHSDIR2_Pos (25) /*!< PWM_T::SYNC: PHSDIR2 Position */
<> 149:156823d33999 7818 #define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) /*!< PWM_T::SYNC: PHSDIR2 Mask */
<> 149:156823d33999 7819
<> 149:156823d33999 7820 #define PWM_SYNC_PHSDIR4_Pos (26) /*!< PWM_T::SYNC: PHSDIR4 Position */
<> 149:156823d33999 7821 #define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) /*!< PWM_T::SYNC: PHSDIR4 Mask */
<> 149:156823d33999 7822
<> 149:156823d33999 7823 #define PWM_SWSYNC_SWSYNCn_Pos (0) /*!< PWM_T::SWSYNC: SWSYNCn Position */
<> 149:156823d33999 7824 #define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) /*!< PWM_T::SWSYNC: SWSYNCn Mask */
<> 149:156823d33999 7825
<> 149:156823d33999 7826 #define PWM_SWSYNC_SWSYNC0_Pos (0) /*!< PWM_T::SWSYNC: SWSYNC0 Position */
<> 149:156823d33999 7827 #define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) /*!< PWM_T::SWSYNC: SWSYNC0 Mask */
<> 149:156823d33999 7828
<> 149:156823d33999 7829 #define PWM_SWSYNC_SWSYNC2_Pos (1) /*!< PWM_T::SWSYNC: SWSYNC2 Position */
<> 149:156823d33999 7830 #define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) /*!< PWM_T::SWSYNC: SWSYNC2 Mask */
<> 149:156823d33999 7831
<> 149:156823d33999 7832 #define PWM_SWSYNC_SWSYNC4_Pos (2) /*!< PWM_T::SWSYNC: SWSYNC4 Position */
<> 149:156823d33999 7833 #define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) /*!< PWM_T::SWSYNC: SWSYNC4 Mask */
<> 149:156823d33999 7834
<> 149:156823d33999 7835 #define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */
<> 149:156823d33999 7836 #define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */
<> 149:156823d33999 7837
<> 149:156823d33999 7838 #define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */
<> 149:156823d33999 7839 #define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */
<> 149:156823d33999 7840
<> 149:156823d33999 7841 #define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */
<> 149:156823d33999 7842 #define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */
<> 149:156823d33999 7843
<> 149:156823d33999 7844 #define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */
<> 149:156823d33999 7845 #define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */
<> 149:156823d33999 7846
<> 149:156823d33999 7847 #define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */
<> 149:156823d33999 7848 #define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */
<> 149:156823d33999 7849
<> 149:156823d33999 7850 #define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */
<> 149:156823d33999 7851 #define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */
<> 149:156823d33999 7852
<> 149:156823d33999 7853 #define PWM_CNTEN_CNTENn_Pos (0) /*!< PWM_T::CNTEN: CNTENn Position */
<> 149:156823d33999 7854 #define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) /*!< PWM_T::CNTEN: CNTENn Mask */
<> 149:156823d33999 7855
<> 149:156823d33999 7856 #define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */
<> 149:156823d33999 7857 #define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */
<> 149:156823d33999 7858
<> 149:156823d33999 7859 #define PWM_CNTEN_CNTEN1_Pos (1) /*!< PWM_T::CNTEN: CNTEN1 Position */
<> 149:156823d33999 7860 #define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) /*!< PWM_T::CNTEN: CNTEN1 Mask */
<> 149:156823d33999 7861
<> 149:156823d33999 7862 #define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */
<> 149:156823d33999 7863 #define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */
<> 149:156823d33999 7864
<> 149:156823d33999 7865 #define PWM_CNTEN_CNTEN3_Pos (3) /*!< PWM_T::CNTEN: CNTEN3 Position */
<> 149:156823d33999 7866 #define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) /*!< PWM_T::CNTEN: CNTEN3 Mask */
<> 149:156823d33999 7867
<> 149:156823d33999 7868 #define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */
<> 149:156823d33999 7869 #define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */
<> 149:156823d33999 7870
<> 149:156823d33999 7871 #define PWM_CNTEN_CNTEN5_Pos (5) /*!< PWM_T::CNTEN: CNTEN5 Position */
<> 149:156823d33999 7872 #define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) /*!< PWM_T::CNTEN: CNTEN5 Mask */
<> 149:156823d33999 7873
<> 149:156823d33999 7874 #define PWM_CNTCLR_CNTCLRn_Pos (0) /*!< PWM_T::CNTCLR: CNTCLRn Position */
<> 149:156823d33999 7875 #define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) /*!< PWM_T::CNTCLR: CNTCLRn Mask */
<> 149:156823d33999 7876
<> 149:156823d33999 7877 #define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */
<> 149:156823d33999 7878 #define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */
<> 149:156823d33999 7879
<> 149:156823d33999 7880 #define PWM_CNTCLR_CNTCLR1_Pos (1) /*!< PWM_T::CNTCLR: CNTCLR1 Position */
<> 149:156823d33999 7881 #define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) /*!< PWM_T::CNTCLR: CNTCLR1 Mask */
<> 149:156823d33999 7882
<> 149:156823d33999 7883 #define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */
<> 149:156823d33999 7884 #define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */
<> 149:156823d33999 7885
<> 149:156823d33999 7886 #define PWM_CNTCLR_CNTCLR3_Pos (3) /*!< PWM_T::CNTCLR: CNTCLR3 Position */
<> 149:156823d33999 7887 #define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) /*!< PWM_T::CNTCLR: CNTCLR3 Mask */
<> 149:156823d33999 7888
<> 149:156823d33999 7889 #define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */
<> 149:156823d33999 7890 #define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */
<> 149:156823d33999 7891
<> 149:156823d33999 7892 #define PWM_CNTCLR_CNTCLR5_Pos (5) /*!< PWM_T::CNTCLR: CNTCLR5 Position */
<> 149:156823d33999 7893 #define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) /*!< PWM_T::CNTCLR: CNTCLR5 Mask */
<> 149:156823d33999 7894
<> 149:156823d33999 7895 #define PWM_LOAD_LOADn_Pos (0) /*!< PWM_T::LOAD: LOADn Position */
<> 149:156823d33999 7896 #define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) /*!< PWM_T::LOAD: LOADn Mask */
<> 149:156823d33999 7897
<> 149:156823d33999 7898 #define PWM_LOAD_LOAD0_Pos (0) /*!< PWM_T::LOAD: LOAD0 Position */
<> 149:156823d33999 7899 #define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) /*!< PWM_T::LOAD: LOAD0 Mask */
<> 149:156823d33999 7900
<> 149:156823d33999 7901 #define PWM_LOAD_LOAD1_Pos (1) /*!< PWM_T::LOAD: LOAD1 Position */
<> 149:156823d33999 7902 #define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) /*!< PWM_T::LOAD: LOAD1 Mask */
<> 149:156823d33999 7903
<> 149:156823d33999 7904 #define PWM_LOAD_LOAD2_Pos (2) /*!< PWM_T::LOAD: LOAD2 Position */
<> 149:156823d33999 7905 #define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) /*!< PWM_T::LOAD: LOAD2 Mask */
<> 149:156823d33999 7906
<> 149:156823d33999 7907 #define PWM_LOAD_LOAD3_Pos (3) /*!< PWM_T::LOAD: LOAD3 Position */
<> 149:156823d33999 7908 #define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) /*!< PWM_T::LOAD: LOAD3 Mask */
<> 149:156823d33999 7909
<> 149:156823d33999 7910 #define PWM_LOAD_LOAD4_Pos (4) /*!< PWM_T::LOAD: LOAD4 Position */
<> 149:156823d33999 7911 #define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) /*!< PWM_T::LOAD: LOAD4 Mask */
<> 149:156823d33999 7912
<> 149:156823d33999 7913 #define PWM_LOAD_LOAD5_Pos (5) /*!< PWM_T::LOAD: LOAD5 Position */
<> 149:156823d33999 7914 #define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) /*!< PWM_T::LOAD: LOAD5 Mask */
<> 149:156823d33999 7915
<> 149:156823d33999 7916 #define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */
<> 149:156823d33999 7917 #define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */
<> 149:156823d33999 7918
<> 149:156823d33999 7919 #define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */
<> 149:156823d33999 7920 #define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */
<> 149:156823d33999 7921
<> 149:156823d33999 7922 #define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */
<> 149:156823d33999 7923 #define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */
<> 149:156823d33999 7924
<> 149:156823d33999 7925 #define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */
<> 149:156823d33999 7926 #define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */
<> 149:156823d33999 7927
<> 149:156823d33999 7928 #define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */
<> 149:156823d33999 7929 #define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */
<> 149:156823d33999 7930
<> 149:156823d33999 7931 #define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */
<> 149:156823d33999 7932 #define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */
<> 149:156823d33999 7933
<> 149:156823d33999 7934 #define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */
<> 149:156823d33999 7935 #define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */
<> 149:156823d33999 7936
<> 149:156823d33999 7937 #define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */
<> 149:156823d33999 7938 #define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */
<> 149:156823d33999 7939
<> 149:156823d33999 7940 #define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */
<> 149:156823d33999 7941 #define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */
<> 149:156823d33999 7942
<> 149:156823d33999 7943 #define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */
<> 149:156823d33999 7944 #define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */
<> 149:156823d33999 7945
<> 149:156823d33999 7946 #define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */
<> 149:156823d33999 7947 #define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */
<> 149:156823d33999 7948
<> 149:156823d33999 7949 #define PWM_PHS0_1_PHS_Pos (0) /*!< PWM_T::PHS0_1: PHS Position */
<> 149:156823d33999 7950 #define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) /*!< PWM_T::PHS0_1: PHS Mask */
<> 149:156823d33999 7951
<> 149:156823d33999 7952 #define PWM_PHS2_3_PHS_Pos (0) /*!< PWM_T::PHS2_3: PHS Position */
<> 149:156823d33999 7953 #define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) /*!< PWM_T::PHS2_3: PHS Mask */
<> 149:156823d33999 7954
<> 149:156823d33999 7955 #define PWM_PHS4_5_PHS_Pos (0) /*!< PWM_T::PHS4_5: PHS Position */
<> 149:156823d33999 7956 #define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) /*!< PWM_T::PHS4_5: PHS Mask */
<> 149:156823d33999 7957
<> 149:156823d33999 7958 #define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */
<> 149:156823d33999 7959 #define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */
<> 149:156823d33999 7960
<> 149:156823d33999 7961 #define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */
<> 149:156823d33999 7962 #define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */
<> 149:156823d33999 7963
<> 149:156823d33999 7964 #define PWM_WGCTL0_ZPCTLn_Pos (0) /*!< PWM_T::WGCTL0: ZPCTLn Position */
<> 149:156823d33999 7965 #define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) /*!< PWM_T::WGCTL0: ZPCTLn Mask */
<> 149:156823d33999 7966
<> 149:156823d33999 7967 #define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */
<> 149:156823d33999 7968 #define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */
<> 149:156823d33999 7969
<> 149:156823d33999 7970 #define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */
<> 149:156823d33999 7971 #define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */
<> 149:156823d33999 7972
<> 149:156823d33999 7973 #define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */
<> 149:156823d33999 7974 #define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */
<> 149:156823d33999 7975
<> 149:156823d33999 7976 #define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */
<> 149:156823d33999 7977 #define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */
<> 149:156823d33999 7978
<> 149:156823d33999 7979 #define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */
<> 149:156823d33999 7980 #define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */
<> 149:156823d33999 7981
<> 149:156823d33999 7982 #define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */
<> 149:156823d33999 7983 #define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */
<> 149:156823d33999 7984
<> 149:156823d33999 7985 #define PWM_WGCTL0_PRDPCTLn_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTLn Position */
<> 149:156823d33999 7986 #define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) /*!< PWM_T::WGCTL0: PRDPCTLn Mask */
<> 149:156823d33999 7987
<> 149:156823d33999 7988 #define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */
<> 149:156823d33999 7989 #define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */
<> 149:156823d33999 7990
<> 149:156823d33999 7991 #define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */
<> 149:156823d33999 7992 #define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */
<> 149:156823d33999 7993
<> 149:156823d33999 7994 #define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */
<> 149:156823d33999 7995 #define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */
<> 149:156823d33999 7996
<> 149:156823d33999 7997 #define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */
<> 149:156823d33999 7998 #define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */
<> 149:156823d33999 7999
<> 149:156823d33999 8000 #define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */
<> 149:156823d33999 8001 #define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */
<> 149:156823d33999 8002
<> 149:156823d33999 8003 #define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */
<> 149:156823d33999 8004 #define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */
<> 149:156823d33999 8005
<> 149:156823d33999 8006 #define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */
<> 149:156823d33999 8007 #define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */
<> 149:156823d33999 8008
<> 149:156823d33999 8009 #define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */
<> 149:156823d33999 8010 #define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */
<> 149:156823d33999 8011
<> 149:156823d33999 8012 #define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */
<> 149:156823d33999 8013 #define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */
<> 149:156823d33999 8014
<> 149:156823d33999 8015 #define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */
<> 149:156823d33999 8016 #define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */
<> 149:156823d33999 8017
<> 149:156823d33999 8018 #define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */
<> 149:156823d33999 8019 #define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */
<> 149:156823d33999 8020
<> 149:156823d33999 8021 #define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */
<> 149:156823d33999 8022 #define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */
<> 149:156823d33999 8023
<> 149:156823d33999 8024 #define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */
<> 149:156823d33999 8025 #define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */
<> 149:156823d33999 8026
<> 149:156823d33999 8027 #define PWM_WGCTL1_CMPDCTLn_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTLn Position */
<> 149:156823d33999 8028 #define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) /*!< PWM_T::WGCTL1: CMPDCTLn Mask */
<> 149:156823d33999 8029
<> 149:156823d33999 8030 #define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */
<> 149:156823d33999 8031 #define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */
<> 149:156823d33999 8032
<> 149:156823d33999 8033 #define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */
<> 149:156823d33999 8034 #define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */
<> 149:156823d33999 8035
<> 149:156823d33999 8036 #define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */
<> 149:156823d33999 8037 #define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */
<> 149:156823d33999 8038
<> 149:156823d33999 8039 #define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */
<> 149:156823d33999 8040 #define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */
<> 149:156823d33999 8041
<> 149:156823d33999 8042 #define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */
<> 149:156823d33999 8043 #define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */
<> 149:156823d33999 8044
<> 149:156823d33999 8045 #define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */
<> 149:156823d33999 8046 #define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */
<> 149:156823d33999 8047
<> 149:156823d33999 8048 #define PWM_MSKEN_MSKENn_Pos (0) /*!< PWM_T::MSKEN: MSKENn Position */
<> 149:156823d33999 8049 #define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) /*!< PWM_T::MSKEN: MSKENn Mask */
<> 149:156823d33999 8050
<> 149:156823d33999 8051 #define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */
<> 149:156823d33999 8052 #define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */
<> 149:156823d33999 8053
<> 149:156823d33999 8054 #define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */
<> 149:156823d33999 8055 #define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */
<> 149:156823d33999 8056
<> 149:156823d33999 8057 #define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */
<> 149:156823d33999 8058 #define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */
<> 149:156823d33999 8059
<> 149:156823d33999 8060 #define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */
<> 149:156823d33999 8061 #define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */
<> 149:156823d33999 8062
<> 149:156823d33999 8063 #define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */
<> 149:156823d33999 8064 #define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */
<> 149:156823d33999 8065
<> 149:156823d33999 8066 #define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */
<> 149:156823d33999 8067 #define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */
<> 149:156823d33999 8068
<> 149:156823d33999 8069 #define PWM_MSK_MSKDATn_Pos (0) /*!< PWM_T::MSK: MSKDATn Position */
<> 149:156823d33999 8070 #define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) /*!< PWM_T::MSK: MSKDATn Mask */
<> 149:156823d33999 8071
<> 149:156823d33999 8072 #define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */
<> 149:156823d33999 8073 #define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */
<> 149:156823d33999 8074
<> 149:156823d33999 8075 #define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */
<> 149:156823d33999 8076 #define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */
<> 149:156823d33999 8077
<> 149:156823d33999 8078 #define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */
<> 149:156823d33999 8079 #define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */
<> 149:156823d33999 8080
<> 149:156823d33999 8081 #define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */
<> 149:156823d33999 8082 #define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */
<> 149:156823d33999 8083
<> 149:156823d33999 8084 #define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */
<> 149:156823d33999 8085 #define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */
<> 149:156823d33999 8086
<> 149:156823d33999 8087 #define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */
<> 149:156823d33999 8088 #define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */
<> 149:156823d33999 8089
<> 149:156823d33999 8090 #define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */
<> 149:156823d33999 8091 #define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */
<> 149:156823d33999 8092
<> 149:156823d33999 8093 #define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */
<> 149:156823d33999 8094 #define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */
<> 149:156823d33999 8095
<> 149:156823d33999 8096 #define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */
<> 149:156823d33999 8097 #define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */
<> 149:156823d33999 8098
<> 149:156823d33999 8099 #define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */
<> 149:156823d33999 8100 #define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */
<> 149:156823d33999 8101
<> 149:156823d33999 8102 #define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */
<> 149:156823d33999 8103 #define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */
<> 149:156823d33999 8104
<> 149:156823d33999 8105 #define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */
<> 149:156823d33999 8106 #define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */
<> 149:156823d33999 8107
<> 149:156823d33999 8108 #define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */
<> 149:156823d33999 8109 #define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */
<> 149:156823d33999 8110
<> 149:156823d33999 8111 #define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */
<> 149:156823d33999 8112 #define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */
<> 149:156823d33999 8113
<> 149:156823d33999 8114 #define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */
<> 149:156823d33999 8115 #define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */
<> 149:156823d33999 8116
<> 149:156823d33999 8117 #define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */
<> 149:156823d33999 8118 #define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */
<> 149:156823d33999 8119
<> 149:156823d33999 8120 #define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */
<> 149:156823d33999 8121 #define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */
<> 149:156823d33999 8122
<> 149:156823d33999 8123 #define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */
<> 149:156823d33999 8124 #define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */
<> 149:156823d33999 8125
<> 149:156823d33999 8126 #define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */
<> 149:156823d33999 8127 #define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */
<> 149:156823d33999 8128
<> 149:156823d33999 8129 #define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */
<> 149:156823d33999 8130 #define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */
<> 149:156823d33999 8131
<> 149:156823d33999 8132 #define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */
<> 149:156823d33999 8133 #define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */
<> 149:156823d33999 8134
<> 149:156823d33999 8135 #define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */
<> 149:156823d33999 8136 #define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */
<> 149:156823d33999 8137
<> 149:156823d33999 8138 #define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */
<> 149:156823d33999 8139 #define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */
<> 149:156823d33999 8140
<> 149:156823d33999 8141 #define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */
<> 149:156823d33999 8142 #define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */
<> 149:156823d33999 8143
<> 149:156823d33999 8144 #define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */
<> 149:156823d33999 8145 #define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */
<> 149:156823d33999 8146
<> 149:156823d33999 8147 #define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */
<> 149:156823d33999 8148 #define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */
<> 149:156823d33999 8149
<> 149:156823d33999 8150 #define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */
<> 149:156823d33999 8151 #define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */
<> 149:156823d33999 8152
<> 149:156823d33999 8153 #define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */
<> 149:156823d33999 8154 #define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */
<> 149:156823d33999 8155
<> 149:156823d33999 8156 #define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */
<> 149:156823d33999 8157 #define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */
<> 149:156823d33999 8158
<> 149:156823d33999 8159 #define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */
<> 149:156823d33999 8160 #define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */
<> 149:156823d33999 8161
<> 149:156823d33999 8162 #define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */
<> 149:156823d33999 8163 #define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */
<> 149:156823d33999 8164
<> 149:156823d33999 8165 #define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */
<> 149:156823d33999 8166 #define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */
<> 149:156823d33999 8167
<> 149:156823d33999 8168 #define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */
<> 149:156823d33999 8169 #define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */
<> 149:156823d33999 8170
<> 149:156823d33999 8171 #define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */
<> 149:156823d33999 8172 #define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */
<> 149:156823d33999 8173
<> 149:156823d33999 8174 #define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */
<> 149:156823d33999 8175 #define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */
<> 149:156823d33999 8176
<> 149:156823d33999 8177 #define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */
<> 149:156823d33999 8178 #define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */
<> 149:156823d33999 8179
<> 149:156823d33999 8180 #define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */
<> 149:156823d33999 8181 #define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */
<> 149:156823d33999 8182
<> 149:156823d33999 8183 #define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */
<> 149:156823d33999 8184 #define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */
<> 149:156823d33999 8185
<> 149:156823d33999 8186 #define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */
<> 149:156823d33999 8187 #define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */
<> 149:156823d33999 8188
<> 149:156823d33999 8189 #define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */
<> 149:156823d33999 8190 #define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */
<> 149:156823d33999 8191
<> 149:156823d33999 8192 #define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */
<> 149:156823d33999 8193 #define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */
<> 149:156823d33999 8194
<> 149:156823d33999 8195 #define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */
<> 149:156823d33999 8196 #define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */
<> 149:156823d33999 8197
<> 149:156823d33999 8198 #define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */
<> 149:156823d33999 8199 #define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */
<> 149:156823d33999 8200
<> 149:156823d33999 8201 #define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */
<> 149:156823d33999 8202 #define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */
<> 149:156823d33999 8203
<> 149:156823d33999 8204 #define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */
<> 149:156823d33999 8205 #define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */
<> 149:156823d33999 8206
<> 149:156823d33999 8207 #define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */
<> 149:156823d33999 8208 #define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */
<> 149:156823d33999 8209
<> 149:156823d33999 8210 #define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */
<> 149:156823d33999 8211 #define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */
<> 149:156823d33999 8212
<> 149:156823d33999 8213 #define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */
<> 149:156823d33999 8214 #define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */
<> 149:156823d33999 8215
<> 149:156823d33999 8216 #define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */
<> 149:156823d33999 8217 #define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */
<> 149:156823d33999 8218
<> 149:156823d33999 8219 #define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */
<> 149:156823d33999 8220 #define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */
<> 149:156823d33999 8221
<> 149:156823d33999 8222 #define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */
<> 149:156823d33999 8223 #define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */
<> 149:156823d33999 8224
<> 149:156823d33999 8225 #define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */
<> 149:156823d33999 8226 #define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */
<> 149:156823d33999 8227
<> 149:156823d33999 8228 #define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */
<> 149:156823d33999 8229 #define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */
<> 149:156823d33999 8230
<> 149:156823d33999 8231 #define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */
<> 149:156823d33999 8232 #define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */
<> 149:156823d33999 8233
<> 149:156823d33999 8234 #define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */
<> 149:156823d33999 8235 #define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */
<> 149:156823d33999 8236
<> 149:156823d33999 8237 #define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */
<> 149:156823d33999 8238 #define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */
<> 149:156823d33999 8239
<> 149:156823d33999 8240 #define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */
<> 149:156823d33999 8241 #define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */
<> 149:156823d33999 8242
<> 149:156823d33999 8243 #define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */
<> 149:156823d33999 8244 #define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */
<> 149:156823d33999 8245
<> 149:156823d33999 8246 #define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */
<> 149:156823d33999 8247 #define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */
<> 149:156823d33999 8248
<> 149:156823d33999 8249 #define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */
<> 149:156823d33999 8250 #define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */
<> 149:156823d33999 8251
<> 149:156823d33999 8252 #define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */
<> 149:156823d33999 8253 #define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */
<> 149:156823d33999 8254
<> 149:156823d33999 8255 #define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */
<> 149:156823d33999 8256 #define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */
<> 149:156823d33999 8257
<> 149:156823d33999 8258 #define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */
<> 149:156823d33999 8259 #define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */
<> 149:156823d33999 8260
<> 149:156823d33999 8261 #define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */
<> 149:156823d33999 8262 #define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */
<> 149:156823d33999 8263
<> 149:156823d33999 8264 #define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */
<> 149:156823d33999 8265 #define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */
<> 149:156823d33999 8266
<> 149:156823d33999 8267 #define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */
<> 149:156823d33999 8268 #define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */
<> 149:156823d33999 8269
<> 149:156823d33999 8270 #define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */
<> 149:156823d33999 8271 #define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */
<> 149:156823d33999 8272
<> 149:156823d33999 8273 #define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */
<> 149:156823d33999 8274 #define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */
<> 149:156823d33999 8275
<> 149:156823d33999 8276 #define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */
<> 149:156823d33999 8277 #define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */
<> 149:156823d33999 8278
<> 149:156823d33999 8279 #define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */
<> 149:156823d33999 8280 #define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */
<> 149:156823d33999 8281
<> 149:156823d33999 8282 #define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */
<> 149:156823d33999 8283 #define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */
<> 149:156823d33999 8284
<> 149:156823d33999 8285 #define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */
<> 149:156823d33999 8286 #define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */
<> 149:156823d33999 8287
<> 149:156823d33999 8288 #define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */
<> 149:156823d33999 8289 #define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */
<> 149:156823d33999 8290
<> 149:156823d33999 8291 #define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */
<> 149:156823d33999 8292 #define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */
<> 149:156823d33999 8293
<> 149:156823d33999 8294 #define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */
<> 149:156823d33999 8295 #define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */
<> 149:156823d33999 8296
<> 149:156823d33999 8297 #define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */
<> 149:156823d33999 8298 #define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */
<> 149:156823d33999 8299
<> 149:156823d33999 8300 #define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */
<> 149:156823d33999 8301 #define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */
<> 149:156823d33999 8302
<> 149:156823d33999 8303 #define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */
<> 149:156823d33999 8304 #define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */
<> 149:156823d33999 8305
<> 149:156823d33999 8306 #define PWM_INTEN0_ZIENn_Pos (0) /*!< PWM_T::INTEN0: ZIENn Position */
<> 149:156823d33999 8307 #define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) /*!< PWM_T::INTEN0: ZIENn Mask */
<> 149:156823d33999 8308
<> 149:156823d33999 8309 #define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */
<> 149:156823d33999 8310 #define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */
<> 149:156823d33999 8311
<> 149:156823d33999 8312 #define PWM_INTEN0_ZIEN1_Pos (1) /*!< PWM_T::INTEN0: ZIEN1 Position */
<> 149:156823d33999 8313 #define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) /*!< PWM_T::INTEN0: ZIEN1 Mask */
<> 149:156823d33999 8314
<> 149:156823d33999 8315 #define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */
<> 149:156823d33999 8316 #define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */
<> 149:156823d33999 8317
<> 149:156823d33999 8318 #define PWM_INTEN0_ZIEN3_Pos (3) /*!< PWM_T::INTEN0: ZIEN3 Position */
<> 149:156823d33999 8319 #define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) /*!< PWM_T::INTEN0: ZIEN3 Mask */
<> 149:156823d33999 8320
<> 149:156823d33999 8321 #define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */
<> 149:156823d33999 8322 #define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */
<> 149:156823d33999 8323
<> 149:156823d33999 8324 #define PWM_INTEN0_ZIEN5_Pos (5) /*!< PWM_T::INTEN0: ZIEN5 Position */
<> 149:156823d33999 8325 #define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) /*!< PWM_T::INTEN0: ZIEN5 Mask */
<> 149:156823d33999 8326
<> 149:156823d33999 8327 #define PWM_INTEN0_IFAIEN0_1_Pos (7) /*!< PWM_T::INTEN0: IFAIEN0_1 Position */
<> 149:156823d33999 8328 #define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) /*!< PWM_T::INTEN0: IFAIEN0_1 Mask */
<> 149:156823d33999 8329
<> 149:156823d33999 8330 #define PWM_INTEN0_PIENn_Pos (8) /*!< PWM_T::INTEN0: PIENn Position */
<> 149:156823d33999 8331 #define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) /*!< PWM_T::INTEN0: PIENn Mask */
<> 149:156823d33999 8332
<> 149:156823d33999 8333 #define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */
<> 149:156823d33999 8334 #define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */
<> 149:156823d33999 8335
<> 149:156823d33999 8336 #define PWM_INTEN0_PIEN1_Pos (9) /*!< PWM_T::INTEN0: PIEN1 Position */
<> 149:156823d33999 8337 #define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) /*!< PWM_T::INTEN0: PIEN1 Mask */
<> 149:156823d33999 8338
<> 149:156823d33999 8339 #define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */
<> 149:156823d33999 8340 #define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */
<> 149:156823d33999 8341
<> 149:156823d33999 8342 #define PWM_INTEN0_PIEN3_Pos (11) /*!< PWM_T::INTEN0: PIEN3 Position */
<> 149:156823d33999 8343 #define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) /*!< PWM_T::INTEN0: PIEN3 Mask */
<> 149:156823d33999 8344
<> 149:156823d33999 8345 #define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */
<> 149:156823d33999 8346 #define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */
<> 149:156823d33999 8347
<> 149:156823d33999 8348 #define PWM_INTEN0_PIEN5_Pos (13) /*!< PWM_T::INTEN0: PIEN5 Position */
<> 149:156823d33999 8349 #define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) /*!< PWM_T::INTEN0: PIEN5 Mask */
<> 149:156823d33999 8350
<> 149:156823d33999 8351 #define PWM_INTEN0_IFAIEN2_3_Pos (15) /*!< PWM_T::INTEN0: IFAIEN2_3 Position */
<> 149:156823d33999 8352 #define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) /*!< PWM_T::INTEN0: IFAIEN2_3 Mask */
<> 149:156823d33999 8353
<> 149:156823d33999 8354 #define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */
<> 149:156823d33999 8355 #define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */
<> 149:156823d33999 8356
<> 149:156823d33999 8357 #define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */
<> 149:156823d33999 8358 #define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */
<> 149:156823d33999 8359
<> 149:156823d33999 8360 #define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */
<> 149:156823d33999 8361 #define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */
<> 149:156823d33999 8362
<> 149:156823d33999 8363 #define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */
<> 149:156823d33999 8364 #define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */
<> 149:156823d33999 8365
<> 149:156823d33999 8366 #define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */
<> 149:156823d33999 8367 #define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */
<> 149:156823d33999 8368
<> 149:156823d33999 8369 #define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */
<> 149:156823d33999 8370 #define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */
<> 149:156823d33999 8371
<> 149:156823d33999 8372 #define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */
<> 149:156823d33999 8373 #define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */
<> 149:156823d33999 8374
<> 149:156823d33999 8375 #define PWM_INTEN0_IFAIEN4_5_Pos (23) /*!< PWM_T::INTEN0: IFAIEN4_5 Position */
<> 149:156823d33999 8376 #define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) /*!< PWM_T::INTEN0: IFAIEN4_5 Mask */
<> 149:156823d33999 8377
<> 149:156823d33999 8378 #define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */
<> 149:156823d33999 8379 #define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */
<> 149:156823d33999 8380
<> 149:156823d33999 8381 #define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */
<> 149:156823d33999 8382 #define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */
<> 149:156823d33999 8383
<> 149:156823d33999 8384 #define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */
<> 149:156823d33999 8385 #define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */
<> 149:156823d33999 8386
<> 149:156823d33999 8387 #define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */
<> 149:156823d33999 8388 #define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */
<> 149:156823d33999 8389
<> 149:156823d33999 8390 #define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */
<> 149:156823d33999 8391 #define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */
<> 149:156823d33999 8392
<> 149:156823d33999 8393 #define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */
<> 149:156823d33999 8394 #define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */
<> 149:156823d33999 8395
<> 149:156823d33999 8396 #define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */
<> 149:156823d33999 8397 #define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */
<> 149:156823d33999 8398
<> 149:156823d33999 8399 #define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */
<> 149:156823d33999 8400 #define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */
<> 149:156823d33999 8401
<> 149:156823d33999 8402 #define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */
<> 149:156823d33999 8403 #define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */
<> 149:156823d33999 8404
<> 149:156823d33999 8405 #define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */
<> 149:156823d33999 8406 #define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */
<> 149:156823d33999 8407
<> 149:156823d33999 8408 #define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */
<> 149:156823d33999 8409 #define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */
<> 149:156823d33999 8410
<> 149:156823d33999 8411 #define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */
<> 149:156823d33999 8412 #define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */
<> 149:156823d33999 8413
<> 149:156823d33999 8414 #define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */
<> 149:156823d33999 8415 #define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */
<> 149:156823d33999 8416
<> 149:156823d33999 8417 #define PWM_INTSTS0_ZIFn_Pos (0) /*!< PWM_T::INTSTS0: ZIFn Position */
<> 149:156823d33999 8418 #define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) /*!< PWM_T::INTSTS0: ZIFn Mask */
<> 149:156823d33999 8419
<> 149:156823d33999 8420 #define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */
<> 149:156823d33999 8421 #define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */
<> 149:156823d33999 8422
<> 149:156823d33999 8423 #define PWM_INTSTS0_ZIF1_Pos (1) /*!< PWM_T::INTSTS0: ZIF1 Position */
<> 149:156823d33999 8424 #define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) /*!< PWM_T::INTSTS0: ZIF1 Mask */
<> 149:156823d33999 8425
<> 149:156823d33999 8426 #define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */
<> 149:156823d33999 8427 #define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */
<> 149:156823d33999 8428
<> 149:156823d33999 8429 #define PWM_INTSTS0_ZIF3_Pos (3) /*!< PWM_T::INTSTS0: ZIF3 Position */
<> 149:156823d33999 8430 #define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) /*!< PWM_T::INTSTS0: ZIF3 Mask */
<> 149:156823d33999 8431
<> 149:156823d33999 8432 #define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */
<> 149:156823d33999 8433 #define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */
<> 149:156823d33999 8434
<> 149:156823d33999 8435 #define PWM_INTSTS0_ZIF5_Pos (5) /*!< PWM_T::INTSTS0: ZIF5 Position */
<> 149:156823d33999 8436 #define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) /*!< PWM_T::INTSTS0: ZIF5 Mask */
<> 149:156823d33999 8437
<> 149:156823d33999 8438 #define PWM_INTSTS0_IFAIF0_1_Pos (7) /*!< PWM_T::INTSTS0: IFAIF0_1 Position */
<> 149:156823d33999 8439 #define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) /*!< PWM_T::INTSTS0: IFAIF0_1 Mask */
<> 149:156823d33999 8440
<> 149:156823d33999 8441 #define PWM_INTSTS0_PIFn_Pos (8) /*!< PWM_T::INTSTS0: PIFn Position */
<> 149:156823d33999 8442 #define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) /*!< PWM_T::INTSTS0: PIFn Mask */
<> 149:156823d33999 8443
<> 149:156823d33999 8444 #define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */
<> 149:156823d33999 8445 #define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */
<> 149:156823d33999 8446
<> 149:156823d33999 8447 #define PWM_INTSTS0_PIF1_Pos (9) /*!< PWM_T::INTSTS0: PIF1 Position */
<> 149:156823d33999 8448 #define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) /*!< PWM_T::INTSTS0: PIF1 Mask */
<> 149:156823d33999 8449
<> 149:156823d33999 8450 #define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */
<> 149:156823d33999 8451 #define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */
<> 149:156823d33999 8452
<> 149:156823d33999 8453 #define PWM_INTSTS0_PIF3_Pos (11) /*!< PWM_T::INTSTS0: PIF3 Position */
<> 149:156823d33999 8454 #define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) /*!< PWM_T::INTSTS0: PIF3 Mask */
<> 149:156823d33999 8455
<> 149:156823d33999 8456 #define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */
<> 149:156823d33999 8457 #define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */
<> 149:156823d33999 8458
<> 149:156823d33999 8459 #define PWM_INTSTS0_PIF5_Pos (13) /*!< PWM_T::INTSTS0: PIF5 Position */
<> 149:156823d33999 8460 #define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) /*!< PWM_T::INTSTS0: PIF5 Mask */
<> 149:156823d33999 8461
<> 149:156823d33999 8462 #define PWM_INTSTS0_IFAIF2_3_Pos (15) /*!< PWM_T::INTSTS0: IFAIF2_3 Position */
<> 149:156823d33999 8463 #define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) /*!< PWM_T::INTSTS0: IFAIF2_3 Mask */
<> 149:156823d33999 8464
<> 149:156823d33999 8465 #define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */
<> 149:156823d33999 8466 #define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */
<> 149:156823d33999 8467
<> 149:156823d33999 8468 #define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */
<> 149:156823d33999 8469 #define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */
<> 149:156823d33999 8470
<> 149:156823d33999 8471 #define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */
<> 149:156823d33999 8472 #define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */
<> 149:156823d33999 8473
<> 149:156823d33999 8474 #define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */
<> 149:156823d33999 8475 #define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */
<> 149:156823d33999 8476
<> 149:156823d33999 8477 #define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */
<> 149:156823d33999 8478 #define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */
<> 149:156823d33999 8479
<> 149:156823d33999 8480 #define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */
<> 149:156823d33999 8481 #define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */
<> 149:156823d33999 8482
<> 149:156823d33999 8483 #define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */
<> 149:156823d33999 8484 #define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */
<> 149:156823d33999 8485
<> 149:156823d33999 8486 #define PWM_INTSTS0_IFAIF4_5_Pos (23) /*!< PWM_T::INTSTS0: IFAIF4_5 Position */
<> 149:156823d33999 8487 #define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) /*!< PWM_T::INTSTS0: IFAIF4_5 Mask */
<> 149:156823d33999 8488
<> 149:156823d33999 8489 #define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */
<> 149:156823d33999 8490 #define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */
<> 149:156823d33999 8491
<> 149:156823d33999 8492 #define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */
<> 149:156823d33999 8493 #define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */
<> 149:156823d33999 8494
<> 149:156823d33999 8495 #define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */
<> 149:156823d33999 8496 #define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */
<> 149:156823d33999 8497
<> 149:156823d33999 8498 #define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */
<> 149:156823d33999 8499 #define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */
<> 149:156823d33999 8500
<> 149:156823d33999 8501 #define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */
<> 149:156823d33999 8502 #define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */
<> 149:156823d33999 8503
<> 149:156823d33999 8504 #define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */
<> 149:156823d33999 8505 #define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */
<> 149:156823d33999 8506
<> 149:156823d33999 8507 #define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */
<> 149:156823d33999 8508 #define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */
<> 149:156823d33999 8509
<> 149:156823d33999 8510 #define PWM_INTSTS1_BRKEIFn_Pos (0) /*!< PWM_T::INTSTS1: BRKEIFn Position */
<> 149:156823d33999 8511 #define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) /*!< PWM_T::INTSTS1: BRKEIFn Mask */
<> 149:156823d33999 8512
<> 149:156823d33999 8513 #define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */
<> 149:156823d33999 8514 #define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */
<> 149:156823d33999 8515
<> 149:156823d33999 8516 #define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */
<> 149:156823d33999 8517 #define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */
<> 149:156823d33999 8518
<> 149:156823d33999 8519 #define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */
<> 149:156823d33999 8520 #define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */
<> 149:156823d33999 8521
<> 149:156823d33999 8522 #define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */
<> 149:156823d33999 8523 #define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */
<> 149:156823d33999 8524
<> 149:156823d33999 8525 #define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */
<> 149:156823d33999 8526 #define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */
<> 149:156823d33999 8527
<> 149:156823d33999 8528 #define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */
<> 149:156823d33999 8529 #define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */
<> 149:156823d33999 8530
<> 149:156823d33999 8531 #define PWM_INTSTS1_BRKLIFn_Pos (8) /*!< PWM_T::INTSTS1: BRKLIFn Position */
<> 149:156823d33999 8532 #define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) /*!< PWM_T::INTSTS1: BRKLIFn Mask */
<> 149:156823d33999 8533
<> 149:156823d33999 8534 #define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */
<> 149:156823d33999 8535 #define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */
<> 149:156823d33999 8536
<> 149:156823d33999 8537 #define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */
<> 149:156823d33999 8538 #define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */
<> 149:156823d33999 8539
<> 149:156823d33999 8540 #define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */
<> 149:156823d33999 8541 #define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */
<> 149:156823d33999 8542
<> 149:156823d33999 8543 #define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */
<> 149:156823d33999 8544 #define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */
<> 149:156823d33999 8545
<> 149:156823d33999 8546 #define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */
<> 149:156823d33999 8547 #define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */
<> 149:156823d33999 8548
<> 149:156823d33999 8549 #define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */
<> 149:156823d33999 8550 #define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */
<> 149:156823d33999 8551
<> 149:156823d33999 8552 #define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */
<> 149:156823d33999 8553 #define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */
<> 149:156823d33999 8554
<> 149:156823d33999 8555 #define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */
<> 149:156823d33999 8556 #define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */
<> 149:156823d33999 8557
<> 149:156823d33999 8558 #define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */
<> 149:156823d33999 8559 #define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */
<> 149:156823d33999 8560
<> 149:156823d33999 8561 #define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */
<> 149:156823d33999 8562 #define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */
<> 149:156823d33999 8563
<> 149:156823d33999 8564 #define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */
<> 149:156823d33999 8565 #define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */
<> 149:156823d33999 8566
<> 149:156823d33999 8567 #define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */
<> 149:156823d33999 8568 #define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */
<> 149:156823d33999 8569
<> 149:156823d33999 8570 #define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */
<> 149:156823d33999 8571 #define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */
<> 149:156823d33999 8572
<> 149:156823d33999 8573 #define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */
<> 149:156823d33999 8574 #define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */
<> 149:156823d33999 8575
<> 149:156823d33999 8576 #define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */
<> 149:156823d33999 8577 #define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */
<> 149:156823d33999 8578
<> 149:156823d33999 8579 #define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */
<> 149:156823d33999 8580 #define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */
<> 149:156823d33999 8581
<> 149:156823d33999 8582 #define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */
<> 149:156823d33999 8583 #define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */
<> 149:156823d33999 8584
<> 149:156823d33999 8585 #define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */
<> 149:156823d33999 8586 #define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */
<> 149:156823d33999 8587
<> 149:156823d33999 8588 #define PWM_IFA_IFCNT0_1_Pos (0) /*!< PWM_T::IFA: IFCNT0_1 Position */
<> 149:156823d33999 8589 #define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) /*!< PWM_T::IFA: IFCNT0_1 Mask */
<> 149:156823d33999 8590
<> 149:156823d33999 8591 #define PWM_IFA_IFSEL0_1_Pos (4) /*!< PWM_T::IFA: IFSEL0_1 Position */
<> 149:156823d33999 8592 #define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) /*!< PWM_T::IFA: IFSEL0_1 Mask */
<> 149:156823d33999 8593
<> 149:156823d33999 8594 #define PWM_IFA_IFAEN0_1_Pos (7) /*!< PWM_T::IFA: IFAEN0_1 Position */
<> 149:156823d33999 8595 #define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) /*!< PWM_T::IFA: IFAEN0_1 Mask */
<> 149:156823d33999 8596
<> 149:156823d33999 8597 #define PWM_IFA_IFCNT2_3_Pos (8) /*!< PWM_T::IFA: IFCNT2_3 Position */
<> 149:156823d33999 8598 #define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) /*!< PWM_T::IFA: IFCNT2_3 Mask */
<> 149:156823d33999 8599
<> 149:156823d33999 8600 #define PWM_IFA_IFSEL2_3_Pos (12) /*!< PWM_T::IFA: IFSEL2_3 Position */
<> 149:156823d33999 8601 #define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) /*!< PWM_T::IFA: IFSEL2_3 Mask */
<> 149:156823d33999 8602
<> 149:156823d33999 8603 #define PWM_IFA_IFAEN2_3_Pos (15) /*!< PWM_T::IFA: IFAEN2_3 Position */
<> 149:156823d33999 8604 #define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) /*!< PWM_T::IFA: IFAEN2_3 Mask */
<> 149:156823d33999 8605
<> 149:156823d33999 8606 #define PWM_IFA_IFCNT4_5_Pos (16) /*!< PWM_T::IFA: IFCNT4_5 Position */
<> 149:156823d33999 8607 #define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) /*!< PWM_T::IFA: IFCNT4_5 Mask */
<> 149:156823d33999 8608
<> 149:156823d33999 8609 #define PWM_IFA_IFSEL4_5_Pos (20) /*!< PWM_T::IFA: IFSEL4_5 Position */
<> 149:156823d33999 8610 #define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) /*!< PWM_T::IFA: IFSEL4_5 Mask */
<> 149:156823d33999 8611
<> 149:156823d33999 8612 #define PWM_IFA_IFAEN4_5_Pos (23) /*!< PWM_T::IFA: IFAEN4_5 Position */
<> 149:156823d33999 8613 #define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) /*!< PWM_T::IFA: IFAEN4_5 Mask */
<> 149:156823d33999 8614
<> 149:156823d33999 8615 #define PWM_DACTRGEN_ZTEn_Pos (0) /*!< PWM_T::DACTRGEN: ZTEn Position */
<> 149:156823d33999 8616 #define PWM_DACTRGEN_ZTEn_Msk (0x3ful << PWM_DACTRGEN_ZTEn_Pos) /*!< PWM_T::DACTRGEN: ZTEn Mask */
<> 149:156823d33999 8617
<> 149:156823d33999 8618 #define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */
<> 149:156823d33999 8619 #define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */
<> 149:156823d33999 8620
<> 149:156823d33999 8621 #define PWM_DACTRGEN_ZTE1_Pos (1) /*!< PWM_T::DACTRGEN: ZTE1 Position */
<> 149:156823d33999 8622 #define PWM_DACTRGEN_ZTE1_Msk (0x1ul << PWM_DACTRGEN_ZTE1_Pos) /*!< PWM_T::DACTRGEN: ZTE1 Mask */
<> 149:156823d33999 8623
<> 149:156823d33999 8624 #define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */
<> 149:156823d33999 8625 #define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */
<> 149:156823d33999 8626
<> 149:156823d33999 8627 #define PWM_DACTRGEN_ZTE3_Pos (3) /*!< PWM_T::DACTRGEN: ZTE3 Position */
<> 149:156823d33999 8628 #define PWM_DACTRGEN_ZTE3_Msk (0x1ul << PWM_DACTRGEN_ZTE3_Pos) /*!< PWM_T::DACTRGEN: ZTE3 Mask */
<> 149:156823d33999 8629
<> 149:156823d33999 8630 #define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */
<> 149:156823d33999 8631 #define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */
<> 149:156823d33999 8632
<> 149:156823d33999 8633 #define PWM_DACTRGEN_ZTE5_Pos (5) /*!< PWM_T::DACTRGEN: ZTE5 Position */
<> 149:156823d33999 8634 #define PWM_DACTRGEN_ZTE5_Msk (0x1ul << PWM_DACTRGEN_ZTE5_Pos) /*!< PWM_T::DACTRGEN: ZTE5 Mask */
<> 149:156823d33999 8635
<> 149:156823d33999 8636 #define PWM_DACTRGEN_PTEn_Pos (8) /*!< PWM_T::DACTRGEN: PTEn Position */
<> 149:156823d33999 8637 #define PWM_DACTRGEN_PTEn_Msk (0x3ful << PWM_DACTRGEN_PTEn_Pos) /*!< PWM_T::DACTRGEN: PTEn Mask */
<> 149:156823d33999 8638
<> 149:156823d33999 8639 #define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */
<> 149:156823d33999 8640 #define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */
<> 149:156823d33999 8641
<> 149:156823d33999 8642 #define PWM_DACTRGEN_PTE1_Pos (9) /*!< PWM_T::DACTRGEN: PTE1 Position */
<> 149:156823d33999 8643 #define PWM_DACTRGEN_PTE1_Msk (0x1ul << PWM_DACTRGEN_PTE1_Pos) /*!< PWM_T::DACTRGEN: PTE1 Mask */
<> 149:156823d33999 8644
<> 149:156823d33999 8645 #define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */
<> 149:156823d33999 8646 #define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */
<> 149:156823d33999 8647
<> 149:156823d33999 8648 #define PWM_DACTRGEN_PTE3_Pos (11) /*!< PWM_T::DACTRGEN: PTE3 Position */
<> 149:156823d33999 8649 #define PWM_DACTRGEN_PTE3_Msk (0x1ul << PWM_DACTRGEN_PTE3_Pos) /*!< PWM_T::DACTRGEN: PTE3 Mask */
<> 149:156823d33999 8650
<> 149:156823d33999 8651 #define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */
<> 149:156823d33999 8652 #define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */
<> 149:156823d33999 8653
<> 149:156823d33999 8654 #define PWM_DACTRGEN_PTE5_Pos (13) /*!< PWM_T::DACTRGEN: PTE5 Position */
<> 149:156823d33999 8655 #define PWM_DACTRGEN_PTE5_Msk (0x1ul << PWM_DACTRGEN_PTE5_Pos) /*!< PWM_T::DACTRGEN: PTE5 Mask */
<> 149:156823d33999 8656
<> 149:156823d33999 8657 #define PWM_DACTRGEN_CUTRGEn_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEn Position */
<> 149:156823d33999 8658 #define PWM_DACTRGEN_CUTRGEn_Msk (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos) /*!< PWM_T::DACTRGEN: CUTRGEn Mask */
<> 149:156823d33999 8659
<> 149:156823d33999 8660 #define PWM_DACTRGEN_CUTRGE0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGE0 Position */
<> 149:156823d33999 8661 #define PWM_DACTRGEN_CUTRGE0_Msk (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos) /*!< PWM_T::DACTRGEN: CUTRGE0 Mask */
<> 149:156823d33999 8662
<> 149:156823d33999 8663 #define PWM_DACTRGEN_CUTRGE1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGE1 Position */
<> 149:156823d33999 8664 #define PWM_DACTRGEN_CUTRGE1_Msk (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos) /*!< PWM_T::DACTRGEN: CUTRGE1 Mask */
<> 149:156823d33999 8665
<> 149:156823d33999 8666 #define PWM_DACTRGEN_CUTRGE2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGE2 Position */
<> 149:156823d33999 8667 #define PWM_DACTRGEN_CUTRGE2_Msk (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos) /*!< PWM_T::DACTRGEN: CUTRGE2 Mask */
<> 149:156823d33999 8668
<> 149:156823d33999 8669 #define PWM_DACTRGEN_CUTRGE3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGE3 Position */
<> 149:156823d33999 8670 #define PWM_DACTRGEN_CUTRGE3_Msk (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos) /*!< PWM_T::DACTRGEN: CUTRGE3 Mask */
<> 149:156823d33999 8671
<> 149:156823d33999 8672 #define PWM_DACTRGEN_CUTRGE4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGE4 Position */
<> 149:156823d33999 8673 #define PWM_DACTRGEN_CUTRGE4_Msk (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos) /*!< PWM_T::DACTRGEN: CUTRGE4 Mask */
<> 149:156823d33999 8674
<> 149:156823d33999 8675 #define PWM_DACTRGEN_CUTRGE5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGE5 Position */
<> 149:156823d33999 8676 #define PWM_DACTRGEN_CUTRGE5_Msk (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos) /*!< PWM_T::DACTRGEN: CUTRGE5 Mask */
<> 149:156823d33999 8677
<> 149:156823d33999 8678 #define PWM_DACTRGEN_CDTRGEn_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEn Position */
<> 149:156823d33999 8679 #define PWM_DACTRGEN_CDTRGEn_Msk (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos) /*!< PWM_T::DACTRGEN: CDTRGEn Mask */
<> 149:156823d33999 8680
<> 149:156823d33999 8681 #define PWM_DACTRGEN_CDTRGE0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGE0 Position */
<> 149:156823d33999 8682 #define PWM_DACTRGEN_CDTRGE0_Msk (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos) /*!< PWM_T::DACTRGEN: CDTRGE0 Mask */
<> 149:156823d33999 8683
<> 149:156823d33999 8684 #define PWM_DACTRGEN_CDTRGE1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGE1 Position */
<> 149:156823d33999 8685 #define PWM_DACTRGEN_CDTRGE1_Msk (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos) /*!< PWM_T::DACTRGEN: CDTRGE1 Mask */
<> 149:156823d33999 8686
<> 149:156823d33999 8687 #define PWM_DACTRGEN_CDTRGE2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGE2 Position */
<> 149:156823d33999 8688 #define PWM_DACTRGEN_CDTRGE2_Msk (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos) /*!< PWM_T::DACTRGEN: CDTRGE2 Mask */
<> 149:156823d33999 8689
<> 149:156823d33999 8690 #define PWM_DACTRGEN_CDTRGE3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGE3 Position */
<> 149:156823d33999 8691 #define PWM_DACTRGEN_CDTRGE3_Msk (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos) /*!< PWM_T::DACTRGEN: CDTRGE3 Mask */
<> 149:156823d33999 8692
<> 149:156823d33999 8693 #define PWM_DACTRGEN_CDTRGE4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGE4 Position */
<> 149:156823d33999 8694 #define PWM_DACTRGEN_CDTRGE4_Msk (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos) /*!< PWM_T::DACTRGEN: CDTRGE4 Mask */
<> 149:156823d33999 8695
<> 149:156823d33999 8696 #define PWM_DACTRGEN_CDTRGE5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGE5 Position */
<> 149:156823d33999 8697 #define PWM_DACTRGEN_CDTRGE5_Msk (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos) /*!< PWM_T::DACTRGEN: CDTRGE5 Mask */
<> 149:156823d33999 8698
<> 149:156823d33999 8699 #define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */
<> 149:156823d33999 8700 #define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */
<> 149:156823d33999 8701
<> 149:156823d33999 8702 #define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */
<> 149:156823d33999 8703 #define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */
<> 149:156823d33999 8704
<> 149:156823d33999 8705 #define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */
<> 149:156823d33999 8706 #define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */
<> 149:156823d33999 8707
<> 149:156823d33999 8708 #define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */
<> 149:156823d33999 8709 #define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */
<> 149:156823d33999 8710
<> 149:156823d33999 8711 #define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */
<> 149:156823d33999 8712 #define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */
<> 149:156823d33999 8713
<> 149:156823d33999 8714 #define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */
<> 149:156823d33999 8715 #define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */
<> 149:156823d33999 8716
<> 149:156823d33999 8717 #define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */
<> 149:156823d33999 8718 #define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */
<> 149:156823d33999 8719
<> 149:156823d33999 8720 #define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */
<> 149:156823d33999 8721 #define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */
<> 149:156823d33999 8722
<> 149:156823d33999 8723 #define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */
<> 149:156823d33999 8724 #define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */
<> 149:156823d33999 8725
<> 149:156823d33999 8726 #define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */
<> 149:156823d33999 8727 #define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */
<> 149:156823d33999 8728
<> 149:156823d33999 8729 #define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */
<> 149:156823d33999 8730 #define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */
<> 149:156823d33999 8731
<> 149:156823d33999 8732 #define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */
<> 149:156823d33999 8733 #define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */
<> 149:156823d33999 8734
<> 149:156823d33999 8735 #define PWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT0_1: FTCMP Position */
<> 149:156823d33999 8736 #define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask */
<> 149:156823d33999 8737
<> 149:156823d33999 8738 #define PWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT2_3: FTCMP Position */
<> 149:156823d33999 8739 #define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask */
<> 149:156823d33999 8740
<> 149:156823d33999 8741 #define PWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT4_5: FTCMP Position */
<> 149:156823d33999 8742 #define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask */
<> 149:156823d33999 8743
<> 149:156823d33999 8744 #define PWM_SSCTL_SSENn_Pos (0) /*!< PWM_T::SSCTL: SSENn Position */
<> 149:156823d33999 8745 #define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) /*!< PWM_T::SSCTL: SSENn Mask */
<> 149:156823d33999 8746
<> 149:156823d33999 8747 #define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */
<> 149:156823d33999 8748 #define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */
<> 149:156823d33999 8749
<> 149:156823d33999 8750 #define PWM_SSCTL_SSEN1_Pos (1) /*!< PWM_T::SSCTL: SSEN1 Position */
<> 149:156823d33999 8751 #define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) /*!< PWM_T::SSCTL: SSEN1 Mask */
<> 149:156823d33999 8752
<> 149:156823d33999 8753 #define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */
<> 149:156823d33999 8754 #define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */
<> 149:156823d33999 8755
<> 149:156823d33999 8756 #define PWM_SSCTL_SSEN3_Pos (3) /*!< PWM_T::SSCTL: SSEN3 Position */
<> 149:156823d33999 8757 #define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) /*!< PWM_T::SSCTL: SSEN3 Mask */
<> 149:156823d33999 8758
<> 149:156823d33999 8759 #define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */
<> 149:156823d33999 8760 #define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */
<> 149:156823d33999 8761
<> 149:156823d33999 8762 #define PWM_SSCTL_SSEN5_Pos (5) /*!< PWM_T::SSCTL: SSEN5 Position */
<> 149:156823d33999 8763 #define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) /*!< PWM_T::SSCTL: SSEN5 Mask */
<> 149:156823d33999 8764
<> 149:156823d33999 8765 #define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */
<> 149:156823d33999 8766 #define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */
<> 149:156823d33999 8767
<> 149:156823d33999 8768 #define PWM_STATUS_CNTMAXFn_Pos (0) /*!< PWM_T::STATUS: CNTMAXFn Position */
<> 149:156823d33999 8769 #define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) /*!< PWM_T::STATUS: CNTMAXFn Mask */
<> 149:156823d33999 8770
<> 149:156823d33999 8771 #define PWM_STATUS_CNTMAXF0_Pos (0) /*!< PWM_T::STATUS: CNTMAXF0 Position */
<> 149:156823d33999 8772 #define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) /*!< PWM_T::STATUS: CNTMAXF0 Mask */
<> 149:156823d33999 8773
<> 149:156823d33999 8774 #define PWM_STATUS_CNTMAXF1_Pos (1) /*!< PWM_T::STATUS: CNTMAXF1 Position */
<> 149:156823d33999 8775 #define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) /*!< PWM_T::STATUS: CNTMAXF1 Mask */
<> 149:156823d33999 8776
<> 149:156823d33999 8777 #define PWM_STATUS_CNTMAXF2_Pos (2) /*!< PWM_T::STATUS: CNTMAXF2 Position */
<> 149:156823d33999 8778 #define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) /*!< PWM_T::STATUS: CNTMAXF2 Mask */
<> 149:156823d33999 8779
<> 149:156823d33999 8780 #define PWM_STATUS_CNTMAXF3_Pos (3) /*!< PWM_T::STATUS: CNTMAXF3 Position */
<> 149:156823d33999 8781 #define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) /*!< PWM_T::STATUS: CNTMAXF3 Mask */
<> 149:156823d33999 8782
<> 149:156823d33999 8783 #define PWM_STATUS_CNTMAXF4_Pos (4) /*!< PWM_T::STATUS: CNTMAXF4 Position */
<> 149:156823d33999 8784 #define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) /*!< PWM_T::STATUS: CNTMAXF4 Mask */
<> 149:156823d33999 8785
<> 149:156823d33999 8786 #define PWM_STATUS_CNTMAXF5_Pos (5) /*!< PWM_T::STATUS: CNTMAXF5 Position */
<> 149:156823d33999 8787 #define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) /*!< PWM_T::STATUS: CNTMAXF5 Mask */
<> 149:156823d33999 8788
<> 149:156823d33999 8789 #define PWM_STATUS_SYNCINFn_Pos (8) /*!< PWM_T::STATUS: SYNCINFn Position */
<> 149:156823d33999 8790 #define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) /*!< PWM_T::STATUS: SYNCINFn Mask */
<> 149:156823d33999 8791
<> 149:156823d33999 8792 #define PWM_STATUS_SYNCINF0_Pos (8) /*!< PWM_T::STATUS: SYNCINF0 Position */
<> 149:156823d33999 8793 #define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) /*!< PWM_T::STATUS: SYNCINF0 Mask */
<> 149:156823d33999 8794
<> 149:156823d33999 8795 #define PWM_STATUS_SYNCINF2_Pos (9) /*!< PWM_T::STATUS: SYNCINF2 Position */
<> 149:156823d33999 8796 #define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) /*!< PWM_T::STATUS: SYNCINF2 Mask */
<> 149:156823d33999 8797
<> 149:156823d33999 8798 #define PWM_STATUS_SYNCINF4_Pos (10) /*!< PWM_T::STATUS: SYNCINF4 Position */
<> 149:156823d33999 8799 #define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) /*!< PWM_T::STATUS: SYNCINF4 Mask */
<> 149:156823d33999 8800
<> 149:156823d33999 8801 #define PWM_STATUS_ADCTRGFn_Pos (16) /*!< PWM_T::STATUS: ADCTRGFn Position */
<> 149:156823d33999 8802 #define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) /*!< PWM_T::STATUS: ADCTRGFn Mask */
<> 149:156823d33999 8803
<> 149:156823d33999 8804 #define PWM_STATUS_ADCTRGF0_Pos (16) /*!< PWM_T::STATUS: ADCTRGF0 Position */
<> 149:156823d33999 8805 #define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) /*!< PWM_T::STATUS: ADCTRGF0 Mask */
<> 149:156823d33999 8806
<> 149:156823d33999 8807 #define PWM_STATUS_ADCTRGF1_Pos (17) /*!< PWM_T::STATUS: ADCTRGF1 Position */
<> 149:156823d33999 8808 #define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) /*!< PWM_T::STATUS: ADCTRGF1 Mask */
<> 149:156823d33999 8809
<> 149:156823d33999 8810 #define PWM_STATUS_ADCTRGF2_Pos (18) /*!< PWM_T::STATUS: ADCTRGF2 Position */
<> 149:156823d33999 8811 #define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) /*!< PWM_T::STATUS: ADCTRGF2 Mask */
<> 149:156823d33999 8812
<> 149:156823d33999 8813 #define PWM_STATUS_ADCTRGF3_Pos (19) /*!< PWM_T::STATUS: ADCTRGF3 Position */
<> 149:156823d33999 8814 #define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) /*!< PWM_T::STATUS: ADCTRGF3 Mask */
<> 149:156823d33999 8815
<> 149:156823d33999 8816 #define PWM_STATUS_ADCTRGF4_Pos (20) /*!< PWM_T::STATUS: ADCTRGF4 Position */
<> 149:156823d33999 8817 #define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) /*!< PWM_T::STATUS: ADCTRGF4 Mask */
<> 149:156823d33999 8818
<> 149:156823d33999 8819 #define PWM_STATUS_ADCTRGF5_Pos (21) /*!< PWM_T::STATUS: ADCTRGF5 Position */
<> 149:156823d33999 8820 #define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) /*!< PWM_T::STATUS: ADCTRGF5 Mask */
<> 149:156823d33999 8821
<> 149:156823d33999 8822 #define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */
<> 149:156823d33999 8823 #define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */
<> 149:156823d33999 8824
<> 149:156823d33999 8825 #define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */
<> 149:156823d33999 8826 #define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */
<> 149:156823d33999 8827
<> 149:156823d33999 8828 #define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */
<> 149:156823d33999 8829 #define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */
<> 149:156823d33999 8830
<> 149:156823d33999 8831 #define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */
<> 149:156823d33999 8832 #define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */
<> 149:156823d33999 8833
<> 149:156823d33999 8834 #define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */
<> 149:156823d33999 8835 #define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */
<> 149:156823d33999 8836
<> 149:156823d33999 8837 #define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */
<> 149:156823d33999 8838 #define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */
<> 149:156823d33999 8839
<> 149:156823d33999 8840 #define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */
<> 149:156823d33999 8841 #define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */
<> 149:156823d33999 8842
<> 149:156823d33999 8843 #define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */
<> 149:156823d33999 8844 #define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */
<> 149:156823d33999 8845
<> 149:156823d33999 8846 #define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */
<> 149:156823d33999 8847 #define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */
<> 149:156823d33999 8848
<> 149:156823d33999 8849 #define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */
<> 149:156823d33999 8850 #define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */
<> 149:156823d33999 8851
<> 149:156823d33999 8852 #define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */
<> 149:156823d33999 8853 #define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */
<> 149:156823d33999 8854
<> 149:156823d33999 8855 #define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */
<> 149:156823d33999 8856 #define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */
<> 149:156823d33999 8857
<> 149:156823d33999 8858 #define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */
<> 149:156823d33999 8859 #define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */
<> 149:156823d33999 8860
<> 149:156823d33999 8861 #define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */
<> 149:156823d33999 8862 #define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */
<> 149:156823d33999 8863
<> 149:156823d33999 8864 #define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */
<> 149:156823d33999 8865 #define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */
<> 149:156823d33999 8866
<> 149:156823d33999 8867 #define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */
<> 149:156823d33999 8868 #define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */
<> 149:156823d33999 8869
<> 149:156823d33999 8870 #define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */
<> 149:156823d33999 8871 #define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */
<> 149:156823d33999 8872
<> 149:156823d33999 8873 #define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */
<> 149:156823d33999 8874 #define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */
<> 149:156823d33999 8875
<> 149:156823d33999 8876 #define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */
<> 149:156823d33999 8877 #define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */
<> 149:156823d33999 8878
<> 149:156823d33999 8879 #define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */
<> 149:156823d33999 8880 #define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */
<> 149:156823d33999 8881
<> 149:156823d33999 8882 #define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */
<> 149:156823d33999 8883 #define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */
<> 149:156823d33999 8884
<> 149:156823d33999 8885 #define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */
<> 149:156823d33999 8886 #define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */
<> 149:156823d33999 8887
<> 149:156823d33999 8888 #define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */
<> 149:156823d33999 8889 #define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */
<> 149:156823d33999 8890
<> 149:156823d33999 8891 #define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */
<> 149:156823d33999 8892 #define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */
<> 149:156823d33999 8893
<> 149:156823d33999 8894 #define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */
<> 149:156823d33999 8895 #define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */
<> 149:156823d33999 8896
<> 149:156823d33999 8897 #define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */
<> 149:156823d33999 8898 #define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */
<> 149:156823d33999 8899
<> 149:156823d33999 8900 #define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */
<> 149:156823d33999 8901 #define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */
<> 149:156823d33999 8902
<> 149:156823d33999 8903 #define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */
<> 149:156823d33999 8904 #define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */
<> 149:156823d33999 8905
<> 149:156823d33999 8906 #define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */
<> 149:156823d33999 8907 #define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */
<> 149:156823d33999 8908
<> 149:156823d33999 8909 #define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */
<> 149:156823d33999 8910 #define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */
<> 149:156823d33999 8911
<> 149:156823d33999 8912 #define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */
<> 149:156823d33999 8913 #define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */
<> 149:156823d33999 8914
<> 149:156823d33999 8915 #define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */
<> 149:156823d33999 8916 #define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */
<> 149:156823d33999 8917
<> 149:156823d33999 8918 #define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */
<> 149:156823d33999 8919 #define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */
<> 149:156823d33999 8920
<> 149:156823d33999 8921 #define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */
<> 149:156823d33999 8922 #define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */
<> 149:156823d33999 8923
<> 149:156823d33999 8924 #define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */
<> 149:156823d33999 8925 #define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */
<> 149:156823d33999 8926
<> 149:156823d33999 8927 #define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */
<> 149:156823d33999 8928 #define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */
<> 149:156823d33999 8929
<> 149:156823d33999 8930 #define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */
<> 149:156823d33999 8931 #define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */
<> 149:156823d33999 8932
<> 149:156823d33999 8933 #define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */
<> 149:156823d33999 8934 #define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */
<> 149:156823d33999 8935
<> 149:156823d33999 8936 #define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */
<> 149:156823d33999 8937 #define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */
<> 149:156823d33999 8938
<> 149:156823d33999 8939 #define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */
<> 149:156823d33999 8940 #define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */
<> 149:156823d33999 8941
<> 149:156823d33999 8942 #define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */
<> 149:156823d33999 8943 #define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */
<> 149:156823d33999 8944
<> 149:156823d33999 8945 #define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */
<> 149:156823d33999 8946 #define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */
<> 149:156823d33999 8947
<> 149:156823d33999 8948 #define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */
<> 149:156823d33999 8949 #define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */
<> 149:156823d33999 8950
<> 149:156823d33999 8951 #define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */
<> 149:156823d33999 8952 #define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */
<> 149:156823d33999 8953
<> 149:156823d33999 8954 #define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */
<> 149:156823d33999 8955 #define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */
<> 149:156823d33999 8956
<> 149:156823d33999 8957 #define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */
<> 149:156823d33999 8958 #define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */
<> 149:156823d33999 8959
<> 149:156823d33999 8960 #define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */
<> 149:156823d33999 8961 #define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */
<> 149:156823d33999 8962
<> 149:156823d33999 8963 #define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */
<> 149:156823d33999 8964 #define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */
<> 149:156823d33999 8965
<> 149:156823d33999 8966 #define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */
<> 149:156823d33999 8967 #define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */
<> 149:156823d33999 8968
<> 149:156823d33999 8969 #define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */
<> 149:156823d33999 8970 #define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */
<> 149:156823d33999 8971
<> 149:156823d33999 8972 #define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */
<> 149:156823d33999 8973 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */
<> 149:156823d33999 8974
<> 149:156823d33999 8975 #define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */
<> 149:156823d33999 8976 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */
<> 149:156823d33999 8977
<> 149:156823d33999 8978 #define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */
<> 149:156823d33999 8979 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */
<> 149:156823d33999 8980
<> 149:156823d33999 8981 #define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */
<> 149:156823d33999 8982 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */
<> 149:156823d33999 8983
<> 149:156823d33999 8984 #define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */
<> 149:156823d33999 8985 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */
<> 149:156823d33999 8986
<> 149:156823d33999 8987 #define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */
<> 149:156823d33999 8988 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */
<> 149:156823d33999 8989
<> 149:156823d33999 8990 #define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */
<> 149:156823d33999 8991 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */
<> 149:156823d33999 8992
<> 149:156823d33999 8993 #define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */
<> 149:156823d33999 8994 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */
<> 149:156823d33999 8995
<> 149:156823d33999 8996 #define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */
<> 149:156823d33999 8997 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */
<> 149:156823d33999 8998
<> 149:156823d33999 8999 #define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */
<> 149:156823d33999 9000 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */
<> 149:156823d33999 9001
<> 149:156823d33999 9002 #define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */
<> 149:156823d33999 9003 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */
<> 149:156823d33999 9004
<> 149:156823d33999 9005 #define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */
<> 149:156823d33999 9006 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */
<> 149:156823d33999 9007
<> 149:156823d33999 9008 #define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */
<> 149:156823d33999 9009 #define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */
<> 149:156823d33999 9010
<> 149:156823d33999 9011 #define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */
<> 149:156823d33999 9012 #define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */
<> 149:156823d33999 9013
<> 149:156823d33999 9014 #define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */
<> 149:156823d33999 9015 #define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */
<> 149:156823d33999 9016
<> 149:156823d33999 9017 #define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */
<> 149:156823d33999 9018 #define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */
<> 149:156823d33999 9019
<> 149:156823d33999 9020 #define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */
<> 149:156823d33999 9021 #define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */
<> 149:156823d33999 9022
<> 149:156823d33999 9023 #define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */
<> 149:156823d33999 9024 #define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */
<> 149:156823d33999 9025
<> 149:156823d33999 9026 #define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */
<> 149:156823d33999 9027 #define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */
<> 149:156823d33999 9028
<> 149:156823d33999 9029 #define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */
<> 149:156823d33999 9030 #define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */
<> 149:156823d33999 9031
<> 149:156823d33999 9032 #define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */
<> 149:156823d33999 9033 #define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */
<> 149:156823d33999 9034
<> 149:156823d33999 9035 #define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */
<> 149:156823d33999 9036 #define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */
<> 149:156823d33999 9037
<> 149:156823d33999 9038 #define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */
<> 149:156823d33999 9039 #define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */
<> 149:156823d33999 9040
<> 149:156823d33999 9041 #define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */
<> 149:156823d33999 9042 #define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */
<> 149:156823d33999 9043
<> 149:156823d33999 9044 #define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */
<> 149:156823d33999 9045 #define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */
<> 149:156823d33999 9046
<> 149:156823d33999 9047 #define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */
<> 149:156823d33999 9048 #define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */
<> 149:156823d33999 9049
<> 149:156823d33999 9050 #define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */
<> 149:156823d33999 9051 #define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */
<> 149:156823d33999 9052
<> 149:156823d33999 9053 #define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */
<> 149:156823d33999 9054 #define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */
<> 149:156823d33999 9055
<> 149:156823d33999 9056 #define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */
<> 149:156823d33999 9057 #define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */
<> 149:156823d33999 9058
<> 149:156823d33999 9059 #define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */
<> 149:156823d33999 9060 #define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */
<> 149:156823d33999 9061
<> 149:156823d33999 9062 #define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */
<> 149:156823d33999 9063 #define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */
<> 149:156823d33999 9064
<> 149:156823d33999 9065 #define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */
<> 149:156823d33999 9066 #define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */
<> 149:156823d33999 9067
<> 149:156823d33999 9068 #define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */
<> 149:156823d33999 9069 #define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */
<> 149:156823d33999 9070
<> 149:156823d33999 9071 #define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */
<> 149:156823d33999 9072 #define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */
<> 149:156823d33999 9073
<> 149:156823d33999 9074 #define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */
<> 149:156823d33999 9075 #define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */
<> 149:156823d33999 9076
<> 149:156823d33999 9077 #define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */
<> 149:156823d33999 9078 #define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */
<> 149:156823d33999 9079
<> 149:156823d33999 9080 #define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */
<> 149:156823d33999 9081 #define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */
<> 149:156823d33999 9082
<> 149:156823d33999 9083 #define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */
<> 149:156823d33999 9084 #define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */
<> 149:156823d33999 9085
<> 149:156823d33999 9086 #define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */
<> 149:156823d33999 9087 #define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */
<> 149:156823d33999 9088
<> 149:156823d33999 9089 #define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */
<> 149:156823d33999 9090 #define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */
<> 149:156823d33999 9091
<> 149:156823d33999 9092 #define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */
<> 149:156823d33999 9093 #define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */
<> 149:156823d33999 9094
<> 149:156823d33999 9095 #define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */
<> 149:156823d33999 9096 #define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */
<> 149:156823d33999 9097
<> 149:156823d33999 9098 #define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */
<> 149:156823d33999 9099 #define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */
<> 149:156823d33999 9100
<> 149:156823d33999 9101 #define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */
<> 149:156823d33999 9102 #define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */
<> 149:156823d33999 9103
<> 149:156823d33999 9104 #define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */
<> 149:156823d33999 9105 #define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */
<> 149:156823d33999 9106
<> 149:156823d33999 9107 #define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */
<> 149:156823d33999 9108 #define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */
<> 149:156823d33999 9109
<> 149:156823d33999 9110 #define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */
<> 149:156823d33999 9111 #define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */
<> 149:156823d33999 9112
<> 149:156823d33999 9113 #define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */
<> 149:156823d33999 9114 #define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */
<> 149:156823d33999 9115
<> 149:156823d33999 9116 #define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */
<> 149:156823d33999 9117 #define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */
<> 149:156823d33999 9118
<> 149:156823d33999 9119 #define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */
<> 149:156823d33999 9120 #define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */
<> 149:156823d33999 9121
<> 149:156823d33999 9122 #define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */
<> 149:156823d33999 9123 #define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */
<> 149:156823d33999 9124
<> 149:156823d33999 9125 #define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */
<> 149:156823d33999 9126 #define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */
<> 149:156823d33999 9127
<> 149:156823d33999 9128 #define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */
<> 149:156823d33999 9129 #define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */
<> 149:156823d33999 9130
<> 149:156823d33999 9131 #define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */
<> 149:156823d33999 9132 #define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */
<> 149:156823d33999 9133
<> 149:156823d33999 9134 #define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */
<> 149:156823d33999 9135 #define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */
<> 149:156823d33999 9136
<> 149:156823d33999 9137 #define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF: PBUF Position */
<> 149:156823d33999 9138 #define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF: PBUF Mask */
<> 149:156823d33999 9139
<> 149:156823d33999 9140 #define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF: CMPBUF Position */
<> 149:156823d33999 9141 #define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF: CMPBUF Mask */
<> 149:156823d33999 9142
<> 149:156823d33999 9143 #define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position */
<> 149:156823d33999 9144 #define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask */
<> 149:156823d33999 9145
<> 149:156823d33999 9146 #define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position */
<> 149:156823d33999 9147 #define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask */
<> 149:156823d33999 9148
<> 149:156823d33999 9149 #define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position */
<> 149:156823d33999 9150 #define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask */
<> 149:156823d33999 9151
<> 149:156823d33999 9152 #define PWM_FTCI_FTCMUn_Pos (0) /*!< PWM_T::FTCI: FTCMUn Position */
<> 149:156823d33999 9153 #define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) /*!< PWM_T::FTCI: FTCMUn Mask */
<> 149:156823d33999 9154
<> 149:156823d33999 9155 #define PWM_FTCI_FTCMU0_Pos (0) /*!< PWM_T::FTCI: FTCMU0 Position */
<> 149:156823d33999 9156 #define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) /*!< PWM_T::FTCI: FTCMU0 Mask */
<> 149:156823d33999 9157
<> 149:156823d33999 9158 #define PWM_FTCI_FTCMU2_Pos (1) /*!< PWM_T::FTCI: FTCMU2 Position */
<> 149:156823d33999 9159 #define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) /*!< PWM_T::FTCI: FTCMU2 Mask */
<> 149:156823d33999 9160
<> 149:156823d33999 9161 #define PWM_FTCI_FTCMU4_Pos (2) /*!< PWM_T::FTCI: FTCMU4 Position */
<> 149:156823d33999 9162 #define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) /*!< PWM_T::FTCI: FTCMU4 Mask */
<> 149:156823d33999 9163
<> 149:156823d33999 9164 #define PWM_FTCI_FTCMDn_Pos (8) /*!< PWM_T::FTCI: FTCMDn Position */
<> 149:156823d33999 9165 #define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) /*!< PWM_T::FTCI: FTCMDn Mask */
<> 149:156823d33999 9166
<> 149:156823d33999 9167 #define PWM_FTCI_FTCMD0_Pos (8) /*!< PWM_T::FTCI: FTCMD0 Position */
<> 149:156823d33999 9168 #define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) /*!< PWM_T::FTCI: FTCMD0 Mask */
<> 149:156823d33999 9169
<> 149:156823d33999 9170 #define PWM_FTCI_FTCMD2_Pos (9) /*!< PWM_T::FTCI: FTCMD2 Position */
<> 149:156823d33999 9171 #define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) /*!< PWM_T::FTCI: FTCMD2 Mask */
<> 149:156823d33999 9172
<> 149:156823d33999 9173 #define PWM_FTCI_FTCMD4_Pos (10) /*!< PWM_T::FTCI: FTCMD4 Position */
<> 149:156823d33999 9174 #define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /*!< PWM_T::FTCI: FTCMD4 Mask */
<> 149:156823d33999 9175
<> 149:156823d33999 9176 /**@}*/ /* PWM_CONST */
<> 149:156823d33999 9177 /**@}*/ /* end of PWM register group */
<> 149:156823d33999 9178
<> 149:156823d33999 9179
<> 149:156823d33999 9180 /*---------------------- Real Time Clock Controller -------------------------*/
<> 149:156823d33999 9181 /**
<> 149:156823d33999 9182 @addtogroup RTC Real Time Clock Controller(RTC)
<> 149:156823d33999 9183 Memory Mapped Structure for RTC Controller
<> 149:156823d33999 9184 @{ */
<> 149:156823d33999 9185
<> 149:156823d33999 9186
<> 149:156823d33999 9187 typedef struct
<> 149:156823d33999 9188 {
<> 149:156823d33999 9189
<> 149:156823d33999 9190
<> 149:156823d33999 9191
<> 149:156823d33999 9192
<> 149:156823d33999 9193 /**
<> 149:156823d33999 9194 * @var RTC_T::INIT
<> 149:156823d33999 9195 * Offset: 0x00 RTC Initiation Register
<> 149:156823d33999 9196 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9197 * |Bits |Field |Descriptions
<> 149:156823d33999 9198 * | :----: | :----: | :---- |
<> 149:156823d33999 9199 * |[0] |INIT[0]/ACTIVE|RTC Active Status (Read Only)
<> 149:156823d33999 9200 * | | |0 = RTC is at reset state.
<> 149:156823d33999 9201 * | | |1 = RTC is at normal active state.
<> 149:156823d33999 9202 * |[31:1] |INIT[31:1]|RTC Initiation
<> 149:156823d33999 9203 * | | |When RTC block is powered on, RTC is at reset state.
<> 149:156823d33999 9204 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
<> 149:156823d33999 9205 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
<> 149:156823d33999 9206 * | | |The INIT is a write-only field and read value will be always 0.
<> 149:156823d33999 9207 * @var RTC_T::RWEN
<> 149:156823d33999 9208 * Offset: 0x04 RTC Access Enable Register
<> 149:156823d33999 9209 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9210 * |Bits |Field |Descriptions
<> 149:156823d33999 9211 * | :----: | :----: | :---- |
<> 149:156823d33999 9212 * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
<> 149:156823d33999 9213 * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
<> 149:156823d33999 9214 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
<> 149:156823d33999 9215 * | | |0 = RTC register read/write Disabled.
<> 149:156823d33999 9216 * | | |1 = RTC register read/write Enabled.
<> 149:156823d33999 9217 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
<> 149:156823d33999 9218 * @var RTC_T::FREQADJ
<> 149:156823d33999 9219 * Offset: 0x08 RTC Frequency Compensation Register
<> 149:156823d33999 9220 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9221 * |Bits |Field |Descriptions
<> 149:156823d33999 9222 * | :----: | :----: | :---- |
<> 149:156823d33999 9223 * |[5:0] |FRACTION |Fraction Part
<> 149:156823d33999 9224 * | | |Formula = (fraction part of detected value) x 60.
<> 149:156823d33999 9225 * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
<> 149:156823d33999 9226 * |[11:8] |INTEGER |Integer Part
<> 149:156823d33999 9227 * @var RTC_T::TIME
<> 149:156823d33999 9228 * Offset: 0x0C Time Loading Register
<> 149:156823d33999 9229 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9230 * |Bits |Field |Descriptions
<> 149:156823d33999 9231 * | :----: | :----: | :---- |
<> 149:156823d33999 9232 * |[3:0] |SEC |1-Sec Time Digit (0~9)
<> 149:156823d33999 9233 * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
<> 149:156823d33999 9234 * |[11:8] |MIN |1-Min Time Digit (0~9)
<> 149:156823d33999 9235 * |[14:12] |TENMIN |10-Min Time Digit (0~5)
<> 149:156823d33999 9236 * |[19:16] |HR |1-Hour Time Digit (0~9)
<> 149:156823d33999 9237 * |[21:20] |TENHR |10-Hour Time Digit (0~2)
<> 149:156823d33999 9238 * @var RTC_T::CAL
<> 149:156823d33999 9239 * Offset: 0x10 RTC Calendar Loading Register
<> 149:156823d33999 9240 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9241 * |Bits |Field |Descriptions
<> 149:156823d33999 9242 * | :----: | :----: | :---- |
<> 149:156823d33999 9243 * |[3:0] |DAY |1-Day Calendar Digit (0~9)
<> 149:156823d33999 9244 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
<> 149:156823d33999 9245 * |[11:8] |MON |1-Month Calendar Digit (0~9)
<> 149:156823d33999 9246 * |[12] |TENMON |10-Month Calendar Digit (0~1)
<> 149:156823d33999 9247 * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
<> 149:156823d33999 9248 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
<> 149:156823d33999 9249 * @var RTC_T::CLKFMT
<> 149:156823d33999 9250 * Offset: 0x14 Time Scale Selection Register
<> 149:156823d33999 9251 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9252 * |Bits |Field |Descriptions
<> 149:156823d33999 9253 * | :----: | :----: | :---- |
<> 149:156823d33999 9254 * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
<> 149:156823d33999 9255 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
<> 149:156823d33999 9256 * | | |0 = 12-hour time scale with AM and PM indication selected.
<> 149:156823d33999 9257 * | | |1 = 24-hour time scale selected.
<> 149:156823d33999 9258 * @var RTC_T::WEEKDAY
<> 149:156823d33999 9259 * Offset: 0x18 Day of the Week Register
<> 149:156823d33999 9260 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9261 * |Bits |Field |Descriptions
<> 149:156823d33999 9262 * | :----: | :----: | :---- |
<> 149:156823d33999 9263 * |[2:0] |WEEKDAY |Day Of The Week Register
<> 149:156823d33999 9264 * | | |000 = Sunday.
<> 149:156823d33999 9265 * | | |001 = Monday.
<> 149:156823d33999 9266 * | | |010 = Tuesday.
<> 149:156823d33999 9267 * | | |011 = Wednesday.
<> 149:156823d33999 9268 * | | |100 = Thursday.
<> 149:156823d33999 9269 * | | |101 = Friday.
<> 149:156823d33999 9270 * | | |110 = Saturday.
<> 149:156823d33999 9271 * | | |111 = Reserved.
<> 149:156823d33999 9272 * @var RTC_T::TALM
<> 149:156823d33999 9273 * Offset: 0x1C Time Alarm Register
<> 149:156823d33999 9274 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9275 * |Bits |Field |Descriptions
<> 149:156823d33999 9276 * | :----: | :----: | :---- |
<> 149:156823d33999 9277 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9278 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
<> 149:156823d33999 9279 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9280 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
<> 149:156823d33999 9281 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9282 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
<> 149:156823d33999 9283 * @var RTC_T::CALM
<> 149:156823d33999 9284 * Offset: 0x20 Calendar Alarm Register
<> 149:156823d33999 9285 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9286 * |Bits |Field |Descriptions
<> 149:156823d33999 9287 * | :----: | :----: | :---- |
<> 149:156823d33999 9288 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9289 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
<> 149:156823d33999 9290 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9291 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
<> 149:156823d33999 9292 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9293 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9294 * @var RTC_T::LEAPYEAR
<> 149:156823d33999 9295 * Offset: 0x24 RTC Leap Year Indicator Register
<> 149:156823d33999 9296 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9297 * |Bits |Field |Descriptions
<> 149:156823d33999 9298 * | :----: | :----: | :---- |
<> 149:156823d33999 9299 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
<> 149:156823d33999 9300 * | | |0 = This year is not a leap year.
<> 149:156823d33999 9301 * | | |1 = This year is leap year.
<> 149:156823d33999 9302 * @var RTC_T::INTEN
<> 149:156823d33999 9303 * Offset: 0x28 RTC Interrupt Enable Register
<> 149:156823d33999 9304 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9305 * |Bits |Field |Descriptions
<> 149:156823d33999 9306 * | :----: | :----: | :---- |
<> 149:156823d33999 9307 * |[0] |ALMIEN |Alarm Interrupt Enable Bit
<> 149:156823d33999 9308 * | | |0 = RTC Alarm interrupt Disabled.
<> 149:156823d33999 9309 * | | |1 = RTC Alarm interrupt Enabled.
<> 149:156823d33999 9310 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
<> 149:156823d33999 9311 * | | |0 = RTC Time Tick interrupt Disabled.
<> 149:156823d33999 9312 * | | |1 = RTC Time Tick interrupt Enabled.
<> 149:156823d33999 9313 * |[2] |SNPDIEN |Snoop Detection Interrupt Enable Bit
<> 149:156823d33999 9314 * | | |0 = Snoop detected interrupt Disabled.
<> 149:156823d33999 9315 * | | |1 = Snoop detected interrupt Enabled.
<> 149:156823d33999 9316 * @var RTC_T::INTSTS
<> 149:156823d33999 9317 * Offset: 0x2C RTC Interrupt Indicator Register
<> 149:156823d33999 9318 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9319 * |Bits |Field |Descriptions
<> 149:156823d33999 9320 * | :----: | :----: | :---- |
<> 149:156823d33999 9321 * |[0] |ALMIF |RTC Alarm Interrupt Flag
<> 149:156823d33999 9322 * | | |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
<> 149:156823d33999 9323 * | | |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
<> 149:156823d33999 9324 * | | |0 = Alarm condition is not matched.
<> 149:156823d33999 9325 * | | |1 = Alarm condition is matched.
<> 149:156823d33999 9326 * | | |Note: Write 1 to clear this bit.
<> 149:156823d33999 9327 * |[1] |TICKIF |RTC Time Tick Interrupt Flag
<> 149:156823d33999 9328 * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
<> 149:156823d33999 9329 * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
<> 149:156823d33999 9330 * | | |0 = Tick condition does not occur.
<> 149:156823d33999 9331 * | | |1 = Tick condition occur.
<> 149:156823d33999 9332 * | | |Note: Write 1 to clear to clear this bit.
<> 149:156823d33999 9333 * |[2] |SNPDIF |Snoop Detect Interrupt Flag
<> 149:156823d33999 9334 * | | |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
<> 149:156823d33999 9335 * | | |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
<> 149:156823d33999 9336 * | | |0 = No snoop event is detected.
<> 149:156823d33999 9337 * | | |1 = Snoop event is detected.
<> 149:156823d33999 9338 * | | |Note: Write 1 to clear this bit.
<> 149:156823d33999 9339 * @var RTC_T::TICK
<> 149:156823d33999 9340 * Offset: 0x30 RTC Time Tick Register
<> 149:156823d33999 9341 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9342 * |Bits |Field |Descriptions
<> 149:156823d33999 9343 * | :----: | :----: | :---- |
<> 149:156823d33999 9344 * |[2:0] |TICK |Time Tick Register
<> 149:156823d33999 9345 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
<> 149:156823d33999 9346 * | | |000 = Time tick is 1 second.
<> 149:156823d33999 9347 * | | |001 = Time tick is 1/2 second.
<> 149:156823d33999 9348 * | | |010 = Time tick is 1/4 second.
<> 149:156823d33999 9349 * | | |011 = Time tick is 1/8 second.
<> 149:156823d33999 9350 * | | |100 = Time tick is 1/16 second.
<> 149:156823d33999 9351 * | | |101 = Time tick is 1/32 second.
<> 149:156823d33999 9352 * | | |110 = Time tick is 1/64 second.
<> 149:156823d33999 9353 * | | |111 = Time tick is 1/28 second.
<> 149:156823d33999 9354 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
<> 149:156823d33999 9355 * @var RTC_T::TAMSK
<> 149:156823d33999 9356 * Offset: 0x34 Time Alarm Mask Register
<> 149:156823d33999 9357 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9358 * |Bits |Field |Descriptions
<> 149:156823d33999 9359 * | :----: | :----: | :---- |
<> 149:156823d33999 9360 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9361 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
<> 149:156823d33999 9362 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9363 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
<> 149:156823d33999 9364 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
<> 149:156823d33999 9365 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
<> 149:156823d33999 9366 * @var RTC_T::CAMSK
<> 149:156823d33999 9367 * Offset: 0x38 Calendar Alarm Mask Register
<> 149:156823d33999 9368 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9369 * |Bits |Field |Descriptions
<> 149:156823d33999 9370 * | :----: | :----: | :---- |
<> 149:156823d33999 9371 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9372 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
<> 149:156823d33999 9373 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9374 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
<> 149:156823d33999 9375 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9376 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
<> 149:156823d33999 9377 * @var RTC_T::SPRCTL
<> 149:156823d33999 9378 * Offset: 0x3C RTC Spare Functional Control Register
<> 149:156823d33999 9379 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9380 * |Bits |Field |Descriptions
<> 149:156823d33999 9381 * | :----: | :----: | :---- |
<> 149:156823d33999 9382 * |[0] |SNPDEN |Snoop Detection Enable Bit
<> 149:156823d33999 9383 * | | |0 = TAMPER pin detection is Disabled.
<> 149:156823d33999 9384 * | | |1 = TAMPER pin detection is Enabled.
<> 149:156823d33999 9385 * |[1] |SNPTYPE0 |Snoop Detection Level
<> 149:156823d33999 9386 * | | |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
<> 149:156823d33999 9387 * | | |0 = Low level/Falling edge detection.
<> 149:156823d33999 9388 * | | |1 = High level/Rising edge detection.
<> 149:156823d33999 9389 * |[2] |SPRRWEN |Spare Register Enable Bit
<> 149:156823d33999 9390 * | | |0 = Spare register is Disabled.
<> 149:156823d33999 9391 * | | |1 = Spare register is Enabled.
<> 149:156823d33999 9392 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
<> 149:156823d33999 9393 * |[3] |SNPTYPE1 |Snoop Detection Mode
<> 149:156823d33999 9394 * | | |This bit controls TAMPER pin is edge or level detection
<> 149:156823d33999 9395 * | | |0 = Level detection.
<> 149:156823d33999 9396 * | | |1 = Edge detection.
<> 149:156823d33999 9397 * |[5] |SPRCSTS |SPR Clear Flag
<> 149:156823d33999 9398 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
<> 149:156823d33999 9399 * | | |0 = Spare register content is not cleared.
<> 149:156823d33999 9400 * | | |1 = Spare register content is cleared.
<> 149:156823d33999 9401 * | | |Writes 1 to clear this bit.
<> 149:156823d33999 9402 * |[7] |SPRRWRDY |SPR Register Ready
<> 149:156823d33999 9403 * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
<> 149:156823d33999 9404 * | | |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
<> 149:156823d33999 9405 * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
<> 149:156823d33999 9406 * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
<> 149:156823d33999 9407 * | | |Note: This bit is read only and any write to it won't take any effect.
<> 149:156823d33999 9408 * @var RTC_T::SPR
<> 149:156823d33999 9409 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
<> 149:156823d33999 9410 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9411 * |Bits |Field |Descriptions
<> 149:156823d33999 9412 * | :----: | :----: | :---- |
<> 149:156823d33999 9413 * |[31:0] |SPARE |Spare Register
<> 149:156823d33999 9414 * | | |This field is used to store back-up information defined by user.
<> 149:156823d33999 9415 * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
<> 149:156823d33999 9416 * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
<> 149:156823d33999 9417 * @var RTC_T::LXTCTL
<> 149:156823d33999 9418 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
<> 149:156823d33999 9419 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9420 * |Bits |Field |Descriptions
<> 149:156823d33999 9421 * | :----: | :----: | :---- |
<> 149:156823d33999 9422 * |[0] |LXTEN |Backup Domain 32K Oscillator Enable Bit
<> 149:156823d33999 9423 * | | |0 = Oscillator is Disabled.
<> 149:156823d33999 9424 * | | |1 = Oscillator is Enabled.
<> 149:156823d33999 9425 * | | |This bit controls 32 kHz oscillator on/off.
<> 149:156823d33999 9426 * | | |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
<> 149:156823d33999 9427 * | | |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
<> 149:156823d33999 9428 * |[3:1] |GAIN |Oscillator Gain Option
<> 149:156823d33999 9429 * | | |User can select oscillator gain according to crystal external loading and operating temperature range.
<> 149:156823d33999 9430 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
<> 149:156823d33999 9431 * | | |000 = L0 mode.
<> 149:156823d33999 9432 * | | |001 = L1 mode.
<> 149:156823d33999 9433 * | | |010 = L2 mode.
<> 149:156823d33999 9434 * | | |011 = L3 mode.
<> 149:156823d33999 9435 * | | |100 = L4 mode.
<> 149:156823d33999 9436 * | | |101 = L5 mode.
<> 149:156823d33999 9437 * | | |110 = L6 mode.
<> 149:156823d33999 9438 * | | |111 = L7 mode (Default).
<> 149:156823d33999 9439 * @var RTC_T::LXTOCTL
<> 149:156823d33999 9440 * Offset: 0x104 X32KO Pin Control Register
<> 149:156823d33999 9441 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9442 * |Bits |Field |Descriptions
<> 149:156823d33999 9443 * | :----: | :----: | :---- |
<> 149:156823d33999 9444 * |[1:0] |OPMODE |GPF0 Operation Mode
<> 149:156823d33999 9445 * | | |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
<> 149:156823d33999 9446 * | | |01 = X32KO (PF.0) is output push pull mode.
<> 149:156823d33999 9447 * | | |10 = X32KO (PF.0) is open drain mode.
<> 149:156823d33999 9448 * | | |11 = X32KO (PF.0) is input only mode with internal pull up.
<> 149:156823d33999 9449 * |[2] |DOUT |IO Output Data
<> 149:156823d33999 9450 * | | |0 = X32KO (PF.0) output low.
<> 149:156823d33999 9451 * | | |1 = X32KO (PF.0) output high.
<> 149:156823d33999 9452 * |[3] |CTLSEL |IO Pin State Backup Selection
<> 149:156823d33999 9453 * | | |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
<> 149:156823d33999 9454 * | | |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
<> 149:156823d33999 9455 * | | |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
<> 149:156823d33999 9456 * | | |It becomes floating when system power is turned off.
<> 149:156823d33999 9457 * | | |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
<> 149:156823d33999 9458 * | | |I/O pin keeps the previous state after system power is turned off.
<> 149:156823d33999 9459 * @var RTC_T::LXTICTL
<> 149:156823d33999 9460 * Offset: 0x108 X32KI Pin Control Register
<> 149:156823d33999 9461 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9462 * |Bits |Field |Descriptions
<> 149:156823d33999 9463 * | :----: | :----: | :---- |
<> 149:156823d33999 9464 * |[1:0] |OPMODE |IO Operation Mode
<> 149:156823d33999 9465 * | | |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
<> 149:156823d33999 9466 * | | |01 = X32KI (PF.1) is output push pull mode.
<> 149:156823d33999 9467 * | | |10 = X32KI (PF.1) is open drain mode.
<> 149:156823d33999 9468 * | | |11 = X32KI (PF.1) is input only mode with internal pull up.
<> 149:156823d33999 9469 * |[2] |DOUT |IO Output Data
<> 149:156823d33999 9470 * | | |0 = X32KI (PF.1) output low.
<> 149:156823d33999 9471 * | | |1 = X32KI (PF.1) output high.
<> 149:156823d33999 9472 * |[3] |CTLSEL |IO Pin State Backup Selection
<> 149:156823d33999 9473 * | | |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
<> 149:156823d33999 9474 * | | |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
<> 149:156823d33999 9475 * | | |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
<> 149:156823d33999 9476 * | | |It becomes floating state when system power is turned off.
<> 149:156823d33999 9477 * | | |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
<> 149:156823d33999 9478 * | | |I/O pin keeps the previous state after system power is turned off.
<> 149:156823d33999 9479 * @var RTC_T::TAMPCTL
<> 149:156823d33999 9480 * Offset: 0x10C TAMPER Pin Control Register
<> 149:156823d33999 9481 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9482 * |Bits |Field |Descriptions
<> 149:156823d33999 9483 * | :----: | :----: | :---- |
<> 149:156823d33999 9484 * |[1:0] |OPMODE |IO Operation Mode
<> 149:156823d33999 9485 * | | |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
<> 149:156823d33999 9486 * | | |01 = TAMPER (PF.2) is output push pull mode.
<> 149:156823d33999 9487 * | | |10 = TAMPER (PF.2) is open drain mode.
<> 149:156823d33999 9488 * | | |11 = TAMPER (PF.2) is input only mode with internal pull up.
<> 149:156823d33999 9489 * |[2] |DOUT |IO Output Data
<> 149:156823d33999 9490 * | | |0 = TAMPER (PF.2) output low.
<> 149:156823d33999 9491 * | | |1 = TAMPER (PF.2) output high.
<> 149:156823d33999 9492 * |[3] |CTLSEL |IO Pin State Backup Selection
<> 149:156823d33999 9493 * | | |When tamper function is disabled, TAMPER pin can be used as GPIO function.
<> 149:156823d33999 9494 * | | |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
<> 149:156823d33999 9495 * | | |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
<> 149:156823d33999 9496 * | | |It becomes floating state when system power is turned off.
<> 149:156823d33999 9497 * | | |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
<> 149:156823d33999 9498 * | | |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
<> 149:156823d33999 9499 * | | |I/O pin state keeps previous state after system power is turned off.
<> 149:156823d33999 9500 */
<> 149:156823d33999 9501
<> 149:156823d33999 9502 __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
<> 149:156823d33999 9503 __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
<> 149:156823d33999 9504 __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
<> 149:156823d33999 9505 __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
<> 149:156823d33999 9506 __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
<> 149:156823d33999 9507 __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
<> 149:156823d33999 9508 __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
<> 149:156823d33999 9509 __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
<> 149:156823d33999 9510 __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
<> 149:156823d33999 9511 __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
<> 149:156823d33999 9512 __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
<> 149:156823d33999 9513 __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
<> 149:156823d33999 9514 __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
<> 149:156823d33999 9515 __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
<> 149:156823d33999 9516 __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
<> 149:156823d33999 9517 __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
<> 149:156823d33999 9518 __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
<> 149:156823d33999 9519 __I uint32_t RESERVE0[28];
<> 149:156823d33999 9520 __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
<> 149:156823d33999 9521 __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
<> 149:156823d33999 9522 __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
<> 149:156823d33999 9523 __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
<> 149:156823d33999 9524
<> 149:156823d33999 9525 } RTC_T;
<> 149:156823d33999 9526
<> 149:156823d33999 9527
<> 149:156823d33999 9528
<> 149:156823d33999 9529 /**
<> 149:156823d33999 9530 @addtogroup RTC_CONST RTC Bit Field Definition
<> 149:156823d33999 9531 Constant Definitions for RTC Controller
<> 149:156823d33999 9532 @{ */
<> 149:156823d33999 9533
<> 149:156823d33999 9534 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
<> 149:156823d33999 9535 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
<> 149:156823d33999 9536
<> 149:156823d33999 9537 #define RTC_INIT_INIT_Pos (0) /*!< RTC_T::INIT: INIT Position */
<> 149:156823d33999 9538 #define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
<> 149:156823d33999 9539
<> 149:156823d33999 9540 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
<> 149:156823d33999 9541 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
<> 149:156823d33999 9542
<> 149:156823d33999 9543 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
<> 149:156823d33999 9544 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
<> 149:156823d33999 9545
<> 149:156823d33999 9546 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
<> 149:156823d33999 9547 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
<> 149:156823d33999 9548
<> 149:156823d33999 9549 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
<> 149:156823d33999 9550 #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
<> 149:156823d33999 9551
<> 149:156823d33999 9552 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
<> 149:156823d33999 9553 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
<> 149:156823d33999 9554
<> 149:156823d33999 9555 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
<> 149:156823d33999 9556 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
<> 149:156823d33999 9557
<> 149:156823d33999 9558 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
<> 149:156823d33999 9559 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
<> 149:156823d33999 9560
<> 149:156823d33999 9561 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
<> 149:156823d33999 9562 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
<> 149:156823d33999 9563
<> 149:156823d33999 9564 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
<> 149:156823d33999 9565 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
<> 149:156823d33999 9566
<> 149:156823d33999 9567 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
<> 149:156823d33999 9568 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
<> 149:156823d33999 9569
<> 149:156823d33999 9570 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
<> 149:156823d33999 9571 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
<> 149:156823d33999 9572
<> 149:156823d33999 9573 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
<> 149:156823d33999 9574 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
<> 149:156823d33999 9575
<> 149:156823d33999 9576 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
<> 149:156823d33999 9577 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
<> 149:156823d33999 9578
<> 149:156823d33999 9579 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
<> 149:156823d33999 9580 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
<> 149:156823d33999 9581
<> 149:156823d33999 9582 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
<> 149:156823d33999 9583 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
<> 149:156823d33999 9584
<> 149:156823d33999 9585 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
<> 149:156823d33999 9586 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
<> 149:156823d33999 9587
<> 149:156823d33999 9588 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
<> 149:156823d33999 9589 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
<> 149:156823d33999 9590
<> 149:156823d33999 9591 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
<> 149:156823d33999 9592 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
<> 149:156823d33999 9593
<> 149:156823d33999 9594 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
<> 149:156823d33999 9595 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
<> 149:156823d33999 9596
<> 149:156823d33999 9597 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
<> 149:156823d33999 9598 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
<> 149:156823d33999 9599
<> 149:156823d33999 9600 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
<> 149:156823d33999 9601 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
<> 149:156823d33999 9602
<> 149:156823d33999 9603 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
<> 149:156823d33999 9604 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
<> 149:156823d33999 9605
<> 149:156823d33999 9606 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
<> 149:156823d33999 9607 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
<> 149:156823d33999 9608
<> 149:156823d33999 9609 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
<> 149:156823d33999 9610 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
<> 149:156823d33999 9611
<> 149:156823d33999 9612 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
<> 149:156823d33999 9613 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
<> 149:156823d33999 9614
<> 149:156823d33999 9615 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
<> 149:156823d33999 9616 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
<> 149:156823d33999 9617
<> 149:156823d33999 9618 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
<> 149:156823d33999 9619 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
<> 149:156823d33999 9620
<> 149:156823d33999 9621 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
<> 149:156823d33999 9622 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
<> 149:156823d33999 9623
<> 149:156823d33999 9624 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
<> 149:156823d33999 9625 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
<> 149:156823d33999 9626
<> 149:156823d33999 9627 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
<> 149:156823d33999 9628 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
<> 149:156823d33999 9629
<> 149:156823d33999 9630 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
<> 149:156823d33999 9631 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
<> 149:156823d33999 9632
<> 149:156823d33999 9633 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
<> 149:156823d33999 9634 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
<> 149:156823d33999 9635
<> 149:156823d33999 9636 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
<> 149:156823d33999 9637 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
<> 149:156823d33999 9638
<> 149:156823d33999 9639 #define RTC_INTEN_SNPDIEN_Pos (2) /*!< RTC_T::INTEN: SNPDIEN Position */
<> 149:156823d33999 9640 #define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) /*!< RTC_T::INTEN: SNPDIEN Mask */
<> 149:156823d33999 9641
<> 149:156823d33999 9642 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
<> 149:156823d33999 9643 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
<> 149:156823d33999 9644
<> 149:156823d33999 9645 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
<> 149:156823d33999 9646 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
<> 149:156823d33999 9647
<> 149:156823d33999 9648 #define RTC_INTSTS_SNPDIF_Pos (2) /*!< RTC_T::INTSTS: SNPDIF Position */
<> 149:156823d33999 9649 #define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) /*!< RTC_T::INTSTS: SNPDIF Mask */
<> 149:156823d33999 9650
<> 149:156823d33999 9651 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
<> 149:156823d33999 9652 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
<> 149:156823d33999 9653
<> 149:156823d33999 9654 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
<> 149:156823d33999 9655 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
<> 149:156823d33999 9656
<> 149:156823d33999 9657 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
<> 149:156823d33999 9658 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
<> 149:156823d33999 9659
<> 149:156823d33999 9660 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
<> 149:156823d33999 9661 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
<> 149:156823d33999 9662
<> 149:156823d33999 9663 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
<> 149:156823d33999 9664 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
<> 149:156823d33999 9665
<> 149:156823d33999 9666 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
<> 149:156823d33999 9667 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
<> 149:156823d33999 9668
<> 149:156823d33999 9669 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
<> 149:156823d33999 9670 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
<> 149:156823d33999 9671
<> 149:156823d33999 9672 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
<> 149:156823d33999 9673 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
<> 149:156823d33999 9674
<> 149:156823d33999 9675 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
<> 149:156823d33999 9676 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
<> 149:156823d33999 9677
<> 149:156823d33999 9678 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
<> 149:156823d33999 9679 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
<> 149:156823d33999 9680
<> 149:156823d33999 9681 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
<> 149:156823d33999 9682 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
<> 149:156823d33999 9683
<> 149:156823d33999 9684 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
<> 149:156823d33999 9685 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
<> 149:156823d33999 9686
<> 149:156823d33999 9687 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
<> 149:156823d33999 9688 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
<> 149:156823d33999 9689
<> 149:156823d33999 9690 #define RTC_SPRCTL_SNPDEN_Pos (0) /*!< RTC_T::SPRCTL: SNPDEN Position */
<> 149:156823d33999 9691 #define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) /*!< RTC_T::SPRCTL: SNPDEN Mask */
<> 149:156823d33999 9692
<> 149:156823d33999 9693 #define RTC_SPRCTL_SNPTYPE0_Pos (1) /*!< RTC_T::SPRCTL: SNPTYPE0 Position */
<> 149:156823d33999 9694 #define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) /*!< RTC_T::SPRCTL: SNPTYPE0 Mask */
<> 149:156823d33999 9695
<> 149:156823d33999 9696 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
<> 149:156823d33999 9697 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
<> 149:156823d33999 9698
<> 149:156823d33999 9699 #define RTC_SPRCTL_SNPTYPE1_Pos (3) /*!< RTC_T::SPRCTL: SNPTYPE1 Position */
<> 149:156823d33999 9700 #define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) /*!< RTC_T::SPRCTL: SNPTYPE1 Mask */
<> 149:156823d33999 9701
<> 149:156823d33999 9702 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
<> 149:156823d33999 9703 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
<> 149:156823d33999 9704
<> 149:156823d33999 9705 #define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRWRDY Position */
<> 149:156823d33999 9706 #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC_T::SPRCTL: SPRRWRDY Mask */
<> 149:156823d33999 9707
<> 149:156823d33999 9708 #define RTC_SPR_SPARE_Pos (0) /*!< RTC_T::SPR: SPARE Position */
<> 149:156823d33999 9709 #define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) /*!< RTC_T::SPR: SPARE Mask */
<> 149:156823d33999 9710
<> 149:156823d33999 9711 #define RTC_LXTCTL_LXTEN_Pos (0) /*!< RTC_T::LXTCTL: LXTEN Position */
<> 149:156823d33999 9712 #define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) /*!< RTC_T::LXTCTL: LXTEN Mask */
<> 149:156823d33999 9713
<> 149:156823d33999 9714 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
<> 149:156823d33999 9715 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
<> 149:156823d33999 9716
<> 149:156823d33999 9717 #define RTC_LXTOCTL_OPMODE_Pos (0) /*!< RTC_T::LXTOCTL: OPMODE Position */
<> 149:156823d33999 9718 #define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) /*!< RTC_T::LXTOCTL: OPMODE Mask */
<> 149:156823d33999 9719
<> 149:156823d33999 9720 #define RTC_LXTOCTL_DOUT_Pos (2) /*!< RTC_T::LXTOCTL: DOUT Position */
<> 149:156823d33999 9721 #define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) /*!< RTC_T::LXTOCTL: DOUT Mask */
<> 149:156823d33999 9722
<> 149:156823d33999 9723 #define RTC_LXTOCTL_CTLSEL_Pos (3) /*!< RTC_T::LXTOCTL: CTLSEL Position */
<> 149:156823d33999 9724 #define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) /*!< RTC_T::LXTOCTL: CTLSEL Mask */
<> 149:156823d33999 9725
<> 149:156823d33999 9726 #define RTC_LXTICTL_OPMODE_Pos (0) /*!< RTC_T::LXTICTL: OPMODE Position */
<> 149:156823d33999 9727 #define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) /*!< RTC_T::LXTICTL: OPMODE Mask */
<> 149:156823d33999 9728
<> 149:156823d33999 9729 #define RTC_LXTICTL_DOUT_Pos (2) /*!< RTC_T::LXTICTL: DOUT Position */
<> 149:156823d33999 9730 #define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) /*!< RTC_T::LXTICTL: DOUT Mask */
<> 149:156823d33999 9731
<> 149:156823d33999 9732 #define RTC_LXTICTL_CTLSEL_Pos (3) /*!< RTC_T::LXTICTL: CTLSEL Position */
<> 149:156823d33999 9733 #define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) /*!< RTC_T::LXTICTL: CTLSEL Mask */
<> 149:156823d33999 9734
<> 149:156823d33999 9735 #define RTC_TAMPCTL_OPMODE_Pos (0) /*!< RTC_T::TAMPCTL: OPMODE Position */
<> 149:156823d33999 9736 #define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) /*!< RTC_T::TAMPCTL: OPMODE Mask */
<> 149:156823d33999 9737
<> 149:156823d33999 9738 #define RTC_TAMPCTL_DOUT_Pos (2) /*!< RTC_T::TAMPCTL: DOUT Position */
<> 149:156823d33999 9739 #define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) /*!< RTC_T::TAMPCTL: DOUT Mask */
<> 149:156823d33999 9740
<> 149:156823d33999 9741 #define RTC_TAMPCTL_CTLSEL_Pos (3) /*!< RTC_T::TAMPCTL: CTLSEL Position */
<> 149:156823d33999 9742 #define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /*!< RTC_T::TAMPCTL: CTLSEL Mask */
<> 149:156823d33999 9743
<> 149:156823d33999 9744 /**@}*/ /* RTC_CONST */
<> 149:156823d33999 9745 /**@}*/ /* end of RTC register group */
<> 149:156823d33999 9746
<> 149:156823d33999 9747
<> 149:156823d33999 9748 /*---------------------- Smart Card Host Interface Controller -------------------------*/
<> 149:156823d33999 9749 /**
<> 149:156823d33999 9750 @addtogroup SC Smart Card Host Interface Controller(SC)
<> 149:156823d33999 9751 Memory Mapped Structure for SC Controller
<> 149:156823d33999 9752 @{ */
<> 149:156823d33999 9753
<> 149:156823d33999 9754
<> 149:156823d33999 9755 typedef struct
<> 149:156823d33999 9756 {
<> 149:156823d33999 9757
<> 149:156823d33999 9758
<> 149:156823d33999 9759 /**
<> 149:156823d33999 9760 * @var SC_T::DAT
<> 149:156823d33999 9761 * Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.
<> 149:156823d33999 9762 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9763 * |Bits |Field |Descriptions
<> 149:156823d33999 9764 * | :----: | :----: | :---- |
<> 149:156823d33999 9765 * |[7:0] |DAT |Receiving/ Transmit Holding Buffer
<> 149:156823d33999 9766 * | | |Write Operation:
<> 149:156823d33999 9767 * | | |By writing data to DAT, the SC will send out an 8-bit data.
<> 149:156823d33999 9768 * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
<> 149:156823d33999 9769 * | | |Read Operation:
<> 149:156823d33999 9770 * | | |By reading DAT, the SC will return an 8-bit received data.
<> 149:156823d33999 9771 * @var SC_T::CTL
<> 149:156823d33999 9772 * Offset: 0x04 SC Control Register.
<> 149:156823d33999 9773 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9774 * |Bits |Field |Descriptions
<> 149:156823d33999 9775 * | :----: | :----: | :---- |
<> 149:156823d33999 9776 * |[0] |SCEN |SC Engine Enable Bit
<> 149:156823d33999 9777 * | | |Set this bit to 1 to enable SC operation.
<> 149:156823d33999 9778 * | | |If this bit is cleared, SC will force all transition to IDLE state.
<> 149:156823d33999 9779 * |[1] |RXOFF |RX Transition Disable Control
<> 149:156823d33999 9780 * | | |0 = The receiver Enabled.
<> 149:156823d33999 9781 * | | |1 = The receiver Disabled.
<> 149:156823d33999 9782 * | | |Note:
<> 149:156823d33999 9783 * | | |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
<> 149:156823d33999 9784 * |[2] |TXOFF |TX Transition Disable Control
<> 149:156823d33999 9785 * | | |0 = The transceiver Enabled.
<> 149:156823d33999 9786 * | | |1 = The transceiver Disabled.
<> 149:156823d33999 9787 * |[3] |AUTOCEN |Auto Convention Enable Bit
<> 149:156823d33999 9788 * | | |0 = Auto-convention Disabled.
<> 149:156823d33999 9789 * | | |1 = Auto-convention Enabled.
<> 149:156823d33999 9790 * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
<> 149:156823d33999 9791 * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
<> 149:156823d33999 9792 * | | |After hardware received first data and stored it at buffer,
<> 149:156823d33999 9793 * | | |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
<> 149:156823d33999 9794 * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
<> 149:156823d33999 9795 * |[5:4] |CONSEL |Convention Selection
<> 149:156823d33999 9796 * | | |00 = Direct convention.
<> 149:156823d33999 9797 * | | |01 = Reserved.
<> 149:156823d33999 9798 * | | |10 = Reserved.
<> 149:156823d33999 9799 * | | |11 = Inverse convention.
<> 149:156823d33999 9800 * | | |Note:
<> 149:156823d33999 9801 * | | |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
<> 149:156823d33999 9802 * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
<> 149:156823d33999 9803 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
<> 149:156823d33999 9804 * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
<> 149:156823d33999 9805 * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
<> 149:156823d33999 9806 * | | |10 = INTR_RDA Trigger Level with 03 Bytes.
<> 149:156823d33999 9807 * | | |11 = Reserved.
<> 149:156823d33999 9808 * |[12:8] |BGT |Block Guard Time (BGT)
<> 149:156823d33999 9809 * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
<> 149:156823d33999 9810 * | | |This field indicates the counter for the bit length of block guard time.
<> 149:156823d33999 9811 * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
<> 149:156823d33999 9812 * | | |Note:
<> 149:156823d33999 9813 * | | |The real block guard time is BGT + 1.
<> 149:156823d33999 9814 * |[14:13] |TMRSEL |Timer Selection
<> 149:156823d33999 9815 * | | |00 = All internal timer function Disabled.
<> 149:156823d33999 9816 * | | |01 = Internal 24 bit timer Enabled.
<> 149:156823d33999 9817 * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
<> 149:156823d33999 9818 * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
<> 149:156823d33999 9819 * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
<> 149:156823d33999 9820 * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
<> 149:156823d33999 9821 * | | |SC_TMRCTL2 will be ignored in this mode.
<> 149:156823d33999 9822 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
<> 149:156823d33999 9823 * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
<> 149:156823d33999 9824 * |[15] |NSB |Stop Bit Length
<> 149:156823d33999 9825 * | | |This field indicates the length of stop bit.
<> 149:156823d33999 9826 * | | |0 = The stop bit length is 2 ETU.
<> 149:156823d33999 9827 * | | |1= The stop bit length is 1 ETU.
<> 149:156823d33999 9828 * | | |Note:
<> 149:156823d33999 9829 * | | |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
<> 149:156823d33999 9830 * |[18:16] |RXRTY |RX Error Retry Count Number
<> 149:156823d33999 9831 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
<> 149:156823d33999 9832 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
<> 149:156823d33999 9833 * | | |Note2: This field cannot be changed when RXRTYEN enabled.
<> 149:156823d33999 9834 * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
<> 149:156823d33999 9835 * |[19] |RXRTYEN |RX Error Retry Enable Bit
<> 149:156823d33999 9836 * | | |This bit enables receiver retry function when parity error has occurred.
<> 149:156823d33999 9837 * | | |0 = RX error retry function Disabled.
<> 149:156823d33999 9838 * | | |1 = RX error retry function Enabled.
<> 149:156823d33999 9839 * | | |Note:
<> 149:156823d33999 9840 * | | |Software must fill in the RXRTY value before enabling this bit.
<> 149:156823d33999 9841 * |[22:20] |TXRTY |TX Error Retry Count Number
<> 149:156823d33999 9842 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
<> 149:156823d33999 9843 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
<> 149:156823d33999 9844 * | | |Note2: This field cannot be changed when TXRTYEN enabled.
<> 149:156823d33999 9845 * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
<> 149:156823d33999 9846 * |[23] |TXRTYEN |TX Error Retry Enable Bit
<> 149:156823d33999 9847 * | | |This bit enables transmitter retry function when parity error has occurred.
<> 149:156823d33999 9848 * | | |0 = TX error retry function Disabled.
<> 149:156823d33999 9849 * | | |1 = TX error retry function Enabled.
<> 149:156823d33999 9850 * |[25:24] |CDDBSEL |Card Detect De-Bounce Selection
<> 149:156823d33999 9851 * | | |This field indicates the card detect de-bounce selection.
<> 149:156823d33999 9852 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
<> 149:156823d33999 9853 * | | |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
<> 149:156823d33999 9854 * | | |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
<> 149:156823d33999 9855 * | | |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
<> 149:156823d33999 9856 * |[26] |CDLV |Card Detect Level
<> 149:156823d33999 9857 * | | |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
<> 149:156823d33999 9858 * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
<> 149:156823d33999 9859 * | | |Note: Software must select card detect level before Smart Card engine enabled.
<> 149:156823d33999 9860 * |[30] |SYNC |SYNC Flag Indicator
<> 149:156823d33999 9861 * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
<> 149:156823d33999 9862 * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
<> 149:156823d33999 9863 * | | |1 = Last value is synchronizing.
<> 149:156823d33999 9864 * | | |Note: This bit is read only.
<> 149:156823d33999 9865 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
<> 149:156823d33999 9866 * | | |0 = ICE debug mode acknowledgement affects SC counting.
<> 149:156823d33999 9867 * | | |SC internal counter will be held while CPU is held by ICE.
<> 149:156823d33999 9868 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 149:156823d33999 9869 * | | |SC internal counter will keep going no matter CPU is held by ICE or not.
<> 149:156823d33999 9870 * @var SC_T::ALTCTL
<> 149:156823d33999 9871 * Offset: 0x08 SC Alternate Control Register.
<> 149:156823d33999 9872 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9873 * |Bits |Field |Descriptions
<> 149:156823d33999 9874 * | :----: | :----: | :---- |
<> 149:156823d33999 9875 * |[0] |TXRST |TX Software Reset
<> 149:156823d33999 9876 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
<> 149:156823d33999 9877 * | | |0 = No effect.
<> 149:156823d33999 9878 * | | |1 = Reset the TX internal state machine and pointers.
<> 149:156823d33999 9879 * | | |Note:
<> 149:156823d33999 9880 * | | |This bit will be auto cleared after reset is complete.
<> 149:156823d33999 9881 * |[1] |RXRST |Rx Software Reset
<> 149:156823d33999 9882 * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
<> 149:156823d33999 9883 * | | |0 = No effect.
<> 149:156823d33999 9884 * | | |1 = Reset the Rx internal state machine and pointers.
<> 149:156823d33999 9885 * | | |Note:
<> 149:156823d33999 9886 * | | |This bit will be auto cleared after reset is complete.
<> 149:156823d33999 9887 * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
<> 149:156823d33999 9888 * | | |This bit enables SC controller to initiate the card by deactivation sequence
<> 149:156823d33999 9889 * | | |0 = No effect.
<> 149:156823d33999 9890 * | | |1 = Deactivation sequence generator Enabled.
<> 149:156823d33999 9891 * | | |Note1:
<> 149:156823d33999 9892 * | | |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 149:156823d33999 9893 * | | |Note2:
<> 149:156823d33999 9894 * | | |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 149:156823d33999 9895 * | | |So don't fill this bit, TXRST, and RXRST at the same time.
<> 149:156823d33999 9896 * | | |Note3:
<> 149:156823d33999 9897 * | | |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9898 * |[3] |ACTEN |Activation Sequence Generator Enable Bit
<> 149:156823d33999 9899 * | | |This bit enables SC controller to initiate the card by activation sequence
<> 149:156823d33999 9900 * | | |0 = No effect.
<> 149:156823d33999 9901 * | | |1 = Activation sequence generator Enabled.
<> 149:156823d33999 9902 * | | |Note1:
<> 149:156823d33999 9903 * | | |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 149:156823d33999 9904 * | | |Note2:
<> 149:156823d33999 9905 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 149:156823d33999 9906 * | | |Note3:
<> 149:156823d33999 9907 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9908 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
<> 149:156823d33999 9909 * | | |This bit enables SC controller to initiate the card by warm reset sequence
<> 149:156823d33999 9910 * | | |0 = No effect.
<> 149:156823d33999 9911 * | | |1 = Warm reset sequence generator Enabled.
<> 149:156823d33999 9912 * | | |Note1:
<> 149:156823d33999 9913 * | | |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 149:156823d33999 9914 * | | |Note2:
<> 149:156823d33999 9915 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
<> 149:156823d33999 9916 * | | |Note3:
<> 149:156823d33999 9917 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9918 * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
<> 149:156823d33999 9919 * | | |This bit enables Timer 0 to start counting.
<> 149:156823d33999 9920 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 149:156823d33999 9921 * | | |0 = Stops counting.
<> 149:156823d33999 9922 * | | |1 = Start counting.
<> 149:156823d33999 9923 * | | |Note1:
<> 149:156823d33999 9924 * | | |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
<> 149:156823d33999 9925 * | | |Note2:
<> 149:156823d33999 9926 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
<> 149:156823d33999 9927 * | | |Note3:
<> 149:156823d33999 9928 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 149:156823d33999 9929 * | | |So don't fill this bit, TXRST and RXRST at the same time.
<> 149:156823d33999 9930 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9931 * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
<> 149:156823d33999 9932 * | | |This bit enables Timer 1 to start counting.
<> 149:156823d33999 9933 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 149:156823d33999 9934 * | | |0 = Stops counting.
<> 149:156823d33999 9935 * | | |1 = Start counting.
<> 149:156823d33999 9936 * | | |Note1:
<> 149:156823d33999 9937 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
<> 149:156823d33999 9938 * | | |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
<> 149:156823d33999 9939 * | | |Note2:
<> 149:156823d33999 9940 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
<> 149:156823d33999 9941 * | | |Note3:
<> 149:156823d33999 9942 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 149:156823d33999 9943 * | | |Note4:
<> 149:156823d33999 9944 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9945 * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
<> 149:156823d33999 9946 * | | |This bit enables Timer 2 to start counting.
<> 149:156823d33999 9947 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 149:156823d33999 9948 * | | |0 = Stops counting.
<> 149:156823d33999 9949 * | | |1 = Start counting.
<> 149:156823d33999 9950 * | | |Note1:
<> 149:156823d33999 9951 * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
<> 149:156823d33999 9952 * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
<> 149:156823d33999 9953 * | | |Note2:
<> 149:156823d33999 9954 * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
<> 149:156823d33999 9955 * | | |Note3:
<> 149:156823d33999 9956 * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 149:156823d33999 9957 * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 149:156823d33999 9958 * | | |Note4:
<> 149:156823d33999 9959 * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 149:156823d33999 9960 * |[9:8] |INITSEL |Initial Timing Selection
<> 149:156823d33999 9961 * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
<> 149:156823d33999 9962 * | | |Unit: SC clock
<> 149:156823d33999 9963 * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4
<> 149:156823d33999 9964 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
<> 149:156823d33999 9965 * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
<> 149:156823d33999 9966 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
<> 149:156823d33999 9967 * | | |0 = Receiver block guard time function Disabled.
<> 149:156823d33999 9968 * | | |1 = Receiver block guard time function Enabled.
<> 149:156823d33999 9969 * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
<> 149:156823d33999 9970 * | | |This bit indicates the timer counter status of timer0.
<> 149:156823d33999 9971 * | | |0 = Timer0 is not active.
<> 149:156823d33999 9972 * | | |1 = Timer0 is active.
<> 149:156823d33999 9973 * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
<> 149:156823d33999 9974 * | | |This bit indicates the timer counter status of timer1.
<> 149:156823d33999 9975 * | | |0 = Timer1 is not active.
<> 149:156823d33999 9976 * | | |1 = Timer1 is active.
<> 149:156823d33999 9977 * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
<> 149:156823d33999 9978 * | | |This bit indicates the timer counter status of timer2.
<> 149:156823d33999 9979 * | | |0 = Timer2 is not active.
<> 149:156823d33999 9980 * | | |1 = Timer2 is active.
<> 149:156823d33999 9981 * @var SC_T::EGT
<> 149:156823d33999 9982 * Offset: 0x0C SC Extend Guard Time Register.
<> 149:156823d33999 9983 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9984 * |Bits |Field |Descriptions
<> 149:156823d33999 9985 * | :----: | :----: | :---- |
<> 149:156823d33999 9986 * |[7:0] |EGT |Extended Guard Time
<> 149:156823d33999 9987 * | | |This field indicates the extended guard timer value.
<> 149:156823d33999 9988 * | | |Note:
<> 149:156823d33999 9989 * | | |The counter is ETU base and the real extended guard time is EGT.
<> 149:156823d33999 9990 * @var SC_T::RXTOUT
<> 149:156823d33999 9991 * Offset: 0x10 SC Receive buffer Time-out Register.
<> 149:156823d33999 9992 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 9993 * |Bits |Field |Descriptions
<> 149:156823d33999 9994 * | :----: | :----: | :---- |
<> 149:156823d33999 9995 * |[8:0] |RFTM |SC Receiver FIFO Time-out (ETU Base)
<> 149:156823d33999 9996 * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
<> 149:156823d33999 9997 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
<> 149:156823d33999 9998 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
<> 149:156823d33999 9999 * | | |Note2:
<> 149:156823d33999 10000 * | | |Filling all 0 to this field indicates to disable this function.
<> 149:156823d33999 10001 * @var SC_T::ETUCTL
<> 149:156823d33999 10002 * Offset: 0x14 SC ETU Control Register.
<> 149:156823d33999 10003 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10004 * |Bits |Field |Descriptions
<> 149:156823d33999 10005 * | :----: | :----: | :---- |
<> 149:156823d33999 10006 * |[11:0] |ETURDIV |ETU Rate Divider
<> 149:156823d33999 10007 * | | |The field indicates the clock rate divider.
<> 149:156823d33999 10008 * | | |The real ETU is ETURDIV + 1.
<> 149:156823d33999 10009 * | | |Note:
<> 149:156823d33999 10010 * | | |Software can configure this field, but this field must be greater than 0x004.
<> 149:156823d33999 10011 * |[15] |CMPEN |Compensation Mode Enable Bit
<> 149:156823d33999 10012 * | | |This bit enables clock compensation function.
<> 149:156823d33999 10013 * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
<> 149:156823d33999 10014 * | | |0 = Compensation function Disabled.
<> 149:156823d33999 10015 * | | |1 = Compensation function Enabled.
<> 149:156823d33999 10016 * @var SC_T::INTEN
<> 149:156823d33999 10017 * Offset: 0x18 SC Interrupt Enable Control Register.
<> 149:156823d33999 10018 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10019 * |Bits |Field |Descriptions
<> 149:156823d33999 10020 * | :----: | :----: | :---- |
<> 149:156823d33999 10021 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
<> 149:156823d33999 10022 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
<> 149:156823d33999 10023 * | | |0 = Receive data reach trigger level interrupt Disabled.
<> 149:156823d33999 10024 * | | |1 = Receive data reach trigger level interrupt Enabled.
<> 149:156823d33999 10025 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
<> 149:156823d33999 10026 * | | |This field is used for transmit buffer empty interrupt enable.
<> 149:156823d33999 10027 * | | |0 = Transmit buffer empty interrupt Disabled.
<> 149:156823d33999 10028 * | | |1 = Transmit buffer empty interrupt Enabled.
<> 149:156823d33999 10029 * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
<> 149:156823d33999 10030 * | | |This field is used for transfer error interrupt enable.
<> 149:156823d33999 10031 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
<> 149:156823d33999 10032 * | | |0 = Transfer error interrupt Disabled.
<> 149:156823d33999 10033 * | | |1 = Transfer error interrupt Enabled.
<> 149:156823d33999 10034 * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
<> 149:156823d33999 10035 * | | |This field is used to enable TMR0 interrupt enable.
<> 149:156823d33999 10036 * | | |0 = Timer0 interrupt Disabled.
<> 149:156823d33999 10037 * | | |1 = Timer0 interrupt Enabled.
<> 149:156823d33999 10038 * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
<> 149:156823d33999 10039 * | | |This field is used to enable the TMR1 interrupt.
<> 149:156823d33999 10040 * | | |0 = Timer1 interrupt Disabled.
<> 149:156823d33999 10041 * | | |1 = Timer1 interrupt Enabled.
<> 149:156823d33999 10042 * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
<> 149:156823d33999 10043 * | | |This field is used for TMR2 interrupt enable.
<> 149:156823d33999 10044 * | | |0 = Timer2 interrupt Disabled.
<> 149:156823d33999 10045 * | | |1 = Timer2 interrupt Enabled.
<> 149:156823d33999 10046 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
<> 149:156823d33999 10047 * | | |This field is used for block guard time interrupt enable.
<> 149:156823d33999 10048 * | | |0 = Block guard time Disabled.
<> 149:156823d33999 10049 * | | |1 = Block guard time Enabled.
<> 149:156823d33999 10050 * |[7] |CDIEN |Card Detect Interrupt Enable Bit
<> 149:156823d33999 10051 * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
<> 149:156823d33999 10052 * | | |0 = Card detect interrupt Disabled.
<> 149:156823d33999 10053 * | | |1 = Card detect interrupt Enabled.
<> 149:156823d33999 10054 * |[8] |INITIEN |Initial End Interrupt Enable Bit
<> 149:156823d33999 10055 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
<> 149:156823d33999 10056 * | | |0 = Initial end interrupt Disabled.
<> 149:156823d33999 10057 * | | |1 = Initial end interrupt Enabled.
<> 149:156823d33999 10058 * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Bit
<> 149:156823d33999 10059 * | | |This field is used for receiver buffer time-out interrupt enable.
<> 149:156823d33999 10060 * | | |0 = Receiver buffer time-out interrupt Disabled.
<> 149:156823d33999 10061 * | | |1 = Receiver buffer time-out interrupt Enabled.
<> 149:156823d33999 10062 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
<> 149:156823d33999 10063 * | | |This field is used for auto-convention error interrupt enable.
<> 149:156823d33999 10064 * | | |0 = Auto-convention error interrupt Disabled.
<> 149:156823d33999 10065 * | | |1 = Auto-convention error interrupt Enabled.
<> 149:156823d33999 10066 * @var SC_T::INTSTS
<> 149:156823d33999 10067 * Offset: 0x1C SC Interrupt Status Register.
<> 149:156823d33999 10068 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10069 * |Bits |Field |Descriptions
<> 149:156823d33999 10070 * | :----: | :----: | :---- |
<> 149:156823d33999 10071 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
<> 149:156823d33999 10072 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
<> 149:156823d33999 10073 * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
<> 149:156823d33999 10074 * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
<> 149:156823d33999 10075 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
<> 149:156823d33999 10076 * | | |This field is used for transmit buffer empty interrupt status flag.
<> 149:156823d33999 10077 * | | |Note: This field is the status flag of transmit buffer empty state.
<> 149:156823d33999 10078 * | | |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
<> 149:156823d33999 10079 * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
<> 149:156823d33999 10080 * | | |This field is used for transfer error interrupt status flag.
<> 149:156823d33999 10081 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
<> 149:156823d33999 10082 * | | |Note: This field is the status flag of
<> 149:156823d33999 10083 * | | |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
<> 149:156823d33999 10084 * | | |So, if software wants to clear this bit, software must write 1 to each field.
<> 149:156823d33999 10085 * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
<> 149:156823d33999 10086 * | | |This field is used for TMR0 interrupt status flag.
<> 149:156823d33999 10087 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10088 * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
<> 149:156823d33999 10089 * | | |This field is used for TMR1 interrupt status flag.
<> 149:156823d33999 10090 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10091 * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
<> 149:156823d33999 10092 * | | |This field is used for TMR2 interrupt status flag.
<> 149:156823d33999 10093 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10094 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
<> 149:156823d33999 10095 * | | |This field is used for block guard time interrupt status flag.
<> 149:156823d33999 10096 * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
<> 149:156823d33999 10097 * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
<> 149:156823d33999 10098 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
<> 149:156823d33999 10099 * | | |This field is used for card detect interrupt status flag.
<> 149:156823d33999 10100 * | | |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
<> 149:156823d33999 10101 * | | |Note:
<> 149:156823d33999 10102 * | | |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
<> 149:156823d33999 10103 * | | |So if software wants to clear this bit, software must write 1 to this field.
<> 149:156823d33999 10104 * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
<> 149:156823d33999 10105 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
<> 149:156823d33999 10106 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10107 * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
<> 149:156823d33999 10108 * | | |This field is used for receiver buffer time-out interrupt status flag.
<> 149:156823d33999 10109 * | | |Note: This field is the status flag of receiver buffer time-out state.
<> 149:156823d33999 10110 * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
<> 149:156823d33999 10111 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
<> 149:156823d33999 10112 * | | |This field indicates auto convention sequence error.
<> 149:156823d33999 10113 * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
<> 149:156823d33999 10114 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10115 * @var SC_T::STATUS
<> 149:156823d33999 10116 * Offset: 0x20 SC Status Register.
<> 149:156823d33999 10117 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10118 * |Bits |Field |Descriptions
<> 149:156823d33999 10119 * | :----: | :----: | :---- |
<> 149:156823d33999 10120 * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
<> 149:156823d33999 10121 * | | |This bit is set when RX buffer overflow.
<> 149:156823d33999 10122 * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
<> 149:156823d33999 10123 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10124 * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
<> 149:156823d33999 10125 * | | |This bit indicates RX buffer empty or not.
<> 149:156823d33999 10126 * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
<> 149:156823d33999 10127 * | | |It will be cleared when SC receives any new data.
<> 149:156823d33999 10128 * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
<> 149:156823d33999 10129 * | | |This bit indicates RX buffer full or not.
<> 149:156823d33999 10130 * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
<> 149:156823d33999 10131 * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
<> 149:156823d33999 10132 * | | |This bit is set to logic 1 whenever the received character does not have a valid
<> 149:156823d33999 10133 * | | |"parity bit".
<> 149:156823d33999 10134 * | | |Note1:
<> 149:156823d33999 10135 * | | |This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10136 * | | |Note2:
<> 149:156823d33999 10137 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 149:156823d33999 10138 * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
<> 149:156823d33999 10139 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
<> 149:156823d33999 10140 * | | |Note1:
<> 149:156823d33999 10141 * | | |This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10142 * | | |Note2:
<> 149:156823d33999 10143 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 149:156823d33999 10144 * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
<> 149:156823d33999 10145 * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
<> 149:156823d33999 10146 * | | |.
<> 149:156823d33999 10147 * | | |Note1:
<> 149:156823d33999 10148 * | | |This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10149 * | | |Note2:
<> 149:156823d33999 10150 * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 149:156823d33999 10151 * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
<> 149:156823d33999 10152 * | | |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
<> 149:156823d33999 10153 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10154 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
<> 149:156823d33999 10155 * | | |This bit indicates TX buffer empty or not.
<> 149:156823d33999 10156 * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
<> 149:156823d33999 10157 * | | |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
<> 149:156823d33999 10158 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
<> 149:156823d33999 10159 * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
<> 149:156823d33999 10160 * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
<> 149:156823d33999 10161 * | | |This bit is set whenever card has been removal.
<> 149:156823d33999 10162 * | | |0 = No effect.
<> 149:156823d33999 10163 * | | |1 = Card removed.
<> 149:156823d33999 10164 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
<> 149:156823d33999 10165 * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
<> 149:156823d33999 10166 * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
<> 149:156823d33999 10167 * | | |This bit is set whenever card has been inserted.
<> 149:156823d33999 10168 * | | |0 = No effect.
<> 149:156823d33999 10169 * | | |1 = Card insert.
<> 149:156823d33999 10170 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
<> 149:156823d33999 10171 * | | |Note2: The
<> 149:156823d33999 10172 * | | |card detect engine will start after SCEN (SC_CTL[0]) set.
<> 149:156823d33999 10173 * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
<> 149:156823d33999 10174 * | | |This bit is the pin status flag of SC_CD
<> 149:156823d33999 10175 * | | |0 = The SC_CD pin state at low.
<> 149:156823d33999 10176 * | | |1 = The SC_CD pin state at high.
<> 149:156823d33999 10177 * |[17:16] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
<> 149:156823d33999 10178 * | | |This field indicates the RX buffer pointer status flag.
<> 149:156823d33999 10179 * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
<> 149:156823d33999 10180 * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
<> 149:156823d33999 10181 * |[21] |RXRERR |Receiver Retry Error (Read Only)
<> 149:156823d33999 10182 * | | |This bit is set by hardware when RX has any error and retries transfer.
<> 149:156823d33999 10183 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10184 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
<> 149:156823d33999 10185 * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
<> 149:156823d33999 10186 * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
<> 149:156823d33999 10187 * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
<> 149:156823d33999 10188 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10189 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
<> 149:156823d33999 10190 * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
<> 149:156823d33999 10191 * | | |This bit is set by hardware when RX transfer is in active.
<> 149:156823d33999 10192 * | | |This bit is cleared automatically when RX transfer is finished.
<> 149:156823d33999 10193 * |[25:24] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
<> 149:156823d33999 10194 * | | |This field indicates the TX buffer pointer status flag.
<> 149:156823d33999 10195 * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
<> 149:156823d33999 10196 * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
<> 149:156823d33999 10197 * |[29] |TXRERR |Transmitter Retry Error (Read Only)
<> 149:156823d33999 10198 * | | |This bit is set by hardware when transmitter re-transmits.
<> 149:156823d33999 10199 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10200 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
<> 149:156823d33999 10201 * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
<> 149:156823d33999 10202 * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
<> 149:156823d33999 10203 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 10204 * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
<> 149:156823d33999 10205 * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
<> 149:156823d33999 10206 * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
<> 149:156823d33999 10207 * @var SC_T::PINCTL
<> 149:156823d33999 10208 * Offset: 0x24 SC Pin Control State Register.
<> 149:156823d33999 10209 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10210 * |Bits |Field |Descriptions
<> 149:156823d33999 10211 * | :----: | :----: | :---- |
<> 149:156823d33999 10212 * |[0] |PWREN |SC_PWREN Pin Signal
<> 149:156823d33999 10213 * | | |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
<> 149:156823d33999 10214 * | | |Write this field to drive SC_PWR pin
<> 149:156823d33999 10215 * | | |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
<> 149:156823d33999 10216 * | | |Read this field to get SC_PWR pin status.
<> 149:156823d33999 10217 * | | |0 = SC_PWR pin status is low.
<> 149:156823d33999 10218 * | | |1 = SC_PWR pin status is high.
<> 149:156823d33999 10219 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10220 * | | |So don't fill this field when operating in these modes.
<> 149:156823d33999 10221 * |[1] |SCRST |SC_RST Pin Signal
<> 149:156823d33999 10222 * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
<> 149:156823d33999 10223 * | | |Write this field to drive SC_RST pin.
<> 149:156823d33999 10224 * | | |0 = Drive SC_RST pin to low.
<> 149:156823d33999 10225 * | | |1 = Drive SC_RST pin to high.
<> 149:156823d33999 10226 * | | |Read this field to get SC_RST pin status.
<> 149:156823d33999 10227 * | | |0 = SC_RST pin status is low.
<> 149:156823d33999 10228 * | | |1 = SC_RST pin status is high.
<> 149:156823d33999 10229 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10230 * | | |So don't fill this field when operating in these modes.
<> 149:156823d33999 10231 * |[5] |CSTOPLV |SC Clock Stop Level
<> 149:156823d33999 10232 * | | |This field indicates the clock polarity control in clock stop mode.
<> 149:156823d33999 10233 * | | |0 = SC_CLK stopped in low level.
<> 149:156823d33999 10234 * | | |1 = SC_CLK stopped in high level.
<> 149:156823d33999 10235 * |[6] |CLKKEEP |SC Clock Enable Bit
<> 149:156823d33999 10236 * | | |0 = SC clock generation Disabled.
<> 149:156823d33999 10237 * | | |1 = SC clock always keeps free running.
<> 149:156823d33999 10238 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10239 * | | |So don't fill this field when operating in these modes.
<> 149:156823d33999 10240 * |[9] |SCDOUT |SC Data Output Pin
<> 149:156823d33999 10241 * | | |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
<> 149:156823d33999 10242 * | | |0 = Drive SCDATOUT pin to low.
<> 149:156823d33999 10243 * | | |1 = Drive SCDATOUT pin to high.
<> 149:156823d33999 10244 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10245 * | | |So don't fill this field when SC is in these modes.
<> 149:156823d33999 10246 * |[11] |PWRINV |SC_POW Pin Inverse
<> 149:156823d33999 10247 * | | |This bit is used for inverse the SC_POW pin.
<> 149:156823d33999 10248 * | | |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
<> 149:156823d33999 10249 * | | |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
<> 149:156823d33999 10250 * | | |00 = SC_POW_ Pin is 0.
<> 149:156823d33999 10251 * | | |01 = SC_POW _Pin is 1.
<> 149:156823d33999 10252 * | | |10 = SC_POW _Pin is 1.
<> 149:156823d33999 10253 * | | |11 = SC_POW_ Pin is 0.
<> 149:156823d33999 10254 * | | |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
<> 149:156823d33999 10255 * |[12] |SCDOSTS |SC Data Pin Output Status
<> 149:156823d33999 10256 * | | |This bit is the pin status of SCDATOUT
<> 149:156823d33999 10257 * | | |0 = SCDATOUT pin to low.
<> 149:156823d33999 10258 * | | |1 = SCDATOUT pin to high.
<> 149:156823d33999 10259 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10260 * | | |This bit is not allowed to program when SC is operated at these modes.
<> 149:156823d33999 10261 * |[16] |DATSTS |This bit is the pin status of SC_DAT
<> 149:156823d33999 10262 * | | |0 = The SC_DAT pin is low.
<> 149:156823d33999 10263 * | | |1 = The SC_DAT pin is high.
<> 149:156823d33999 10264 * |[17] |PWRSTS |SC_PWR Pin Signal
<> 149:156823d33999 10265 * | | |This bit is the pin status of SC_PWR
<> 149:156823d33999 10266 * | | |0 = SC_PWR pin to low.
<> 149:156823d33999 10267 * | | |1 = SC_PWR pin to high.
<> 149:156823d33999 10268 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10269 * | | |This bit is not allowed to program when SC is operated at these modes.
<> 149:156823d33999 10270 * |[18] |RSTSTS |SCRST Pin Signals
<> 149:156823d33999 10271 * | | |This bit is the pin status of SC_RST
<> 149:156823d33999 10272 * | | |0 = SC_RST pin is low.
<> 149:156823d33999 10273 * | | |1 = SC_RST pin is high.
<> 149:156823d33999 10274 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 149:156823d33999 10275 * | | |This bit is not allowed to program when SC is operated at these modes.
<> 149:156823d33999 10276 * |[30] |SYNC |SYNC Flag Indicator
<> 149:156823d33999 10277 * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
<> 149:156823d33999 10278 * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
<> 149:156823d33999 10279 * | | |1 = Last value is synchronizing.
<> 149:156823d33999 10280 * | | |Note: This bit is read only.
<> 149:156823d33999 10281 * |[31] |LOOPBK |Loop Back Test
<> 149:156823d33999 10282 * | | |0 = loop back test Disabled.
<> 149:156823d33999 10283 * | | |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
<> 149:156823d33999 10284 * @var SC_T::TMRCTL0
<> 149:156823d33999 10285 * Offset: 0x28 SC Internal Timer Control Register 0.
<> 149:156823d33999 10286 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10287 * |Bits |Field |Descriptions
<> 149:156823d33999 10288 * | :----: | :----: | :---- |
<> 149:156823d33999 10289 * |[23:0] |CNT |Timer 0 Counter Value (ETU Base)
<> 149:156823d33999 10290 * | | |This field indicates the internal timer operation values.
<> 149:156823d33999 10291 * |[27:24] |OPMODE |Timer 0 Operation Mode Selection
<> 149:156823d33999 10292 * | | |This field indicates the internal 24-bit timer operation selection.
<> 149:156823d33999 10293 * | | |Refer to 6.17.5.4 for programming Timer0
<> 149:156823d33999 10294 * @var SC_T::TMRCTL1
<> 149:156823d33999 10295 * Offset: 0x2C SC Internal Timer Control Register 1.
<> 149:156823d33999 10296 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10297 * |Bits |Field |Descriptions
<> 149:156823d33999 10298 * | :----: | :----: | :---- |
<> 149:156823d33999 10299 * |[7:0] |CNT |Timer 1 Counter Value (ETU Base)
<> 149:156823d33999 10300 * | | |This field indicates the internal timer operation values.
<> 149:156823d33999 10301 * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
<> 149:156823d33999 10302 * | | |This field indicates the internal 8-bit timer operation selection.
<> 149:156823d33999 10303 * | | |Refer to 6.17.5.4 for programming Timer1
<> 149:156823d33999 10304 * @var SC_T::TMRCTL2
<> 149:156823d33999 10305 * Offset: 0x30 SC Internal Timer Control Register 2.
<> 149:156823d33999 10306 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10307 * |Bits |Field |Descriptions
<> 149:156823d33999 10308 * | :----: | :----: | :---- |
<> 149:156823d33999 10309 * |[7:0] |CNT |Timer 2 Counter Value (ETU Base)
<> 149:156823d33999 10310 * | | |This field indicates the internal timer operation values.
<> 149:156823d33999 10311 * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
<> 149:156823d33999 10312 * | | |This field indicates the internal 8-bit timer operation selection
<> 149:156823d33999 10313 * | | |Refer to 6.17.5.4 for programming Timer2
<> 149:156823d33999 10314 * @var SC_T::UARTCTL
<> 149:156823d33999 10315 * Offset: 0x34 SC UART Mode Control Register.
<> 149:156823d33999 10316 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10317 * |Bits |Field |Descriptions
<> 149:156823d33999 10318 * | :----: | :----: | :---- |
<> 149:156823d33999 10319 * |[0] |UARTEN |UART Mode Enable Bit
<> 149:156823d33999 10320 * | | |0 = Smart Card mode.
<> 149:156823d33999 10321 * | | |1 = UART mode.
<> 149:156823d33999 10322 * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
<> 149:156823d33999 10323 * | | |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
<> 149:156823d33999 10324 * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
<> 149:156823d33999 10325 * |[5:4] |WLS10 |Word Length Selection
<> 149:156823d33999 10326 * | | |00 = Word length is 8 bits.
<> 149:156823d33999 10327 * | | |01 = Word length is 7 bits.
<> 149:156823d33999 10328 * | | |10 = Word length is 6 bits.
<> 149:156823d33999 10329 * | | |11 = Word length is 5 bits.
<> 149:156823d33999 10330 * | | |Note: In smart card mode, this WLS must be '00'
<> 149:156823d33999 10331 * |[6] |PBOFF |Parity Bit Disable Control
<> 149:156823d33999 10332 * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
<> 149:156823d33999 10333 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
<> 149:156823d33999 10334 * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
<> 149:156823d33999 10335 * |[7] |OPE |Odd Parity Enable Bit
<> 149:156823d33999 10336 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
<> 149:156823d33999 10337 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
<> 149:156823d33999 10338 * | | |Note: This bit has effect only when PBOFF bit is '0'.
<> 149:156823d33999 10339 * @var SC_T::TMRDAT0
<> 149:156823d33999 10340 * Offset: 0x38 SC Timer Current Data Register A.
<> 149:156823d33999 10341 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10342 * |Bits |Field |Descriptions
<> 149:156823d33999 10343 * | :----: | :----: | :---- |
<> 149:156823d33999 10344 * |[23:0] |CNT0 |Timer0 Current Data Value (Read Only)
<> 149:156823d33999 10345 * | | |This field indicates the current count values of timer0.
<> 149:156823d33999 10346 * @var SC_T::TMRDAT1_2
<> 149:156823d33999 10347 * Offset: 0x3C SC Timer Current Data Register B.
<> 149:156823d33999 10348 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10349 * |Bits |Field |Descriptions
<> 149:156823d33999 10350 * | :----: | :----: | :---- |
<> 149:156823d33999 10351 * |[7:0] |CNT1 |Timer1 Current Data Value (Read Only)
<> 149:156823d33999 10352 * | | |This field indicates the current count values of timer1.
<> 149:156823d33999 10353 * |[15:8] |CNT2 |Timer2 Current Data Value (Read Only)
<> 149:156823d33999 10354 * | | |This field indicates the current count values of timer2.
<> 149:156823d33999 10355 */
<> 149:156823d33999 10356
<> 149:156823d33999 10357 __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
<> 149:156823d33999 10358 __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
<> 149:156823d33999 10359 __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
<> 149:156823d33999 10360 __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
<> 149:156823d33999 10361 __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
<> 149:156823d33999 10362 __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
<> 149:156823d33999 10363 __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
<> 149:156823d33999 10364 __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
<> 149:156823d33999 10365 __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
<> 149:156823d33999 10366 __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
<> 149:156823d33999 10367 __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
<> 149:156823d33999 10368 __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
<> 149:156823d33999 10369 __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
<> 149:156823d33999 10370 __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
<> 149:156823d33999 10371 __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
<> 149:156823d33999 10372 __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
<> 149:156823d33999 10373
<> 149:156823d33999 10374 } SC_T;
<> 149:156823d33999 10375
<> 149:156823d33999 10376
<> 149:156823d33999 10377
<> 149:156823d33999 10378 /**
<> 149:156823d33999 10379 @addtogroup SC_CONST SC Bit Field Definition
<> 149:156823d33999 10380 Constant Definitions for SC Controller
<> 149:156823d33999 10381 @{ */
<> 149:156823d33999 10382
<> 149:156823d33999 10383 #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
<> 149:156823d33999 10384 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
<> 149:156823d33999 10385
<> 149:156823d33999 10386 #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
<> 149:156823d33999 10387 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
<> 149:156823d33999 10388
<> 149:156823d33999 10389 #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
<> 149:156823d33999 10390 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
<> 149:156823d33999 10391
<> 149:156823d33999 10392 #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
<> 149:156823d33999 10393 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
<> 149:156823d33999 10394
<> 149:156823d33999 10395 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
<> 149:156823d33999 10396 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
<> 149:156823d33999 10397
<> 149:156823d33999 10398 #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
<> 149:156823d33999 10399 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
<> 149:156823d33999 10400
<> 149:156823d33999 10401 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
<> 149:156823d33999 10402 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
<> 149:156823d33999 10403
<> 149:156823d33999 10404 #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
<> 149:156823d33999 10405 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
<> 149:156823d33999 10406
<> 149:156823d33999 10407 #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
<> 149:156823d33999 10408 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
<> 149:156823d33999 10409
<> 149:156823d33999 10410 #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
<> 149:156823d33999 10411 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
<> 149:156823d33999 10412
<> 149:156823d33999 10413 #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
<> 149:156823d33999 10414 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
<> 149:156823d33999 10415
<> 149:156823d33999 10416 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
<> 149:156823d33999 10417 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
<> 149:156823d33999 10418
<> 149:156823d33999 10419 #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
<> 149:156823d33999 10420 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
<> 149:156823d33999 10421
<> 149:156823d33999 10422 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
<> 149:156823d33999 10423 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
<> 149:156823d33999 10424
<> 149:156823d33999 10425 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
<> 149:156823d33999 10426 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
<> 149:156823d33999 10427
<> 149:156823d33999 10428 #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
<> 149:156823d33999 10429 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
<> 149:156823d33999 10430
<> 149:156823d33999 10431 #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
<> 149:156823d33999 10432 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
<> 149:156823d33999 10433
<> 149:156823d33999 10434 #define SC_CTL_ICEDEBUG_Pos (31) /*!< SC_T::CTL: ICEDEBUG Position */
<> 149:156823d33999 10435 #define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) /*!< SC_T::CTL: ICEDEBUG Mask */
<> 149:156823d33999 10436
<> 149:156823d33999 10437 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
<> 149:156823d33999 10438 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
<> 149:156823d33999 10439
<> 149:156823d33999 10440 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
<> 149:156823d33999 10441 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
<> 149:156823d33999 10442
<> 149:156823d33999 10443 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
<> 149:156823d33999 10444 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
<> 149:156823d33999 10445
<> 149:156823d33999 10446 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
<> 149:156823d33999 10447 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
<> 149:156823d33999 10448
<> 149:156823d33999 10449 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
<> 149:156823d33999 10450 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
<> 149:156823d33999 10451
<> 149:156823d33999 10452 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
<> 149:156823d33999 10453 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
<> 149:156823d33999 10454
<> 149:156823d33999 10455 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
<> 149:156823d33999 10456 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
<> 149:156823d33999 10457
<> 149:156823d33999 10458 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
<> 149:156823d33999 10459 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
<> 149:156823d33999 10460
<> 149:156823d33999 10461 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
<> 149:156823d33999 10462 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
<> 149:156823d33999 10463
<> 149:156823d33999 10464 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
<> 149:156823d33999 10465 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
<> 149:156823d33999 10466
<> 149:156823d33999 10467 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
<> 149:156823d33999 10468 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
<> 149:156823d33999 10469
<> 149:156823d33999 10470 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
<> 149:156823d33999 10471 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
<> 149:156823d33999 10472
<> 149:156823d33999 10473 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
<> 149:156823d33999 10474 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
<> 149:156823d33999 10475
<> 149:156823d33999 10476 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
<> 149:156823d33999 10477 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
<> 149:156823d33999 10478
<> 149:156823d33999 10479 #define SC_ALTCTL_OUTSEL_Pos (16) /*!< SC_T::ALTCTL: OUTSEL Position */
<> 149:156823d33999 10480 #define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */
<> 149:156823d33999 10481
<> 149:156823d33999 10482 #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
<> 149:156823d33999 10483 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
<> 149:156823d33999 10484
<> 149:156823d33999 10485 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
<> 149:156823d33999 10486 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
<> 149:156823d33999 10487
<> 149:156823d33999 10488 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV_ Position */
<> 149:156823d33999 10489 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV_ Mask */
<> 149:156823d33999 10490
<> 149:156823d33999 10491 #define SC_ETUCTL_CMPEN_Pos (15) /*!< SC_T::ETUCTL: CMPEN_ Position */
<> 149:156823d33999 10492 #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC_T::ETUCTL: CMPEN_ Mask */
<> 149:156823d33999 10493
<> 149:156823d33999 10494 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
<> 149:156823d33999 10495 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
<> 149:156823d33999 10496
<> 149:156823d33999 10497 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
<> 149:156823d33999 10498 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
<> 149:156823d33999 10499
<> 149:156823d33999 10500 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
<> 149:156823d33999 10501 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
<> 149:156823d33999 10502
<> 149:156823d33999 10503 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN_Position */
<> 149:156823d33999 10504 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
<> 149:156823d33999 10505
<> 149:156823d33999 10506 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
<> 149:156823d33999 10507 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
<> 149:156823d33999 10508
<> 149:156823d33999 10509 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
<> 149:156823d33999 10510 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
<> 149:156823d33999 10511
<> 149:156823d33999 10512 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
<> 149:156823d33999 10513 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
<> 149:156823d33999 10514
<> 149:156823d33999 10515 #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
<> 149:156823d33999 10516 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
<> 149:156823d33999 10517
<> 149:156823d33999 10518 #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
<> 149:156823d33999 10519 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
<> 149:156823d33999 10520
<> 149:156823d33999 10521 #define SC_INTEN_RXTOIF_Pos (9) /*!< SC_T::INTEN: RXTOIF Position */
<> 149:156823d33999 10522 #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC_T::INTEN: RXTOIF Mask */
<> 149:156823d33999 10523
<> 149:156823d33999 10524 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
<> 149:156823d33999 10525 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
<> 149:156823d33999 10526
<> 149:156823d33999 10527 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
<> 149:156823d33999 10528 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
<> 149:156823d33999 10529
<> 149:156823d33999 10530 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
<> 149:156823d33999 10531 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
<> 149:156823d33999 10532
<> 149:156823d33999 10533 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
<> 149:156823d33999 10534 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
<> 149:156823d33999 10535
<> 149:156823d33999 10536 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
<> 149:156823d33999 10537 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
<> 149:156823d33999 10538
<> 149:156823d33999 10539 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
<> 149:156823d33999 10540 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
<> 149:156823d33999 10541
<> 149:156823d33999 10542 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
<> 149:156823d33999 10543 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
<> 149:156823d33999 10544
<> 149:156823d33999 10545 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
<> 149:156823d33999 10546 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
<> 149:156823d33999 10547
<> 149:156823d33999 10548 #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
<> 149:156823d33999 10549 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
<> 149:156823d33999 10550
<> 149:156823d33999 10551 #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
<> 149:156823d33999 10552 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
<> 149:156823d33999 10553
<> 149:156823d33999 10554 #define SC_INTSTS_RBTOIF_Pos (9) /*!< SC_T::INTSTS: RBTOIF Position */
<> 149:156823d33999 10555 #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC_T::INTSTS: RBTOIF Mask */
<> 149:156823d33999 10556
<> 149:156823d33999 10557 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
<> 149:156823d33999 10558 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
<> 149:156823d33999 10559
<> 149:156823d33999 10560 #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXO Position */
<> 149:156823d33999 10561 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXO Mask */
<> 149:156823d33999 10562
<> 149:156823d33999 10563 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
<> 149:156823d33999 10564 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
<> 149:156823d33999 10565
<> 149:156823d33999 10566 #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
<> 149:156823d33999 10567 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
<> 149:156823d33999 10568
<> 149:156823d33999 10569 #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
<> 149:156823d33999 10570 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
<> 149:156823d33999 10571
<> 149:156823d33999 10572 #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
<> 149:156823d33999 10573 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
<> 149:156823d33999 10574
<> 149:156823d33999 10575 #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
<> 149:156823d33999 10576 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
<> 149:156823d33999 10577
<> 149:156823d33999 10578 #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
<> 149:156823d33999 10579 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
<> 149:156823d33999 10580
<> 149:156823d33999 10581 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
<> 149:156823d33999 10582 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
<> 149:156823d33999 10583
<> 149:156823d33999 10584 #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
<> 149:156823d33999 10585 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
<> 149:156823d33999 10586
<> 149:156823d33999 10587 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
<> 149:156823d33999 10588 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
<> 149:156823d33999 10589
<> 149:156823d33999 10590 #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
<> 149:156823d33999 10591 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
<> 149:156823d33999 10592
<> 149:156823d33999 10593 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
<> 149:156823d33999 10594 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
<> 149:156823d33999 10595
<> 149:156823d33999 10596 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
<> 149:156823d33999 10597 #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
<> 149:156823d33999 10598
<> 149:156823d33999 10599 #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
<> 149:156823d33999 10600 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
<> 149:156823d33999 10601
<> 149:156823d33999 10602 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
<> 149:156823d33999 10603 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
<> 149:156823d33999 10604
<> 149:156823d33999 10605 #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
<> 149:156823d33999 10606 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Msk */
<> 149:156823d33999 10607
<> 149:156823d33999 10608 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
<> 149:156823d33999 10609 #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Msk */
<> 149:156823d33999 10610
<> 149:156823d33999 10611 #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
<> 149:156823d33999 10612 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Msk */
<> 149:156823d33999 10613
<> 149:156823d33999 10614 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR_ Position */
<> 149:156823d33999 10615 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR_ Msk */
<> 149:156823d33999 10616
<> 149:156823d33999 10617 #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
<> 149:156823d33999 10618 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Msk */
<> 149:156823d33999 10619
<> 149:156823d33999 10620 #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
<> 149:156823d33999 10621 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Msk */
<> 149:156823d33999 10622
<> 149:156823d33999 10623 #define SC_PINCTL_SCRST_Pos (1) /*!< SC_T::PINCTL: SCRST Position */
<> 149:156823d33999 10624 #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC_T::PINCTL: SCRST Msk */
<> 149:156823d33999 10625
<> 149:156823d33999 10626 #define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
<> 149:156823d33999 10627 #define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Msk */
<> 149:156823d33999 10628
<> 149:156823d33999 10629 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
<> 149:156823d33999 10630 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Msk */
<> 149:156823d33999 10631
<> 149:156823d33999 10632 #define SC_PINCTL_SCDOUT_Pos (9) /*!< SC_T::PINCTL: SCDOUT Position */
<> 149:156823d33999 10633 #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC_T::PINCTL: SCDOUT Msk */
<> 149:156823d33999 10634
<> 149:156823d33999 10635 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
<> 149:156823d33999 10636 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Msk */
<> 149:156823d33999 10637
<> 149:156823d33999 10638 #define SC_PINCTL_SCDOSTS_Pos (12) /*!< SC_T::PINCTL: SCDOSTS Position */
<> 149:156823d33999 10639 #define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) /*!< SC_T::PINCTL: SCDOSTS Msk */
<> 149:156823d33999 10640
<> 149:156823d33999 10641 #define SC_PINCTL_DATSTS_Pos (16) /*!< SC_T::PINCTL: DATSTS Position */
<> 149:156823d33999 10642 #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC_T::PINCTL: DATSTS Msk */
<> 149:156823d33999 10643
<> 149:156823d33999 10644 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
<> 149:156823d33999 10645 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Msk */
<> 149:156823d33999 10646
<> 149:156823d33999 10647 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
<> 149:156823d33999 10648 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Msk */
<> 149:156823d33999 10649
<> 149:156823d33999 10650 #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
<> 149:156823d33999 10651 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Msk */
<> 149:156823d33999 10652
<> 149:156823d33999 10653 #define SC_PINCTL_LOOPBK_Pos (31) /*!< SC_T::PINCTL: LOOPBK Position */
<> 149:156823d33999 10654 #define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) /*!< SC_T::PINCTL: LOOPBK Msk */
<> 149:156823d33999 10655
<> 149:156823d33999 10656 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
<> 149:156823d33999 10657 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Msk */
<> 149:156823d33999 10658
<> 149:156823d33999 10659 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
<> 149:156823d33999 10660 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Msk */
<> 149:156823d33999 10661
<> 149:156823d33999 10662 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
<> 149:156823d33999 10663 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Msk */
<> 149:156823d33999 10664
<> 149:156823d33999 10665 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
<> 149:156823d33999 10666 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Msk */
<> 149:156823d33999 10667
<> 149:156823d33999 10668 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
<> 149:156823d33999 10669 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Msk */
<> 149:156823d33999 10670
<> 149:156823d33999 10671 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
<> 149:156823d33999 10672 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Msk */
<> 149:156823d33999 10673
<> 149:156823d33999 10674 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
<> 149:156823d33999 10675 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Msk */
<> 149:156823d33999 10676
<> 149:156823d33999 10677 #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
<> 149:156823d33999 10678 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) /*!< SC_T::UARTCTL: WLS Msk */
<> 149:156823d33999 10679
<> 149:156823d33999 10680 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
<> 149:156823d33999 10681 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Msk */
<> 149:156823d33999 10682
<> 149:156823d33999 10683 #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
<> 149:156823d33999 10684 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Msk */
<> 149:156823d33999 10685
<> 149:156823d33999 10686 #define SC_TMRDAT0_CNT0_Pos (0) /*!< SC_T::TMRDAT0: CNT0 Position */
<> 149:156823d33999 10687 #define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) /*!< SC_T::TMRDAT0: CNT0 Msk */
<> 149:156823d33999 10688
<> 149:156823d33999 10689 #define SC_TMRDAT1_2_CNT1_Pos (0) /*!< SC_T::TMRDAT1_2: CNT1 Position */
<> 149:156823d33999 10690 #define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) /*!< SC_T::TMRDAT1_2: CNT1 Msk */
<> 149:156823d33999 10691
<> 149:156823d33999 10692 #define SC_TMRDAT1_2_CNT2_Pos (8) /*!< SC_T::TMRDAT1_2: CNT2 Position */
<> 149:156823d33999 10693 #define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /*!< SC_T::TMRDAT1_2: CNT2 Msk */
<> 149:156823d33999 10694
<> 149:156823d33999 10695 /**@}*/ /* SC_CONST */
<> 149:156823d33999 10696 /**@}*/ /* end of SC register group */
<> 149:156823d33999 10697
<> 149:156823d33999 10698
<> 149:156823d33999 10699 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
<> 149:156823d33999 10700 /**
<> 149:156823d33999 10701 @addtogroup SPI Serial Peripheral Interface Controller(SPI)
<> 149:156823d33999 10702 Memory Mapped Structure for SPI Controller
<> 149:156823d33999 10703 @{ */
<> 149:156823d33999 10704
<> 149:156823d33999 10705
<> 149:156823d33999 10706 typedef struct
<> 149:156823d33999 10707 {
<> 149:156823d33999 10708
<> 149:156823d33999 10709
<> 149:156823d33999 10710 /**
<> 149:156823d33999 10711 * @var SPI_T::CTL
<> 149:156823d33999 10712 * Offset: 0x00 Control Register
<> 149:156823d33999 10713 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10714 * |Bits |Field |Descriptions
<> 149:156823d33999 10715 * | :----: | :----: | :---- |
<> 149:156823d33999 10716 * |[0] |SPIEN |SPI Transfer Control Enable Bit
<> 149:156823d33999 10717 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
<> 149:156823d33999 10718 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
<> 149:156823d33999 10719 * | | |0 = Transfer control Disabled.
<> 149:156823d33999 10720 * | | |1 = Transfer control Enabled.
<> 149:156823d33999 10721 * | | |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
<> 149:156823d33999 10722 * |[1] |RXNEG |Receive On Negative Edge
<> 149:156823d33999 10723 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
<> 149:156823d33999 10724 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
<> 149:156823d33999 10725 * |[2] |TXNEG |Transmit On Negative Edge
<> 149:156823d33999 10726 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
<> 149:156823d33999 10727 * | | |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
<> 149:156823d33999 10728 * |[3] |CLKPOL |Clock Polarity
<> 149:156823d33999 10729 * | | |0 = SPI bus clock is idle low.
<> 149:156823d33999 10730 * | | |1 = SPI bus clock is idle high.
<> 149:156823d33999 10731 * |[7:4] |SUSPITV |Suspend Interval (Master Only)
<> 149:156823d33999 10732 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
<> 149:156823d33999 10733 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
<> 149:156823d33999 10734 * | | |The default value is 0x3.
<> 149:156823d33999 10735 * | | |The period of the suspend interval is obtained according to the following equation.
<> 149:156823d33999 10736 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
<> 149:156823d33999 10737 * | | |Example:
<> 149:156823d33999 10738 * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
<> 149:156823d33999 10739 * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
<> 149:156823d33999 10740 * | | |...
<> 149:156823d33999 10741 * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
<> 149:156823d33999 10742 * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
<> 149:156823d33999 10743 * |[12:8] |DWIDTH |Data Width
<> 149:156823d33999 10744 * | | |This field specifies how many bits can be transmitted / received in one transaction.
<> 149:156823d33999 10745 * | | |The minimum bit length is 8 bits and can up to 32 bits.
<> 149:156823d33999 10746 * | | |DWIDTH = 0x08 ... 8 bits.
<> 149:156823d33999 10747 * | | |DWIDTH = 0x09 ... 9 bits.
<> 149:156823d33999 10748 * | | |...
<> 149:156823d33999 10749 * | | |DWIDTH = 0x1F ... 31 bits.
<> 149:156823d33999 10750 * | | |DWIDTH = 0x00 ... 32 bits.
<> 149:156823d33999 10751 * |[13] |LSB |Send LSB First
<> 149:156823d33999 10752 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
<> 149:156823d33999 10753 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
<> 149:156823d33999 10754 * |[16] |TWOBIT |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
<> 149:156823d33999 10755 * | | |0 = 2-Bit Transfer mode Disabled.
<> 149:156823d33999 10756 * | | |1 = 2-Bit Transfer mode Enabled.
<> 149:156823d33999 10757 * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
<> 149:156823d33999 10758 * | | |serial transmitted bit data is from the second FIFO buffer data.
<> 149:156823d33999 10759 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
<> 149:156823d33999 10760 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
<> 149:156823d33999 10761 * | | |0 = SPI unit transfer interrupt Disabled.
<> 149:156823d33999 10762 * | | |1 = SPI unit transfer interrupt Enabled.
<> 149:156823d33999 10763 * |[18] |SLAVE |Slave Mode Control
<> 149:156823d33999 10764 * | | |0 = Master mode.
<> 149:156823d33999 10765 * | | |1 = Slave mode.
<> 149:156823d33999 10766 * |[19] |REORDER |Byte Reorder Function Enable Bit
<> 149:156823d33999 10767 * | | |0 = Byte Reorder function Disabled.
<> 149:156823d33999 10768 * | | |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
<> 149:156823d33999 10769 * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
<> 149:156823d33999 10770 * | | |Note:
<> 149:156823d33999 10771 * | | |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
<> 149:156823d33999 10772 * | | |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
<> 149:156823d33999 10773 * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
<> 149:156823d33999 10774 * | | |0 = Quad or Dual Input mode.
<> 149:156823d33999 10775 * | | |1 = Quad or Dual Output mode.
<> 149:156823d33999 10776 * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
<> 149:156823d33999 10777 * | | |0 = Dual I/O mode Disabled.
<> 149:156823d33999 10778 * | | |1 = Dual I/O mode Enabled.
<> 149:156823d33999 10779 * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
<> 149:156823d33999 10780 * | | |0 = Quad I/O mode Disabled.
<> 149:156823d33999 10781 * | | |1 = Quad I/O mode Enabled.
<> 149:156823d33999 10782 * @var SPI_T::CLKDIV
<> 149:156823d33999 10783 * Offset: 0x04 Clock Divider Register
<> 149:156823d33999 10784 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10785 * |Bits |Field |Descriptions
<> 149:156823d33999 10786 * | :----: | :----: | :---- |
<> 149:156823d33999 10787 * |[7:0] |DIVIDER |Clock Divider
<> 149:156823d33999 10788 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
<> 149:156823d33999 10789 * | | |The frequency is obtained according to the following equation.
<> 149:156823d33999 10790 * | | | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
<> 149:156823d33999 10791 * | | |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
<> 149:156823d33999 10792 * @var SPI_T::SSCTL
<> 149:156823d33999 10793 * Offset: 0x08 Slave Select Control Register
<> 149:156823d33999 10794 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10795 * |Bits |Field |Descriptions
<> 149:156823d33999 10796 * | :----: | :----: | :---- |
<> 149:156823d33999 10797 * |[0] |SS |Slave Selection Control (Master Only)
<> 149:156823d33999 10798 * | | |If AUTOSS bit is cleared to 0,
<> 149:156823d33999 10799 * | | |0 = set the SPIn_SS line to inactive state.
<> 149:156823d33999 10800 * | | |1 = set the SPIn_SS line to active state
<> 149:156823d33999 10801 * | | |If the AUTOSS bit is set to 1,
<> 149:156823d33999 10802 * | | |0 = Keep the SPIn_SS line at inactive state.
<> 149:156823d33999 10803 * | | |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
<> 149:156823d33999 10804 * | | |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
<> 149:156823d33999 10805 * |[2] |SSACTPOL |Slave Selection Active Polarity
<> 149:156823d33999 10806 * | | |This bit defines the active polarity of slave selection signal (SPIn_SS).
<> 149:156823d33999 10807 * | | |0 = The slave selection signal SPIn_SS is active low.
<> 149:156823d33999 10808 * | | |1 = The slave selection signal SPIn_SS is active high.
<> 149:156823d33999 10809 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
<> 149:156823d33999 10810 * | | |0 = Automatic slave selection function Disabled.
<> 149:156823d33999 10811 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
<> 149:156823d33999 10812 * | | |1 = Automatic slave selection function Enabled.
<> 149:156823d33999 10813 * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Bit
<> 149:156823d33999 10814 * | | |Slave 3-wire mode is only available in SPI0.
<> 149:156823d33999 10815 * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
<> 149:156823d33999 10816 * | | |0 = 4-wire bi-direction interface.
<> 149:156823d33999 10817 * | | |1 = 3-wire bi-direction interface.
<> 149:156823d33999 10818 * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
<> 149:156823d33999 10819 * | | |0 = Slave mode time-out interrupt Disabled.
<> 149:156823d33999 10820 * | | |1 = Slave mode time-out interrupt Enabled.
<> 149:156823d33999 10821 * |[6] |SLVTORST |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
<> 149:156823d33999 10822 * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
<> 149:156823d33999 10823 * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
<> 149:156823d33999 10824 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
<> 149:156823d33999 10825 * | | |0 = Slave mode bit count error interrupt Disabled.
<> 149:156823d33999 10826 * | | |1 = Slave mode bit count error interrupt Enabled.
<> 149:156823d33999 10827 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
<> 149:156823d33999 10828 * | | |0 = Slave mode TX under run interrupt Disabled.
<> 149:156823d33999 10829 * | | |1 = Slave mode TX under run interrupt Enabled.
<> 149:156823d33999 10830 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
<> 149:156823d33999 10831 * | | |0 = Slave select active interrupt Disabled.
<> 149:156823d33999 10832 * | | |1 = Slave select active interrupt Enabled.
<> 149:156823d33999 10833 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
<> 149:156823d33999 10834 * | | |0 = Slave select inactive interrupt Disabled.
<> 149:156823d33999 10835 * | | |1 = Slave select inactive interrupt Enabled.
<> 149:156823d33999 10836 * |[31:16] |SLVTOCNT |Slave Mode Time-Out Period (Only Supported in SPI0)
<> 149:156823d33999 10837 * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
<> 149:156823d33999 10838 * | | |The clock source of the time-out counter is Slave peripheral clock.
<> 149:156823d33999 10839 * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
<> 149:156823d33999 10840 * @var SPI_T::PDMACTL
<> 149:156823d33999 10841 * Offset: 0x0C SPI PDMA Control Register
<> 149:156823d33999 10842 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10843 * |Bits |Field |Descriptions
<> 149:156823d33999 10844 * | :----: | :----: | :---- |
<> 149:156823d33999 10845 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
<> 149:156823d33999 10846 * | | |0 = Transmit PDMA function Disabled.
<> 149:156823d33999 10847 * | | |1 = Transmit PDMA function Enabled.
<> 149:156823d33999 10848 * | | |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
<> 149:156823d33999 10849 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
<> 149:156823d33999 10850 * |[1] |RXPDMAEN |Receive PDMA Enable Bit
<> 149:156823d33999 10851 * | | |0 = Receiver PDMA function Disabled.
<> 149:156823d33999 10852 * | | |1 = Receiver PDMA function Enabled.
<> 149:156823d33999 10853 * |[2] |PDMARST |PDMA Reset
<> 149:156823d33999 10854 * | | |0 = No effect.
<> 149:156823d33999 10855 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
<> 149:156823d33999 10856 * @var SPI_T::FIFOCTL
<> 149:156823d33999 10857 * Offset: 0x10 SPI FIFO Control Register
<> 149:156823d33999 10858 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10859 * |Bits |Field |Descriptions
<> 149:156823d33999 10860 * | :----: | :----: | :---- |
<> 149:156823d33999 10861 * |[0] |RXRST |Receive Reset
<> 149:156823d33999 10862 * | | |0 = No effect.
<> 149:156823d33999 10863 * | | |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
<> 149:156823d33999 10864 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
<> 149:156823d33999 10865 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
<> 149:156823d33999 10866 * | | |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
<> 149:156823d33999 10867 * |[1] |TXRST |Transmit Reset
<> 149:156823d33999 10868 * | | |0 = No effect.
<> 149:156823d33999 10869 * | | |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
<> 149:156823d33999 10870 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
<> 149:156823d33999 10871 * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
<> 149:156823d33999 10872 * | | |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
<> 149:156823d33999 10873 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
<> 149:156823d33999 10874 * | | |0 = RX FIFO threshold interrupt Disabled.
<> 149:156823d33999 10875 * | | |1 = RX FIFO threshold interrupt Enabled.
<> 149:156823d33999 10876 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
<> 149:156823d33999 10877 * | | |0 = TX FIFO threshold interrupt Disabled.
<> 149:156823d33999 10878 * | | |1 = TX FIFO threshold interrupt Enabled.
<> 149:156823d33999 10879 * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Bit
<> 149:156823d33999 10880 * | | |0 = Receive time-out interrupt Disabled.
<> 149:156823d33999 10881 * | | |1 = Receive time-out interrupt Enabled.
<> 149:156823d33999 10882 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
<> 149:156823d33999 10883 * | | |0 = Receive FIFO overrun interrupt Disabled.
<> 149:156823d33999 10884 * | | |1 = Receive FIFO overrun interrupt Enabled.
<> 149:156823d33999 10885 * |[6] |TXUFPOL |TX Underflow Data Polarity
<> 149:156823d33999 10886 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
<> 149:156823d33999 10887 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
<> 149:156823d33999 10888 * | | |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
<> 149:156823d33999 10889 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
<> 149:156823d33999 10890 * | | |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
<> 149:156823d33999 10891 * | | |0 = Slave TX underflow interrupt Disabled.
<> 149:156823d33999 10892 * | | |1 = Slave TX underflow interrupt Enabled.
<> 149:156823d33999 10893 * |[8] |RXFBCLR |Receive FIFO Buffer Clear
<> 149:156823d33999 10894 * | | |0 = No effect.
<> 149:156823d33999 10895 * | | |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
<> 149:156823d33999 10896 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
<> 149:156823d33999 10897 * | | |Note: The RX shift register will not be cleared.
<> 149:156823d33999 10898 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
<> 149:156823d33999 10899 * | | |0 = No effect.
<> 149:156823d33999 10900 * | | |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
<> 149:156823d33999 10901 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
<> 149:156823d33999 10902 * | | |Note: The TX shift register will not be cleared.
<> 149:156823d33999 10903 * |[26:24] |RXTH |Receive FIFO Threshold
<> 149:156823d33999 10904 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
<> 149:156823d33999 10905 * | | |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
<> 149:156823d33999 10906 * |[30:28] |TXTH |Transmit FIFO Threshold
<> 149:156823d33999 10907 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
<> 149:156823d33999 10908 * | | |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
<> 149:156823d33999 10909 * @var SPI_T::STATUS
<> 149:156823d33999 10910 * Offset: 0x14 SPI Status Register
<> 149:156823d33999 10911 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 10912 * |Bits |Field |Descriptions
<> 149:156823d33999 10913 * | :----: | :----: | :---- |
<> 149:156823d33999 10914 * |[0] |BUSY |Busy Status (Read Only)
<> 149:156823d33999 10915 * | | |0 = SPI controller is in idle state.
<> 149:156823d33999 10916 * | | |1 = SPI controller is in busy state.
<> 149:156823d33999 10917 * | | |The following listing are the bus busy conditions:
<> 149:156823d33999 10918 * | | |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
<> 149:156823d33999 10919 * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
<> 149:156823d33999 10920 * | | |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
<> 149:156823d33999 10921 * | | |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
<> 149:156823d33999 10922 * |[1] |UNITIF |Unit Transfer Interrupt Flag
<> 149:156823d33999 10923 * | | |0 = No transaction has been finished since this bit was cleared to 0.
<> 149:156823d33999 10924 * | | |1 = SPI controller has finished one unit transfer.
<> 149:156823d33999 10925 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10926 * |[2] |SSACTIF |Slave Select Active Interrupt Flag
<> 149:156823d33999 10927 * | | |0 = Slave select active interrupt was cleared or not occurred.
<> 149:156823d33999 10928 * | | |1 = Slave select active interrupt event occurred.
<> 149:156823d33999 10929 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10930 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
<> 149:156823d33999 10931 * | | |0 = Slave select inactive interrupt was cleared or not occurred.
<> 149:156823d33999 10932 * | | |1 = Slave select inactive interrupt event occurred.
<> 149:156823d33999 10933 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10934 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
<> 149:156823d33999 10935 * | | |0 = The slave select line status is 0.
<> 149:156823d33999 10936 * | | |1 = The slave select line status is 1.
<> 149:156823d33999 10937 * | | |Note: This bit is only available in Slave mode.
<> 149:156823d33999 10938 * | | |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
<> 149:156823d33999 10939 * |[5] |SLVTOIF |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
<> 149:156823d33999 10940 * | | |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
<> 149:156823d33999 10941 * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
<> 149:156823d33999 10942 * | | |0 = Slave time-out is not active.
<> 149:156823d33999 10943 * | | |1 = Slave time-out is active.
<> 149:156823d33999 10944 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10945 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
<> 149:156823d33999 10946 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
<> 149:156823d33999 10947 * | | |0 = No Slave mode bit count error event.
<> 149:156823d33999 10948 * | | |1 = Slave mode bit count error event occurs.
<> 149:156823d33999 10949 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
<> 149:156823d33999 10950 * | | |This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10951 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
<> 149:156823d33999 10952 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
<> 149:156823d33999 10953 * | | |0 = No Slave TX under run event.
<> 149:156823d33999 10954 * | | |1 = Slave TX under run occurs.
<> 149:156823d33999 10955 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10956 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
<> 149:156823d33999 10957 * | | |0 = Receive FIFO buffer is not empty.
<> 149:156823d33999 10958 * | | |1 = Receive FIFO buffer is empty.
<> 149:156823d33999 10959 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
<> 149:156823d33999 10960 * | | |0 = Receive FIFO buffer is not full.
<> 149:156823d33999 10961 * | | |1 = Receive FIFO buffer is full.
<> 149:156823d33999 10962 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
<> 149:156823d33999 10963 * | | |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
<> 149:156823d33999 10964 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
<> 149:156823d33999 10965 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
<> 149:156823d33999 10966 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
<> 149:156823d33999 10967 * | | |0 = No FIFO is over run.
<> 149:156823d33999 10968 * | | |1 = Receive FIFO over run.
<> 149:156823d33999 10969 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10970 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
<> 149:156823d33999 10971 * | | |0 = No receive FIFO time-out event.
<> 149:156823d33999 10972 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
<> 149:156823d33999 10973 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
<> 149:156823d33999 10974 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10975 * |[15] |SPIENSTS |SPI Enable Status (Read Only)
<> 149:156823d33999 10976 * | | |0 = The SPI controller is disabled.
<> 149:156823d33999 10977 * | | |1 = The SPI controller is enabled.
<> 149:156823d33999 10978 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
<> 149:156823d33999 10979 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
<> 149:156823d33999 10980 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
<> 149:156823d33999 10981 * | | |0 = Transmit FIFO buffer is not empty.
<> 149:156823d33999 10982 * | | |1 = Transmit FIFO buffer is empty.
<> 149:156823d33999 10983 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
<> 149:156823d33999 10984 * | | |0 = Transmit FIFO buffer is not full.
<> 149:156823d33999 10985 * | | |1 = Transmit FIFO buffer is full.
<> 149:156823d33999 10986 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
<> 149:156823d33999 10987 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
<> 149:156823d33999 10988 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
<> 149:156823d33999 10989 * |[19] |TXUFIF |TX Underflow Interrupt Flag
<> 149:156823d33999 10990 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
<> 149:156823d33999 10991 * | | |0 = No effect.
<> 149:156823d33999 10992 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
<> 149:156823d33999 10993 * | | |Note 1: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 10994 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
<> 149:156823d33999 10995 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
<> 149:156823d33999 10996 * | | |0 = The reset function of TXRST or RXRST is done.
<> 149:156823d33999 10997 * | | |1 = Doing the reset function of TXRST or RXRST.
<> 149:156823d33999 10998 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
<> 149:156823d33999 10999 * | | |User can check the status of this bit to monitor the reset function is doing or done.
<> 149:156823d33999 11000 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
<> 149:156823d33999 11001 * | | |This bit field indicates the valid data count of receive FIFO buffer.
<> 149:156823d33999 11002 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
<> 149:156823d33999 11003 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
<> 149:156823d33999 11004 * @var SPI_T::TX
<> 149:156823d33999 11005 * Offset: 0x20 Data Transmit Register
<> 149:156823d33999 11006 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11007 * |Bits |Field |Descriptions
<> 149:156823d33999 11008 * | :----: | :----: | :---- |
<> 149:156823d33999 11009 * |[31:0] |TX |Data Transmit Register
<> 149:156823d33999 11010 * | | |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
<> 149:156823d33999 11011 * | | |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
<> 149:156823d33999 11012 * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
<> 149:156823d33999 11013 * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
<> 149:156823d33999 11014 * | | |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
<> 149:156823d33999 11015 * @var SPI_T::RX
<> 149:156823d33999 11016 * Offset: 0x30 Data Receive Register
<> 149:156823d33999 11017 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11018 * |Bits |Field |Descriptions
<> 149:156823d33999 11019 * | :----: | :----: | :---- |
<> 149:156823d33999 11020 * |[31:0] |RX |Data Receive Register
<> 149:156823d33999 11021 * | | |There are 8-/4-level FIFO buffers in this controller.
<> 149:156823d33999 11022 * | | |The data receive register holds the data received from SPI data input pin.
<> 149:156823d33999 11023 * | | |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
<> 149:156823d33999 11024 * | | |This is a read only register.
<> 149:156823d33999 11025 * @var SPI_T::I2SCTL
<> 149:156823d33999 11026 * Offset: 0x60 I2S Control Register
<> 149:156823d33999 11027 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11028 * |Bits |Field |Descriptions
<> 149:156823d33999 11029 * | :----: | :----: | :---- |
<> 149:156823d33999 11030 * |[0] |I2SEN |I2S Controller Enable Bit
<> 149:156823d33999 11031 * | | |0 = Disabled.
<> 149:156823d33999 11032 * | | |1 = Enabled.
<> 149:156823d33999 11033 * | | |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
<> 149:156823d33999 11034 * |[1] |TXEN |Transmit Enable Bit
<> 149:156823d33999 11035 * | | |0 = Data transmit Disabled.
<> 149:156823d33999 11036 * | | |1 = Data transmit Enabled.
<> 149:156823d33999 11037 * |[2] |RXEN |Receive Enable Bit
<> 149:156823d33999 11038 * | | |0 = Data receiving Disabled.
<> 149:156823d33999 11039 * | | |1 = Data receiving Enabled.
<> 149:156823d33999 11040 * |[3] |MUTE |Transmit Mute Enable Bit
<> 149:156823d33999 11041 * | | |0 = Transmit data is shifted from buffer.
<> 149:156823d33999 11042 * | | |1= Transmit channel zero.
<> 149:156823d33999 11043 * |[5:4] |WDWIDTH |Word Width
<> 149:156823d33999 11044 * | | |00 = data is 8-bit.
<> 149:156823d33999 11045 * | | |01 = data is 16-bit.
<> 149:156823d33999 11046 * | | |10 = data is 24-bit.
<> 149:156823d33999 11047 * | | |11 = data is 32-bit.
<> 149:156823d33999 11048 * |[6] |MONO |Monaural Data
<> 149:156823d33999 11049 * | | |0 = Data is stereo format.
<> 149:156823d33999 11050 * | | |1 = Data is monaural format.
<> 149:156823d33999 11051 * |[7] |ORDER |Stereo Data Order In FIFO
<> 149:156823d33999 11052 * | | |0 = Left channel data at high byte.
<> 149:156823d33999 11053 * | | |1 = Left channel data at low byte.
<> 149:156823d33999 11054 * |[8] |SLAVE |Slave Mode
<> 149:156823d33999 11055 * | | |I2S can operate as master or slave.
<> 149:156823d33999 11056 * | | |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
<> 149:156823d33999 11057 * | | |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
<> 149:156823d33999 11058 * | | |0 = Master mode.
<> 149:156823d33999 11059 * | | |1 = Slave mode.
<> 149:156823d33999 11060 * |[15] |MCLKEN |Master Clock Enable Bit
<> 149:156823d33999 11061 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
<> 149:156823d33999 11062 * | | |0 = Master clock Disabled.
<> 149:156823d33999 11063 * | | |1 = Master clock Enabled.
<> 149:156823d33999 11064 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
<> 149:156823d33999 11065 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
<> 149:156823d33999 11066 * | | |This function is only available in transmit operation.
<> 149:156823d33999 11067 * | | |0 = Right channel zero cross detection Disabled.
<> 149:156823d33999 11068 * | | |1 = Right channel zero cross detection Enabled.
<> 149:156823d33999 11069 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
<> 149:156823d33999 11070 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
<> 149:156823d33999 11071 * | | |This function is only available in transmit operation.
<> 149:156823d33999 11072 * | | |0 = Left channel zero cross detection Disabled.
<> 149:156823d33999 11073 * | | |1 = Left channel zero cross detection Enabled.
<> 149:156823d33999 11074 * |[23] |RXLCH |Receive Left Channel Enable Bit
<> 149:156823d33999 11075 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
<> 149:156823d33999 11076 * | | |0 = Receive right channel data in Mono mode.
<> 149:156823d33999 11077 * | | |1 = Receive left channel data in Mono mode.
<> 149:156823d33999 11078 * |[24] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Bit
<> 149:156823d33999 11079 * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
<> 149:156823d33999 11080 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 11081 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 11082 * |[25] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Bit
<> 149:156823d33999 11083 * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
<> 149:156823d33999 11084 * | | |0 = Interrupt Disabled.
<> 149:156823d33999 11085 * | | |1 = Interrupt Enabled.
<> 149:156823d33999 11086 * |[29:28] |FORMAT |Data Format Selection
<> 149:156823d33999 11087 * | | |00 = I2S data format.
<> 149:156823d33999 11088 * | | |01 = MSB justified data format.
<> 149:156823d33999 11089 * | | |10 = PCM mode A.
<> 149:156823d33999 11090 * | | |11 = PCM mode B.
<> 149:156823d33999 11091 * @var SPI_T::I2SCLK
<> 149:156823d33999 11092 * Offset: 0x64 I2S Clock Divider Control Register
<> 149:156823d33999 11093 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11094 * |Bits |Field |Descriptions
<> 149:156823d33999 11095 * | :----: | :----: | :---- |
<> 149:156823d33999 11096 * |[5:0] |MCLKDIV |Master Clock Divider
<> 149:156823d33999 11097 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
<> 149:156823d33999 11098 * | | |The master clock rate, F_MCLK, is determined by the following expressions.
<> 149:156823d33999 11099 * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
<> 149:156823d33999 11100 * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
<> 149:156823d33999 11101 * | | |F_I2SCLK is the frequency of I2S peripheral clock.
<> 149:156823d33999 11102 * | | |In general, the master clock rate is 256 times sampling clock rate.
<> 149:156823d33999 11103 * |[16:8] |BCLKDIV |Bit Clock Divider
<> 149:156823d33999 11104 * | | |The I2S controller will generate bit clock in Master mode.
<> 149:156823d33999 11105 * | | |The bit clock rate, F_BCLK, is determined by the following expression.
<> 149:156823d33999 11106 * | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
<> 149:156823d33999 11107 * @var SPI_T::I2SSTS
<> 149:156823d33999 11108 * Offset: 0x68 I2S Status Register
<> 149:156823d33999 11109 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11110 * |Bits |Field |Descriptions
<> 149:156823d33999 11111 * | :----: | :----: | :---- |
<> 149:156823d33999 11112 * |[4] |RIGHT |Right Channel (Read Only)
<> 149:156823d33999 11113 * | | |This bit indicates the current transmit data is belong to which channel.
<> 149:156823d33999 11114 * | | |0 = Left channel.
<> 149:156823d33999 11115 * | | |1 = Right channel.
<> 149:156823d33999 11116 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
<> 149:156823d33999 11117 * | | |0 = Receive FIFO buffer is not empty.
<> 149:156823d33999 11118 * | | |1 = Receive FIFO buffer is empty.
<> 149:156823d33999 11119 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
<> 149:156823d33999 11120 * | | |0 = Receive FIFO buffer is not full.
<> 149:156823d33999 11121 * | | |1 = Receive FIFO buffer is full.
<> 149:156823d33999 11122 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
<> 149:156823d33999 11123 * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
<> 149:156823d33999 11124 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
<> 149:156823d33999 11125 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
<> 149:156823d33999 11126 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
<> 149:156823d33999 11127 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
<> 149:156823d33999 11128 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 11129 * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
<> 149:156823d33999 11130 * | | |0 = No receive FIFO time-out event.
<> 149:156823d33999 11131 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
<> 149:156823d33999 11132 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
<> 149:156823d33999 11133 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 11134 * |[15] |I2SENSTS |I2S Enable Status (Read Only)
<> 149:156823d33999 11135 * | | |0 = The SPI/I2S control logic is disabled.
<> 149:156823d33999 11136 * | | |1 = The SPI/I2S control logic is enabled.
<> 149:156823d33999 11137 * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
<> 149:156823d33999 11138 * | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
<> 149:156823d33999 11139 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
<> 149:156823d33999 11140 * | | |0 = Transmit FIFO buffer is not empty.
<> 149:156823d33999 11141 * | | |1 = Transmit FIFO buffer is empty.
<> 149:156823d33999 11142 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
<> 149:156823d33999 11143 * | | |0 = Transmit FIFO buffer is not full.
<> 149:156823d33999 11144 * | | |1 = Transmit FIFO buffer is full.
<> 149:156823d33999 11145 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
<> 149:156823d33999 11146 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
<> 149:156823d33999 11147 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
<> 149:156823d33999 11148 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
<> 149:156823d33999 11149 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
<> 149:156823d33999 11150 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
<> 149:156823d33999 11151 * | | | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
<> 149:156823d33999 11152 * | | |Note: This bit will be cleared by writing 1 to it.
<> 149:156823d33999 11153 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
<> 149:156823d33999 11154 * | | |0 = No zero cross event occurred on right channel.
<> 149:156823d33999 11155 * | | |1 = Zero cross event occurred on right channel.
<> 149:156823d33999 11156 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
<> 149:156823d33999 11157 * | | |0 = No zero cross event occurred on left channel.
<> 149:156823d33999 11158 * | | |1 = Zero cross event occurred on left channel.
<> 149:156823d33999 11159 * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
<> 149:156823d33999 11160 * | | |0 = The reset function of TXRST or RXRST is done.
<> 149:156823d33999 11161 * | | |1 = Doing the reset function of TXRST or RXRST.
<> 149:156823d33999 11162 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
<> 149:156823d33999 11163 * | | |User can check the status of this bit to monitor the reset function is doing or done.
<> 149:156823d33999 11164 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
<> 149:156823d33999 11165 * | | |This bit field indicates the valid data count of receive FIFO buffer.
<> 149:156823d33999 11166 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
<> 149:156823d33999 11167 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
<> 149:156823d33999 11168 */
<> 149:156823d33999 11169
<> 149:156823d33999 11170 __IO uint32_t CTL; /* Offset: 0x00 Control Register */
<> 149:156823d33999 11171 __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
<> 149:156823d33999 11172 __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
<> 149:156823d33999 11173 __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
<> 149:156823d33999 11174 __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
<> 149:156823d33999 11175 __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
<> 149:156823d33999 11176 __I uint32_t RESERVE0[2];
<> 149:156823d33999 11177 __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
<> 149:156823d33999 11178 __I uint32_t RESERVE1[3];
<> 149:156823d33999 11179 __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
<> 149:156823d33999 11180 __I uint32_t RESERVE2[11];
<> 149:156823d33999 11181 __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
<> 149:156823d33999 11182 __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
<> 149:156823d33999 11183 __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
<> 149:156823d33999 11184
<> 149:156823d33999 11185 } SPI_T;
<> 149:156823d33999 11186
<> 149:156823d33999 11187
<> 149:156823d33999 11188
<> 149:156823d33999 11189 /**
<> 149:156823d33999 11190 @addtogroup SPI_CONST SPI Bit Field Definition
<> 149:156823d33999 11191 Constant Definitions for SPI Controller
<> 149:156823d33999 11192 @{ */
<> 149:156823d33999 11193
<> 149:156823d33999 11194 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
<> 149:156823d33999 11195 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
<> 149:156823d33999 11196
<> 149:156823d33999 11197 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
<> 149:156823d33999 11198 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
<> 149:156823d33999 11199
<> 149:156823d33999 11200 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
<> 149:156823d33999 11201 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
<> 149:156823d33999 11202
<> 149:156823d33999 11203 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
<> 149:156823d33999 11204 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
<> 149:156823d33999 11205
<> 149:156823d33999 11206 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
<> 149:156823d33999 11207 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
<> 149:156823d33999 11208
<> 149:156823d33999 11209 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
<> 149:156823d33999 11210 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
<> 149:156823d33999 11211
<> 149:156823d33999 11212 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
<> 149:156823d33999 11213 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
<> 149:156823d33999 11214
<> 149:156823d33999 11215 #define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
<> 149:156823d33999 11216 #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
<> 149:156823d33999 11217
<> 149:156823d33999 11218 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
<> 149:156823d33999 11219 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
<> 149:156823d33999 11220
<> 149:156823d33999 11221 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
<> 149:156823d33999 11222 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
<> 149:156823d33999 11223
<> 149:156823d33999 11224 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
<> 149:156823d33999 11225 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
<> 149:156823d33999 11226
<> 149:156823d33999 11227 #define SPI_CTL_QDIODIR_Pos (20) /*!< SPI_T::CTL: QDIODIR Position */
<> 149:156823d33999 11228 #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI_T::CTL: QDIODIR Mask */
<> 149:156823d33999 11229
<> 149:156823d33999 11230 #define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
<> 149:156823d33999 11231 #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
<> 149:156823d33999 11232
<> 149:156823d33999 11233 #define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
<> 149:156823d33999 11234 #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
<> 149:156823d33999 11235
<> 149:156823d33999 11236 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
<> 149:156823d33999 11237 #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
<> 149:156823d33999 11238
<> 149:156823d33999 11239 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
<> 149:156823d33999 11240 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
<> 149:156823d33999 11241
<> 149:156823d33999 11242 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
<> 149:156823d33999 11243 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
<> 149:156823d33999 11244
<> 149:156823d33999 11245 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
<> 149:156823d33999 11246 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
<> 149:156823d33999 11247
<> 149:156823d33999 11248 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
<> 149:156823d33999 11249 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
<> 149:156823d33999 11250
<> 149:156823d33999 11251 #define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
<> 149:156823d33999 11252 #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
<> 149:156823d33999 11253
<> 149:156823d33999 11254 #define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
<> 149:156823d33999 11255 #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
<> 149:156823d33999 11256
<> 149:156823d33999 11257 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
<> 149:156823d33999 11258 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
<> 149:156823d33999 11259
<> 149:156823d33999 11260 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
<> 149:156823d33999 11261 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
<> 149:156823d33999 11262
<> 149:156823d33999 11263 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
<> 149:156823d33999 11264 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
<> 149:156823d33999 11265
<> 149:156823d33999 11266 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
<> 149:156823d33999 11267 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
<> 149:156823d33999 11268
<> 149:156823d33999 11269 #define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
<> 149:156823d33999 11270 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
<> 149:156823d33999 11271
<> 149:156823d33999 11272 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
<> 149:156823d33999 11273 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
<> 149:156823d33999 11274
<> 149:156823d33999 11275 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
<> 149:156823d33999 11276 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
<> 149:156823d33999 11277
<> 149:156823d33999 11278 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
<> 149:156823d33999 11279 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
<> 149:156823d33999 11280
<> 149:156823d33999 11281 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
<> 149:156823d33999 11282 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
<> 149:156823d33999 11283
<> 149:156823d33999 11284 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
<> 149:156823d33999 11285 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
<> 149:156823d33999 11286
<> 149:156823d33999 11287 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
<> 149:156823d33999 11288 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
<> 149:156823d33999 11289
<> 149:156823d33999 11290 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
<> 149:156823d33999 11291 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
<> 149:156823d33999 11292
<> 149:156823d33999 11293 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
<> 149:156823d33999 11294 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
<> 149:156823d33999 11295
<> 149:156823d33999 11296 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
<> 149:156823d33999 11297 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
<> 149:156823d33999 11298
<> 149:156823d33999 11299 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
<> 149:156823d33999 11300 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
<> 149:156823d33999 11301
<> 149:156823d33999 11302 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
<> 149:156823d33999 11303 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
<> 149:156823d33999 11304
<> 149:156823d33999 11305 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
<> 149:156823d33999 11306 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
<> 149:156823d33999 11307
<> 149:156823d33999 11308 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
<> 149:156823d33999 11309 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
<> 149:156823d33999 11310
<> 149:156823d33999 11311 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
<> 149:156823d33999 11312 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
<> 149:156823d33999 11313
<> 149:156823d33999 11314 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
<> 149:156823d33999 11315 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
<> 149:156823d33999 11316
<> 149:156823d33999 11317 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
<> 149:156823d33999 11318 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
<> 149:156823d33999 11319
<> 149:156823d33999 11320 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
<> 149:156823d33999 11321 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
<> 149:156823d33999 11322
<> 149:156823d33999 11323 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
<> 149:156823d33999 11324 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
<> 149:156823d33999 11325
<> 149:156823d33999 11326 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
<> 149:156823d33999 11327 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
<> 149:156823d33999 11328
<> 149:156823d33999 11329 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
<> 149:156823d33999 11330 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
<> 149:156823d33999 11331
<> 149:156823d33999 11332 #define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
<> 149:156823d33999 11333 #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
<> 149:156823d33999 11334
<> 149:156823d33999 11335 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
<> 149:156823d33999 11336 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
<> 149:156823d33999 11337
<> 149:156823d33999 11338 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
<> 149:156823d33999 11339 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
<> 149:156823d33999 11340
<> 149:156823d33999 11341 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
<> 149:156823d33999 11342 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
<> 149:156823d33999 11343
<> 149:156823d33999 11344 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
<> 149:156823d33999 11345 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
<> 149:156823d33999 11346
<> 149:156823d33999 11347 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
<> 149:156823d33999 11348 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
<> 149:156823d33999 11349
<> 149:156823d33999 11350 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
<> 149:156823d33999 11351 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
<> 149:156823d33999 11352
<> 149:156823d33999 11353 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
<> 149:156823d33999 11354 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
<> 149:156823d33999 11355
<> 149:156823d33999 11356 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
<> 149:156823d33999 11357 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
<> 149:156823d33999 11358
<> 149:156823d33999 11359 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
<> 149:156823d33999 11360 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
<> 149:156823d33999 11361
<> 149:156823d33999 11362 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
<> 149:156823d33999 11363 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
<> 149:156823d33999 11364
<> 149:156823d33999 11365 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
<> 149:156823d33999 11366 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
<> 149:156823d33999 11367
<> 149:156823d33999 11368 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
<> 149:156823d33999 11369 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
<> 149:156823d33999 11370
<> 149:156823d33999 11371 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
<> 149:156823d33999 11372 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
<> 149:156823d33999 11373
<> 149:156823d33999 11374 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
<> 149:156823d33999 11375 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
<> 149:156823d33999 11376
<> 149:156823d33999 11377 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
<> 149:156823d33999 11378 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
<> 149:156823d33999 11379
<> 149:156823d33999 11380 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
<> 149:156823d33999 11381 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
<> 149:156823d33999 11382
<> 149:156823d33999 11383 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
<> 149:156823d33999 11384 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
<> 149:156823d33999 11385
<> 149:156823d33999 11386 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
<> 149:156823d33999 11387 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
<> 149:156823d33999 11388
<> 149:156823d33999 11389 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
<> 149:156823d33999 11390 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
<> 149:156823d33999 11391
<> 149:156823d33999 11392 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
<> 149:156823d33999 11393 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
<> 149:156823d33999 11394
<> 149:156823d33999 11395 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
<> 149:156823d33999 11396 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
<> 149:156823d33999 11397
<> 149:156823d33999 11398 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
<> 149:156823d33999 11399 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
<> 149:156823d33999 11400
<> 149:156823d33999 11401 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
<> 149:156823d33999 11402 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
<> 149:156823d33999 11403
<> 149:156823d33999 11404 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
<> 149:156823d33999 11405 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
<> 149:156823d33999 11406
<> 149:156823d33999 11407 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
<> 149:156823d33999 11408 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
<> 149:156823d33999 11409
<> 149:156823d33999 11410 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
<> 149:156823d33999 11411 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
<> 149:156823d33999 11412
<> 149:156823d33999 11413 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
<> 149:156823d33999 11414 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
<> 149:156823d33999 11415
<> 149:156823d33999 11416 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
<> 149:156823d33999 11417 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
<> 149:156823d33999 11418
<> 149:156823d33999 11419 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
<> 149:156823d33999 11420 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
<> 149:156823d33999 11421
<> 149:156823d33999 11422 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
<> 149:156823d33999 11423 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
<> 149:156823d33999 11424
<> 149:156823d33999 11425 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
<> 149:156823d33999 11426 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
<> 149:156823d33999 11427
<> 149:156823d33999 11428 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
<> 149:156823d33999 11429 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
<> 149:156823d33999 11430
<> 149:156823d33999 11431 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
<> 149:156823d33999 11432 #define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
<> 149:156823d33999 11433
<> 149:156823d33999 11434 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
<> 149:156823d33999 11435 #define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
<> 149:156823d33999 11436
<> 149:156823d33999 11437 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
<> 149:156823d33999 11438 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
<> 149:156823d33999 11439
<> 149:156823d33999 11440 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
<> 149:156823d33999 11441 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
<> 149:156823d33999 11442
<> 149:156823d33999 11443 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
<> 149:156823d33999 11444 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
<> 149:156823d33999 11445
<> 149:156823d33999 11446 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
<> 149:156823d33999 11447 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
<> 149:156823d33999 11448
<> 149:156823d33999 11449 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
<> 149:156823d33999 11450 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
<> 149:156823d33999 11451
<> 149:156823d33999 11452 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
<> 149:156823d33999 11453 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
<> 149:156823d33999 11454
<> 149:156823d33999 11455 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
<> 149:156823d33999 11456 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
<> 149:156823d33999 11457
<> 149:156823d33999 11458 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
<> 149:156823d33999 11459 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
<> 149:156823d33999 11460
<> 149:156823d33999 11461 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
<> 149:156823d33999 11462 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
<> 149:156823d33999 11463
<> 149:156823d33999 11464 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
<> 149:156823d33999 11465 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
<> 149:156823d33999 11466
<> 149:156823d33999 11467 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
<> 149:156823d33999 11468 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
<> 149:156823d33999 11469
<> 149:156823d33999 11470 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
<> 149:156823d33999 11471 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
<> 149:156823d33999 11472
<> 149:156823d33999 11473 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
<> 149:156823d33999 11474 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
<> 149:156823d33999 11475
<> 149:156823d33999 11476 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
<> 149:156823d33999 11477 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
<> 149:156823d33999 11478
<> 149:156823d33999 11479 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
<> 149:156823d33999 11480 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
<> 149:156823d33999 11481
<> 149:156823d33999 11482 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
<> 149:156823d33999 11483 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
<> 149:156823d33999 11484
<> 149:156823d33999 11485 /**@}*/ /* SPI_CONST */
<> 149:156823d33999 11486 /**@}*/ /* end of SPI register group */
<> 149:156823d33999 11487
<> 149:156823d33999 11488
<> 149:156823d33999 11489 /*---------------------- System Manger Controller -------------------------*/
<> 149:156823d33999 11490 /**
<> 149:156823d33999 11491 @addtogroup SYS System Manger Controller(SYS)
<> 149:156823d33999 11492 Memory Mapped Structure for SYS Controller
<> 149:156823d33999 11493 @{ */
<> 149:156823d33999 11494
<> 149:156823d33999 11495
<> 149:156823d33999 11496 typedef struct
<> 149:156823d33999 11497 {
<> 149:156823d33999 11498
<> 149:156823d33999 11499 /**
<> 149:156823d33999 11500 * @var SYS_T::PDID
<> 149:156823d33999 11501 * Offset: 0x00 Part Device Identification Number Register
<> 149:156823d33999 11502 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11503 * |Bits |Field |Descriptions
<> 149:156823d33999 11504 * | :----: | :----: | :---- |
<> 149:156823d33999 11505 * |[31:0] |PDID |Part Device Identification Number (Read Only)
<> 149:156823d33999 11506 * | | |This register reflects device part number code.
<> 149:156823d33999 11507 * | | |Software can read this register to identify which device is used.
<> 149:156823d33999 11508 * @var SYS_T::RSTSTS
<> 149:156823d33999 11509 * Offset: 0x04 System Reset Status Register
<> 149:156823d33999 11510 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11511 * |Bits |Field |Descriptions
<> 149:156823d33999 11512 * | :----: | :----: | :---- |
<> 149:156823d33999 11513 * |[0] |PORF |POR Reset Flag
<> 149:156823d33999 11514 * | | |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
<> 149:156823d33999 11515 * | | |0 = No reset from POR or CHIPRST.
<> 149:156823d33999 11516 * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
<> 149:156823d33999 11517 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11518 * |[1] |PINRF |nRESET Pin Reset Flag
<> 149:156823d33999 11519 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
<> 149:156823d33999 11520 * | | |0 = No reset from nRESET pin.
<> 149:156823d33999 11521 * | | |1 = Pin nRESET had issued the reset signal to reset the system.
<> 149:156823d33999 11522 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11523 * |[2] |WDTRF |WDT Reset Flag
<> 149:156823d33999 11524 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
<> 149:156823d33999 11525 * | | |0 = No reset from watchdog timer or window watchdog timer.
<> 149:156823d33999 11526 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
<> 149:156823d33999 11527 * | | |Note1:
<> 149:156823d33999 11528 * | | |Write 1 to clear this bit to 0.
<> 149:156823d33999 11529 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
<> 149:156823d33999 11530 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
<> 149:156823d33999 11531 * |[3] |LVRF |LVR Reset Flag
<> 149:156823d33999 11532 * | | |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
<> 149:156823d33999 11533 * | | |0 = No reset from LVR.
<> 149:156823d33999 11534 * | | |1 = LVR controller had issued the reset signal to reset the system.
<> 149:156823d33999 11535 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11536 * |[4] |BODRF |BOD Reset Flag
<> 149:156823d33999 11537 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
<> 149:156823d33999 11538 * | | |0 = No reset from BOD.
<> 149:156823d33999 11539 * | | |1 = The BOD had issued the reset signal to reset the system.
<> 149:156823d33999 11540 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11541 * |[5] |SYSRF |System Reset Flag
<> 149:156823d33999 11542 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
<> 149:156823d33999 11543 * | | |0 = No reset from Cortex-M4.
<> 149:156823d33999 11544 * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
<> 149:156823d33999 11545 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11546 * |[7] |CPURF |CPU Reset Flag
<> 149:156823d33999 11547 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
<> 149:156823d33999 11548 * | | |0 = No reset from CPU.
<> 149:156823d33999 11549 * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
<> 149:156823d33999 11550 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11551 * |[8] |CPULKRF |CPU Lockup Reset Flag
<> 149:156823d33999 11552 * | | |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
<> 149:156823d33999 11553 * | | |0 = No reset from CPU lockup happened.
<> 149:156823d33999 11554 * | | |1 = The Cortex-M4 lockup happened and chip is reset.
<> 149:156823d33999 11555 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11556 * @var SYS_T::IPRST0
<> 149:156823d33999 11557 * Offset: 0x08 Peripheral Reset Control Register 0
<> 149:156823d33999 11558 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11559 * |Bits |Field |Descriptions
<> 149:156823d33999 11560 * | :----: | :----: | :---- |
<> 149:156823d33999 11561 * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
<> 149:156823d33999 11562 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
<> 149:156823d33999 11563 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
<> 149:156823d33999 11564 * | | |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
<> 149:156823d33999 11565 * | | |0 = Chip normal operation.
<> 149:156823d33999 11566 * | | |1 = Chip one shot reset.
<> 149:156823d33999 11567 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11568 * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
<> 149:156823d33999 11569 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
<> 149:156823d33999 11570 * | | |0 = Processor core normal operation.
<> 149:156823d33999 11571 * | | |1 = Processor core one-shot reset.
<> 149:156823d33999 11572 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11573 * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
<> 149:156823d33999 11574 * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
<> 149:156823d33999 11575 * | | |User needs to set this bit to 0 to release from reset state.
<> 149:156823d33999 11576 * | | |0 = PDMA controller normal operation.
<> 149:156823d33999 11577 * | | |1 = PDMA controller reset.
<> 149:156823d33999 11578 * |[3] |EBIRST |EBI Controller Reset (Write Protect)
<> 149:156823d33999 11579 * | | |Set this bit to 1 will generate a reset signal to the EBI.
<> 149:156823d33999 11580 * | | |User needs to set this bit to 0 to release from the reset state.
<> 149:156823d33999 11581 * | | |0 = EBI controller normal operation.
<> 149:156823d33999 11582 * | | |1 = EBI controller reset.
<> 149:156823d33999 11583 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11584 * |[4] |USBHRST |USBH Controller Reset (Write Protect)
<> 149:156823d33999 11585 * | | |Set this bit to 1 will generate a reset signal to the USB host controller.
<> 149:156823d33999 11586 * | | |User needs to set this bit to 0 to release from the reset state.
<> 149:156823d33999 11587 * | | |0 = USBH controller normal operation.
<> 149:156823d33999 11588 * | | |1 = USBH controller reset.
<> 149:156823d33999 11589 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11590 * |[7] |CRCRST |CRC Calculation Unit Reset (Write Protect)
<> 149:156823d33999 11591 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation module.
<> 149:156823d33999 11592 * | | |User needs to set this bit to 0 to release from the reset state.
<> 149:156823d33999 11593 * | | |0 = CRC Calculation unit normal operation.
<> 149:156823d33999 11594 * | | |1 = CRC Calculation unit reset.
<> 149:156823d33999 11595 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11596 * @var SYS_T::IPRST1
<> 149:156823d33999 11597 * Offset: 0x0C Peripheral Reset Control Register 1
<> 149:156823d33999 11598 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11599 * |Bits |Field |Descriptions
<> 149:156823d33999 11600 * | :----: | :----: | :---- |
<> 149:156823d33999 11601 * |[1] |GPIORST |GPIO Controller Reset
<> 149:156823d33999 11602 * | | |0 = GPIO controller normal operation.
<> 149:156823d33999 11603 * | | |1 = GPIO controller reset.
<> 149:156823d33999 11604 * |[2] |TMR0RST |Timer0 Controller Reset
<> 149:156823d33999 11605 * | | |0 = Timer0 controller normal operation.
<> 149:156823d33999 11606 * | | |1 = Timer0 controller reset.
<> 149:156823d33999 11607 * |[3] |TMR1RST |Timer1 Controller Reset
<> 149:156823d33999 11608 * | | |0 = Timer1 controller normal operation.
<> 149:156823d33999 11609 * | | |1 = Timer1 controller reset.
<> 149:156823d33999 11610 * |[4] |TMR2RST |Timer2 Controller Reset
<> 149:156823d33999 11611 * | | |0 = Timer2 controller normal operation.
<> 149:156823d33999 11612 * | | |1 = Timer2 controller reset.
<> 149:156823d33999 11613 * |[5] |TMR3RST |Timer3 Controller Reset
<> 149:156823d33999 11614 * | | |0 = Timer3 controller normal operation.
<> 149:156823d33999 11615 * | | |1 = Timer3 controller reset.
<> 149:156823d33999 11616 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
<> 149:156823d33999 11617 * | | |0 = Analog Comparator 0/1 controller normal operation.
<> 149:156823d33999 11618 * | | |1 = Analog Comparator 0/1 controller reset.
<> 149:156823d33999 11619 * |[8] |I2C0RST |I2C0 Controller Reset
<> 149:156823d33999 11620 * | | |0 = I2C0 controller normal operation.
<> 149:156823d33999 11621 * | | |1 = I2C0 controller reset.
<> 149:156823d33999 11622 * |[9] |I2C1RST |I2C1 Controller Reset
<> 149:156823d33999 11623 * | | |0 = I2C1 controller normal operation.
<> 149:156823d33999 11624 * | | |1 = I2C1 controller reset.
<> 149:156823d33999 11625 * |[12] |SPI0RST |SPI0 Controller Reset
<> 149:156823d33999 11626 * | | |0 = SPI0 controller normal operation.
<> 149:156823d33999 11627 * | | |1 = SPI0 controller reset.
<> 149:156823d33999 11628 * |[13] |SPI1RST |SPI1 Controller Reset
<> 149:156823d33999 11629 * | | |0 = SPI1 controller normal operation.
<> 149:156823d33999 11630 * | | |1 = SPI1 controller reset.
<> 149:156823d33999 11631 * |[14] |SPI2RST |SPI2 Controller Reset
<> 149:156823d33999 11632 * | | |0 = SPI2 controller normal operation.
<> 149:156823d33999 11633 * | | |1 = SPI2 controller reset.
<> 149:156823d33999 11634 * |[16] |UART0RST |UART0 Controller Reset
<> 149:156823d33999 11635 * | | |0 = UART0 controller normal operation.
<> 149:156823d33999 11636 * | | |1 = UART0 controller reset.
<> 149:156823d33999 11637 * |[17] |UART1RST |UART1 Controller Reset
<> 149:156823d33999 11638 * | | |0 = UART1 controller normal operation.
<> 149:156823d33999 11639 * | | |1 = UART1 controller reset.
<> 149:156823d33999 11640 * |[18] |UART2RST |UART2 Controller Reset
<> 149:156823d33999 11641 * | | |0 = UART2 controller normal operation.
<> 149:156823d33999 11642 * | | |1 = UART2 controller reset.
<> 149:156823d33999 11643 * |[19] |UART3RST |UART3 Controller Reset
<> 149:156823d33999 11644 * | | |0 = UART3 controller normal operation.
<> 149:156823d33999 11645 * | | |1 = UART3 controller reset.
<> 149:156823d33999 11646 * |[24] |CAN0RST |CAN0 Controller Reset
<> 149:156823d33999 11647 * | | |0 = CAN0 controller normal operation.
<> 149:156823d33999 11648 * | | |1 = CAN0 controller reset.
<> 149:156823d33999 11649 * |[26] |OTGRST |OTG Controller Reset
<> 149:156823d33999 11650 * | | |0 = OTG controller normal operation.
<> 149:156823d33999 11651 * | | |1 = OTG controller reset.
<> 149:156823d33999 11652 * |[27] |USBDRST |USB Device Controller Reset
<> 149:156823d33999 11653 * | | |0 = USB device controller normal operation.
<> 149:156823d33999 11654 * | | |1 = USB device controller reset.
<> 149:156823d33999 11655 * |[28] |EADCRST |EADC Controller Reset
<> 149:156823d33999 11656 * | | |0 = EADC controller normal operation.
<> 149:156823d33999 11657 * | | |1 = EADC controller reset.
<> 149:156823d33999 11658 * @var SYS_T::IPRST2
<> 149:156823d33999 11659 * Offset: 0x10 Peripheral Reset Control Register 2
<> 149:156823d33999 11660 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11661 * |Bits |Field |Descriptions
<> 149:156823d33999 11662 * | :----: | :----: | :---- |
<> 149:156823d33999 11663 * |[0] |SC0RST |SC0 Controller Reset
<> 149:156823d33999 11664 * | | |0 = SC0 controller normal operation.
<> 149:156823d33999 11665 * | | |1 = SC0 controller reset.
<> 149:156823d33999 11666 * |[12] |DACRST |DAC Controller Reset
<> 149:156823d33999 11667 * | | |0 = DAC controller normal operation.
<> 149:156823d33999 11668 * | | |1 = DAC controller reset.
<> 149:156823d33999 11669 * |[16] |PWM0RST |PWM0 Controller Reset
<> 149:156823d33999 11670 * | | |0 = PWM0 controller normal operation.
<> 149:156823d33999 11671 * | | |1 = PWM0 controller reset.
<> 149:156823d33999 11672 * |[17] |PWM1RST |PWM1 Controller Reset
<> 149:156823d33999 11673 * | | |0 = PWM1 controller normal operation.
<> 149:156823d33999 11674 * | | |1 = PWM1 controller reset.
<> 149:156823d33999 11675 * |[25] |TKRST |Touch Key Controller Reset
<> 149:156823d33999 11676 * | | |0 = Touch Key controller normal operation.
<> 149:156823d33999 11677 * | | |1 = Touch Key controller reset.
<> 149:156823d33999 11678 * @var SYS_T::BODCTL
<> 149:156823d33999 11679 * Offset: 0x18 Brown-Out Detector Control Register
<> 149:156823d33999 11680 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11681 * |Bits |Field |Descriptions
<> 149:156823d33999 11682 * | :----: | :----: | :---- |
<> 149:156823d33999 11683 * |[0] |BODEN |Brown-Out Detector Enable Bit (Write Protect)
<> 149:156823d33999 11684 * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
<> 149:156823d33999 11685 * | | |0 = Brown-out Detector function Disabled.
<> 149:156823d33999 11686 * | | |1 = Brown-out Detector function Enabled.
<> 149:156823d33999 11687 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11688 * |[2:1] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
<> 149:156823d33999 11689 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
<> 149:156823d33999 11690 * | | |00 = Brown-Out Detector Threshold Voltage is 2.2V
<> 149:156823d33999 11691 * | | |01 = Brown-Out Detector Threshold Voltage is 2.7V
<> 149:156823d33999 11692 * | | |10 = Brown-Out Detector Threshold Voltage is 3.7V
<> 149:156823d33999 11693 * | | |11 = Brown-Out Detector Threshold Voltage is 4.5V
<> 149:156823d33999 11694 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11695 * |[3] |BODRSTEN |Brown-Out Reset Enable Bit (Write Protect)
<> 149:156823d33999 11696 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
<> 149:156823d33999 11697 * | | |0 = Brown-out "INTERRUPT" function Enabled.
<> 149:156823d33999 11698 * | | |1 = Brown-out "RESET" function Enabled.
<> 149:156823d33999 11699 * | | |Note1:
<> 149:156823d33999 11700 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
<> 149:156823d33999 11701 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
<> 149:156823d33999 11702 * | | |BOD interrupt will keep till to the BODEN set to 0.
<> 149:156823d33999 11703 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
<> 149:156823d33999 11704 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11705 * |[4] |BODIF |Brown-Out Detector Interrupt Flag
<> 149:156823d33999 11706 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
<> 149:156823d33999 11707 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
<> 149:156823d33999 11708 * | | |Note: Write 1 to clear this bit to 0.
<> 149:156823d33999 11709 * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
<> 149:156823d33999 11710 * | | |0 = BOD operate in normal mode (default).
<> 149:156823d33999 11711 * | | |1 = BOD Low Power mode Enabled.
<> 149:156823d33999 11712 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
<> 149:156823d33999 11713 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11714 * |[6] |BODOUT |Brown-Out Detector Output Status
<> 149:156823d33999 11715 * | | |0 = Brown-out Detector output status is 0.
<> 149:156823d33999 11716 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
<> 149:156823d33999 11717 * | | |1 = Brown-out Detector output status is 1.
<> 149:156823d33999 11718 * | | |It means the detected voltage is lower than BODVL setting.
<> 149:156823d33999 11719 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
<> 149:156823d33999 11720 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
<> 149:156823d33999 11721 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
<> 149:156823d33999 11722 * | | |LVR function is enabled by default.
<> 149:156823d33999 11723 * | | |0 = Low Voltage Reset function Disabled.
<> 149:156823d33999 11724 * | | |1 = Low Voltage Reset function Enabled
<> 149:156823d33999 11725 * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
<> 149:156823d33999 11726 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11727 * |[10:8] |BODDGSEL |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
<> 149:156823d33999 11728 * | | |000 = BOD output is sampled by RC10K clock.
<> 149:156823d33999 11729 * | | |001 = 4 system clock (HCLK).
<> 149:156823d33999 11730 * | | |010 = 8 system clock (HCLK).
<> 149:156823d33999 11731 * | | |011 = 16 system clock (HCLK).
<> 149:156823d33999 11732 * | | |100 = 32 system clock (HCLK).
<> 149:156823d33999 11733 * | | |101 = 64 system clock (HCLK).
<> 149:156823d33999 11734 * | | |110 = 128 system clock (HCLK).
<> 149:156823d33999 11735 * | | |111 = 256 system clock (HCLK).
<> 149:156823d33999 11736 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11737 * |[14:12] |LVRDGSEL |LVR Output De-Glitch Time Select (Write Protect)
<> 149:156823d33999 11738 * | | |000 = Without de-glitch function.
<> 149:156823d33999 11739 * | | |001 = 4 system clock (HCLK).
<> 149:156823d33999 11740 * | | |010 = 8 system clock (HCLK).
<> 149:156823d33999 11741 * | | |011 = 16 system clock (HCLK).
<> 149:156823d33999 11742 * | | |100 = 32 system clock (HCLK).
<> 149:156823d33999 11743 * | | |101 = 64 system clock (HCLK).
<> 149:156823d33999 11744 * | | |110 = 128 system clock (HCLK).
<> 149:156823d33999 11745 * | | |111 = 256 system clock (HCLK).
<> 149:156823d33999 11746 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11747 * @var SYS_T::IVSCTL
<> 149:156823d33999 11748 * Offset: 0x1C Internal Voltage Source Control Register
<> 149:156823d33999 11749 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11750 * |Bits |Field |Descriptions
<> 149:156823d33999 11751 * | :----: | :----: | :---- |
<> 149:156823d33999 11752 * |[0] |VTEMPEN |Temperature Sensor Enable Bit
<> 149:156823d33999 11753 * | | |This bit is used to enable/disable temperature sensor function.
<> 149:156823d33999 11754 * | | |0 = Temperature sensor function Disabled (default).
<> 149:156823d33999 11755 * | | |1 = Temperature sensor function Enabled.
<> 149:156823d33999 11756 * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
<> 149:156823d33999 11757 * | | |Please refer to ADC function chapter for details.
<> 149:156823d33999 11758 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
<> 149:156823d33999 11759 * | | |This bit is used to enable/disable VBAT unity gain buffer function.
<> 149:156823d33999 11760 * | | |0 = VBAT unity gain buffer function Disabled (default).
<> 149:156823d33999 11761 * | | |1 = VBAT unity gain buffer function Enabled.
<> 149:156823d33999 11762 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
<> 149:156823d33999 11763 * @var SYS_T::PORCTL
<> 149:156823d33999 11764 * Offset: 0x24 Power-On-Reset Controller Register
<> 149:156823d33999 11765 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11766 * |Bits |Field |Descriptions
<> 149:156823d33999 11767 * | :----: | :----: | :---- |
<> 149:156823d33999 11768 * |[15:0] |POROFF |Power-On-Reset Enable Bit (Write Protect)
<> 149:156823d33999 11769 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
<> 149:156823d33999 11770 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
<> 149:156823d33999 11771 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
<> 149:156823d33999 11772 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
<> 149:156823d33999 11773 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11774 * @var SYS_T::VREFCTL
<> 149:156823d33999 11775 * Offset: 0x28 VREF Control Register
<> 149:156823d33999 11776 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11777 * |Bits |Field |Descriptions
<> 149:156823d33999 11778 * | :----: | :----: | :---- |
<> 149:156823d33999 11779 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
<> 149:156823d33999 11780 * | | |00011 = VREF is internal 2.65V.
<> 149:156823d33999 11781 * | | |00111 = VREF is internal 2.048V.
<> 149:156823d33999 11782 * | | |01011 = VREF is internal 3.072V.
<> 149:156823d33999 11783 * | | |01111 = VREF is internal 4.096V.
<> 149:156823d33999 11784 * | | |Others = Reserved.
<> 149:156823d33999 11785 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11786 * @var SYS_T::USBPHY
<> 149:156823d33999 11787 * Offset: 0x2C USB PHY Control Register
<> 149:156823d33999 11788 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11789 * |Bits |Field |Descriptions
<> 149:156823d33999 11790 * | :----: | :----: | :---- |
<> 149:156823d33999 11791 * |[1:0] |USBROLE |USB Role Option (Write Protect)
<> 149:156823d33999 11792 * | | |These two bits are used to select the role of USB.
<> 149:156823d33999 11793 * | | |00 = Standard USB Device mode.
<> 149:156823d33999 11794 * | | |01 = Standard USB Host mode.
<> 149:156823d33999 11795 * | | |10 = ID dependent mode.
<> 149:156823d33999 11796 * | | |11 = On-The-Go device mode.
<> 149:156823d33999 11797 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11798 * |[8] |LDO33EN |USB LDO33 Enable Bit (Write Protect)
<> 149:156823d33999 11799 * | | |0 = USB LDO33 Disabled.
<> 149:156823d33999 11800 * | | |1 = USB LDO33 Enabled.
<> 149:156823d33999 11801 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 11802 * @var SYS_T::GPA_MFPL
<> 149:156823d33999 11803 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
<> 149:156823d33999 11804 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11805 * |Bits |Field |Descriptions
<> 149:156823d33999 11806 * | :----: | :----: | :---- |
<> 149:156823d33999 11807 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
<> 149:156823d33999 11808 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
<> 149:156823d33999 11809 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
<> 149:156823d33999 11810 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
<> 149:156823d33999 11811 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
<> 149:156823d33999 11812 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
<> 149:156823d33999 11813 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
<> 149:156823d33999 11814 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
<> 149:156823d33999 11815 * @var SYS_T::GPA_MFPH
<> 149:156823d33999 11816 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
<> 149:156823d33999 11817 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11818 * |Bits |Field |Descriptions
<> 149:156823d33999 11819 * | :----: | :----: | :---- |
<> 149:156823d33999 11820 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
<> 149:156823d33999 11821 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
<> 149:156823d33999 11822 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
<> 149:156823d33999 11823 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
<> 149:156823d33999 11824 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
<> 149:156823d33999 11825 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
<> 149:156823d33999 11826 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
<> 149:156823d33999 11827 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
<> 149:156823d33999 11828 * @var SYS_T::GPB_MFPL
<> 149:156823d33999 11829 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
<> 149:156823d33999 11830 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11831 * |Bits |Field |Descriptions
<> 149:156823d33999 11832 * | :----: | :----: | :---- |
<> 149:156823d33999 11833 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
<> 149:156823d33999 11834 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
<> 149:156823d33999 11835 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
<> 149:156823d33999 11836 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
<> 149:156823d33999 11837 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
<> 149:156823d33999 11838 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
<> 149:156823d33999 11839 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
<> 149:156823d33999 11840 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
<> 149:156823d33999 11841 * @var SYS_T::GPB_MFPH
<> 149:156823d33999 11842 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
<> 149:156823d33999 11843 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11844 * |Bits |Field |Descriptions
<> 149:156823d33999 11845 * | :----: | :----: | :---- |
<> 149:156823d33999 11846 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
<> 149:156823d33999 11847 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
<> 149:156823d33999 11848 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
<> 149:156823d33999 11849 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
<> 149:156823d33999 11850 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
<> 149:156823d33999 11851 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
<> 149:156823d33999 11852 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
<> 149:156823d33999 11853 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
<> 149:156823d33999 11854 * @var SYS_T::GPC_MFPL
<> 149:156823d33999 11855 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
<> 149:156823d33999 11856 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11857 * |Bits |Field |Descriptions
<> 149:156823d33999 11858 * | :----: | :----: | :---- |
<> 149:156823d33999 11859 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
<> 149:156823d33999 11860 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
<> 149:156823d33999 11861 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
<> 149:156823d33999 11862 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
<> 149:156823d33999 11863 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
<> 149:156823d33999 11864 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
<> 149:156823d33999 11865 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
<> 149:156823d33999 11866 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
<> 149:156823d33999 11867 * @var SYS_T::GPC_MFPH
<> 149:156823d33999 11868 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
<> 149:156823d33999 11869 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11870 * |Bits |Field |Descriptions
<> 149:156823d33999 11871 * | :----: | :----: | :---- |
<> 149:156823d33999 11872 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
<> 149:156823d33999 11873 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
<> 149:156823d33999 11874 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
<> 149:156823d33999 11875 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
<> 149:156823d33999 11876 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
<> 149:156823d33999 11877 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
<> 149:156823d33999 11878 * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
<> 149:156823d33999 11879 * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
<> 149:156823d33999 11880 * @var SYS_T::GPD_MFPL
<> 149:156823d33999 11881 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
<> 149:156823d33999 11882 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11883 * |Bits |Field |Descriptions
<> 149:156823d33999 11884 * | :----: | :----: | :---- |
<> 149:156823d33999 11885 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
<> 149:156823d33999 11886 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
<> 149:156823d33999 11887 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
<> 149:156823d33999 11888 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
<> 149:156823d33999 11889 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
<> 149:156823d33999 11890 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
<> 149:156823d33999 11891 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
<> 149:156823d33999 11892 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
<> 149:156823d33999 11893 * @var SYS_T::GPD_MFPH
<> 149:156823d33999 11894 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
<> 149:156823d33999 11895 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11896 * |Bits |Field |Descriptions
<> 149:156823d33999 11897 * | :----: | :----: | :---- |
<> 149:156823d33999 11898 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
<> 149:156823d33999 11899 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
<> 149:156823d33999 11900 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
<> 149:156823d33999 11901 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
<> 149:156823d33999 11902 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
<> 149:156823d33999 11903 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
<> 149:156823d33999 11904 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
<> 149:156823d33999 11905 * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
<> 149:156823d33999 11906 * @var SYS_T::GPE_MFPL
<> 149:156823d33999 11907 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
<> 149:156823d33999 11908 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11909 * |Bits |Field |Descriptions
<> 149:156823d33999 11910 * | :----: | :----: | :---- |
<> 149:156823d33999 11911 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
<> 149:156823d33999 11912 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
<> 149:156823d33999 11913 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
<> 149:156823d33999 11914 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
<> 149:156823d33999 11915 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
<> 149:156823d33999 11916 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
<> 149:156823d33999 11917 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
<> 149:156823d33999 11918 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
<> 149:156823d33999 11919 * @var SYS_T::GPE_MFPH
<> 149:156823d33999 11920 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
<> 149:156823d33999 11921 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11922 * |Bits |Field |Descriptions
<> 149:156823d33999 11923 * | :----: | :----: | :---- |
<> 149:156823d33999 11924 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
<> 149:156823d33999 11925 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
<> 149:156823d33999 11926 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
<> 149:156823d33999 11927 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
<> 149:156823d33999 11928 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
<> 149:156823d33999 11929 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
<> 149:156823d33999 11930 * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection
<> 149:156823d33999 11931 * @var SYS_T::GPF_MFPL
<> 149:156823d33999 11932 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
<> 149:156823d33999 11933 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11934 * |Bits |Field |Descriptions
<> 149:156823d33999 11935 * | :----: | :----: | :---- |
<> 149:156823d33999 11936 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
<> 149:156823d33999 11937 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
<> 149:156823d33999 11938 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
<> 149:156823d33999 11939 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
<> 149:156823d33999 11940 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
<> 149:156823d33999 11941 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
<> 149:156823d33999 11942 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
<> 149:156823d33999 11943 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
<> 149:156823d33999 11944 * @var SYS_T::SRAM_INTCTL
<> 149:156823d33999 11945 * Offset: 0xC0 System SRAM Interrupt Enable Control Register
<> 149:156823d33999 11946 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11947 * |Bits |Field |Descriptions
<> 149:156823d33999 11948 * | :----: | :----: | :---- |
<> 149:156823d33999 11949 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
<> 149:156823d33999 11950 * | | |0 = SRAM parity check error interrupt Disabled.
<> 149:156823d33999 11951 * | | |1 = SRAM parity check error interrupt Enabled.
<> 149:156823d33999 11952 * @var SYS_T::SRAM_STATUS
<> 149:156823d33999 11953 * Offset: 0xC4 System SRAM Parity Error Status Register
<> 149:156823d33999 11954 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11955 * |Bits |Field |Descriptions
<> 149:156823d33999 11956 * | :----: | :----: | :---- |
<> 149:156823d33999 11957 * |[0] |PERRIF |SRAM Parity Check Error Flag
<> 149:156823d33999 11958 * | | |0 = No System SRAM parity error.
<> 149:156823d33999 11959 * | | |1 = System SRAM parity error occur.
<> 149:156823d33999 11960 * @var SYS_T::SRAM_ERRADDR
<> 149:156823d33999 11961 * Offset: 0xC8 System SRAM Parity Check Error Address Register
<> 149:156823d33999 11962 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11963 * |Bits |Field |Descriptions
<> 149:156823d33999 11964 * | :----: | :----: | :---- |
<> 149:156823d33999 11965 * |[31:0] |ERRADDR |System SRAM Parity Error Address
<> 149:156823d33999 11966 * | | |This register shows system SRAM parity error byte address.
<> 149:156823d33999 11967 * @var SYS_T::SRAM_BISTCTL
<> 149:156823d33999 11968 * Offset: 0xD0 System SRAM BIST Test Control Register
<> 149:156823d33999 11969 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11970 * |Bits |Field |Descriptions
<> 149:156823d33999 11971 * | :----: | :----: | :---- |
<> 149:156823d33999 11972 * |[0] |SRBIST0 |1st
<> 149:156823d33999 11973 * | | |SRAM BIST Enable Bit
<> 149:156823d33999 11974 * | | |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
<> 149:156823d33999 11975 * | | |0 = system SRAM BIST Disabled.
<> 149:156823d33999 11976 * | | |1 = system SRAM BIST Enabled.
<> 149:156823d33999 11977 * |[1] |SRBIST1 |2nd
<> 149:156823d33999 11978 * | | |SRAM BIST Enable Bit
<> 149:156823d33999 11979 * | | |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
<> 149:156823d33999 11980 * | | |0 = system SRAM BIST Disabled.
<> 149:156823d33999 11981 * | | |1 = system SRAM BIST Enabled.
<> 149:156823d33999 11982 * |[2] |CRBIST |CACHE BIST Enable Bit
<> 149:156823d33999 11983 * | | |This bit enables BIST test for CACHE RAM
<> 149:156823d33999 11984 * | | |0 = system CACHE BIST Disabled.
<> 149:156823d33999 11985 * | | |1 = system CACHE BIST Enabled.
<> 149:156823d33999 11986 * |[3] |CANBIST |CAN BIST Enable Bit
<> 149:156823d33999 11987 * | | |This bit enables BIST test for CAN RAM
<> 149:156823d33999 11988 * | | |0 = system CAN BIST Disabled.
<> 149:156823d33999 11989 * | | |1 = system CAN BIST Enabled.
<> 149:156823d33999 11990 * |[4] |USBBIST |USB BIST Enable Bit
<> 149:156823d33999 11991 * | | |This bit enables BIST test for USB RAM
<> 149:156823d33999 11992 * | | |0 = system USB BIST Disabled.
<> 149:156823d33999 11993 * | | |1 = system USB BIST Enabled.
<> 149:156823d33999 11994 * @var SYS_T::SRAM_BISTSTS
<> 149:156823d33999 11995 * Offset: 0xD4 System SRAM BIST Test Status Register
<> 149:156823d33999 11996 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 11997 * |Bits |Field |Descriptions
<> 149:156823d33999 11998 * | :----: | :----: | :---- |
<> 149:156823d33999 11999 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
<> 149:156823d33999 12000 * | | |0 = 1st system SRAM BIST test pass.
<> 149:156823d33999 12001 * | | |1 = 1st system SRAM BIST test fail.
<> 149:156823d33999 12002 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
<> 149:156823d33999 12003 * | | |0 = 2nd system SRAM BIST test pass.
<> 149:156823d33999 12004 * | | |1 = 2nd system SRAM BIST test fail.
<> 149:156823d33999 12005 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
<> 149:156823d33999 12006 * | | |0 = System CACHE RAM BIST test pass.
<> 149:156823d33999 12007 * | | |1 = System CACHE RAM BIST test fail.
<> 149:156823d33999 12008 * |[3] |CANBEF |CAN SRAM BIST Fail Flag
<> 149:156823d33999 12009 * | | |0 = CAN SRAM BIST test pass.
<> 149:156823d33999 12010 * | | |1 = CAN SRAM BIST test fail.
<> 149:156823d33999 12011 * |[4] |USBBEF |USB SRAM BIST Fail Flag
<> 149:156823d33999 12012 * | | |0 = USB SRAM BIST test pass.
<> 149:156823d33999 12013 * | | |1 = USB SRAM BIST test fail.
<> 149:156823d33999 12014 * |[16] |SRBEND0 |1st SRAM BIST Test Finish
<> 149:156823d33999 12015 * | | |0 = 1st system SRAM BIST active.
<> 149:156823d33999 12016 * | | |1 = 1st system SRAM BIST finish.
<> 149:156823d33999 12017 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
<> 149:156823d33999 12018 * | | |0 = 2nd system SRAM BIST is active.
<> 149:156823d33999 12019 * | | |1 = 2nd system SRAM BIST finish.
<> 149:156823d33999 12020 * |[18] |CRBEND |CACHE SRAM BIST Test Finish
<> 149:156823d33999 12021 * | | |0 = System CACHE RAM BIST is active.
<> 149:156823d33999 12022 * | | |1 = System CACHE RAM BIST test finish.
<> 149:156823d33999 12023 * |[19] |CANBEND |CAN SRAM BIST Test Finish
<> 149:156823d33999 12024 * | | |0 = CAN SRAM BIST is active.
<> 149:156823d33999 12025 * | | |1 = CAN SRAM BIST test finish.
<> 149:156823d33999 12026 * |[20] |USBBEND |USB SRAM BIST Test Finish
<> 149:156823d33999 12027 * | | |0 = USB SRAM BIST is active.
<> 149:156823d33999 12028 * | | |1 = USB SRAM BIST test finish.
<> 149:156823d33999 12029 * @var SYS_T::IRCTCTL
<> 149:156823d33999 12030 * Offset: 0xF0 IRC Trim Control Register
<> 149:156823d33999 12031 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12032 * |Bits |Field |Descriptions
<> 149:156823d33999 12033 * | :----: | :----: | :---- |
<> 149:156823d33999 12034 * |[1:0] |FREQSEL |Trim Frequency Selection
<> 149:156823d33999 12035 * | | |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
<> 149:156823d33999 12036 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
<> 149:156823d33999 12037 * | | |00 = Disable HIRC auto trim function.
<> 149:156823d33999 12038 * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
<> 149:156823d33999 12039 * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
<> 149:156823d33999 12040 * | | |11 = Reserved.
<> 149:156823d33999 12041 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
<> 149:156823d33999 12042 * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
<> 149:156823d33999 12043 * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
<> 149:156823d33999 12044 * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
<> 149:156823d33999 12045 * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
<> 149:156823d33999 12046 * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
<> 149:156823d33999 12047 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
<> 149:156823d33999 12048 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
<> 149:156823d33999 12049 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
<> 149:156823d33999 12050 * | | |Once the HIRC locked, the internal trim value update counter will be reset.
<> 149:156823d33999 12051 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
<> 149:156823d33999 12052 * | | |00 = Trim retry count limitation is 64 loops.
<> 149:156823d33999 12053 * | | |01 = Trim retry count limitation is 128 loops.
<> 149:156823d33999 12054 * | | |10 = Trim retry count limitation is 256 loops.
<> 149:156823d33999 12055 * | | |11 = Trim retry count limitation is 512 loops.
<> 149:156823d33999 12056 * |[8] |CESTOPEN |Clock Error Stop Enable Bit
<> 149:156823d33999 12057 * | | |0 = The trim operation is keep going if clock is inaccuracy.
<> 149:156823d33999 12058 * | | |1 = The trim operation is stopped if clock is inaccuracy.
<> 149:156823d33999 12059 * @var SYS_T::IRCTIEN
<> 149:156823d33999 12060 * Offset: 0xF4 IRC Trim Interrupt Enable Register
<> 149:156823d33999 12061 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12062 * |Bits |Field |Descriptions
<> 149:156823d33999 12063 * | :----: | :----: | :---- |
<> 149:156823d33999 12064 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
<> 149:156823d33999 12065 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
<> 149:156823d33999 12066 * | | |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
<> 149:156823d33999 12067 * | | |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
<> 149:156823d33999 12068 * | | |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
<> 149:156823d33999 12069 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
<> 149:156823d33999 12070 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
<> 149:156823d33999 12071 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
<> 149:156823d33999 12072 * | | |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
<> 149:156823d33999 12073 * | | |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
<> 149:156823d33999 12074 * @var SYS_T::IRCTISTS
<> 149:156823d33999 12075 * Offset: 0xF8 IRC Trim Interrupt Status Register
<> 149:156823d33999 12076 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12077 * |Bits |Field |Descriptions
<> 149:156823d33999 12078 * | :----: | :----: | :---- |
<> 149:156823d33999 12079 * |[0] |FREQLOCK |HIRC Frequency Lock Status
<> 149:156823d33999 12080 * | | |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
<> 149:156823d33999 12081 * | | |This is a status bit and doesn't trigger any interrupt.
<> 149:156823d33999 12082 * |[1] |TFAILIF |Trim Failure Interrupt Status
<> 149:156823d33999 12083 * | | |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
<> 149:156823d33999 12084 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
<> 149:156823d33999 12085 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
<> 149:156823d33999 12086 * | | |Write 1 to clear this to 0.
<> 149:156823d33999 12087 * | | |0 = Trim value update limitation count does not reach.
<> 149:156823d33999 12088 * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
<> 149:156823d33999 12089 * |[2] |CLKERRIF |Clock Error Interrupt Status
<> 149:156823d33999 12090 * | | |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
<> 149:156823d33999 12091 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
<> 149:156823d33999 12092 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
<> 149:156823d33999 12093 * | | |Write 1 to clear this to 0.
<> 149:156823d33999 12094 * | | |0 = Clock frequency is accuracy.
<> 149:156823d33999 12095 * | | |1 = Clock frequency is inaccuracy.
<> 149:156823d33999 12096 * @var SYS_T::REGLCTL
<> 149:156823d33999 12097 * Offset: 0x100 Register Lock Control Register
<> 149:156823d33999 12098 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12099 * |Bits |Field |Descriptions
<> 149:156823d33999 12100 * | :----: | :----: | :---- |
<> 149:156823d33999 12101 * |[7:0] |REGLCTL |Register Lock Control Code
<> 149:156823d33999 12102 * | | |Write operation:
<> 149:156823d33999 12103 * | | |Some registers have write-protection function.
<> 149:156823d33999 12104 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
<> 149:156823d33999 12105 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
<> 149:156823d33999 12106 * | | |Read operation:
<> 149:156823d33999 12107 * | | |0 = Write-protection Enabled for writing protected registers.
<> 149:156823d33999 12108 * | | |Any write to the protected register is ignored.
<> 149:156823d33999 12109 * | | |1 = Write-protection Disabled for writing protected registers.
<> 149:156823d33999 12110 * | | |The Protected registers are:
<> 149:156823d33999 12111 * | | |SYS_IPRST0: address 0x4000_0008
<> 149:156823d33999 12112 * | | |SYS_BODCTL: address 0x4000_0018
<> 149:156823d33999 12113 * | | |SYS_PORCTL: address 0x4000_0024
<> 149:156823d33999 12114 * | | |SYS_VREFCTL: address 0x4000_0028
<> 149:156823d33999 12115 * | | |SYS_USBPHY: address 0x4000_002C
<> 149:156823d33999 12116 * | | |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
<> 149:156823d33999 12117 * | | |SYS_SRAM_BISTCTL: address 0x4000_00D0
<> 149:156823d33999 12118 * | | |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
<> 149:156823d33999 12119 * | | |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
<> 149:156823d33999 12120 * | | |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
<> 149:156823d33999 12121 * | | |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
<> 149:156823d33999 12122 * | | |CLK_CLKDSTS: address 0x4000_0274
<> 149:156823d33999 12123 * | | |NMIEN: address 0x4000_0300
<> 149:156823d33999 12124 * | | |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
<> 149:156823d33999 12125 * | | |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
<> 149:156823d33999 12126 * | | |FMC_ISPSTS: address 0x4000_C040
<> 149:156823d33999 12127 * | | |WDT_CTL: address 0x4004_0000
<> 149:156823d33999 12128 * | | |FMC_FTCTL: address 0x4000_5018
<> 149:156823d33999 12129 * | | |FMC_ICPCMD: address 0x4000_501C
<> 149:156823d33999 12130 * | | |CLK_PLLCTL: address 0x40000240
<> 149:156823d33999 12131 * | | |PWM_CTL0: address 0x4005_8000
<> 149:156823d33999 12132 * | | |PWM_CTL0: address 0x4005_9000
<> 149:156823d33999 12133 * | | |PWM_DTCTL0_1: address 0x4005_8070
<> 149:156823d33999 12134 * | | |PWM_DTCTL0_1: address 0x4005_9070
<> 149:156823d33999 12135 * | | |PWM_DTCTL2_3: address 0x4005_8074
<> 149:156823d33999 12136 * | | |PWM_DTCTL2_3: address 0x4005_9074
<> 149:156823d33999 12137 * | | |PWM_DTCTL4_5: address 0x4005_8078
<> 149:156823d33999 12138 * | | |PWM_DTCTL4_5: address 0x4005_9078
<> 149:156823d33999 12139 * | | |PWM_BRKCTL0_1: address 0x4005_80C8
<> 149:156823d33999 12140 * | | |PWM_BRKCTL0_1: address 0x4005_90C8
<> 149:156823d33999 12141 * | | |PWM_BRKCTL2_3: address0x4005_80CC
<> 149:156823d33999 12142 * | | |PWM_BRKCTL2_3: address0x4005_90CC
<> 149:156823d33999 12143 * | | |PWM_BRKCTL4_5: address0x4005_80D0
<> 149:156823d33999 12144 * | | |PWM_BRKCTL4_5: address0x4005_90D0
<> 149:156823d33999 12145 * | | |PWM_INTEN1: address0x4005_80E4
<> 149:156823d33999 12146 * | | |PWM_INTEN1: address0x4005_90E4
<> 149:156823d33999 12147 * | | |PWM_INTSTS1: address0x4005_80EC
<> 149:156823d33999 12148 * | | |PWM_INTSTS1: address0x4005_90EC
<> 149:156823d33999 12149 */
<> 149:156823d33999 12150
<> 149:156823d33999 12151 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
<> 149:156823d33999 12152 __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
<> 149:156823d33999 12153 __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
<> 149:156823d33999 12154 __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
<> 149:156823d33999 12155 __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
<> 149:156823d33999 12156 __I uint32_t RESERVE0[1];
<> 149:156823d33999 12157 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
<> 149:156823d33999 12158 __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
<> 149:156823d33999 12159 __I uint32_t RESERVE1[1];
<> 149:156823d33999 12160 __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
<> 149:156823d33999 12161 __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
<> 149:156823d33999 12162 __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
<> 149:156823d33999 12163 __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
<> 149:156823d33999 12164 __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
<> 149:156823d33999 12165 __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
<> 149:156823d33999 12166 __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
<> 149:156823d33999 12167 __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
<> 149:156823d33999 12168 __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
<> 149:156823d33999 12169 __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
<> 149:156823d33999 12170 __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
<> 149:156823d33999 12171 __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
<> 149:156823d33999 12172 __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
<> 149:156823d33999 12173 __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
<> 149:156823d33999 12174 __I uint32_t RESERVE2[25];
<> 149:156823d33999 12175 __IO uint32_t SRAM_INTCTL; /* Offset: 0xC0 System SRAM Interrupt Enable Control Register */
<> 149:156823d33999 12176 __I uint32_t SRAM_STATUS; /* Offset: 0xC4 System SRAM Parity Error Status Register */
<> 149:156823d33999 12177 __I uint32_t SRAM_ERRADDR; /* Offset: 0xC8 System SRAM Parity Check Error Address Register */
<> 149:156823d33999 12178 __I uint32_t RESERVE3[1];
<> 149:156823d33999 12179 __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
<> 149:156823d33999 12180 __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
<> 149:156823d33999 12181 __I uint32_t RESERVE4[6];
<> 149:156823d33999 12182 __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
<> 149:156823d33999 12183 __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
<> 149:156823d33999 12184 __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
<> 149:156823d33999 12185 __I uint32_t RESERVE5[1];
<> 149:156823d33999 12186 __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
<> 149:156823d33999 12187
<> 149:156823d33999 12188 } SYS_T;
<> 149:156823d33999 12189
<> 149:156823d33999 12190
<> 149:156823d33999 12191
<> 149:156823d33999 12192 /**
<> 149:156823d33999 12193 @addtogroup SYS_CONST SYS Bit Field Definition
<> 149:156823d33999 12194 Constant Definitions for SYS Controller
<> 149:156823d33999 12195 @{ */
<> 149:156823d33999 12196
<> 149:156823d33999 12197 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
<> 149:156823d33999 12198 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
<> 149:156823d33999 12199
<> 149:156823d33999 12200 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
<> 149:156823d33999 12201 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
<> 149:156823d33999 12202
<> 149:156823d33999 12203 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
<> 149:156823d33999 12204 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
<> 149:156823d33999 12205
<> 149:156823d33999 12206 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
<> 149:156823d33999 12207 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
<> 149:156823d33999 12208
<> 149:156823d33999 12209 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
<> 149:156823d33999 12210 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
<> 149:156823d33999 12211
<> 149:156823d33999 12212 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
<> 149:156823d33999 12213 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
<> 149:156823d33999 12214
<> 149:156823d33999 12215 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
<> 149:156823d33999 12216 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
<> 149:156823d33999 12217
<> 149:156823d33999 12218 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
<> 149:156823d33999 12219 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
<> 149:156823d33999 12220
<> 149:156823d33999 12221 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
<> 149:156823d33999 12222 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
<> 149:156823d33999 12223
<> 149:156823d33999 12224 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
<> 149:156823d33999 12225 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
<> 149:156823d33999 12226
<> 149:156823d33999 12227 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
<> 149:156823d33999 12228 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
<> 149:156823d33999 12229
<> 149:156823d33999 12230 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
<> 149:156823d33999 12231 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
<> 149:156823d33999 12232
<> 149:156823d33999 12233 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
<> 149:156823d33999 12234 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
<> 149:156823d33999 12235
<> 149:156823d33999 12236 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */
<> 149:156823d33999 12237 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
<> 149:156823d33999 12238
<> 149:156823d33999 12239 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
<> 149:156823d33999 12240 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
<> 149:156823d33999 12241
<> 149:156823d33999 12242 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
<> 149:156823d33999 12243 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
<> 149:156823d33999 12244
<> 149:156823d33999 12245 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
<> 149:156823d33999 12246 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
<> 149:156823d33999 12247
<> 149:156823d33999 12248 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
<> 149:156823d33999 12249 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
<> 149:156823d33999 12250
<> 149:156823d33999 12251 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
<> 149:156823d33999 12252 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
<> 149:156823d33999 12253
<> 149:156823d33999 12254 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
<> 149:156823d33999 12255 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
<> 149:156823d33999 12256
<> 149:156823d33999 12257 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
<> 149:156823d33999 12258 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
<> 149:156823d33999 12259
<> 149:156823d33999 12260 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
<> 149:156823d33999 12261 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
<> 149:156823d33999 12262
<> 149:156823d33999 12263 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
<> 149:156823d33999 12264 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
<> 149:156823d33999 12265
<> 149:156823d33999 12266 #define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
<> 149:156823d33999 12267 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
<> 149:156823d33999 12268
<> 149:156823d33999 12269 #define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
<> 149:156823d33999 12270 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
<> 149:156823d33999 12271
<> 149:156823d33999 12272 #define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
<> 149:156823d33999 12273 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
<> 149:156823d33999 12274
<> 149:156823d33999 12275 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
<> 149:156823d33999 12276 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
<> 149:156823d33999 12277
<> 149:156823d33999 12278 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
<> 149:156823d33999 12279 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
<> 149:156823d33999 12280
<> 149:156823d33999 12281 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
<> 149:156823d33999 12282 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
<> 149:156823d33999 12283
<> 149:156823d33999 12284 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
<> 149:156823d33999 12285 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
<> 149:156823d33999 12286
<> 149:156823d33999 12287 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
<> 149:156823d33999 12288 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
<> 149:156823d33999 12289
<> 149:156823d33999 12290 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
<> 149:156823d33999 12291 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
<> 149:156823d33999 12292
<> 149:156823d33999 12293 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
<> 149:156823d33999 12294 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
<> 149:156823d33999 12295
<> 149:156823d33999 12296 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
<> 149:156823d33999 12297 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
<> 149:156823d33999 12298
<> 149:156823d33999 12299 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
<> 149:156823d33999 12300 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
<> 149:156823d33999 12301
<> 149:156823d33999 12302 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
<> 149:156823d33999 12303 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
<> 149:156823d33999 12304
<> 149:156823d33999 12305 #define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */
<> 149:156823d33999 12306 #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */
<> 149:156823d33999 12307
<> 149:156823d33999 12308 #define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */
<> 149:156823d33999 12309 #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */
<> 149:156823d33999 12310
<> 149:156823d33999 12311 #define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */
<> 149:156823d33999 12312 #define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */
<> 149:156823d33999 12313
<> 149:156823d33999 12314 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
<> 149:156823d33999 12315 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
<> 149:156823d33999 12316
<> 149:156823d33999 12317 #define SYS_BODCTL_BODVL_Pos (1) /*!< SYS_T::BODCTL: BODVL Position */
<> 149:156823d33999 12318 #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
<> 149:156823d33999 12319
<> 149:156823d33999 12320 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
<> 149:156823d33999 12321 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
<> 149:156823d33999 12322
<> 149:156823d33999 12323 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
<> 149:156823d33999 12324 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
<> 149:156823d33999 12325
<> 149:156823d33999 12326 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
<> 149:156823d33999 12327 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
<> 149:156823d33999 12328
<> 149:156823d33999 12329 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
<> 149:156823d33999 12330 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
<> 149:156823d33999 12331
<> 149:156823d33999 12332 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
<> 149:156823d33999 12333 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
<> 149:156823d33999 12334
<> 149:156823d33999 12335 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
<> 149:156823d33999 12336 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
<> 149:156823d33999 12337
<> 149:156823d33999 12338 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
<> 149:156823d33999 12339 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
<> 149:156823d33999 12340
<> 149:156823d33999 12341 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
<> 149:156823d33999 12342 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
<> 149:156823d33999 12343
<> 149:156823d33999 12344 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
<> 149:156823d33999 12345 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
<> 149:156823d33999 12346
<> 149:156823d33999 12347 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
<> 149:156823d33999 12348 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
<> 149:156823d33999 12349
<> 149:156823d33999 12350 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
<> 149:156823d33999 12351 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
<> 149:156823d33999 12352
<> 149:156823d33999 12353 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
<> 149:156823d33999 12354 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
<> 149:156823d33999 12355
<> 149:156823d33999 12356 #define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS_T::USBPHY: LDO33EN Position */
<> 149:156823d33999 12357 #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS_T::USBPHY: LDO33EN Mask */
<> 149:156823d33999 12358
<> 149:156823d33999 12359 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
<> 149:156823d33999 12360 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
<> 149:156823d33999 12361
<> 149:156823d33999 12362 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
<> 149:156823d33999 12363 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
<> 149:156823d33999 12364
<> 149:156823d33999 12365 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
<> 149:156823d33999 12366 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
<> 149:156823d33999 12367
<> 149:156823d33999 12368 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
<> 149:156823d33999 12369 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
<> 149:156823d33999 12370
<> 149:156823d33999 12371 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
<> 149:156823d33999 12372 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
<> 149:156823d33999 12373
<> 149:156823d33999 12374 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
<> 149:156823d33999 12375 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
<> 149:156823d33999 12376
<> 149:156823d33999 12377 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
<> 149:156823d33999 12378 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
<> 149:156823d33999 12379
<> 149:156823d33999 12380 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
<> 149:156823d33999 12381 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
<> 149:156823d33999 12382
<> 149:156823d33999 12383 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
<> 149:156823d33999 12384 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
<> 149:156823d33999 12385
<> 149:156823d33999 12386 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
<> 149:156823d33999 12387 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
<> 149:156823d33999 12388
<> 149:156823d33999 12389 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
<> 149:156823d33999 12390 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
<> 149:156823d33999 12391
<> 149:156823d33999 12392 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
<> 149:156823d33999 12393 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
<> 149:156823d33999 12394
<> 149:156823d33999 12395 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
<> 149:156823d33999 12396 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
<> 149:156823d33999 12397
<> 149:156823d33999 12398 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
<> 149:156823d33999 12399 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
<> 149:156823d33999 12400
<> 149:156823d33999 12401 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
<> 149:156823d33999 12402 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
<> 149:156823d33999 12403
<> 149:156823d33999 12404 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
<> 149:156823d33999 12405 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
<> 149:156823d33999 12406
<> 149:156823d33999 12407 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
<> 149:156823d33999 12408 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
<> 149:156823d33999 12409
<> 149:156823d33999 12410 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
<> 149:156823d33999 12411 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
<> 149:156823d33999 12412
<> 149:156823d33999 12413 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
<> 149:156823d33999 12414 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
<> 149:156823d33999 12415
<> 149:156823d33999 12416 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
<> 149:156823d33999 12417 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
<> 149:156823d33999 12418
<> 149:156823d33999 12419 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
<> 149:156823d33999 12420 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
<> 149:156823d33999 12421
<> 149:156823d33999 12422 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
<> 149:156823d33999 12423 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
<> 149:156823d33999 12424
<> 149:156823d33999 12425 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
<> 149:156823d33999 12426 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
<> 149:156823d33999 12427
<> 149:156823d33999 12428 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
<> 149:156823d33999 12429 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
<> 149:156823d33999 12430
<> 149:156823d33999 12431 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
<> 149:156823d33999 12432 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
<> 149:156823d33999 12433
<> 149:156823d33999 12434 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
<> 149:156823d33999 12435 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
<> 149:156823d33999 12436
<> 149:156823d33999 12437 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
<> 149:156823d33999 12438 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
<> 149:156823d33999 12439
<> 149:156823d33999 12440 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
<> 149:156823d33999 12441 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
<> 149:156823d33999 12442
<> 149:156823d33999 12443 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
<> 149:156823d33999 12444 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
<> 149:156823d33999 12445
<> 149:156823d33999 12446 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
<> 149:156823d33999 12447 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
<> 149:156823d33999 12448
<> 149:156823d33999 12449 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
<> 149:156823d33999 12450 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
<> 149:156823d33999 12451
<> 149:156823d33999 12452 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
<> 149:156823d33999 12453 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
<> 149:156823d33999 12454
<> 149:156823d33999 12455 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
<> 149:156823d33999 12456 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
<> 149:156823d33999 12457
<> 149:156823d33999 12458 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
<> 149:156823d33999 12459 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
<> 149:156823d33999 12460
<> 149:156823d33999 12461 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
<> 149:156823d33999 12462 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
<> 149:156823d33999 12463
<> 149:156823d33999 12464 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
<> 149:156823d33999 12465 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
<> 149:156823d33999 12466
<> 149:156823d33999 12467 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
<> 149:156823d33999 12468 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
<> 149:156823d33999 12469
<> 149:156823d33999 12470 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
<> 149:156823d33999 12471 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
<> 149:156823d33999 12472
<> 149:156823d33999 12473 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
<> 149:156823d33999 12474 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
<> 149:156823d33999 12475
<> 149:156823d33999 12476 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
<> 149:156823d33999 12477 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
<> 149:156823d33999 12478
<> 149:156823d33999 12479 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
<> 149:156823d33999 12480 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
<> 149:156823d33999 12481
<> 149:156823d33999 12482 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
<> 149:156823d33999 12483 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
<> 149:156823d33999 12484
<> 149:156823d33999 12485 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
<> 149:156823d33999 12486 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
<> 149:156823d33999 12487
<> 149:156823d33999 12488 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
<> 149:156823d33999 12489 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
<> 149:156823d33999 12490
<> 149:156823d33999 12491 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
<> 149:156823d33999 12492 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
<> 149:156823d33999 12493
<> 149:156823d33999 12494 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
<> 149:156823d33999 12495 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
<> 149:156823d33999 12496
<> 149:156823d33999 12497 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
<> 149:156823d33999 12498 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
<> 149:156823d33999 12499
<> 149:156823d33999 12500 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
<> 149:156823d33999 12501 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
<> 149:156823d33999 12502
<> 149:156823d33999 12503 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
<> 149:156823d33999 12504 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
<> 149:156823d33999 12505
<> 149:156823d33999 12506 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
<> 149:156823d33999 12507 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
<> 149:156823d33999 12508
<> 149:156823d33999 12509 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
<> 149:156823d33999 12510 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
<> 149:156823d33999 12511
<> 149:156823d33999 12512 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
<> 149:156823d33999 12513 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
<> 149:156823d33999 12514
<> 149:156823d33999 12515 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
<> 149:156823d33999 12516 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
<> 149:156823d33999 12517
<> 149:156823d33999 12518 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
<> 149:156823d33999 12519 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
<> 149:156823d33999 12520
<> 149:156823d33999 12521 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
<> 149:156823d33999 12522 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
<> 149:156823d33999 12523
<> 149:156823d33999 12524 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
<> 149:156823d33999 12525 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
<> 149:156823d33999 12526
<> 149:156823d33999 12527 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
<> 149:156823d33999 12528 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
<> 149:156823d33999 12529
<> 149:156823d33999 12530 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
<> 149:156823d33999 12531 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
<> 149:156823d33999 12532
<> 149:156823d33999 12533 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
<> 149:156823d33999 12534 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
<> 149:156823d33999 12535
<> 149:156823d33999 12536 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
<> 149:156823d33999 12537 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
<> 149:156823d33999 12538
<> 149:156823d33999 12539 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
<> 149:156823d33999 12540 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
<> 149:156823d33999 12541
<> 149:156823d33999 12542 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
<> 149:156823d33999 12543 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
<> 149:156823d33999 12544
<> 149:156823d33999 12545 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
<> 149:156823d33999 12546 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
<> 149:156823d33999 12547
<> 149:156823d33999 12548 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
<> 149:156823d33999 12549 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
<> 149:156823d33999 12550
<> 149:156823d33999 12551 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
<> 149:156823d33999 12552 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
<> 149:156823d33999 12553
<> 149:156823d33999 12554 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
<> 149:156823d33999 12555 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
<> 149:156823d33999 12556
<> 149:156823d33999 12557 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
<> 149:156823d33999 12558 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
<> 149:156823d33999 12559
<> 149:156823d33999 12560 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
<> 149:156823d33999 12561 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
<> 149:156823d33999 12562
<> 149:156823d33999 12563 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
<> 149:156823d33999 12564 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
<> 149:156823d33999 12565
<> 149:156823d33999 12566 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
<> 149:156823d33999 12567 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
<> 149:156823d33999 12568
<> 149:156823d33999 12569 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
<> 149:156823d33999 12570 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
<> 149:156823d33999 12571
<> 149:156823d33999 12572 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
<> 149:156823d33999 12573 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
<> 149:156823d33999 12574
<> 149:156823d33999 12575 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
<> 149:156823d33999 12576 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
<> 149:156823d33999 12577
<> 149:156823d33999 12578 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
<> 149:156823d33999 12579 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
<> 149:156823d33999 12580
<> 149:156823d33999 12581 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
<> 149:156823d33999 12582 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
<> 149:156823d33999 12583
<> 149:156823d33999 12584 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
<> 149:156823d33999 12585 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
<> 149:156823d33999 12586
<> 149:156823d33999 12587 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
<> 149:156823d33999 12588 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
<> 149:156823d33999 12589
<> 149:156823d33999 12590 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
<> 149:156823d33999 12591 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
<> 149:156823d33999 12592
<> 149:156823d33999 12593 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
<> 149:156823d33999 12594 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
<> 149:156823d33999 12595
<> 149:156823d33999 12596 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
<> 149:156823d33999 12597 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
<> 149:156823d33999 12598
<> 149:156823d33999 12599 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
<> 149:156823d33999 12600 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
<> 149:156823d33999 12601
<> 149:156823d33999 12602 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
<> 149:156823d33999 12603 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
<> 149:156823d33999 12604
<> 149:156823d33999 12605 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
<> 149:156823d33999 12606 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
<> 149:156823d33999 12607
<> 149:156823d33999 12608 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
<> 149:156823d33999 12609 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
<> 149:156823d33999 12610
<> 149:156823d33999 12611 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
<> 149:156823d33999 12612 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
<> 149:156823d33999 12613
<> 149:156823d33999 12614 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
<> 149:156823d33999 12615 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
<> 149:156823d33999 12616
<> 149:156823d33999 12617 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
<> 149:156823d33999 12618 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
<> 149:156823d33999 12619
<> 149:156823d33999 12620 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
<> 149:156823d33999 12621 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
<> 149:156823d33999 12622
<> 149:156823d33999 12623 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
<> 149:156823d33999 12624 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
<> 149:156823d33999 12625
<> 149:156823d33999 12626 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
<> 149:156823d33999 12627 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
<> 149:156823d33999 12628
<> 149:156823d33999 12629 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
<> 149:156823d33999 12630 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
<> 149:156823d33999 12631
<> 149:156823d33999 12632 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
<> 149:156823d33999 12633 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
<> 149:156823d33999 12634
<> 149:156823d33999 12635 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
<> 149:156823d33999 12636 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
<> 149:156823d33999 12637
<> 149:156823d33999 12638 #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
<> 149:156823d33999 12639 #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
<> 149:156823d33999 12640
<> 149:156823d33999 12641 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
<> 149:156823d33999 12642 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
<> 149:156823d33999 12643
<> 149:156823d33999 12644 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position */
<> 149:156823d33999 12645 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
<> 149:156823d33999 12646
<> 149:156823d33999 12647 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position */
<> 149:156823d33999 12648 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
<> 149:156823d33999 12649
<> 149:156823d33999 12650 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
<> 149:156823d33999 12651 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
<> 149:156823d33999 12652
<> 149:156823d33999 12653 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
<> 149:156823d33999 12654 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
<> 149:156823d33999 12655
<> 149:156823d33999 12656 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
<> 149:156823d33999 12657 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
<> 149:156823d33999 12658
<> 149:156823d33999 12659 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
<> 149:156823d33999 12660 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
<> 149:156823d33999 12661
<> 149:156823d33999 12662 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
<> 149:156823d33999 12663 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
<> 149:156823d33999 12664
<> 149:156823d33999 12665 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
<> 149:156823d33999 12666 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
<> 149:156823d33999 12667
<> 149:156823d33999 12668 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
<> 149:156823d33999 12669 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
<> 149:156823d33999 12670
<> 149:156823d33999 12671 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
<> 149:156823d33999 12672 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
<> 149:156823d33999 12673
<> 149:156823d33999 12674 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
<> 149:156823d33999 12675 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
<> 149:156823d33999 12676
<> 149:156823d33999 12677 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
<> 149:156823d33999 12678 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
<> 149:156823d33999 12679
<> 149:156823d33999 12680 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
<> 149:156823d33999 12681 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
<> 149:156823d33999 12682
<> 149:156823d33999 12683 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
<> 149:156823d33999 12684 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
<> 149:156823d33999 12685
<> 149:156823d33999 12686 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
<> 149:156823d33999 12687 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
<> 149:156823d33999 12688
<> 149:156823d33999 12689 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
<> 149:156823d33999 12690 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
<> 149:156823d33999 12691
<> 149:156823d33999 12692 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
<> 149:156823d33999 12693 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
<> 149:156823d33999 12694
<> 149:156823d33999 12695 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
<> 149:156823d33999 12696 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
<> 149:156823d33999 12697
<> 149:156823d33999 12698 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
<> 149:156823d33999 12699 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
<> 149:156823d33999 12700
<> 149:156823d33999 12701 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
<> 149:156823d33999 12702 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
<> 149:156823d33999 12703
<> 149:156823d33999 12704 /**@}*/ /* SYS_CONST */
<> 149:156823d33999 12705
<> 149:156823d33999 12706
<> 149:156823d33999 12707 typedef struct
<> 149:156823d33999 12708 {
<> 149:156823d33999 12709
<> 149:156823d33999 12710 /**
<> 149:156823d33999 12711 * @var SYS_INT_T::NMIEN
<> 149:156823d33999 12712 * Offset: 0x00 NMI Source Interrupt Enable Register
<> 149:156823d33999 12713 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12714 * |Bits |Field |Descriptions
<> 149:156823d33999 12715 * | :----: | :----: | :---- |
<> 149:156823d33999 12716 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
<> 149:156823d33999 12717 * | | |0 = BOD NMI source Disabled.
<> 149:156823d33999 12718 * | | |1 = BOD NMI source Enabled.
<> 149:156823d33999 12719 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12720 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
<> 149:156823d33999 12721 * | | |0 = IRC TRIM NMI source Disabled.
<> 149:156823d33999 12722 * | | |1 = IRC TRIM NMI source Enabled.
<> 149:156823d33999 12723 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12724 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
<> 149:156823d33999 12725 * | | |0 = Power-down mode wake-up NMI source Disabled.
<> 149:156823d33999 12726 * | | |1 = Power-down mode wake-up NMI source Enabled.
<> 149:156823d33999 12727 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12728 * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect)
<> 149:156823d33999 12729 * | | |0 = SRAM parity check error NMI source Disabled.
<> 149:156823d33999 12730 * | | |1 = SRAM parity check error NMI source Enabled.
<> 149:156823d33999 12731 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12732 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)
<> 149:156823d33999 12733 * | | |0 = Clock fail detected interrupt NMI source Disabled.
<> 149:156823d33999 12734 * | | |1 = Clock fail detected interrupt NMI source Enabled.
<> 149:156823d33999 12735 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12736 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
<> 149:156823d33999 12737 * | | |0 = RTC NMI source Disabled.
<> 149:156823d33999 12738 * | | |1 = RTC NMI source Enabled.
<> 149:156823d33999 12739 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12740 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
<> 149:156823d33999 12741 * | | |0 = Backup register tamper detected interrupt.NMI source Disabled.
<> 149:156823d33999 12742 * | | |1 = Backup register tamper detected interrupt.NMI source Enabled.
<> 149:156823d33999 12743 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12744 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12745 * | | |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
<> 149:156823d33999 12746 * | | |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
<> 149:156823d33999 12747 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12748 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12749 * | | |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
<> 149:156823d33999 12750 * | | |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
<> 149:156823d33999 12751 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12752 * |[10] |EINT2 |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12753 * | | |0 = External interrupt from PC.0 pin NMI source Disabled.
<> 149:156823d33999 12754 * | | |1 = External interrupt from PC.0 pin NMI source Enabled.
<> 149:156823d33999 12755 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12756 * |[11] |EINT3 |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12757 * | | |0 = External interrupt from PD.0 pin NMI source Disabled.
<> 149:156823d33999 12758 * | | |1 = External interrupt from PD.0 pin NMI source Enabled.
<> 149:156823d33999 12759 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12760 * |[12] |EINT4 |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12761 * | | |0 = External interrupt from PE.0 pin NMI source Disabled.
<> 149:156823d33999 12762 * | | |1 = External interrupt from PE.0 pin NMI source Enabled.
<> 149:156823d33999 12763 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12764 * |[13] |EINT5 |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
<> 149:156823d33999 12765 * | | |0 = External interrupt from PF.0 pin NMI source Disabled.
<> 149:156823d33999 12766 * | | |1 = External interrupt from PF.0 pin NMI source Enabled.
<> 149:156823d33999 12767 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12768 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
<> 149:156823d33999 12769 * | | |0 = UART0 NMI source Disabled.
<> 149:156823d33999 12770 * | | |1 = UART0 NMI source Enabled.
<> 149:156823d33999 12771 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12772 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
<> 149:156823d33999 12773 * | | |0 = UART1 NMI source Disabled.
<> 149:156823d33999 12774 * | | |1 = UART1 NMI source Enabled.
<> 149:156823d33999 12775 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 12776 * @var SYS_INT_T::NMISTS
<> 149:156823d33999 12777 * Offset: 0x04 NMI source interrupt Status Register
<> 149:156823d33999 12778 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12779 * |Bits |Field |Descriptions
<> 149:156823d33999 12780 * | :----: | :----: | :---- |
<> 149:156823d33999 12781 * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
<> 149:156823d33999 12782 * | | |0 = BOD interrupt is deasserted.
<> 149:156823d33999 12783 * | | |1 = BOD interrupt is asserted.
<> 149:156823d33999 12784 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
<> 149:156823d33999 12785 * | | |0 = HIRC TRIM interrupt is deasserted.
<> 149:156823d33999 12786 * | | |1 = HIRC TRIM interrupt is asserted.
<> 149:156823d33999 12787 * |[2] |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
<> 149:156823d33999 12788 * | | |0 = Power-down mode wake-up interrupt is deasserted.
<> 149:156823d33999 12789 * | | |1 = Power-down mode wake-up interrupt is asserted.
<> 149:156823d33999 12790 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
<> 149:156823d33999 12791 * | | |0 = SRAM parity check error interrupt is deasserted.
<> 149:156823d33999 12792 * | | |1 = SRAM parity check error interrupt is asserted.
<> 149:156823d33999 12793 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)
<> 149:156823d33999 12794 * | | |0 = Clock fail detected interrupt is deasserted.
<> 149:156823d33999 12795 * | | |1 = Clock fail detected interrupt is asserted.
<> 149:156823d33999 12796 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
<> 149:156823d33999 12797 * | | |0 = RTC interrupt is deasserted.
<> 149:156823d33999 12798 * | | |1 = RTC interrupt is asserted.
<> 149:156823d33999 12799 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
<> 149:156823d33999 12800 * | | |0 = Backup register tamper detected interrupt is deasserted.
<> 149:156823d33999 12801 * | | |1 = Backup register tamper detected interrupt is asserted.
<> 149:156823d33999 12802 * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12803 * | | |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
<> 149:156823d33999 12804 * | | |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
<> 149:156823d33999 12805 * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12806 * | | |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
<> 149:156823d33999 12807 * | | |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
<> 149:156823d33999 12808 * |[10] |EINT2 |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12809 * | | |0 = External Interrupt from PC.0 interrupt is deasserted.
<> 149:156823d33999 12810 * | | |1 = External Interrupt from PC.0 interrupt is asserted.
<> 149:156823d33999 12811 * |[11] |EINT3 |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12812 * | | |0 = External Interrupt from PD.0 interrupt is deasserted.
<> 149:156823d33999 12813 * | | |1 = External Interrupt from PD.0 interrupt is asserted.
<> 149:156823d33999 12814 * |[12] |EINT4 |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12815 * | | |0 = External Interrupt from PE.0 interrupt is deasserted.
<> 149:156823d33999 12816 * | | |1 = External Interrupt from PE.0 interrupt is asserted.
<> 149:156823d33999 12817 * |[13] |EINT5 |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
<> 149:156823d33999 12818 * | | |0 = External Interrupt from PF.0 interrupt is deasserted.
<> 149:156823d33999 12819 * | | |1 = External Interrupt from PF.0 interrupt is asserted.
<> 149:156823d33999 12820 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
<> 149:156823d33999 12821 * | | |0 = UART1 interrupt is deasserted.
<> 149:156823d33999 12822 * | | |1 = UART1 interrupt is asserted.
<> 149:156823d33999 12823 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
<> 149:156823d33999 12824 * | | |0 = UART1 interrupt is deasserted.
<> 149:156823d33999 12825 * | | |1 = UART1 interrupt is asserted.
<> 149:156823d33999 12826 */
<> 149:156823d33999 12827
<> 149:156823d33999 12828 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
<> 149:156823d33999 12829 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
<> 149:156823d33999 12830
<> 149:156823d33999 12831 } SYS_INT_T;
<> 149:156823d33999 12832
<> 149:156823d33999 12833
<> 149:156823d33999 12834
<> 149:156823d33999 12835 /**
<> 149:156823d33999 12836 @addtogroup INT_CONST INT Bit Field Definition
<> 149:156823d33999 12837 Constant Definitions for SYS Controller
<> 149:156823d33999 12838 @{ */
<> 149:156823d33999 12839
<> 149:156823d33999 12840 #define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */
<> 149:156823d33999 12841 #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */
<> 149:156823d33999 12842
<> 149:156823d33999 12843 #define SYS_NMIEN_IRC_INT_Pos (1) /*!< SYS_INT_T::NMIEN: IRC_INT Position */
<> 149:156823d33999 12844 #define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) /*!< SYS_INT_T::NMIEN: IRC_INT Mask */
<> 149:156823d33999 12845
<> 149:156823d33999 12846 #define SYS_NMIEN_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWU_INT Position */
<> 149:156823d33999 12847 #define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask */
<> 149:156823d33999 12848
<> 149:156823d33999 12849 #define SYS_NMIEN_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAM_PERR Position */
<> 149:156823d33999 12850 #define SYS_NMIEN_SRAM_PERR_Msk (0x1ul << SYS_NMIEN_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask */
<> 149:156823d33999 12851
<> 149:156823d33999 12852 #define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */
<> 149:156823d33999 12853 #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */
<> 149:156823d33999 12854
<> 149:156823d33999 12855 #define SYS_NMIEN_RTC_INT_Pos (6) /*!< SYS_INT_T::NMIEN: RTC_INT Position */
<> 149:156823d33999 12856 #define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) /*!< SYS_INT_T::NMIEN: RTC_INT Mask */
<> 149:156823d33999 12857
<> 149:156823d33999 12858 #define SYS_NMIEN_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPER_INT Position */
<> 149:156823d33999 12859 #define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask */
<> 149:156823d33999 12860
<> 149:156823d33999 12861 #define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */
<> 149:156823d33999 12862 #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */
<> 149:156823d33999 12863
<> 149:156823d33999 12864 #define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */
<> 149:156823d33999 12865 #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */
<> 149:156823d33999 12866
<> 149:156823d33999 12867 #define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */
<> 149:156823d33999 12868 #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */
<> 149:156823d33999 12869
<> 149:156823d33999 12870 #define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */
<> 149:156823d33999 12871 #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */
<> 149:156823d33999 12872
<> 149:156823d33999 12873 #define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */
<> 149:156823d33999 12874 #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */
<> 149:156823d33999 12875
<> 149:156823d33999 12876 #define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */
<> 149:156823d33999 12877 #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */
<> 149:156823d33999 12878
<> 149:156823d33999 12879 #define SYS_NMIEN_UART0_INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0_INT Position */
<> 149:156823d33999 12880 #define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0_INT Mask */
<> 149:156823d33999 12881
<> 149:156823d33999 12882 #define SYS_NMIEN_UART1_INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1_INT Position */
<> 149:156823d33999 12883 #define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1_INT Mask */
<> 149:156823d33999 12884
<> 149:156823d33999 12885 #define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */
<> 149:156823d33999 12886 #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */
<> 149:156823d33999 12887
<> 149:156823d33999 12888 #define SYS_NMISTS_IRC_INT_Pos (1) /*!< SYS_INT_T::NMISTS: IRC_INT Position */
<> 149:156823d33999 12889 #define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) /*!< SYS_INT_T::NMISTS: IRC_INT Mask */
<> 149:156823d33999 12890
<> 149:156823d33999 12891 #define SYS_NMISTS_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWU_INT Position */
<> 149:156823d33999 12892 #define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask */
<> 149:156823d33999 12893
<> 149:156823d33999 12894 #define SYS_NMISTS_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAM_PERR Position */
<> 149:156823d33999 12895 #define SYS_NMISTS_SRAM_PERR_Msk (0x1ul << SYS_NMISTS_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask */
<> 149:156823d33999 12896
<> 149:156823d33999 12897 #define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */
<> 149:156823d33999 12898 #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */
<> 149:156823d33999 12899
<> 149:156823d33999 12900 #define SYS_NMISTS_RTC_INT_Pos (6) /*!< SYS_INT_T::NMISTS: RTC_INT Position */
<> 149:156823d33999 12901 #define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) /*!< SYS_INT_T::NMISTS: RTC_INT Mask */
<> 149:156823d33999 12902
<> 149:156823d33999 12903 #define SYS_NMISTS_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPER_INT Position */
<> 149:156823d33999 12904 #define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask */
<> 149:156823d33999 12905
<> 149:156823d33999 12906 #define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */
<> 149:156823d33999 12907 #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */
<> 149:156823d33999 12908
<> 149:156823d33999 12909 #define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */
<> 149:156823d33999 12910 #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */
<> 149:156823d33999 12911
<> 149:156823d33999 12912 #define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */
<> 149:156823d33999 12913 #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */
<> 149:156823d33999 12914
<> 149:156823d33999 12915 #define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */
<> 149:156823d33999 12916 #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */
<> 149:156823d33999 12917
<> 149:156823d33999 12918 #define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */
<> 149:156823d33999 12919 #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */
<> 149:156823d33999 12920
<> 149:156823d33999 12921 #define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */
<> 149:156823d33999 12922 #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */
<> 149:156823d33999 12923
<> 149:156823d33999 12924 #define SYS_NMISTS_UART0_INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */
<> 149:156823d33999 12925 #define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */
<> 149:156823d33999 12926
<> 149:156823d33999 12927 #define SYS_NMISTS_UART1_INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */
<> 149:156823d33999 12928 #define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */
<> 149:156823d33999 12929
<> 149:156823d33999 12930 /**@}*/ /* INT_CONST */
<> 149:156823d33999 12931 /**@}*/ /* end of SYS register group */
<> 149:156823d33999 12932
<> 149:156823d33999 12933
<> 149:156823d33999 12934 /*---------------------- Touch Key Controller -------------------------*/
<> 149:156823d33999 12935 /**
<> 149:156823d33999 12936 @addtogroup TK Touch Key Controller(TK)
<> 149:156823d33999 12937 Memory Mapped Structure for TK Controller
<> 149:156823d33999 12938 @{ */
<> 149:156823d33999 12939
<> 149:156823d33999 12940
<> 149:156823d33999 12941 typedef struct
<> 149:156823d33999 12942 {
<> 149:156823d33999 12943
<> 149:156823d33999 12944
<> 149:156823d33999 12945 /**
<> 149:156823d33999 12946 * @var TK_T::CTL
<> 149:156823d33999 12947 * Offset: 0x00 Touch Key Scan Control Register
<> 149:156823d33999 12948 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 12949 * |Bits |Field |Descriptions
<> 149:156823d33999 12950 * | :----: | :----: | :---- |
<> 149:156823d33999 12951 * |[0] |TKSEN0 |TK0 Scan Enable Bit
<> 149:156823d33999 12952 * | | |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
<> 149:156823d33999 12953 * | | |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
<> 149:156823d33999 12954 * | | |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
<> 149:156823d33999 12955 * |[1] |TKSEN1 |TK1 Scan Enable Bit
<> 149:156823d33999 12956 * | | |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
<> 149:156823d33999 12957 * | | |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
<> 149:156823d33999 12958 * | | |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
<> 149:156823d33999 12959 * |[2] |TKSEN2 |TK2 Scan Enable Bit
<> 149:156823d33999 12960 * | | |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
<> 149:156823d33999 12961 * | | |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
<> 149:156823d33999 12962 * | | |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
<> 149:156823d33999 12963 * |[3] |TKSEN3 |TK3 Scan Enable Bit
<> 149:156823d33999 12964 * | | |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
<> 149:156823d33999 12965 * | | |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
<> 149:156823d33999 12966 * | | |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
<> 149:156823d33999 12967 * |[4] |TKSEN4 |TK4 Scan Enable Bit
<> 149:156823d33999 12968 * | | |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
<> 149:156823d33999 12969 * | | |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
<> 149:156823d33999 12970 * | | |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
<> 149:156823d33999 12971 * |[5] |TKSEN5 |TK5 Scan Enable Bit
<> 149:156823d33999 12972 * | | |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
<> 149:156823d33999 12973 * | | |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
<> 149:156823d33999 12974 * | | |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
<> 149:156823d33999 12975 * |[6] |TKSEN6 |TK6 Scan Enable Bit
<> 149:156823d33999 12976 * | | |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
<> 149:156823d33999 12977 * | | |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
<> 149:156823d33999 12978 * | | |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
<> 149:156823d33999 12979 * |[7] |TKSEN7 |TK7 Scan Enable
<> 149:156823d33999 12980 * | | |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
<> 149:156823d33999 12981 * | | |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
<> 149:156823d33999 12982 * | | |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
<> 149:156823d33999 12983 * |[8] |TKSEN8 |TK8 Scan Enable Bit
<> 149:156823d33999 12984 * | | |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
<> 149:156823d33999 12985 * | | |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
<> 149:156823d33999 12986 * | | |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
<> 149:156823d33999 12987 * |[9] |TKSEN9 |TK9 Scan Enable Bit
<> 149:156823d33999 12988 * | | |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
<> 149:156823d33999 12989 * | | |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
<> 149:156823d33999 12990 * | | |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
<> 149:156823d33999 12991 * |[10] |TKSEN10 |TK10 Scan Enable Bit
<> 149:156823d33999 12992 * | | |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
<> 149:156823d33999 12993 * | | |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
<> 149:156823d33999 12994 * | | |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
<> 149:156823d33999 12995 * |[11] |TKSEN11 |TK11 Scan Enable
<> 149:156823d33999 12996 * | | |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
<> 149:156823d33999 12997 * | | |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
<> 149:156823d33999 12998 * | | |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
<> 149:156823d33999 12999 * |[12] |TKSEN12 |TK12 Scan Enable Bit
<> 149:156823d33999 13000 * | | |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
<> 149:156823d33999 13001 * | | |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
<> 149:156823d33999 13002 * | | |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
<> 149:156823d33999 13003 * |[13] |TKSEN13 |TK13 Scan Enable Bit
<> 149:156823d33999 13004 * | | |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
<> 149:156823d33999 13005 * | | |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
<> 149:156823d33999 13006 * | | |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
<> 149:156823d33999 13007 * |[14] |TKSEN14 |TK14 Scan Enable Bit
<> 149:156823d33999 13008 * | | |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
<> 149:156823d33999 13009 * | | |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
<> 149:156823d33999 13010 * | | |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
<> 149:156823d33999 13011 * |[15] |TKSEN15 |TK15 Scan Enable Bit
<> 149:156823d33999 13012 * | | |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
<> 149:156823d33999 13013 * | | |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
<> 149:156823d33999 13014 * | | |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
<> 149:156823d33999 13015 * |[16] |TKSEN16 |TK16 Scan Enable Bit
<> 149:156823d33999 13016 * | | |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
<> 149:156823d33999 13017 * | | |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
<> 149:156823d33999 13018 * | | |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
<> 149:156823d33999 13019 * |[22:20] |AVCCHSEL |AVCCH Voltage Select
<> 149:156823d33999 13020 * | | |000 = 1/16 VDD.
<> 149:156823d33999 13021 * | | |001 = 1/8 VDD.
<> 149:156823d33999 13022 * | | |010 = 3/16 VDD.
<> 149:156823d33999 13023 * | | |011 = 1/4 VDD.
<> 149:156823d33999 13024 * | | |100 = 5/16 VDD.
<> 149:156823d33999 13025 * | | |101 = 3/8 VDD.
<> 149:156823d33999 13026 * | | |110 = 7/16 VDD.
<> 149:156823d33999 13027 * | | |111 = 1/2 VDD.
<> 149:156823d33999 13028 * |[24] |SCAN |Scan
<> 149:156823d33999 13029 * | | |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
<> 149:156823d33999 13030 * | | |This bit will be self-cleared after key scan started.
<> 149:156823d33999 13031 * |[25] |TMRTRGEN |Timer Trigger Enable Bit
<> 149:156823d33999 13032 * | | |0 = Disable timer to trigger key scan.
<> 149:156823d33999 13033 * | | |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
<> 149:156823d33999 13034 * |[31] |TKEN |Touch Key Scan Enable Bit
<> 149:156823d33999 13035 * | | |0 = Disable Touch Key Function.
<> 149:156823d33999 13036 * | | |1 = Enable Touch Key Function.
<> 149:156823d33999 13037 * @var TK_T::REFCTL
<> 149:156823d33999 13038 * Offset: 0x04 Touch Key Reference Control Register
<> 149:156823d33999 13039 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13040 * |Bits |Field |Descriptions
<> 149:156823d33999 13041 * | :----: | :----: | :---- |
<> 149:156823d33999 13042 * |[0] |TKREN0 |TK0 Reference Enable Bit
<> 149:156823d33999 13043 * | | |0 = TK0 is not reference.
<> 149:156823d33999 13044 * | | |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
<> 149:156823d33999 13045 * |[1] |TKREN1 |TK1 Reference Enable Bit
<> 149:156823d33999 13046 * | | |0 = TK1 is not reference.
<> 149:156823d33999 13047 * | | |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
<> 149:156823d33999 13048 * |[2] |TKREN2 |TK2 Reference Enable Bit
<> 149:156823d33999 13049 * | | |0 = TK2 is not reference.
<> 149:156823d33999 13050 * | | |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
<> 149:156823d33999 13051 * |[3] |TKREN3 |TK3 Reference Enable Bit
<> 149:156823d33999 13052 * | | |0 = TK3 is not reference.
<> 149:156823d33999 13053 * | | |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
<> 149:156823d33999 13054 * |[4] |TKREN4 |TK4 Reference Enable Bit
<> 149:156823d33999 13055 * | | |0 = TK4 is not reference.
<> 149:156823d33999 13056 * | | |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
<> 149:156823d33999 13057 * |[5] |TKREN5 |TK5 Reference Enable Bit
<> 149:156823d33999 13058 * | | |0 = TK5 is not reference.
<> 149:156823d33999 13059 * | | |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
<> 149:156823d33999 13060 * |[6] |TKREN6 |TK6 Reference Enable Bit
<> 149:156823d33999 13061 * | | |0 = TK6 is not reference.
<> 149:156823d33999 13062 * | | |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
<> 149:156823d33999 13063 * |[7] |TKREN7 |TK7 Reference Enable Bit
<> 149:156823d33999 13064 * | | |0 = TK7 is not reference.
<> 149:156823d33999 13065 * | | |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
<> 149:156823d33999 13066 * |[8] |TKREN8 |TK8 Reference Enable Bit
<> 149:156823d33999 13067 * | | |0 = TK8 is not reference.
<> 149:156823d33999 13068 * | | |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
<> 149:156823d33999 13069 * |[9] |TKREN9 |TK9 Reference Enable Bit
<> 149:156823d33999 13070 * | | |0 = TK9 is not reference.
<> 149:156823d33999 13071 * | | |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
<> 149:156823d33999 13072 * |[10] |TKREN10 |TK10 Reference Enable Bit
<> 149:156823d33999 13073 * | | |0 = TK10 is not reference.
<> 149:156823d33999 13074 * | | |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
<> 149:156823d33999 13075 * |[11] |TKREN11 |TK11 Reference Enable Bit
<> 149:156823d33999 13076 * | | |0 = TK11 is not reference.
<> 149:156823d33999 13077 * | | |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
<> 149:156823d33999 13078 * |[12] |TKREN12 |TK12 Reference Enable Bit
<> 149:156823d33999 13079 * | | |0 = TK12 is not reference.
<> 149:156823d33999 13080 * | | |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
<> 149:156823d33999 13081 * |[13] |TKREN13 |TK13 Reference Enable Bit
<> 149:156823d33999 13082 * | | |0 = TK13 is not reference.
<> 149:156823d33999 13083 * | | |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
<> 149:156823d33999 13084 * |[14] |TKREN14 |TK14 Reference Enable Bit
<> 149:156823d33999 13085 * | | |0 = TK14 is not reference.
<> 149:156823d33999 13086 * | | |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
<> 149:156823d33999 13087 * |[15] |TKREN15 |TK15 Reference Enable Bit
<> 149:156823d33999 13088 * | | |0 = TK15 is not reference.
<> 149:156823d33999 13089 * | | |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
<> 149:156823d33999 13090 * |[16] |TKREN16 |TK16 Reference Enable Bit
<> 149:156823d33999 13091 * | | |0 = TK16 is not reference.
<> 149:156823d33999 13092 * | | |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
<> 149:156823d33999 13093 * | | |Note: This bit is forced to "1" automatically if none is set as reference.
<> 149:156823d33999 13094 * |[23] |SCANALL |All Key Scan Enable Bit
<> 149:156823d33999 13095 * | | |This function is used for low power key scanning operation.
<> 149:156823d33999 13096 * | | |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
<> 149:156823d33999 13097 * | | |0 = Disable All Keys Scan function.
<> 149:156823d33999 13098 * | | |1 = Enable All Keys Scan function.
<> 149:156823d33999 13099 * |[25:24] |SENTCTL |Touch Key Sensing Time Control
<> 149:156823d33999 13100 * | | |00 = 128 x SENPTCTL.
<> 149:156823d33999 13101 * | | |01 = 255 x SENPTCTL.
<> 149:156823d33999 13102 * | | |10 = 511 x SENPTCTL.
<> 149:156823d33999 13103 * | | |11 = 1023 x SENPTCTL.
<> 149:156823d33999 13104 * |[29:28] |SENPTCTL |Touch Key Sensing Pulse Width Time Control
<> 149:156823d33999 13105 * | | |00 = 1us.
<> 149:156823d33999 13106 * | | |01 = 2us.
<> 149:156823d33999 13107 * | | |10 = 4us.
<> 149:156823d33999 13108 * | | |11 = 8us.
<> 149:156823d33999 13109 * @var TK_T::CCBDAT0
<> 149:156823d33999 13110 * Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0
<> 149:156823d33999 13111 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13112 * |Bits |Field |Descriptions
<> 149:156823d33999 13113 * | :----: | :----: | :---- |
<> 149:156823d33999 13114 * |[7:0] |CCBDAT0 |TK0 Complement CB Data
<> 149:156823d33999 13115 * | | |This is register is used for TK0 sensitivity adjustment.
<> 149:156823d33999 13116 * |[15:8] |CCBDAT1 |TK1 Complement CB Data
<> 149:156823d33999 13117 * | | |This is register is used for TK1 sensitivity adjustment.
<> 149:156823d33999 13118 * |[23:16] |CCBDAT2 |TK2 Complement CB Data
<> 149:156823d33999 13119 * | | |This is register is used for TK2 sensitivity adjustment.
<> 149:156823d33999 13120 * |[31:24] |CCBDAT3 |TK3 Complement CB Data
<> 149:156823d33999 13121 * | | |This is register is used for TK3 sensitivity adjustment.
<> 149:156823d33999 13122 * @var TK_T::CCBDAT1
<> 149:156823d33999 13123 * Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1
<> 149:156823d33999 13124 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13125 * |Bits |Field |Descriptions
<> 149:156823d33999 13126 * | :----: | :----: | :---- |
<> 149:156823d33999 13127 * |[7:0] |CCBDAT4 |TK4 Complement CB Data
<> 149:156823d33999 13128 * | | |This is register is used for TK4 sensitivity adjustment.
<> 149:156823d33999 13129 * |[15:8] |CCBDAT5 |TK5 Complement CB Data
<> 149:156823d33999 13130 * | | |This is register is used for TK5 sensitivity adjustment.
<> 149:156823d33999 13131 * |[23:16] |CCBDAT6 |TK6 Complement CB Data
<> 149:156823d33999 13132 * | | |This is register is used for TK6 sensitivity adjustment.
<> 149:156823d33999 13133 * |[31:24] |CCBDAT7 |TK7 Complement CB Data
<> 149:156823d33999 13134 * | | |This is register is used for TK7 sensitivity adjustment.
<> 149:156823d33999 13135 * @var TK_T::CCBDAT2
<> 149:156823d33999 13136 * Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2
<> 149:156823d33999 13137 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13138 * |Bits |Field |Descriptions
<> 149:156823d33999 13139 * | :----: | :----: | :---- |
<> 149:156823d33999 13140 * |[7:0] |CCBDAT8 |TK8 Complement CB Data
<> 149:156823d33999 13141 * | | |This is register is used for TK8 sensitivity adjustment.
<> 149:156823d33999 13142 * |[15:8] |CCBDAT9 |TK9 Complement CB Data
<> 149:156823d33999 13143 * | | |This is register is used for TK9 sensitivity adjustment.
<> 149:156823d33999 13144 * |[23:16] |CCBDAT10 |TK10 Complement CB Data
<> 149:156823d33999 13145 * | | |This is register is used for TK10 sensitivity adjustment.
<> 149:156823d33999 13146 * |[31:24] |CCBDAT11 |TK11 Complement CB Data
<> 149:156823d33999 13147 * | | |This is register is used for TK11 sensitivity adjustment.
<> 149:156823d33999 13148 * @var TK_T::CCBDAT3
<> 149:156823d33999 13149 * Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3
<> 149:156823d33999 13150 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13151 * |Bits |Field |Descriptions
<> 149:156823d33999 13152 * | :----: | :----: | :---- |
<> 149:156823d33999 13153 * |[7:0] |CCBDAT12 |TK12 Complement CB Data
<> 149:156823d33999 13154 * | | |This is register is used for TK12 sensitivity adjustment.
<> 149:156823d33999 13155 * |[15:8] |CCBDAT13 |TK13 Complement CB Data
<> 149:156823d33999 13156 * | | |This is register is used for TK13 sensitivity adjustment.
<> 149:156823d33999 13157 * |[23:16] |CCBDAT14 |TK14 Complement CB Data
<> 149:156823d33999 13158 * | | |This is register is used for TK14 sensitivity adjustment.
<> 149:156823d33999 13159 * |[31:24] |CCBDAT15 |TK15 Complement CB Data
<> 149:156823d33999 13160 * | | |This is register is used for TK15 sensitivity adjustment.
<> 149:156823d33999 13161 * @var TK_T::CCBDAT4
<> 149:156823d33999 13162 * Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4
<> 149:156823d33999 13163 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13164 * |Bits |Field |Descriptions
<> 149:156823d33999 13165 * | :----: | :----: | :---- |
<> 149:156823d33999 13166 * |[7:0] |CCBDAT16 |TK16 Complement CB Data
<> 149:156823d33999 13167 * | | |This is register is used for TK16 sensitivity adjustment.
<> 149:156823d33999 13168 * |[31:24] |REFCBDAT |Reference CB Data
<> 149:156823d33999 13169 * @var TK_T::IDLESEL
<> 149:156823d33999 13170 * Offset: 0x1C Touch Key Idle State Control Register
<> 149:156823d33999 13171 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13172 * |Bits |Field |Descriptions
<> 149:156823d33999 13173 * | :----: | :----: | :---- |
<> 149:156823d33999 13174 * |[31:0] |IDLSn |TKn Idle State Control
<> 149:156823d33999 13175 * | | |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
<> 149:156823d33999 13176 * | | |00 = TKn connected to GND.
<> 149:156823d33999 13177 * | | |01 = TKn connected to AVCCH.
<> 149:156823d33999 13178 * | | |10 = TKn connected to VDD.
<> 149:156823d33999 13179 * | | |11 = TKn connected to VDD.
<> 149:156823d33999 13180 * | | |n = 0 to 15.
<> 149:156823d33999 13181 * @var TK_T::POLSEL
<> 149:156823d33999 13182 * Offset: 0x20 Touch Key Polarity Select Register
<> 149:156823d33999 13183 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13184 * |Bits |Field |Descriptions
<> 149:156823d33999 13185 * | :----: | :----: | :---- |
<> 149:156823d33999 13186 * |[31:0] |POLSELn |TKn Polarity Select
<> 149:156823d33999 13187 * | | |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
<> 149:156823d33999 13188 * | | |00 = TKn connected to Gnd.
<> 149:156823d33999 13189 * | | |01 = TKn connected to AVCCH.
<> 149:156823d33999 13190 * | | |10 = TKn connected to VDD.
<> 149:156823d33999 13191 * | | |11 = TKn connected to VDD.
<> 149:156823d33999 13192 * @var TK_T::POLCTL
<> 149:156823d33999 13193 * Offset: 0x24 Touch Key Polarity Control Register
<> 149:156823d33999 13194 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13195 * |Bits |Field |Descriptions
<> 149:156823d33999 13196 * | :----: | :----: | :---- |
<> 149:156823d33999 13197 * |[1:0] |IDLS16 |TK16 Idle State Control
<> 149:156823d33999 13198 * | | |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
<> 149:156823d33999 13199 * | | |00 = TK16 connected to Gnd.
<> 149:156823d33999 13200 * | | |01 = TK16 connected to AVCCH.
<> 149:156823d33999 13201 * | | |10 = TK16 connected to VDD.
<> 149:156823d33999 13202 * | | |11 = TK16 connected to VDD.
<> 149:156823d33999 13203 * |[3:2] |POLSEL16 |TK16 Polarity Control
<> 149:156823d33999 13204 * | | |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
<> 149:156823d33999 13205 * | | |00 = TK16 connected to Gnd.
<> 149:156823d33999 13206 * | | |01 = TK16 connected to AVCCH.
<> 149:156823d33999 13207 * | | |10 = TK16 connected to VDD.
<> 149:156823d33999 13208 * | | |11 = TK16 connected to VDD.
<> 149:156823d33999 13209 * |[5:4] |CBPOLSEL |Capacitor Bank Polarity Select
<> 149:156823d33999 13210 * | | |00 = Gnd.
<> 149:156823d33999 13211 * | | |01 = AVCCH.
<> 149:156823d33999 13212 * | | |10 = VDD.
<> 149:156823d33999 13213 * | | |11 = VDD.
<> 149:156823d33999 13214 * |[8] |POLEN0 |TK0 Polarity Function Enable Control
<> 149:156823d33999 13215 * | | |0 = Disabled.
<> 149:156823d33999 13216 * | | |1 = Enabled.
<> 149:156823d33999 13217 * |[9] |POLEN1 |TK1 Polarity Function Enable Control
<> 149:156823d33999 13218 * | | |0 = Disabled.
<> 149:156823d33999 13219 * | | |1 = Enabled.
<> 149:156823d33999 13220 * |[10] |POLEN2 |TK2 Polarity Function Enable Control
<> 149:156823d33999 13221 * | | |0 = Disabled.
<> 149:156823d33999 13222 * | | |1 = Enabled.
<> 149:156823d33999 13223 * |[11] |POLEN3 |TK3 Polarity Function Enable Control
<> 149:156823d33999 13224 * | | |0 = Disabled.
<> 149:156823d33999 13225 * | | |1 = Enabled.
<> 149:156823d33999 13226 * |[12] |POLEN4 |TK4 Polarity Function Enable Control
<> 149:156823d33999 13227 * | | |0 = Disabled.
<> 149:156823d33999 13228 * | | |1 = Enabled.
<> 149:156823d33999 13229 * |[13] |POLEN5 |TK5 Polarity Function Enable Control
<> 149:156823d33999 13230 * | | |0 = Disabled.
<> 149:156823d33999 13231 * | | |1 = Enabled.
<> 149:156823d33999 13232 * |[14] |POLEN6 |TK6 Polarity Function Enable Control
<> 149:156823d33999 13233 * | | |0 = Disabled.
<> 149:156823d33999 13234 * | | |1 = Enabled.
<> 149:156823d33999 13235 * |[15] |POLEN7 |TK7 Polarity Function Enable Control
<> 149:156823d33999 13236 * | | |0 = Disabled.
<> 149:156823d33999 13237 * | | |1 = Enabled.
<> 149:156823d33999 13238 * |[16] |POLEN8 |TK8 Polarity Function Enable Control
<> 149:156823d33999 13239 * | | |0 = Disabled.
<> 149:156823d33999 13240 * | | |1 = Enabled.
<> 149:156823d33999 13241 * |[17] |POLEN9 |TK9 Polarity Function Enable Control
<> 149:156823d33999 13242 * | | |0 = Disabled.
<> 149:156823d33999 13243 * | | |1 = Enabled.
<> 149:156823d33999 13244 * |[18] |POLEN10 |TK10 Polarity Function Enable Control
<> 149:156823d33999 13245 * | | |0 = Disabled.
<> 149:156823d33999 13246 * | | |1 = Enabled.
<> 149:156823d33999 13247 * |[19] |POLEN11 |TK11 Polarity Function Enable Control
<> 149:156823d33999 13248 * | | |0 = Disabled.
<> 149:156823d33999 13249 * | | |1 = Enabled.
<> 149:156823d33999 13250 * |[20] |POLEN12 |TK12 Polarity Function Enable Control
<> 149:156823d33999 13251 * | | |0 = Disabled.
<> 149:156823d33999 13252 * | | |1 = Enabled.
<> 149:156823d33999 13253 * |[21] |POLEN13 |TK13 Polarity Function Enable Control
<> 149:156823d33999 13254 * | | |0 = Disabled.
<> 149:156823d33999 13255 * | | |1 = Enabled.
<> 149:156823d33999 13256 * |[22] |POLEN14 |TK14 Polarity Function Enable Control
<> 149:156823d33999 13257 * | | |0 = Disabled.
<> 149:156823d33999 13258 * | | |1 = Enabled.
<> 149:156823d33999 13259 * |[23] |POLEN15 |TK15 Polarity Function Enable Control
<> 149:156823d33999 13260 * | | |0 = Disabled.
<> 149:156823d33999 13261 * | | |1 = Enabled.
<> 149:156823d33999 13262 * |[24] |POLEN16 |TK16 Polarity Function Enable Control
<> 149:156823d33999 13263 * | | |0 = Disabled.
<> 149:156823d33999 13264 * | | |1 = Enabled.
<> 149:156823d33999 13265 * |[31] |SPOTINIT |Touch Key Sensing Initial Potential Control
<> 149:156823d33999 13266 * | | |0 = Key pad is connected to Gnd before sensing.
<> 149:156823d33999 13267 * | | |1 = Key pad is connected to AVCCH before sensing.
<> 149:156823d33999 13268 * @var TK_T::STATUS
<> 149:156823d33999 13269 * Offset: 0x28 Touch Key Status Register
<> 149:156823d33999 13270 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13271 * |Bits |Field |Descriptions
<> 149:156823d33999 13272 * | :----: | :----: | :---- |
<> 149:156823d33999 13273 * |[0] |BUSY |Touch Key Busy (Read Only)
<> 149:156823d33999 13274 * | | |0 = Key scan is complete or stopped.
<> 149:156823d33999 13275 * | | |1 = Key scan is proceeding.
<> 149:156823d33999 13276 * |[1] |SCIF |Touch Key Scan Complete Interrupt Flag
<> 149:156823d33999 13277 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13278 * | | |0 = Key scan is proceeding and data is not ready for read.
<> 149:156823d33999 13279 * | | |1 = Key scan is complete and data is ready for read in TKDATx registers.
<> 149:156823d33999 13280 * | | |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
<> 149:156823d33999 13281 * | | |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
<> 149:156823d33999 13282 * |[8] |TKIF0 |TK0 Interrupt Flag
<> 149:156823d33999 13283 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13284 * | | |0 = No threshold control event with TK0.
<> 149:156823d33999 13285 * | | |1 = Threshold control event occurs with TK0.
<> 149:156823d33999 13286 * |[9] |TKIF1 |TK1 Interrupt Flag
<> 149:156823d33999 13287 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13288 * | | |0 = No threshold control event with TK1.
<> 149:156823d33999 13289 * | | |1 = Threshold control event occurs with TK1.
<> 149:156823d33999 13290 * |[10] |TKIF2 |TK2 Interrupt Flag
<> 149:156823d33999 13291 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13292 * | | |0 = No threshold control event with TK2.
<> 149:156823d33999 13293 * | | |1 = Threshold control event occurs with TK2.
<> 149:156823d33999 13294 * |[11] |TKIF3 |TK3 Interrupt Flag
<> 149:156823d33999 13295 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13296 * | | |0 = No threshold control event with TK3.
<> 149:156823d33999 13297 * | | |1 = Threshold control event occurs with TK3.
<> 149:156823d33999 13298 * |[12] |TKIF4 |TK4 Interrupt Flag
<> 149:156823d33999 13299 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13300 * | | |0 = No threshold control event with TK4.
<> 149:156823d33999 13301 * | | |1 = Threshold control event occurs with TK4.
<> 149:156823d33999 13302 * |[13] |TKIF5 |TK5 Interrupt Flag
<> 149:156823d33999 13303 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13304 * | | |0 = No threshold control event with TK5.
<> 149:156823d33999 13305 * | | |1 = Threshold control event occurs with TK5.
<> 149:156823d33999 13306 * |[14] |TKIF6 |TK6 Interrupt Flag
<> 149:156823d33999 13307 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13308 * | | |0 = No threshold control event with TK6.
<> 149:156823d33999 13309 * | | |1 = Threshold control event occurs with TK6.
<> 149:156823d33999 13310 * |[15] |TKIF7 |TK7 Interrupt Flag
<> 149:156823d33999 13311 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13312 * | | |0 = No threshold control event with TK7.
<> 149:156823d33999 13313 * | | |1 = Threshold control event occurs with TK7.
<> 149:156823d33999 13314 * |[16] |TKIF8 |TK8 Interrupt Flag
<> 149:156823d33999 13315 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13316 * | | |0 = No threshold control event with TK8.
<> 149:156823d33999 13317 * | | |1 = Threshold control event occurs with TK8.
<> 149:156823d33999 13318 * |[17] |TKIF9 |TK9 Interrupt Flag
<> 149:156823d33999 13319 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13320 * | | |0 = No threshold control event with TK9.
<> 149:156823d33999 13321 * | | |1 = Threshold control event occurs with TK9.
<> 149:156823d33999 13322 * |[18] |TKIF10 |TK10 Interrupt Flag
<> 149:156823d33999 13323 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13324 * | | |0 = No threshold control event with TK10.
<> 149:156823d33999 13325 * | | |1 = Threshold control event occurs with TK10.
<> 149:156823d33999 13326 * |[19] |TKIF11 |TK11 Interrupt Flag
<> 149:156823d33999 13327 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13328 * | | |0 = No threshold control event with TK11.
<> 149:156823d33999 13329 * | | |1 = Threshold control event occurs with TK11.
<> 149:156823d33999 13330 * |[20] |TKIF12 |TK12 Interrupt Flag
<> 149:156823d33999 13331 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13332 * | | |0 = No threshold control event with TK12.
<> 149:156823d33999 13333 * | | |1 = Threshold control event occurs with TK12.
<> 149:156823d33999 13334 * |[21] |TKIF13 |TK13 Interrupt Flag
<> 149:156823d33999 13335 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13336 * | | |0 = No threshold control event with TK13.
<> 149:156823d33999 13337 * | | |1 = Threshold control event occurs with TK13.
<> 149:156823d33999 13338 * |[22] |TKIF14 |TK14 Interrupt Flag
<> 149:156823d33999 13339 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13340 * | | |0 = No threshold control event with TK14.
<> 149:156823d33999 13341 * | | |1 = Threshold control event occurs with TK14.
<> 149:156823d33999 13342 * |[23] |TKIF15 |TK15 Interrupt Flag
<> 149:156823d33999 13343 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13344 * | | |0 = No threshold control event with TK15.
<> 149:156823d33999 13345 * | | |1 = Threshold control event occurs with TK15.
<> 149:156823d33999 13346 * |[24] |TKIF16 |TK16 Interrupt Flag
<> 149:156823d33999 13347 * | | |This bit will be cleared by writing a "1" to this bit.
<> 149:156823d33999 13348 * | | |0 = No threshold control event with TK16.
<> 149:156823d33999 13349 * | | |1 = Threshold control event occurs with TK16.
<> 149:156823d33999 13350 * @var TK_T::DAT0
<> 149:156823d33999 13351 * Offset: 0x2C Touch Key Data Register 0
<> 149:156823d33999 13352 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13353 * |Bits |Field |Descriptions
<> 149:156823d33999 13354 * | :----: | :----: | :---- |
<> 149:156823d33999 13355 * |[7:0] |TKDAT0 |TK0 Sensing Result Data (Read Only)
<> 149:156823d33999 13356 * | | |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
<> 149:156823d33999 13357 * |[15:8] |TKDAT1 |TK1 Sensing Result Data (Read Only)
<> 149:156823d33999 13358 * | | |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
<> 149:156823d33999 13359 * |[23:16] |TKDAT2 |TK2 Sensing Result Data (Read Only)
<> 149:156823d33999 13360 * | | |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
<> 149:156823d33999 13361 * |[31:24] |TKDAT3 |TK3 Sensing Result Data (Read Only)
<> 149:156823d33999 13362 * | | |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
<> 149:156823d33999 13363 * @var TK_T::DAT1
<> 149:156823d33999 13364 * Offset: 0x30 Touch Key Data Register 1
<> 149:156823d33999 13365 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13366 * |Bits |Field |Descriptions
<> 149:156823d33999 13367 * | :----: | :----: | :---- |
<> 149:156823d33999 13368 * |[7:0] |TKDAT4 |TK0 Sensing Result Data (Read Only)
<> 149:156823d33999 13369 * | | |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
<> 149:156823d33999 13370 * |[15:8] |TKDAT5 |TK5 Sensing Result Data (Read Only)
<> 149:156823d33999 13371 * | | |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
<> 149:156823d33999 13372 * |[23:16] |TKDAT6 |TK6 Sensing Result Data (Read Only)
<> 149:156823d33999 13373 * | | |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
<> 149:156823d33999 13374 * |[31:24] |TKDAT7 |TK7 Sensing Result Data (Read Only)
<> 149:156823d33999 13375 * | | |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
<> 149:156823d33999 13376 * @var TK_T::DAT2
<> 149:156823d33999 13377 * Offset: 0x34 Touch Key Data Register 2
<> 149:156823d33999 13378 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13379 * |Bits |Field |Descriptions
<> 149:156823d33999 13380 * | :----: | :----: | :---- |
<> 149:156823d33999 13381 * |[7:0] |TKDAT8 |TK8 Sensing Result Data (Read Only)
<> 149:156823d33999 13382 * | | |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
<> 149:156823d33999 13383 * |[15:8] |TKDAT9 |TK9 Sensing Result Data (Read Only)
<> 149:156823d33999 13384 * | | |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
<> 149:156823d33999 13385 * |[23:16] |TKDAT10 |TK10 Sensing Result Data (Read Only)
<> 149:156823d33999 13386 * | | |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
<> 149:156823d33999 13387 * |[31:24] |TKDAT11 |TK11 Sensing Result Data (Read Only)
<> 149:156823d33999 13388 * | | |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
<> 149:156823d33999 13389 * @var TK_T::DAT3
<> 149:156823d33999 13390 * Offset: 0x38 Touch Key Data Register 3
<> 149:156823d33999 13391 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13392 * |Bits |Field |Descriptions
<> 149:156823d33999 13393 * | :----: | :----: | :---- |
<> 149:156823d33999 13394 * |[7:0] |TKDAT12 |TK12 Sensing Result Data (Read Only)
<> 149:156823d33999 13395 * | | |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
<> 149:156823d33999 13396 * |[15:8] |TKDAT13 |TK13 Sensing Result Data (Read Only)
<> 149:156823d33999 13397 * | | |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
<> 149:156823d33999 13398 * |[23:16] |TKDAT14 |TK14 Sensing Result Data (Read Only)
<> 149:156823d33999 13399 * | | |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
<> 149:156823d33999 13400 * |[31:24] |TKDAT15 |TK15 Sensing Result Data (Read Only)
<> 149:156823d33999 13401 * | | |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
<> 149:156823d33999 13402 * @var TK_T::DAT4
<> 149:156823d33999 13403 * Offset: 0x3C Touch Key Data Register 4
<> 149:156823d33999 13404 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13405 * |Bits |Field |Descriptions
<> 149:156823d33999 13406 * | :----: | :----: | :---- |
<> 149:156823d33999 13407 * |[7:0] |TKDAT16 |TK16 Sensing Result Data (Read Only)
<> 149:156823d33999 13408 * | | |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
<> 149:156823d33999 13409 * @var TK_T::INTEN
<> 149:156823d33999 13410 * Offset: 0x40 Touch Key Interrupt Enable Register
<> 149:156823d33999 13411 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13412 * |Bits |Field |Descriptions
<> 149:156823d33999 13413 * | :----: | :----: | :---- |
<> 149:156823d33999 13414 * |[0] |SCTHIEN |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
<> 149:156823d33999 13415 * | | |0 = Key scan complete with threshold control interrupt is disable.
<> 149:156823d33999 13416 * | | |1 = Key scan complete with threshold control interrupt is enable.
<> 149:156823d33999 13417 * |[1] |SCINTEN |Touch Key Scan Complete Interrupt Enable
<> 149:156823d33999 13418 * | | |Bit
<> 149:156823d33999 13419 * | | |0 = Key scan complete without threshold control interrupt is disable.
<> 149:156823d33999 13420 * | | |1 = Key scan complete without threshold control interrupt is enable.
<> 149:156823d33999 13421 * |[31] |THIMOD |Touch Key Threshold Interrupt Mode Select
<> 149:156823d33999 13422 * | | |0 = Edge trigger mode.
<> 149:156823d33999 13423 * | | |1 = Level trigger mode.
<> 149:156823d33999 13424 * @var TK_T::TH0_1
<> 149:156823d33999 13425 * Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register
<> 149:156823d33999 13426 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13427 * |Bits |Field |Descriptions
<> 149:156823d33999 13428 * | :----: | :----: | :---- |
<> 149:156823d33999 13429 * |[7:0] |LTH0 |Low Threshold Of TK0
<> 149:156823d33999 13430 * | | |Low level for TK0 threshold control.
<> 149:156823d33999 13431 * |[15:8] |HTH0 |High Threshold Of TK0
<> 149:156823d33999 13432 * | | |High level for TK0 threshold control.
<> 149:156823d33999 13433 * |[23:16] |LTH1 |Low Threshold Of TK1
<> 149:156823d33999 13434 * | | |Low level for TK1 threshold control.
<> 149:156823d33999 13435 * |[31:24] |HTH1 |High Threshold Of TK1
<> 149:156823d33999 13436 * | | |High level for TK1 threshold control.
<> 149:156823d33999 13437 * @var TK_T::TH2_3
<> 149:156823d33999 13438 * Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register
<> 149:156823d33999 13439 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13440 * |Bits |Field |Descriptions
<> 149:156823d33999 13441 * | :----: | :----: | :---- |
<> 149:156823d33999 13442 * |[7:0] |LTH2 |Low Threshold Of TK2
<> 149:156823d33999 13443 * | | |Low level for TK2 threshold control.
<> 149:156823d33999 13444 * |[15:8] |HTH2 |High Threshold Of TK2
<> 149:156823d33999 13445 * | | |High level for TK2 threshold control.
<> 149:156823d33999 13446 * |[23:16] |LTH3 |Low Threshold Of TK3
<> 149:156823d33999 13447 * | | |Low level for TK3 threshold control.
<> 149:156823d33999 13448 * |[31:24] |HTH3 |High Threshold Of TK3
<> 149:156823d33999 13449 * | | |High level for TK3 threshold control.
<> 149:156823d33999 13450 * @var TK_T::TH4_5
<> 149:156823d33999 13451 * Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register
<> 149:156823d33999 13452 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13453 * |Bits |Field |Descriptions
<> 149:156823d33999 13454 * | :----: | :----: | :---- |
<> 149:156823d33999 13455 * |[7:0] |LTH4 |Low Threshold Of TK4
<> 149:156823d33999 13456 * | | |Low level for TK4 threshold control.
<> 149:156823d33999 13457 * |[15:8] |HTH4 |High Threshold Of TK4
<> 149:156823d33999 13458 * | | |High level for TK4 threshold control.
<> 149:156823d33999 13459 * |[23:16] |LTH5 |Low Threshold Of TK5
<> 149:156823d33999 13460 * | | |Low level for TK5 threshold control.
<> 149:156823d33999 13461 * |[31:24] |HTH5 |High Threshold Of TK5
<> 149:156823d33999 13462 * | | |High level for TK5 threshold control.
<> 149:156823d33999 13463 * @var TK_T::TH6_7
<> 149:156823d33999 13464 * Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register
<> 149:156823d33999 13465 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13466 * |Bits |Field |Descriptions
<> 149:156823d33999 13467 * | :----: | :----: | :---- |
<> 149:156823d33999 13468 * |[7:0] |LTH6 |Low Threshold Of TK6
<> 149:156823d33999 13469 * | | |Low level for TK6 threshold control.
<> 149:156823d33999 13470 * |[15:8] |HTH6 |High Threshold Of TK6
<> 149:156823d33999 13471 * | | |High level for TK6 threshold control.
<> 149:156823d33999 13472 * |[23:16] |LTH7 |Low Threshold Of TK7
<> 149:156823d33999 13473 * | | |Low level for TK7 threshold control.
<> 149:156823d33999 13474 * |[31:24] |HTH7 |High Threshold Of TK7
<> 149:156823d33999 13475 * | | |High level for TK7 threshold control.
<> 149:156823d33999 13476 * @var TK_T::TH8_9
<> 149:156823d33999 13477 * Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register
<> 149:156823d33999 13478 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13479 * |Bits |Field |Descriptions
<> 149:156823d33999 13480 * | :----: | :----: | :---- |
<> 149:156823d33999 13481 * |[7:0] |LTH8 |Low Threshold Of TK8
<> 149:156823d33999 13482 * | | |Low level for TK8 threshold control.
<> 149:156823d33999 13483 * |[15:8] |HTH8 |High Threshold Of TK8
<> 149:156823d33999 13484 * | | |High level for TK8 threshold control.
<> 149:156823d33999 13485 * |[23:16] |LTH9 |Low Threshold Of TK9
<> 149:156823d33999 13486 * | | |Low level for TK9 threshold control.
<> 149:156823d33999 13487 * |[31:24] |HTH9 |High Threshold Of TK9
<> 149:156823d33999 13488 * | | |High level for TK9 threshold control.
<> 149:156823d33999 13489 * @var TK_T::TH10_11
<> 149:156823d33999 13490 * Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register
<> 149:156823d33999 13491 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13492 * |Bits |Field |Descriptions
<> 149:156823d33999 13493 * | :----: | :----: | :---- |
<> 149:156823d33999 13494 * |[7:0] |LTH10 |Low Threshold Of TK10
<> 149:156823d33999 13495 * | | |Low level for TK10 threshold control.
<> 149:156823d33999 13496 * |[15:8] |HTH10 |High Threshold Of TK10
<> 149:156823d33999 13497 * | | |High level for TK10 threshold control.
<> 149:156823d33999 13498 * |[23:16] |LTH11 |Low Threshold Of TK11
<> 149:156823d33999 13499 * | | |Low level for TK11 threshold control.
<> 149:156823d33999 13500 * |[31:24] |HTH11 |High Threshold Of TK11
<> 149:156823d33999 13501 * | | |High level for TK11 threshold control.
<> 149:156823d33999 13502 * @var TK_T::TH12_13
<> 149:156823d33999 13503 * Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register
<> 149:156823d33999 13504 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13505 * |Bits |Field |Descriptions
<> 149:156823d33999 13506 * | :----: | :----: | :---- |
<> 149:156823d33999 13507 * |[7:0] |LTH12 |Low Threshold Of TK12
<> 149:156823d33999 13508 * | | |Low level for TK12 threshold control.
<> 149:156823d33999 13509 * |[15:8] |HTH12 |High Threshold Of TK12
<> 149:156823d33999 13510 * | | |High level for TK12 threshold control.
<> 149:156823d33999 13511 * |[23:16] |LTH13 |Low Threshold Of TK13
<> 149:156823d33999 13512 * | | |Low level for TK13 threshold control.
<> 149:156823d33999 13513 * |[31:24] |HTH13 |High Threshold Of TK13
<> 149:156823d33999 13514 * | | |High level for TK13 threshold control.
<> 149:156823d33999 13515 * @var TK_T::TH14_15
<> 149:156823d33999 13516 * Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register
<> 149:156823d33999 13517 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13518 * |Bits |Field |Descriptions
<> 149:156823d33999 13519 * | :----: | :----: | :---- |
<> 149:156823d33999 13520 * |[7:0] |LTH14 |Low Threshold Of TK14
<> 149:156823d33999 13521 * | | |Low level for TK14 threshold control.
<> 149:156823d33999 13522 * |[15:8] |HTH14 |High Threshold Of TK14
<> 149:156823d33999 13523 * | | |High level for TK14 threshold control.
<> 149:156823d33999 13524 * |[23:16] |LTH15 |Low Threshold Of TK15
<> 149:156823d33999 13525 * | | |Low level for TK15 threshold control.
<> 149:156823d33999 13526 * |[31:24] |HTH15 |High Threshold Of TK15
<> 149:156823d33999 13527 * | | |High level for TK15 threshold control.
<> 149:156823d33999 13528 * @var TK_T::TH16
<> 149:156823d33999 13529 * Offset: 0x64 Touch Key TK16 Threshold Control Register
<> 149:156823d33999 13530 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 13531 * |Bits |Field |Descriptions
<> 149:156823d33999 13532 * | :----: | :----: | :---- |
<> 149:156823d33999 13533 * |[7:0] |LTH16 |Low Threshold Of TK16
<> 149:156823d33999 13534 * | | |Low level for TK16 threshold control.
<> 149:156823d33999 13535 * |[15:8] |HTH16 |High Threshold Of TK16
<> 149:156823d33999 13536 * | | |High level for TK16 threshold control.
<> 149:156823d33999 13537 */
<> 149:156823d33999 13538
<> 149:156823d33999 13539 __IO uint32_t CTL; /* Offset: 0x00 Touch Key Scan Control Register */
<> 149:156823d33999 13540 __IO uint32_t REFCTL; /* Offset: 0x04 Touch Key Reference Control Register */
<> 149:156823d33999 13541 __IO uint32_t CCBDAT0; /* Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0 */
<> 149:156823d33999 13542 __IO uint32_t CCBDAT1; /* Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1 */
<> 149:156823d33999 13543 __IO uint32_t CCBDAT2; /* Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2 */
<> 149:156823d33999 13544 __IO uint32_t CCBDAT3; /* Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3 */
<> 149:156823d33999 13545 __IO uint32_t CCBDAT4; /* Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4 */
<> 149:156823d33999 13546 __IO uint32_t IDLESEL; /* Offset: 0x1C Touch Key Idle State Control Register */
<> 149:156823d33999 13547 __IO uint32_t POLSEL; /* Offset: 0x20 Touch Key Polarity Select Register */
<> 149:156823d33999 13548 __IO uint32_t POLCTL; /* Offset: 0x24 Touch Key Polarity Control Register */
<> 149:156823d33999 13549 __IO uint32_t STATUS; /* Offset: 0x28 Touch Key Status Register */
<> 149:156823d33999 13550 __I uint32_t DAT0; /* Offset: 0x2C Touch Key Data Register 0 */
<> 149:156823d33999 13551 __I uint32_t DAT1; /* Offset: 0x30 Touch Key Data Register 1 */
<> 149:156823d33999 13552 __I uint32_t DAT2; /* Offset: 0x34 Touch Key Data Register 2 */
<> 149:156823d33999 13553 __I uint32_t DAT3; /* Offset: 0x38 Touch Key Data Register 3 */
<> 149:156823d33999 13554 __I uint32_t DAT4; /* Offset: 0x3C Touch Key Data Register 4 */
<> 149:156823d33999 13555 __IO uint32_t INTEN; /* Offset: 0x40 Touch Key Interrupt Enable Register */
<> 149:156823d33999 13556 __IO uint32_t TH0_1; /* Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register */
<> 149:156823d33999 13557 __IO uint32_t TH2_3; /* Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register */
<> 149:156823d33999 13558 __IO uint32_t TH4_5; /* Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register */
<> 149:156823d33999 13559 __IO uint32_t TH6_7; /* Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register */
<> 149:156823d33999 13560 __IO uint32_t TH8_9; /* Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register */
<> 149:156823d33999 13561 __IO uint32_t TH10_11; /* Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register */
<> 149:156823d33999 13562 __IO uint32_t TH12_13; /* Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register */
<> 149:156823d33999 13563 __IO uint32_t TH14_15; /* Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register */
<> 149:156823d33999 13564 __IO uint32_t TH16; /* Offset: 0x64 Touch Key TK16 Threshold Control Register */
<> 149:156823d33999 13565
<> 149:156823d33999 13566 } TK_T;
<> 149:156823d33999 13567
<> 149:156823d33999 13568
<> 149:156823d33999 13569
<> 149:156823d33999 13570 /**
<> 149:156823d33999 13571 @addtogroup TK_CONST TK Bit Field Definition
<> 149:156823d33999 13572 Constant Definitions for TK Controller
<> 149:156823d33999 13573 @{ */
<> 149:156823d33999 13574
<> 149:156823d33999 13575
<> 149:156823d33999 13576 #define TK_CTL_TKSEN0_Pos (0) /*!< TK_T::CTL: TKSEN0 Position */
<> 149:156823d33999 13577 #define TK_CTL_TKSEN0_Msk (0x1ul << TK_CTL_TKSEN0_Pos) /*!< TK_T::CTL: TKSEN0 Mask */
<> 149:156823d33999 13578
<> 149:156823d33999 13579 #define TK_CTL_TKSEN1_Pos (1) /*!< TK_T::CTL: TKSEN1 Position */
<> 149:156823d33999 13580 #define TK_CTL_TKSEN1_Msk (0x1ul << TK_CTL_TKSEN1_Pos) /*!< TK_T::CTL: TKSEN1 Mask */
<> 149:156823d33999 13581
<> 149:156823d33999 13582 #define TK_CTL_TKSEN2_Pos (2) /*!< TK_T::CTL: TKSEN2 Position */
<> 149:156823d33999 13583 #define TK_CTL_TKSEN2_Msk (0x1ul << TK_CTL_TKSEN2_Pos) /*!< TK_T::CTL: TKSEN2 Mask */
<> 149:156823d33999 13584
<> 149:156823d33999 13585 #define TK_CTL_TKSEN3_Pos (3) /*!< TK_T::CTL: TKSEN3 Position */
<> 149:156823d33999 13586 #define TK_CTL_TKSEN3_Msk (0x1ul << TK_CTL_TKSEN3_Pos) /*!< TK_T::CTL: TKSEN3 Mask */
<> 149:156823d33999 13587
<> 149:156823d33999 13588 #define TK_CTL_TKSEN4_Pos (4) /*!< TK_T::CTL: TKSEN4 Position */
<> 149:156823d33999 13589 #define TK_CTL_TKSEN4_Msk (0x1ul << TK_CTL_TKSEN4_Pos) /*!< TK_T::CTL: TKSEN4 Mask */
<> 149:156823d33999 13590
<> 149:156823d33999 13591 #define TK_CTL_TKSEN5_Pos (5) /*!< TK_T::CTL: TKSEN5 Position */
<> 149:156823d33999 13592 #define TK_CTL_TKSEN5_Msk (0x1ul << TK_CTL_TKSEN5_Pos) /*!< TK_T::CTL: TKSEN5 Mask */
<> 149:156823d33999 13593
<> 149:156823d33999 13594 #define TK_CTL_TKSEN6_Pos (6) /*!< TK_T::CTL: TKSEN6 Position */
<> 149:156823d33999 13595 #define TK_CTL_TKSEN6_Msk (0x1ul << TK_CTL_TKSEN6_Pos) /*!< TK_T::CTL: TKSEN6 Mask */
<> 149:156823d33999 13596
<> 149:156823d33999 13597 #define TK_CTL_TKSEN7_Pos (7) /*!< TK_T::CTL: TKSEN7 Position */
<> 149:156823d33999 13598 #define TK_CTL_TKSEN7_Msk (0x1ul << TK_CTL_TKSEN7_Pos) /*!< TK_T::CTL: TKSEN7 Mask */
<> 149:156823d33999 13599
<> 149:156823d33999 13600 #define TK_CTL_TKSEN8_Pos (8) /*!< TK_T::CTL: TKSEN8 Position */
<> 149:156823d33999 13601 #define TK_CTL_TKSEN8_Msk (0x1ul << TK_CTL_TKSEN8_Pos) /*!< TK_T::CTL: TKSEN8 Mask */
<> 149:156823d33999 13602
<> 149:156823d33999 13603 #define TK_CTL_TKSEN9_Pos (9) /*!< TK_T::CTL: TKSEN9 Position */
<> 149:156823d33999 13604 #define TK_CTL_TKSEN9_Msk (0x1ul << TK_CTL_TKSEN9_Pos) /*!< TK_T::CTL: TKSEN9 Mask */
<> 149:156823d33999 13605
<> 149:156823d33999 13606 #define TK_CTL_TKSEN10_Pos (10) /*!< TK_T::CTL: TKSEN10 Position */
<> 149:156823d33999 13607 #define TK_CTL_TKSEN10_Msk (0x1ul << TK_CTL_TKSEN10_Pos) /*!< TK_T::CTL: TKSEN10 Mask */
<> 149:156823d33999 13608
<> 149:156823d33999 13609 #define TK_CTL_TKSEN11_Pos (11) /*!< TK_T::CTL: TKSEN11 Position */
<> 149:156823d33999 13610 #define TK_CTL_TKSEN11_Msk (0x1ul << TK_CTL_TKSEN11_Pos) /*!< TK_T::CTL: TKSEN11 Mask */
<> 149:156823d33999 13611
<> 149:156823d33999 13612 #define TK_CTL_TKSEN12_Pos (12) /*!< TK_T::CTL: TKSEN12 Position */
<> 149:156823d33999 13613 #define TK_CTL_TKSEN12_Msk (0x1ul << TK_CTL_TKSEN12_Pos) /*!< TK_T::CTL: TKSEN12 Mask */
<> 149:156823d33999 13614
<> 149:156823d33999 13615 #define TK_CTL_TKSEN13_Pos (13) /*!< TK_T::CTL: TKSEN13 Position */
<> 149:156823d33999 13616 #define TK_CTL_TKSEN13_Msk (0x1ul << TK_CTL_TKSEN13_Pos) /*!< TK_T::CTL: TKSEN13 Mask */
<> 149:156823d33999 13617
<> 149:156823d33999 13618 #define TK_CTL_TKSEN14_Pos (14) /*!< TK_T::CTL: TKSEN14 Position */
<> 149:156823d33999 13619 #define TK_CTL_TKSEN14_Msk (0x1ul << TK_CTL_TKSEN14_Pos) /*!< TK_T::CTL: TKSEN14 Mask */
<> 149:156823d33999 13620
<> 149:156823d33999 13621 #define TK_CTL_TKSEN15_Pos (15) /*!< TK_T::CTL: TKSEN15 Position */
<> 149:156823d33999 13622 #define TK_CTL_TKSEN15_Msk (0x1ul << TK_CTL_TKSEN15_Pos) /*!< TK_T::CTL: TKSEN15 Mask */
<> 149:156823d33999 13623
<> 149:156823d33999 13624 #define TK_CTL_TKSEN16_Pos (16) /*!< TK_T::CTL: TKSEN16 Position */
<> 149:156823d33999 13625 #define TK_CTL_TKSEN16_Msk (0x1ul << TK_CTL_TKSEN16_Pos) /*!< TK_T::CTL: TKSEN16 Mask */
<> 149:156823d33999 13626
<> 149:156823d33999 13627 #define TK_CTL_AVCCHSEL_Pos (20) /*!< TK_T::CTL: AVCCHSEL Position */
<> 149:156823d33999 13628 #define TK_CTL_AVCCHSEL_Msk (0x7ul << TK_CTL_AVCCHSEL_Pos) /*!< TK_T::CTL: AVCCHSEL Mask */
<> 149:156823d33999 13629
<> 149:156823d33999 13630 #define TK_CTL_SCAN_Pos (24) /*!< TK_T::CTL: SCAN Position */
<> 149:156823d33999 13631 #define TK_CTL_SCAN_Msk (0x1ul << TK_CTL_SCAN_Pos) /*!< TK_T::CTL: SCAN Mask */
<> 149:156823d33999 13632
<> 149:156823d33999 13633 #define TK_CTL_TMRTRGEN_Pos (25) /*!< TK_T::CTL: TMRTRGEN Position */
<> 149:156823d33999 13634 #define TK_CTL_TMRTRGEN_Msk (0x1ul << TK_CTL_TMRTRGEN_Pos) /*!< TK_T::CTL: TMRTRGEN Mask */
<> 149:156823d33999 13635
<> 149:156823d33999 13636 #define TK_CTL_TKEN_Pos (31) /*!< TK_T::CTL: TKEN Position */
<> 149:156823d33999 13637 #define TK_CTL_TKEN_Msk (0x1ul << TK_CTL_TKEN_Pos) /*!< TK_T::CTL: TKEN Mask */
<> 149:156823d33999 13638
<> 149:156823d33999 13639 #define TK_REFCTL_TKREN0_Pos (0) /*!< TK_T::REFCTL: TKREN0 Position */
<> 149:156823d33999 13640 #define TK_REFCTL_TKREN0_Msk (0x1ul << TK_REFCTL_TKREN0_Pos) /*!< TK_T::REFCTL: TKREN0 Mask */
<> 149:156823d33999 13641
<> 149:156823d33999 13642 #define TK_REFCTL_TKREN1_Pos (1) /*!< TK_T::REFCTL: TKREN1 Position */
<> 149:156823d33999 13643 #define TK_REFCTL_TKREN1_Msk (0x1ul << TK_REFCTL_TKREN1_Pos) /*!< TK_T::REFCTL: TKREN1 Mask */
<> 149:156823d33999 13644
<> 149:156823d33999 13645 #define TK_REFCTL_TKREN2_Pos (2) /*!< TK_T::REFCTL: TKREN2 Position */
<> 149:156823d33999 13646 #define TK_REFCTL_TKREN2_Msk (0x1ul << TK_REFCTL_TKREN2_Pos) /*!< TK_T::REFCTL: TKREN2 Mask */
<> 149:156823d33999 13647
<> 149:156823d33999 13648 #define TK_REFCTL_TKREN3_Pos (3) /*!< TK_T::REFCTL: TKREN3 Position */
<> 149:156823d33999 13649 #define TK_REFCTL_TKREN3_Msk (0x1ul << TK_REFCTL_TKREN3_Pos) /*!< TK_T::REFCTL: TKREN3 Mask */
<> 149:156823d33999 13650
<> 149:156823d33999 13651 #define TK_REFCTL_TKREN4_Pos (4) /*!< TK_T::REFCTL: TKREN4 Position */
<> 149:156823d33999 13652 #define TK_REFCTL_TKREN4_Msk (0x1ul << TK_REFCTL_TKREN4_Pos) /*!< TK_T::REFCTL: TKREN4 Mask */
<> 149:156823d33999 13653
<> 149:156823d33999 13654 #define TK_REFCTL_TKREN5_Pos (5) /*!< TK_T::REFCTL: TKREN5 Position */
<> 149:156823d33999 13655 #define TK_REFCTL_TKREN5_Msk (0x1ul << TK_REFCTL_TKREN5_Pos) /*!< TK_T::REFCTL: TKREN5 Mask */
<> 149:156823d33999 13656
<> 149:156823d33999 13657 #define TK_REFCTL_TKREN6_Pos (6) /*!< TK_T::REFCTL: TKREN6 Position */
<> 149:156823d33999 13658 #define TK_REFCTL_TKREN6_Msk (0x1ul << TK_REFCTL_TKREN6_Pos) /*!< TK_T::REFCTL: TKREN6 Mask */
<> 149:156823d33999 13659
<> 149:156823d33999 13660 #define TK_REFCTL_TKREN7_Pos (7) /*!< TK_T::REFCTL: TKREN7 Position */
<> 149:156823d33999 13661 #define TK_REFCTL_TKREN7_Msk (0x1ul << TK_REFCTL_TKREN7_Pos) /*!< TK_T::REFCTL: TKREN7 Mask */
<> 149:156823d33999 13662
<> 149:156823d33999 13663 #define TK_REFCTL_TKREN8_Pos (8) /*!< TK_T::REFCTL: TKREN8 Position */
<> 149:156823d33999 13664 #define TK_REFCTL_TKREN8_Msk (0x1ul << TK_REFCTL_TKREN8_Pos) /*!< TK_T::REFCTL: TKREN8 Mask */
<> 149:156823d33999 13665
<> 149:156823d33999 13666 #define TK_REFCTL_TKREN9_Pos (9) /*!< TK_T::REFCTL: TKREN9 Position */
<> 149:156823d33999 13667 #define TK_REFCTL_TKREN9_Msk (0x1ul << TK_REFCTL_TKREN9_Pos) /*!< TK_T::REFCTL: TKREN9 Mask */
<> 149:156823d33999 13668
<> 149:156823d33999 13669 #define TK_REFCTL_TKREN10_Pos (10) /*!< TK_T::REFCTL: TKREN10 Position */
<> 149:156823d33999 13670 #define TK_REFCTL_TKREN10_Msk (0x1ul << TK_REFCTL_TKREN10_Pos) /*!< TK_T::REFCTL: TKREN10 Mask */
<> 149:156823d33999 13671
<> 149:156823d33999 13672 #define TK_REFCTL_TKREN11_Pos (11) /*!< TK_T::REFCTL: TKREN11 Position */
<> 149:156823d33999 13673 #define TK_REFCTL_TKREN11_Msk (0x1ul << TK_REFCTL_TKREN11_Pos) /*!< TK_T::REFCTL: TKREN11 Mask */
<> 149:156823d33999 13674
<> 149:156823d33999 13675 #define TK_REFCTL_TKREN12_Pos (12) /*!< TK_T::REFCTL: TKREN12 Position */
<> 149:156823d33999 13676 #define TK_REFCTL_TKREN12_Msk (0x1ul << TK_REFCTL_TKREN12_Pos) /*!< TK_T::REFCTL: TKREN12 Mask */
<> 149:156823d33999 13677
<> 149:156823d33999 13678 #define TK_REFCTL_TKREN13_Pos (13) /*!< TK_T::REFCTL: TKREN13 Position */
<> 149:156823d33999 13679 #define TK_REFCTL_TKREN13_Msk (0x1ul << TK_REFCTL_TKREN13_Pos) /*!< TK_T::REFCTL: TKREN13 Mask */
<> 149:156823d33999 13680
<> 149:156823d33999 13681 #define TK_REFCTL_TKREN14_Pos (14) /*!< TK_T::REFCTL: TKREN14 Position */
<> 149:156823d33999 13682 #define TK_REFCTL_TKREN14_Msk (0x1ul << TK_REFCTL_TKREN14_Pos) /*!< TK_T::REFCTL: TKREN14 Mask */
<> 149:156823d33999 13683
<> 149:156823d33999 13684 #define TK_REFCTL_TKREN15_Pos (15) /*!< TK_T::REFCTL: TKREN15 Position */
<> 149:156823d33999 13685 #define TK_REFCTL_TKREN15_Msk (0x1ul << TK_REFCTL_TKREN15_Pos) /*!< TK_T::REFCTL: TKREN15 Mask */
<> 149:156823d33999 13686
<> 149:156823d33999 13687 #define TK_REFCTL_TKREN16_Pos (16) /*!< TK_T::REFCTL: TKREN16 Position */
<> 149:156823d33999 13688 #define TK_REFCTL_TKREN16_Msk (0x1ul << TK_REFCTL_TKREN16_Pos) /*!< TK_T::REFCTL: TKREN16 Mask */
<> 149:156823d33999 13689
<> 149:156823d33999 13690 #define TK_REFCTL_SCANALL_Pos (23) /*!< TK_T::REFCTL: SCANALL Position */
<> 149:156823d33999 13691 #define TK_REFCTL_SCANALL_Msk (0x1ul << TK_REFCTL_SCANALL_Pos) /*!< TK_T::REFCTL: SCANALL Mask */
<> 149:156823d33999 13692
<> 149:156823d33999 13693 #define TK_REFCTL_SENTCTL_Pos (24) /*!< TK_T::REFCTL: SENTCTL Position */
<> 149:156823d33999 13694 #define TK_REFCTL_SENTCTL_Msk (0x3ul << TK_REFCTL_SENTCTL_Pos) /*!< TK_T::REFCTL: SENTCTL Mask */
<> 149:156823d33999 13695
<> 149:156823d33999 13696 #define TK_REFCTL_SENPTCTL_Pos (28) /*!< TK_T::REFCTL: SENPTCTL Position */
<> 149:156823d33999 13697 #define TK_REFCTL_SENPTCTL_Msk (0x3ul << TK_REFCTL_SENPTCTL_Pos) /*!< TK_T::REFCTL: SENPTCTL Mask */
<> 149:156823d33999 13698
<> 149:156823d33999 13699 #define TK_CCBDAT0_CCBDAT0_Pos (0) /*!< TK_T::CCBDAT0: CCBDAT0 Position */
<> 149:156823d33999 13700 #define TK_CCBDAT0_CCBDAT0_Msk (0xfful << TK_CCBDAT0_CCBDAT0_Pos) /*!< TK_T::CCBDAT0: CCBDAT0 Mask */
<> 149:156823d33999 13701
<> 149:156823d33999 13702 #define TK_CCBDAT0_CCBDAT1_Pos (8) /*!< TK_T::CCBDAT0: CCBDAT1 Position */
<> 149:156823d33999 13703 #define TK_CCBDAT0_CCBDAT1_Msk (0xfful << TK_CCBDAT0_CCBDAT1_Pos) /*!< TK_T::CCBDAT0: CCBDAT1 Mask */
<> 149:156823d33999 13704
<> 149:156823d33999 13705 #define TK_CCBDAT0_CCBDAT2_Pos (16) /*!< TK_T::CCBDAT0: CCBDAT2 Position */
<> 149:156823d33999 13706 #define TK_CCBDAT0_CCBDAT2_Msk (0xfful << TK_CCBDAT0_CCBDAT2_Pos) /*!< TK_T::CCBDAT0: CCBDAT2 Mask */
<> 149:156823d33999 13707
<> 149:156823d33999 13708 #define TK_CCBDAT0_CCBDAT3_Pos (24) /*!< TK_T::CCBDAT0: CCBDAT3 Position */
<> 149:156823d33999 13709 #define TK_CCBDAT0_CCBDAT3_Msk (0xfful << TK_CCBDAT0_CCBDAT3_Pos) /*!< TK_T::CCBDAT0: CCBDAT3 Mask */
<> 149:156823d33999 13710
<> 149:156823d33999 13711 #define TK_CCBDAT1_CCBDAT4_Pos (0) /*!< TK_T::CCBDAT1: CCBDAT4 Position */
<> 149:156823d33999 13712 #define TK_CCBDAT1_CCBDAT4_Msk (0xfful << TK_CCBDAT1_CCBDAT4_Pos) /*!< TK_T::CCBDAT1: CCBDAT4 Mask */
<> 149:156823d33999 13713
<> 149:156823d33999 13714 #define TK_CCBDAT1_CCBDAT5_Pos (8) /*!< TK_T::CCBDAT1: CCBDAT5 Position */
<> 149:156823d33999 13715 #define TK_CCBDAT1_CCBDAT5_Msk (0xfful << TK_CCBDAT1_CCBDAT5_Pos) /*!< TK_T::CCBDAT1: CCBDAT5 Mask */
<> 149:156823d33999 13716
<> 149:156823d33999 13717 #define TK_CCBDAT1_CCBDAT6_Pos (16) /*!< TK_T::CCBDAT1: CCBDAT6 Position */
<> 149:156823d33999 13718 #define TK_CCBDAT1_CCBDAT6_Msk (0xfful << TK_CCBDAT1_CCBDAT6_Pos) /*!< TK_T::CCBDAT1: CCBDAT6 Mask */
<> 149:156823d33999 13719
<> 149:156823d33999 13720 #define TK_CCBDAT1_CCBDAT7_Pos (24) /*!< TK_T::CCBDAT1: CCBDAT7 Position */
<> 149:156823d33999 13721 #define TK_CCBDAT1_CCBDAT7_Msk (0xfful << TK_CCBDAT1_CCBDAT7_Pos) /*!< TK_T::CCBDAT1: CCBDAT7 Mask */
<> 149:156823d33999 13722
<> 149:156823d33999 13723 #define TK_CCBDAT2_CCBDAT8_Pos (0) /*!< TK_T::CCBDAT2: CCBDAT8 Position */
<> 149:156823d33999 13724 #define TK_CCBDAT2_CCBDAT8_Msk (0xfful << TK_CCBDAT2_CCBDAT8_Pos) /*!< TK_T::CCBDAT2: CCBDAT8 Mask */
<> 149:156823d33999 13725
<> 149:156823d33999 13726 #define TK_CCBDAT2_CCBDAT9_Pos (8) /*!< TK_T::CCBDAT2: CCBDAT9 Position */
<> 149:156823d33999 13727 #define TK_CCBDAT2_CCBDAT9_Msk (0xfful << TK_CCBDAT2_CCBDAT9_Pos) /*!< TK_T::CCBDAT2: CCBDAT9 Mask */
<> 149:156823d33999 13728
<> 149:156823d33999 13729 #define TK_CCBDAT2_CCBDAT10_Pos (16) /*!< TK_T::CCBDAT2: CCBDAT10 Position */
<> 149:156823d33999 13730 #define TK_CCBDAT2_CCBDAT10_Msk (0xfful << TK_CCBDAT2_CCBDAT10_Pos) /*!< TK_T::CCBDAT2: CCBDAT10 Mask */
<> 149:156823d33999 13731
<> 149:156823d33999 13732 #define TK_CCBDAT2_CCBDAT11_Pos (24) /*!< TK_T::CCBDAT2: CCBDAT11 Position */
<> 149:156823d33999 13733 #define TK_CCBDAT2_CCBDAT11_Msk (0xfful << TK_CCBDAT2_CCBDAT11_Pos) /*!< TK_T::CCBDAT2: CCBDAT11 Mask */
<> 149:156823d33999 13734
<> 149:156823d33999 13735 #define TK_CCBDAT3_CCBDAT12_Pos (0) /*!< TK_T::CCBDAT3: CCBDAT12 Position */
<> 149:156823d33999 13736 #define TK_CCBDAT3_CCBDAT12_Msk (0xfful << TK_CCBDAT3_CCBDAT12_Pos) /*!< TK_T::CCBDAT3: CCBDAT12 Mask */
<> 149:156823d33999 13737
<> 149:156823d33999 13738 #define TK_CCBDAT3_CCBDAT13_Pos (8) /*!< TK_T::CCBDAT3: CCBDAT13 Position */
<> 149:156823d33999 13739 #define TK_CCBDAT3_CCBDAT13_Msk (0xfful << TK_CCBDAT3_CCBDAT13_Pos) /*!< TK_T::CCBDAT3: CCBDAT13 Mask */
<> 149:156823d33999 13740
<> 149:156823d33999 13741 #define TK_CCBDAT3_CCBDAT14_Pos (16) /*!< TK_T::CCBDAT3: CCBDAT14 Position */
<> 149:156823d33999 13742 #define TK_CCBDAT3_CCBDAT14_Msk (0xfful << TK_CCBDAT3_CCBDAT14_Pos) /*!< TK_T::CCBDAT3: CCBDAT14 Mask */
<> 149:156823d33999 13743
<> 149:156823d33999 13744 #define TK_CCBDAT3_CCBDAT15_Pos (24) /*!< TK_T::CCBDAT3: CCBDAT15 Position */
<> 149:156823d33999 13745 #define TK_CCBDAT3_CCBDAT15_Msk (0xfful << TK_CCBDAT3_CCBDAT15_Pos) /*!< TK_T::CCBDAT3: CCBDAT15 Mask */
<> 149:156823d33999 13746
<> 149:156823d33999 13747 #define TK_CCBDAT4_CCBDAT16_Pos (0) /*!< TK_T::CCBDAT4: CCBDAT16 Position */
<> 149:156823d33999 13748 #define TK_CCBDAT4_CCBDAT16_Msk (0xfful << TK_CCBDAT4_CCBDAT16_Pos) /*!< TK_T::CCBDAT4: CCBDAT16 Mask */
<> 149:156823d33999 13749
<> 149:156823d33999 13750 #define TK_CCBDAT4_REFCBDAT_Pos (24) /*!< TK_T::CCBDAT4: REFCBDAT Position */
<> 149:156823d33999 13751 #define TK_CCBDAT4_REFCBDAT_Msk (0xfful << TK_CCBDAT4_REFCBDAT_Pos) /*!< TK_T::CCBDAT4: REFCBDAT Mask */
<> 149:156823d33999 13752
<> 149:156823d33999 13753 #define TK_IDLESEL_IDLS_Pos (0) /*!< TK_T::IDLESEL: IDLS Position */
<> 149:156823d33999 13754 #define TK_IDLESEL_IDLS_Msk (0xfffffffful << TK_IDLESEL_IDLS_Pos) /*!< TK_T::IDLESEL: IDLS Mask */
<> 149:156823d33999 13755
<> 149:156823d33999 13756 #define TK_IDLESEL_IDLSn_Pos (0) /*!< TK_T::IDLESEL: IDLSn Position */
<> 149:156823d33999 13757 #define TK_IDLESEL_IDLSn_Msk (0x3ul << TK_IDLESEL_IDLSn_Pos) /*!< TK_T::IDLESEL: IDLSn Mask */
<> 149:156823d33999 13758
<> 149:156823d33999 13759 #define TK_POLSEL_POLSEL_Pos (0) /*!< TK_T::POLSEL: POLSEL Position */
<> 149:156823d33999 13760 #define TK_POLSEL_POLSEL_Msk (0xfffffffful << TK_POLSEL_POLSEL_Pos) /*!< TK_T::POLSEL: POLSEL Mask */
<> 149:156823d33999 13761
<> 149:156823d33999 13762 #define TK_POLSEL_POLSELn_Pos (0) /*!< TK_T::POLSEL: POLSELn Position */
<> 149:156823d33999 13763 #define TK_POLSEL_POLSELn_Msk (0x3ul << TK_POLSEL_POLSELn_Pos) /*!< TK_T::POLSEL: POLSELn Mask */
<> 149:156823d33999 13764
<> 149:156823d33999 13765 #define TK_POLCTL_IDLS16_Pos (0) /*!< TK_T::POLCTL: IDLS16 Position */
<> 149:156823d33999 13766 #define TK_POLCTL_IDLS16_Msk (0x3ul << TK_POLCTL_IDLS16_Pos) /*!< TK_T::POLCTL: IDLS16 Mask */
<> 149:156823d33999 13767
<> 149:156823d33999 13768 #define TK_POLCTL_POLSEL16_Pos (2) /*!< TK_T::POLCTL: POLSEL16 Position */
<> 149:156823d33999 13769 #define TK_POLCTL_POLSEL16_Msk (0x3ul << TK_POLCTL_POLSEL16_Pos) /*!< TK_T::POLCTL: POLSEL16 Mask */
<> 149:156823d33999 13770
<> 149:156823d33999 13771 #define TK_POLCTL_CBPOLSEL_Pos (4) /*!< TK_T::POLCTL: CBPOLSEL Position */
<> 149:156823d33999 13772 #define TK_POLCTL_CBPOLSEL_Msk (0x3ul << TK_POLCTL_CBPOLSEL_Pos) /*!< TK_T::POLCTL: CBPOLSEL Mask */
<> 149:156823d33999 13773
<> 149:156823d33999 13774 #define TK_POLCTL_POLEN0_Pos (8) /*!< TK_T::POLCTL: POLEN0 Position */
<> 149:156823d33999 13775 #define TK_POLCTL_POLEN0_Msk (0x1ul << TK_POLCTL_POLEN0_Pos) /*!< TK_T::POLCTL: POLEN0 Mask */
<> 149:156823d33999 13776
<> 149:156823d33999 13777 #define TK_POLCTL_POLEN1_Pos (9) /*!< TK_T::POLCTL: POLEN1 Position */
<> 149:156823d33999 13778 #define TK_POLCTL_POLEN1_Msk (0x1ul << TK_POLCTL_POLEN1_Pos) /*!< TK_T::POLCTL: POLEN1 Mask */
<> 149:156823d33999 13779
<> 149:156823d33999 13780 #define TK_POLCTL_POLEN2_Pos (10) /*!< TK_T::POLCTL: POLEN2 Position */
<> 149:156823d33999 13781 #define TK_POLCTL_POLEN2_Msk (0x1ul << TK_POLCTL_POLEN2_Pos) /*!< TK_T::POLCTL: POLEN2 Mask */
<> 149:156823d33999 13782
<> 149:156823d33999 13783 #define TK_POLCTL_POLEN3_Pos (11) /*!< TK_T::POLCTL: POLEN3 Position */
<> 149:156823d33999 13784 #define TK_POLCTL_POLEN3_Msk (0x1ul << TK_POLCTL_POLEN3_Pos) /*!< TK_T::POLCTL: POLEN3 Mask */
<> 149:156823d33999 13785
<> 149:156823d33999 13786 #define TK_POLCTL_POLEN4_Pos (12) /*!< TK_T::POLCTL: POLEN4 Position */
<> 149:156823d33999 13787 #define TK_POLCTL_POLEN4_Msk (0x1ul << TK_POLCTL_POLEN4_Pos) /*!< TK_T::POLCTL: POLEN4 Mask */
<> 149:156823d33999 13788
<> 149:156823d33999 13789 #define TK_POLCTL_POLEN5_Pos (13) /*!< TK_T::POLCTL: POLEN5 Position */
<> 149:156823d33999 13790 #define TK_POLCTL_POLEN5_Msk (0x1ul << TK_POLCTL_POLEN5_Pos) /*!< TK_T::POLCTL: POLEN5 Mask */
<> 149:156823d33999 13791
<> 149:156823d33999 13792 #define TK_POLCTL_POLEN6_Pos (14) /*!< TK_T::POLCTL: POLEN6 Position */
<> 149:156823d33999 13793 #define TK_POLCTL_POLEN6_Msk (0x1ul << TK_POLCTL_POLEN6_Pos) /*!< TK_T::POLCTL: POLEN6 Mask */
<> 149:156823d33999 13794
<> 149:156823d33999 13795 #define TK_POLCTL_POLEN7_Pos (15) /*!< TK_T::POLCTL: POLEN7 Position */
<> 149:156823d33999 13796 #define TK_POLCTL_POLEN7_Msk (0x1ul << TK_POLCTL_POLEN7_Pos) /*!< TK_T::POLCTL: POLEN7 Mask */
<> 149:156823d33999 13797
<> 149:156823d33999 13798 #define TK_POLCTL_POLEN8_Pos (16) /*!< TK_T::POLCTL: POLEN8 Position */
<> 149:156823d33999 13799 #define TK_POLCTL_POLEN8_Msk (0x1ul << TK_POLCTL_POLEN8_Pos) /*!< TK_T::POLCTL: POLEN8 Mask */
<> 149:156823d33999 13800
<> 149:156823d33999 13801 #define TK_POLCTL_POLEN9_Pos (17) /*!< TK_T::POLCTL: POLEN9 Position */
<> 149:156823d33999 13802 #define TK_POLCTL_POLEN9_Msk (0x1ul << TK_POLCTL_POLEN9_Pos) /*!< TK_T::POLCTL: POLEN9 Mask */
<> 149:156823d33999 13803
<> 149:156823d33999 13804 #define TK_POLCTL_POLEN10_Pos (18) /*!< TK_T::POLCTL: POLEN10 Position */
<> 149:156823d33999 13805 #define TK_POLCTL_POLEN10_Msk (0x1ul << TK_POLCTL_POLEN10_Pos) /*!< TK_T::POLCTL: POLEN10 Mask */
<> 149:156823d33999 13806
<> 149:156823d33999 13807 #define TK_POLCTL_POLEN11_Pos (19) /*!< TK_T::POLCTL: POLEN11 Position */
<> 149:156823d33999 13808 #define TK_POLCTL_POLEN11_Msk (0x1ul << TK_POLCTL_POLEN11_Pos) /*!< TK_T::POLCTL: POLEN11 Mask */
<> 149:156823d33999 13809
<> 149:156823d33999 13810 #define TK_POLCTL_POLEN12_Pos (20) /*!< TK_T::POLCTL: POLEN12 Position */
<> 149:156823d33999 13811 #define TK_POLCTL_POLEN12_Msk (0x1ul << TK_POLCTL_POLEN12_Pos) /*!< TK_T::POLCTL: POLEN12 Mask */
<> 149:156823d33999 13812
<> 149:156823d33999 13813 #define TK_POLCTL_POLEN13_Pos (21) /*!< TK_T::POLCTL: POLEN13 Position */
<> 149:156823d33999 13814 #define TK_POLCTL_POLEN13_Msk (0x1ul << TK_POLCTL_POLEN13_Pos) /*!< TK_T::POLCTL: POLEN13 Mask */
<> 149:156823d33999 13815
<> 149:156823d33999 13816 #define TK_POLCTL_POLEN14_Pos (22) /*!< TK_T::POLCTL: POLEN14 Position */
<> 149:156823d33999 13817 #define TK_POLCTL_POLEN14_Msk (0x1ul << TK_POLCTL_POLEN14_Pos) /*!< TK_T::POLCTL: POLEN14 Mask */
<> 149:156823d33999 13818
<> 149:156823d33999 13819 #define TK_POLCTL_POLEN15_Pos (23) /*!< TK_T::POLCTL: POLEN15 Position */
<> 149:156823d33999 13820 #define TK_POLCTL_POLEN15_Msk (0x1ul << TK_POLCTL_POLEN15_Pos) /*!< TK_T::POLCTL: POLEN15 Mask */
<> 149:156823d33999 13821
<> 149:156823d33999 13822 #define TK_POLCTL_POLEN16_Pos (24) /*!< TK_T::POLCTL: POLEN16 Position */
<> 149:156823d33999 13823 #define TK_POLCTL_POLEN16_Msk (0x1ul << TK_POLCTL_POLEN16_Pos) /*!< TK_T::POLCTL: POLEN16 Mask */
<> 149:156823d33999 13824
<> 149:156823d33999 13825 #define TK_POLCTL_SPOTINIT_Pos (31) /*!< TK_T::POLCTL: SPOTINIT Position */
<> 149:156823d33999 13826 #define TK_POLCTL_SPOTINIT_Msk (0x1ul << TK_POLCTL_SPOTINIT_Pos) /*!< TK_T::POLCTL: SPOTINIT Mask */
<> 149:156823d33999 13827
<> 149:156823d33999 13828 #define TK_STATUS_BUSY_Pos (0) /*!< TK_T::STATUS: BUSY Position */
<> 149:156823d33999 13829 #define TK_STATUS_BUSY_Msk (0x1ul << TK_STATUS_BUSY_Pos) /*!< TK_T::STATUS: BUSY Mask */
<> 149:156823d33999 13830
<> 149:156823d33999 13831 #define TK_STATUS_SCIF_Pos (1) /*!< TK_T::STATUS: SCIF Position */
<> 149:156823d33999 13832 #define TK_STATUS_SCIF_Msk (0x1ul << TK_STATUS_SCIF_Pos) /*!< TK_T::STATUS: SCIF Mask */
<> 149:156823d33999 13833
<> 149:156823d33999 13834 #define TK_STATUS_TKIF0_Pos (8) /*!< TK_T::STATUS: TKIF0 Position */
<> 149:156823d33999 13835 #define TK_STATUS_TKIF0_Msk (0x1ul << TK_STATUS_TKIF0_Pos) /*!< TK_T::STATUS: TKIF0 Mask */
<> 149:156823d33999 13836
<> 149:156823d33999 13837 #define TK_STATUS_TKIF1_Pos (9) /*!< TK_T::STATUS: TKIF1 Position */
<> 149:156823d33999 13838 #define TK_STATUS_TKIF1_Msk (0x1ul << TK_STATUS_TKIF1_Pos) /*!< TK_T::STATUS: TKIF1 Mask */
<> 149:156823d33999 13839
<> 149:156823d33999 13840 #define TK_STATUS_TKIF2_Pos (10) /*!< TK_T::STATUS: TKIF2 Position */
<> 149:156823d33999 13841 #define TK_STATUS_TKIF2_Msk (0x1ul << TK_STATUS_TKIF2_Pos) /*!< TK_T::STATUS: TKIF2 Mask */
<> 149:156823d33999 13842
<> 149:156823d33999 13843 #define TK_STATUS_TKIF3_Pos (11) /*!< TK_T::STATUS: TKIF3 Position */
<> 149:156823d33999 13844 #define TK_STATUS_TKIF3_Msk (0x1ul << TK_STATUS_TKIF3_Pos) /*!< TK_T::STATUS: TKIF3 Mask */
<> 149:156823d33999 13845
<> 149:156823d33999 13846 #define TK_STATUS_TKIF4_Pos (12) /*!< TK_T::STATUS: TKIF4 Position */
<> 149:156823d33999 13847 #define TK_STATUS_TKIF4_Msk (0x1ul << TK_STATUS_TKIF4_Pos) /*!< TK_T::STATUS: TKIF4 Mask */
<> 149:156823d33999 13848
<> 149:156823d33999 13849 #define TK_STATUS_TKIF5_Pos (13) /*!< TK_T::STATUS: TKIF5 Position */
<> 149:156823d33999 13850 #define TK_STATUS_TKIF5_Msk (0x1ul << TK_STATUS_TKIF5_Pos) /*!< TK_T::STATUS: TKIF5 Mask */
<> 149:156823d33999 13851
<> 149:156823d33999 13852 #define TK_STATUS_TKIF6_Pos (14) /*!< TK_T::STATUS: TKIF6 Position */
<> 149:156823d33999 13853 #define TK_STATUS_TKIF6_Msk (0x1ul << TK_STATUS_TKIF6_Pos) /*!< TK_T::STATUS: TKIF6 Mask */
<> 149:156823d33999 13854
<> 149:156823d33999 13855 #define TK_STATUS_TKIF7_Pos (15) /*!< TK_T::STATUS: TKIF7 Position */
<> 149:156823d33999 13856 #define TK_STATUS_TKIF7_Msk (0x1ul << TK_STATUS_TKIF7_Pos) /*!< TK_T::STATUS: TKIF7 Mask */
<> 149:156823d33999 13857
<> 149:156823d33999 13858 #define TK_STATUS_TKIF8_Pos (16) /*!< TK_T::STATUS: TKIF8 Position */
<> 149:156823d33999 13859 #define TK_STATUS_TKIF8_Msk (0x1ul << TK_STATUS_TKIF8_Pos) /*!< TK_T::STATUS: TKIF8 Mask */
<> 149:156823d33999 13860
<> 149:156823d33999 13861 #define TK_STATUS_TKIF9_Pos (17) /*!< TK_T::STATUS: TKIF9 Position */
<> 149:156823d33999 13862 #define TK_STATUS_TKIF9_Msk (0x1ul << TK_STATUS_TKIF9_Pos) /*!< TK_T::STATUS: TKIF9 Mask */
<> 149:156823d33999 13863
<> 149:156823d33999 13864 #define TK_STATUS_TKIF10_Pos (18) /*!< TK_T::STATUS: TKIF10 Position */
<> 149:156823d33999 13865 #define TK_STATUS_TKIF10_Msk (0x1ul << TK_STATUS_TKIF10_Pos) /*!< TK_T::STATUS: TKIF10 Mask */
<> 149:156823d33999 13866
<> 149:156823d33999 13867 #define TK_STATUS_TKIF11_Pos (19) /*!< TK_T::STATUS: TKIF11 Position */
<> 149:156823d33999 13868 #define TK_STATUS_TKIF11_Msk (0x1ul << TK_STATUS_TKIF11_Pos) /*!< TK_T::STATUS: TKIF11 Mask */
<> 149:156823d33999 13869
<> 149:156823d33999 13870 #define TK_STATUS_TKIF12_Pos (20) /*!< TK_T::STATUS: TKIF12 Position */
<> 149:156823d33999 13871 #define TK_STATUS_TKIF12_Msk (0x1ul << TK_STATUS_TKIF12_Pos) /*!< TK_T::STATUS: TKIF12 Mask */
<> 149:156823d33999 13872
<> 149:156823d33999 13873 #define TK_STATUS_TKIF13_Pos (21) /*!< TK_T::STATUS: TKIF13 Position */
<> 149:156823d33999 13874 #define TK_STATUS_TKIF13_Msk (0x1ul << TK_STATUS_TKIF13_Pos) /*!< TK_T::STATUS: TKIF13 Mask */
<> 149:156823d33999 13875
<> 149:156823d33999 13876 #define TK_STATUS_TKIF14_Pos (22) /*!< TK_T::STATUS: TKIF14 Position */
<> 149:156823d33999 13877 #define TK_STATUS_TKIF14_Msk (0x1ul << TK_STATUS_TKIF14_Pos) /*!< TK_T::STATUS: TKIF14 Mask */
<> 149:156823d33999 13878
<> 149:156823d33999 13879 #define TK_STATUS_TKIF15_Pos (23) /*!< TK_T::STATUS: TKIF15 Position */
<> 149:156823d33999 13880 #define TK_STATUS_TKIF15_Msk (0x1ul << TK_STATUS_TKIF15_Pos) /*!< TK_T::STATUS: TKIF15 Mask */
<> 149:156823d33999 13881
<> 149:156823d33999 13882 #define TK_STATUS_TKIF16_Pos (24) /*!< TK_T::STATUS: TKIF16 Position */
<> 149:156823d33999 13883 #define TK_STATUS_TKIF16_Msk (0x1ul << TK_STATUS_TKIF16_Pos) /*!< TK_T::STATUS: TKIF16 Mask */
<> 149:156823d33999 13884
<> 149:156823d33999 13885 #define TK_DAT0_TKDAT0_Pos (0) /*!< TK_T::DAT0: TKDAT0 Position */
<> 149:156823d33999 13886 #define TK_DAT0_TKDAT0_Msk (0xfful << TK_DAT0_TKDAT0_Pos) /*!< TK_T::DAT0: TKDAT0 Mask */
<> 149:156823d33999 13887
<> 149:156823d33999 13888 #define TK_DAT0_TKDAT1_Pos (8) /*!< TK_T::DAT0: TKDAT1 Position */
<> 149:156823d33999 13889 #define TK_DAT0_TKDAT1_Msk (0xfful << TK_DAT0_TKDAT1_Pos) /*!< TK_T::DAT0: TKDAT1 Mask */
<> 149:156823d33999 13890
<> 149:156823d33999 13891 #define TK_DAT0_TKDAT2_Pos (16) /*!< TK_T::DAT0: TKDAT2 Position */
<> 149:156823d33999 13892 #define TK_DAT0_TKDAT2_Msk (0xfful << TK_DAT0_TKDAT2_Pos) /*!< TK_T::DAT0: TKDAT2 Mask */
<> 149:156823d33999 13893
<> 149:156823d33999 13894 #define TK_DAT0_TKDAT3_Pos (24) /*!< TK_T::DAT0: TKDAT3 Position */
<> 149:156823d33999 13895 #define TK_DAT0_TKDAT3_Msk (0xfful << TK_DAT0_TKDAT3_Pos) /*!< TK_T::DAT0: TKDAT3 Mask */
<> 149:156823d33999 13896
<> 149:156823d33999 13897 #define TK_DAT1_TKDAT4_Pos (0) /*!< TK_T::DAT1: TKDAT4 Position */
<> 149:156823d33999 13898 #define TK_DAT1_TKDAT4_Msk (0xfful << TK_DAT1_TKDAT4_Pos) /*!< TK_T::DAT1: TKDAT4 Mask */
<> 149:156823d33999 13899
<> 149:156823d33999 13900 #define TK_DAT1_TKDAT5_Pos (8) /*!< TK_T::DAT1: TKDAT5 Position */
<> 149:156823d33999 13901 #define TK_DAT1_TKDAT5_Msk (0xfful << TK_DAT1_TKDAT5_Pos) /*!< TK_T::DAT1: TKDAT5 Mask */
<> 149:156823d33999 13902
<> 149:156823d33999 13903 #define TK_DAT1_TKDAT6_Pos (16) /*!< TK_T::DAT1: TKDAT6 Position */
<> 149:156823d33999 13904 #define TK_DAT1_TKDAT6_Msk (0xfful << TK_DAT1_TKDAT6_Pos) /*!< TK_T::DAT1: TKDAT6 Mask */
<> 149:156823d33999 13905
<> 149:156823d33999 13906 #define TK_DAT1_TKDAT7_Pos (24) /*!< TK_T::DAT1: TKDAT7 Position */
<> 149:156823d33999 13907 #define TK_DAT1_TKDAT7_Msk (0xfful << TK_DAT1_TKDAT7_Pos) /*!< TK_T::DAT1: TKDAT7 Mask */
<> 149:156823d33999 13908
<> 149:156823d33999 13909 #define TK_DAT2_TKDAT8_Pos (0) /*!< TK_T::DAT2: TKDAT8 Position */
<> 149:156823d33999 13910 #define TK_DAT2_TKDAT8_Msk (0xfful << TK_DAT2_TKDAT8_Pos) /*!< TK_T::DAT2: TKDAT8 Mask */
<> 149:156823d33999 13911
<> 149:156823d33999 13912 #define TK_DAT2_TKDAT9_Pos (8) /*!< TK_T::DAT2: TKDAT9 Position */
<> 149:156823d33999 13913 #define TK_DAT2_TKDAT9_Msk (0xfful << TK_DAT2_TKDAT9_Pos) /*!< TK_T::DAT2: TKDAT9 Mask */
<> 149:156823d33999 13914
<> 149:156823d33999 13915 #define TK_DAT2_TKDAT10_Pos (16) /*!< TK_T::DAT2: TKDAT10 Position */
<> 149:156823d33999 13916 #define TK_DAT2_TKDAT10_Msk (0xfful << TK_DAT2_TKDAT10_Pos) /*!< TK_T::DAT2: TKDAT10 Mask */
<> 149:156823d33999 13917
<> 149:156823d33999 13918 #define TK_DAT2_TKDAT11_Pos (24) /*!< TK_T::DAT2: TKDAT11 Position */
<> 149:156823d33999 13919 #define TK_DAT2_TKDAT11_Msk (0xfful << TK_DAT2_TKDAT11_Pos) /*!< TK_T::DAT2: TKDAT11 Mask */
<> 149:156823d33999 13920
<> 149:156823d33999 13921 #define TK_DAT3_TKDAT12_Pos (0) /*!< TK_T::DAT3: TKDAT12 Position */
<> 149:156823d33999 13922 #define TK_DAT3_TKDAT12_Msk (0xfful << TK_DAT3_TKDAT12_Pos) /*!< TK_T::DAT3: TKDAT12 Mask */
<> 149:156823d33999 13923
<> 149:156823d33999 13924 #define TK_DAT3_TKDAT13_Pos (8) /*!< TK_T::DAT3: TKDAT13 Position */
<> 149:156823d33999 13925 #define TK_DAT3_TKDAT13_Msk (0xfful << TK_DAT3_TKDAT13_Pos) /*!< TK_T::DAT3: TKDAT13 Mask */
<> 149:156823d33999 13926
<> 149:156823d33999 13927 #define TK_DAT3_TKDAT14_Pos (16) /*!< TK_T::DAT3: TKDAT14 Position */
<> 149:156823d33999 13928 #define TK_DAT3_TKDAT14_Msk (0xfful << TK_DAT3_TKDAT14_Pos) /*!< TK_T::DAT3: TKDAT14 Mask */
<> 149:156823d33999 13929
<> 149:156823d33999 13930 #define TK_DAT3_TKDAT15_Pos (24) /*!< TK_T::DAT3: TKDAT15 Position */
<> 149:156823d33999 13931 #define TK_DAT3_TKDAT15_Msk (0xfful << TK_DAT3_TKDAT15_Pos) /*!< TK_T::DAT3: TKDAT15 Mask */
<> 149:156823d33999 13932
<> 149:156823d33999 13933 #define TK_DAT4_TKDAT16_Pos (0) /*!< TK_T::DAT4: TKDAT16 Position */
<> 149:156823d33999 13934 #define TK_DAT4_TKDAT16_Msk (0xfful << TK_DAT4_TKDAT16_Pos) /*!< TK_T::DAT4: TKDAT16 Mask */
<> 149:156823d33999 13935
<> 149:156823d33999 13936 #define TK_INTEN_SCTHIEN_Pos (0) /*!< TK_T::INTEN: SCTHIEN Position */
<> 149:156823d33999 13937 #define TK_INTEN_SCTHIEN_Msk (0x1ul << TK_INTEN_SCTHIEN_Pos) /*!< TK_T::INTEN: SCTHIEN Mask */
<> 149:156823d33999 13938
<> 149:156823d33999 13939 #define TK_INTEN_SCINTEN_Pos (1) /*!< TK_T::INTEN: SCINTEN Position */
<> 149:156823d33999 13940 #define TK_INTEN_SCINTEN_Msk (0x1ul << TK_INTEN_SCINTEN_Pos) /*!< TK_T::INTEN: SCINTEN Mask */
<> 149:156823d33999 13941
<> 149:156823d33999 13942 #define TK_INTEN_THIMOD_Pos (31) /*!< TK_T::INTEN: THIMOD Position */
<> 149:156823d33999 13943 #define TK_INTEN_THIMOD_Msk (0x1ul << TK_INTEN_THIMOD_Pos) /*!< TK_T::INTEN: THIMOD Mask */
<> 149:156823d33999 13944
<> 149:156823d33999 13945 #define TK_TH0_1_LTH0_Pos (0) /*!< TK_T::TH0_1: LTH0 Position */
<> 149:156823d33999 13946 #define TK_TH0_1_LTH0_Msk (0xfful << TK_TH0_1_LTH0_Pos) /*!< TK_T::TH0_1: LTH0 Mask */
<> 149:156823d33999 13947
<> 149:156823d33999 13948 #define TK_TH0_1_HTH0_Pos (8) /*!< TK_T::TH0_1: HTH0 Position */
<> 149:156823d33999 13949 #define TK_TH0_1_HTH0_Msk (0xfful << TK_TH0_1_HTH0_Pos) /*!< TK_T::TH0_1: HTH0 Mask */
<> 149:156823d33999 13950
<> 149:156823d33999 13951 #define TK_TH0_1_LTH1_Pos (16) /*!< TK_T::TH0_1: LTH1 Position */
<> 149:156823d33999 13952 #define TK_TH0_1_LTH1_Msk (0xfful << TK_TH0_1_LTH1_Pos) /*!< TK_T::TH0_1: LTH1 Mask */
<> 149:156823d33999 13953
<> 149:156823d33999 13954 #define TK_TH0_1_HTH1_Pos (24) /*!< TK_T::TH0_1: HTH1 Position */
<> 149:156823d33999 13955 #define TK_TH0_1_HTH1_Msk (0xfful << TK_TH0_1_HTH1_Pos) /*!< TK_T::TH0_1: HTH1 Mask */
<> 149:156823d33999 13956
<> 149:156823d33999 13957 #define TK_TH2_3_LTH2_Pos (0) /*!< TK_T::TH2_3: LTH2 Position */
<> 149:156823d33999 13958 #define TK_TH2_3_LTH2_Msk (0xfful << TK_TH2_3_LTH2_Pos) /*!< TK_T::TH2_3: LTH2 Mask */
<> 149:156823d33999 13959
<> 149:156823d33999 13960 #define TK_TH2_3_HTH2_Pos (8) /*!< TK_T::TH2_3: HTH2 Position */
<> 149:156823d33999 13961 #define TK_TH2_3_HTH2_Msk (0xfful << TK_TH2_3_HTH2_Pos) /*!< TK_T::TH2_3: HTH2 Mask */
<> 149:156823d33999 13962
<> 149:156823d33999 13963 #define TK_TH2_3_LTH3_Pos (16) /*!< TK_T::TH2_3: LTH3 Position */
<> 149:156823d33999 13964 #define TK_TH2_3_LTH3_Msk (0xfful << TK_TH2_3_LTH3_Pos) /*!< TK_T::TH2_3: LTH3 Mask */
<> 149:156823d33999 13965
<> 149:156823d33999 13966 #define TK_TH2_3_HTH3_Pos (24) /*!< TK_T::TH2_3: HTH3 Position */
<> 149:156823d33999 13967 #define TK_TH2_3_HTH3_Msk (0xfful << TK_TH2_3_HTH3_Pos) /*!< TK_T::TH2_3: HTH3 Mask */
<> 149:156823d33999 13968
<> 149:156823d33999 13969 #define TK_TH4_5_LTH4_Pos (0) /*!< TK_T::TH4_5: LTH4 Position */
<> 149:156823d33999 13970 #define TK_TH4_5_LTH4_Msk (0xfful << TK_TH4_5_LTH4_Pos) /*!< TK_T::TH4_5: LTH4 Mask */
<> 149:156823d33999 13971
<> 149:156823d33999 13972 #define TK_TH4_5_HTH4_Pos (8) /*!< TK_T::TH4_5: HTH4 Position */
<> 149:156823d33999 13973 #define TK_TH4_5_HTH4_Msk (0xfful << TK_TH4_5_HTH4_Pos) /*!< TK_T::TH4_5: HTH4 Mask */
<> 149:156823d33999 13974
<> 149:156823d33999 13975 #define TK_TH4_5_LTH5_Pos (16) /*!< TK_T::TH4_5: LTH5 Position */
<> 149:156823d33999 13976 #define TK_TH4_5_LTH5_Msk (0xfful << TK_TH4_5_LTH5_Pos) /*!< TK_T::TH4_5: LTH5 Mask */
<> 149:156823d33999 13977
<> 149:156823d33999 13978 #define TK_TH4_5_HTH5_Pos (24) /*!< TK_T::TH4_5: HTH5 Position */
<> 149:156823d33999 13979 #define TK_TH4_5_HTH5_Msk (0xfful << TK_TH4_5_HTH5_Pos) /*!< TK_T::TH4_5: HTH5 Mask */
<> 149:156823d33999 13980
<> 149:156823d33999 13981 #define TK_TH6_7_LTH6_Pos (0) /*!< TK_T::TH6_7: LTH6 Position */
<> 149:156823d33999 13982 #define TK_TH6_7_LTH6_Msk (0xfful << TK_TH6_7_LTH6_Pos) /*!< TK_T::TH6_7: LTH6 Mask */
<> 149:156823d33999 13983
<> 149:156823d33999 13984 #define TK_TH6_7_HTH6_Pos (8) /*!< TK_T::TH6_7: HTH6 Position */
<> 149:156823d33999 13985 #define TK_TH6_7_HTH6_Msk (0xfful << TK_TH6_7_HTH6_Pos) /*!< TK_T::TH6_7: HTH6 Mask */
<> 149:156823d33999 13986
<> 149:156823d33999 13987 #define TK_TH6_7_LTH7_Pos (16) /*!< TK_T::TH6_7: LTH7 Position */
<> 149:156823d33999 13988 #define TK_TH6_7_LTH7_Msk (0xfful << TK_TH6_7_LTH7_Pos) /*!< TK_T::TH6_7: LTH7 Mask */
<> 149:156823d33999 13989
<> 149:156823d33999 13990 #define TK_TH6_7_HTH7_Pos (24) /*!< TK_T::TH6_7: HTH7 Position */
<> 149:156823d33999 13991 #define TK_TH6_7_HTH7_Msk (0xfful << TK_TH6_7_HTH7_Pos) /*!< TK_T::TH6_7: HTH7 Mask */
<> 149:156823d33999 13992
<> 149:156823d33999 13993 #define TK_TH8_9_LTH8_Pos (0) /*!< TK_T::TH8_9: LTH8 Position */
<> 149:156823d33999 13994 #define TK_TH8_9_LTH8_Msk (0xfful << TK_TH8_9_LTH8_Pos) /*!< TK_T::TH8_9: LTH8 Mask */
<> 149:156823d33999 13995
<> 149:156823d33999 13996 #define TK_TH8_9_HTH8_Pos (8) /*!< TK_T::TH8_9: HTH8 Position */
<> 149:156823d33999 13997 #define TK_TH8_9_HTH8_Msk (0xfful << TK_TH8_9_HTH8_Pos) /*!< TK_T::TH8_9: HTH8 Mask */
<> 149:156823d33999 13998
<> 149:156823d33999 13999 #define TK_TH8_9_LTH9_Pos (16) /*!< TK_T::TH8_9: LTH9 Position */
<> 149:156823d33999 14000 #define TK_TH8_9_LTH9_Msk (0xfful << TK_TH8_9_LTH9_Pos) /*!< TK_T::TH8_9: LTH9 Mask */
<> 149:156823d33999 14001
<> 149:156823d33999 14002 #define TK_TH8_9_HTH9_Pos (24) /*!< TK_T::TH8_9: HTH9 Position */
<> 149:156823d33999 14003 #define TK_TH8_9_HTH9_Msk (0xfful << TK_TH8_9_HTH9_Pos) /*!< TK_T::TH8_9: HTH9 Mask */
<> 149:156823d33999 14004
<> 149:156823d33999 14005 #define TK_TH10_11_LTH10_Pos (0) /*!< TK_T::TH10_11: LTH10 Position */
<> 149:156823d33999 14006 #define TK_TH10_11_LTH10_Msk (0xfful << TK_TH10_11_LTH10_Pos) /*!< TK_T::TH10_11: LTH10 Mask */
<> 149:156823d33999 14007
<> 149:156823d33999 14008 #define TK_TH10_11_HTH10_Pos (8) /*!< TK_T::TH10_11: HTH10 Position */
<> 149:156823d33999 14009 #define TK_TH10_11_HTH10_Msk (0xfful << TK_TH10_11_HTH10_Pos) /*!< TK_T::TH10_11: HTH10 Mask */
<> 149:156823d33999 14010
<> 149:156823d33999 14011 #define TK_TH10_11_LTH11_Pos (16) /*!< TK_T::TH10_11: LTH11 Position */
<> 149:156823d33999 14012 #define TK_TH10_11_LTH11_Msk (0xfful << TK_TH10_11_LTH11_Pos) /*!< TK_T::TH10_11: LTH11 Mask */
<> 149:156823d33999 14013
<> 149:156823d33999 14014 #define TK_TH10_11_HTH11_Pos (24) /*!< TK_T::TH10_11: HTH11 Position */
<> 149:156823d33999 14015 #define TK_TH10_11_HTH11_Msk (0xfful << TK_TH10_11_HTH11_Pos) /*!< TK_T::TH10_11: HTH11 Mask */
<> 149:156823d33999 14016
<> 149:156823d33999 14017 #define TK_TH12_13_LTH12_Pos (0) /*!< TK_T::TH12_13: LTH12 Position */
<> 149:156823d33999 14018 #define TK_TH12_13_LTH12_Msk (0xfful << TK_TH12_13_LTH12_Pos) /*!< TK_T::TH12_13: LTH12 Mask */
<> 149:156823d33999 14019
<> 149:156823d33999 14020 #define TK_TH12_13_HTH12_Pos (8) /*!< TK_T::TH12_13: HTH12 Position */
<> 149:156823d33999 14021 #define TK_TH12_13_HTH12_Msk (0xfful << TK_TH12_13_HTH12_Pos) /*!< TK_T::TH12_13: HTH12 Mask */
<> 149:156823d33999 14022
<> 149:156823d33999 14023 #define TK_TH12_13_LTH13_Pos (16) /*!< TK_T::TH12_13: LTH13 Position */
<> 149:156823d33999 14024 #define TK_TH12_13_LTH13_Msk (0xfful << TK_TH12_13_LTH13_Pos) /*!< TK_T::TH12_13: LTH13 Mask */
<> 149:156823d33999 14025
<> 149:156823d33999 14026 #define TK_TH12_13_HTH13_Pos (24) /*!< TK_T::TH12_13: HTH13 Position */
<> 149:156823d33999 14027 #define TK_TH12_13_HTH13_Msk (0xfful << TK_TH12_13_HTH13_Pos) /*!< TK_T::TH12_13: HTH13 Mask */
<> 149:156823d33999 14028
<> 149:156823d33999 14029 #define TK_TH14_15_LTH14_Pos (0) /*!< TK_T::TH14_15: LTH14 Position */
<> 149:156823d33999 14030 #define TK_TH14_15_LTH14_Msk (0xfful << TK_TH14_15_LTH14_Pos) /*!< TK_T::TH14_15: LTH14 Mask */
<> 149:156823d33999 14031
<> 149:156823d33999 14032 #define TK_TH14_15_HTH14_Pos (8) /*!< TK_T::TH14_15: HTH14 Position */
<> 149:156823d33999 14033 #define TK_TH14_15_HTH14_Msk (0xfful << TK_TH14_15_HTH14_Pos) /*!< TK_T::TH14_15: HTH14 Mask */
<> 149:156823d33999 14034
<> 149:156823d33999 14035 #define TK_TH14_15_LTH15_Pos (16) /*!< TK_T::TH14_15: LTH15 Position */
<> 149:156823d33999 14036 #define TK_TH14_15_LTH15_Msk (0xfful << TK_TH14_15_LTH15_Pos) /*!< TK_T::TH14_15: LTH15 Mask */
<> 149:156823d33999 14037
<> 149:156823d33999 14038 #define TK_TH14_15_HTH15_Pos (24) /*!< TK_T::TH14_15: HTH15 Position */
<> 149:156823d33999 14039 #define TK_TH14_15_HTH15_Msk (0xfful << TK_TH14_15_HTH15_Pos) /*!< TK_T::TH14_15: HTH15 Mask */
<> 149:156823d33999 14040
<> 149:156823d33999 14041 #define TK_TH16_LTH16_Pos (0) /*!< TK_T::TH16: LTH16 Position */
<> 149:156823d33999 14042 #define TK_TH16_LTH16_Msk (0xfful << TK_TH16_LTH16_Pos) /*!< TK_T::TH16: LTH16 Mask */
<> 149:156823d33999 14043
<> 149:156823d33999 14044 #define TK_TH16_HTH16_Pos (8) /*!< TK_T::TH16: HTH16 Position */
<> 149:156823d33999 14045 #define TK_TH16_HTH16_Msk (0xfful << TK_TH16_HTH16_Pos) /*!< TK_T::TH16: HTH16 Mask */
<> 149:156823d33999 14046
<> 149:156823d33999 14047 /**@}*/ /* TK_CONST */
<> 149:156823d33999 14048 /**@}*/ /* end of TK register group */
<> 149:156823d33999 14049
<> 149:156823d33999 14050
<> 149:156823d33999 14051 /*---------------------- Timer Controller -------------------------*/
<> 149:156823d33999 14052 /**
<> 149:156823d33999 14053 @addtogroup TMR Timer Controller(TMR)
<> 149:156823d33999 14054 Memory Mapped Structure for TMR Controller
<> 149:156823d33999 14055 @{ */
<> 149:156823d33999 14056
<> 149:156823d33999 14057
<> 149:156823d33999 14058 typedef struct
<> 149:156823d33999 14059 {
<> 149:156823d33999 14060
<> 149:156823d33999 14061
<> 149:156823d33999 14062
<> 149:156823d33999 14063
<> 149:156823d33999 14064 /**
<> 149:156823d33999 14065 * @var TIMER_T::CTL
<> 149:156823d33999 14066 * Offset: 0x00 Timer Control and Status Register
<> 149:156823d33999 14067 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14068 * |Bits |Field |Descriptions
<> 149:156823d33999 14069 * | :----: | :----: | :---- |
<> 149:156823d33999 14070 * |[7:0] |PSC |Prescale Counter
<> 149:156823d33999 14071 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
<> 149:156823d33999 14072 * | | |If this field is 0 (PSC = 0), then there is no scaling.
<> 149:156823d33999 14073 * |[17] |WKTKEN |Wake-Up Touch-Key Scan Enable Bit
<> 149:156823d33999 14074 * | | |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
<> 149:156823d33999 14075 * | | |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
<> 149:156823d33999 14076 * | | |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
<> 149:156823d33999 14077 * | | |Note: This bit is only available in TIMER0_CTL.
<> 149:156823d33999 14078 * |[18] |TRGSSEL |Trigger Source Select Bit
<> 149:156823d33999 14079 * | | |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
<> 149:156823d33999 14080 * | | |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
<> 149:156823d33999 14081 * | | |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
<> 149:156823d33999 14082 * |[19] |TRGPWM |Trigger PWM Enable Bit
<> 149:156823d33999 14083 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
<> 149:156823d33999 14084 * | | |0 = Timer interrupt trigger PWM Disabled.
<> 149:156823d33999 14085 * | | |1 = Timer interrupt trigger PWM Enabled.
<> 149:156823d33999 14086 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
<> 149:156823d33999 14087 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
<> 149:156823d33999 14088 * |[20] |TRGDAC |Trigger DAC Enable Bit
<> 149:156823d33999 14089 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
<> 149:156823d33999 14090 * | | |0 = Timer interrupt trigger DAC Disabled.
<> 149:156823d33999 14091 * | | |1 = Timer interrupt trigger DAC Enabled.
<> 149:156823d33999 14092 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
<> 149:156823d33999 14093 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
<> 149:156823d33999 14094 * |[21] |TRGEADC |Trigger EADC Enable Bit
<> 149:156823d33999 14095 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
<> 149:156823d33999 14096 * | | |0 = Timer interrupt trigger EADC Disabled.
<> 149:156823d33999 14097 * | | |1 = Timer interrupt trigger EADC Enabled.
<> 149:156823d33999 14098 * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
<> 149:156823d33999 14099 * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
<> 149:156823d33999 14100 * |[22] |TGLPINSEL |Toggle-Output Pin Select
<> 149:156823d33999 14101 * | | |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
<> 149:156823d33999 14102 * | | |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
<> 149:156823d33999 14103 * |[23] |WKEN |Wake-Up Function Enable Bit
<> 149:156823d33999 14104 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
<> 149:156823d33999 14105 * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
<> 149:156823d33999 14106 * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
<> 149:156823d33999 14107 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
<> 149:156823d33999 14108 * | | |This bit is for external counting pin function enabled.
<> 149:156823d33999 14109 * | | |0 = Event counter mode Disabled.
<> 149:156823d33999 14110 * | | |1 = Event counter mode Enabled.
<> 149:156823d33999 14111 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
<> 149:156823d33999 14112 * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
<> 149:156823d33999 14113 * | | |This bit indicates the 24-bit up counter status.
<> 149:156823d33999 14114 * | | |0 = 24-bit up counter is not active.
<> 149:156823d33999 14115 * | | |1 = 24-bit up counter is active.
<> 149:156823d33999 14116 * |[26] |RSTCNT |Timer Counter Reset Bit
<> 149:156823d33999 14117 * | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
<> 149:156823d33999 14118 * | | |0 = No effect.
<> 149:156823d33999 14119 * | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
<> 149:156823d33999 14120 * |[28:27] |OPMODE |Timer Counting Mode Select
<> 149:156823d33999 14121 * | | |00 = The Timer controller is operated in One-shot mode.
<> 149:156823d33999 14122 * | | |01 = The Timer controller is operated in Periodic mode.
<> 149:156823d33999 14123 * | | |10 = The Timer controller is operated in Toggle-output mode.
<> 149:156823d33999 14124 * | | |11 = The Timer controller is operated in Continuous Counting mode.
<> 149:156823d33999 14125 * |[29] |INTEN |Timer Interrupt Enable Bit
<> 149:156823d33999 14126 * | | |0 = Timer Interrupt Disabled.
<> 149:156823d33999 14127 * | | |1 = Timer Interrupt Enabled.
<> 149:156823d33999 14128 * | | |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
<> 149:156823d33999 14129 * |[30] |CNTEN |Timer Counting Enable Bit
<> 149:156823d33999 14130 * | | |0 = Stops/Suspends counting.
<> 149:156823d33999 14131 * | | |1 = Starts counting.
<> 149:156823d33999 14132 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
<> 149:156823d33999 14133 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
<> 149:156823d33999 14134 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable
<> 149:156823d33999 14135 * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
<> 149:156823d33999 14136 * | | |TIMER counter will be held while CPU is held by ICE.
<> 149:156823d33999 14137 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 149:156823d33999 14138 * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
<> 149:156823d33999 14139 * @var TIMER_T::CMP
<> 149:156823d33999 14140 * Offset: 0x04 Timer Compare Register
<> 149:156823d33999 14141 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14142 * |Bits |Field |Descriptions
<> 149:156823d33999 14143 * | :----: | :----: | :---- |
<> 149:156823d33999 14144 * |[23:0] |CMPDAT |Timer Compared Value
<> 149:156823d33999 14145 * | | |CMPDAT is a 24-bit compared value register.
<> 149:156823d33999 14146 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
<> 149:156823d33999 14147 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
<> 149:156823d33999 14148 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
<> 149:156823d33999 14149 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
<> 149:156823d33999 14150 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
<> 149:156823d33999 14151 * @var TIMER_T::INTSTS
<> 149:156823d33999 14152 * Offset: 0x08 Timer Interrupt Status Register
<> 149:156823d33999 14153 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14154 * |Bits |Field |Descriptions
<> 149:156823d33999 14155 * | :----: | :----: | :---- |
<> 149:156823d33999 14156 * |[0] |TIF |Timer Interrupt Flag
<> 149:156823d33999 14157 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
<> 149:156823d33999 14158 * | | |0 = No effect.
<> 149:156823d33999 14159 * | | |1 = CNT value matches the CMPDAT value.
<> 149:156823d33999 14160 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 14161 * |[1] |TWKF |Timer Wake-Up Flag
<> 149:156823d33999 14162 * | | |This bit indicates the interrupt wake-up flag status of timer.
<> 149:156823d33999 14163 * | | |0 = Timer does not cause CPU wake-up.
<> 149:156823d33999 14164 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
<> 149:156823d33999 14165 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 14166 * @var TIMER_T::CNT
<> 149:156823d33999 14167 * Offset: 0x0C Timer Data Register
<> 149:156823d33999 14168 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14169 * |Bits |Field |Descriptions
<> 149:156823d33999 14170 * | :----: | :----: | :---- |
<> 149:156823d33999 14171 * |[23:0] |CNT |Timer Data Register
<> 149:156823d33999 14172 * | | |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
<> 149:156823d33999 14173 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
<> 149:156823d33999 14174 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
<> 149:156823d33999 14175 * @var TIMER_T::CAP
<> 149:156823d33999 14176 * Offset: 0x10 Timer Capture Data Register
<> 149:156823d33999 14177 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14178 * |Bits |Field |Descriptions
<> 149:156823d33999 14179 * | :----: | :----: | :---- |
<> 149:156823d33999 14180 * |[23:0] |CAPDAT |Timer Capture Data Register
<> 149:156823d33999 14181 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
<> 149:156823d33999 14182 * @var TIMER_T::EXTCTL
<> 149:156823d33999 14183 * Offset: 0x14 Timer External Control Register
<> 149:156823d33999 14184 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14185 * |Bits |Field |Descriptions
<> 149:156823d33999 14186 * | :----: | :----: | :---- |
<> 149:156823d33999 14187 * |[0] |CNTPHASE |Timer External Count Phase
<> 149:156823d33999 14188 * | | |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
<> 149:156823d33999 14189 * | | |0 = A Falling edge of external counting pin will be counted.
<> 149:156823d33999 14190 * | | |1 = A Rising edge of external counting pin will be counted.
<> 149:156823d33999 14191 * |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
<> 149:156823d33999 14192 * | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
<> 149:156823d33999 14193 * | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
<> 149:156823d33999 14194 * | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
<> 149:156823d33999 14195 * | | |11 = Reserved.
<> 149:156823d33999 14196 * |[3] |CAPEN |Timer External Capture Pin Enable
<> 149:156823d33999 14197 * | | |This bit enables the Tx_EXT pin.
<> 149:156823d33999 14198 * | | |0 =Tx_EXT (x= 0~3) pin Disabled.
<> 149:156823d33999 14199 * | | |1 =Tx_EXT (x= 0~3) pin Enabled.
<> 149:156823d33999 14200 * |[4] |CAPFUNCS |Capture Function Selection
<> 149:156823d33999 14201 * | | |0 = External Capture Mode Enabled.
<> 149:156823d33999 14202 * | | |1 = External Reset Mode Enabled.
<> 149:156823d33999 14203 * | | |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
<> 149:156823d33999 14204 * | | |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
<> 149:156823d33999 14205 * |[5] |CAPIEN |Timer External Capture Interrupt Enable
<> 149:156823d33999 14206 * | | |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
<> 149:156823d33999 14207 * | | |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
<> 149:156823d33999 14208 * | | |Note: CAPIEN is used to enable timer external interrupt.
<> 149:156823d33999 14209 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
<> 149:156823d33999 14210 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
<> 149:156823d33999 14211 * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
<> 149:156823d33999 14212 * | | |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
<> 149:156823d33999 14213 * | | |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
<> 149:156823d33999 14214 * | | |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
<> 149:156823d33999 14215 * |[7] |CNTDBEN |Timer Counter Pin De-Bounce Enable
<> 149:156823d33999 14216 * | | |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
<> 149:156823d33999 14217 * | | |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
<> 149:156823d33999 14218 * | | |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
<> 149:156823d33999 14219 * @var TIMER_T::EINTSTS
<> 149:156823d33999 14220 * Offset: 0x18 Timer External Interrupt Status Register
<> 149:156823d33999 14221 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14222 * |Bits |Field |Descriptions
<> 149:156823d33999 14223 * | :----: | :----: | :---- |
<> 149:156823d33999 14224 * |[0] |CAPIF |Timer External Capture Interrupt Flag
<> 149:156823d33999 14225 * | | |This bit indicates the timer external capture interrupt flag status.
<> 149:156823d33999 14226 * | | |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
<> 149:156823d33999 14227 * | | |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
<> 149:156823d33999 14228 * | | |Note1: This bit is cleared by writing 1 to it.
<> 149:156823d33999 14229 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
<> 149:156823d33999 14230 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
<> 149:156823d33999 14231 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
<> 149:156823d33999 14232 */
<> 149:156823d33999 14233
<> 149:156823d33999 14234 __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
<> 149:156823d33999 14235 __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
<> 149:156823d33999 14236 __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
<> 149:156823d33999 14237 __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
<> 149:156823d33999 14238 __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
<> 149:156823d33999 14239 __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
<> 149:156823d33999 14240 __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
<> 149:156823d33999 14241
<> 149:156823d33999 14242 } TIMER_T;
<> 149:156823d33999 14243
<> 149:156823d33999 14244
<> 149:156823d33999 14245
<> 149:156823d33999 14246 /**
<> 149:156823d33999 14247 @addtogroup TMR_CONST TMR Bit Field Definition
<> 149:156823d33999 14248 Constant Definitions for TMR Controller
<> 149:156823d33999 14249 @{ */
<> 149:156823d33999 14250
<> 149:156823d33999 14251 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
<> 149:156823d33999 14252 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
<> 149:156823d33999 14253
<> 149:156823d33999 14254 #define TIMER_CTL_WKTKEN_Pos (17) /*!< TIMER_T::CTL: WKTKEN Position */
<> 149:156823d33999 14255 #define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) /*!< TIMER_T::CTL: WKTKEN Mask */
<> 149:156823d33999 14256
<> 149:156823d33999 14257 #define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
<> 149:156823d33999 14258 #define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
<> 149:156823d33999 14259
<> 149:156823d33999 14260 #define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
<> 149:156823d33999 14261 #define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
<> 149:156823d33999 14262
<> 149:156823d33999 14263 #define TIMER_CTL_TRGDAC_Pos (20) /*!< TIMER_T::CTL: TRGDAC Position */
<> 149:156823d33999 14264 #define TIMER_CTL_TRGDAC_Msk (0x1ul << TIMER_CTL_TRGDAC_Pos) /*!< TIMER_T::CTL: TRGDAC Mask */
<> 149:156823d33999 14265
<> 149:156823d33999 14266 #define TIMER_CTL_TRGEADC_Pos (21) /*!< TIMER_T::CTL: TRGEADC Position */
<> 149:156823d33999 14267 #define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) /*!< TIMER_T::CTL: TRGEADC Mask */
<> 149:156823d33999 14268
<> 149:156823d33999 14269 #define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
<> 149:156823d33999 14270 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
<> 149:156823d33999 14271
<> 149:156823d33999 14272 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
<> 149:156823d33999 14273 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
<> 149:156823d33999 14274
<> 149:156823d33999 14275 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
<> 149:156823d33999 14276 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
<> 149:156823d33999 14277
<> 149:156823d33999 14278 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
<> 149:156823d33999 14279 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
<> 149:156823d33999 14280
<> 149:156823d33999 14281 #define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
<> 149:156823d33999 14282 #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
<> 149:156823d33999 14283
<> 149:156823d33999 14284 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
<> 149:156823d33999 14285 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
<> 149:156823d33999 14286
<> 149:156823d33999 14287 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
<> 149:156823d33999 14288 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
<> 149:156823d33999 14289
<> 149:156823d33999 14290 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
<> 149:156823d33999 14291 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
<> 149:156823d33999 14292
<> 149:156823d33999 14293 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
<> 149:156823d33999 14294 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
<> 149:156823d33999 14295
<> 149:156823d33999 14296 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
<> 149:156823d33999 14297 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
<> 149:156823d33999 14298
<> 149:156823d33999 14299 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
<> 149:156823d33999 14300 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
<> 149:156823d33999 14301
<> 149:156823d33999 14302 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
<> 149:156823d33999 14303 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
<> 149:156823d33999 14304
<> 149:156823d33999 14305 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
<> 149:156823d33999 14306 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
<> 149:156823d33999 14307
<> 149:156823d33999 14308 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
<> 149:156823d33999 14309 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
<> 149:156823d33999 14310
<> 149:156823d33999 14311 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
<> 149:156823d33999 14312 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
<> 149:156823d33999 14313
<> 149:156823d33999 14314 #define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
<> 149:156823d33999 14315 #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
<> 149:156823d33999 14316
<> 149:156823d33999 14317 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
<> 149:156823d33999 14318 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
<> 149:156823d33999 14319
<> 149:156823d33999 14320 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
<> 149:156823d33999 14321 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
<> 149:156823d33999 14322
<> 149:156823d33999 14323 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
<> 149:156823d33999 14324 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
<> 149:156823d33999 14325
<> 149:156823d33999 14326 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
<> 149:156823d33999 14327 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
<> 149:156823d33999 14328
<> 149:156823d33999 14329 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
<> 149:156823d33999 14330 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
<> 149:156823d33999 14331
<> 149:156823d33999 14332 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
<> 149:156823d33999 14333 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
<> 149:156823d33999 14334
<> 149:156823d33999 14335 /**@}*/ /* TIMER_CONST */
<> 149:156823d33999 14336 /**@}*/ /* end of TIMER register group */
<> 149:156823d33999 14337
<> 149:156823d33999 14338
<> 149:156823d33999 14339 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
<> 149:156823d33999 14340 /**
<> 149:156823d33999 14341 @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
<> 149:156823d33999 14342 Memory Mapped Structure for UART Controller
<> 149:156823d33999 14343 @{ */
<> 149:156823d33999 14344
<> 149:156823d33999 14345
<> 149:156823d33999 14346 typedef struct
<> 149:156823d33999 14347 {
<> 149:156823d33999 14348
<> 149:156823d33999 14349
<> 149:156823d33999 14350
<> 149:156823d33999 14351
<> 149:156823d33999 14352 /**
<> 149:156823d33999 14353 * @var UART_T::DAT
<> 149:156823d33999 14354 * Offset: 0x00 UART Receive/Transmit Buffer Register
<> 149:156823d33999 14355 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14356 * |Bits |Field |Descriptions
<> 149:156823d33999 14357 * | :----: | :----: | :---- |
<> 149:156823d33999 14358 * |[7:0] |DAT |Receiving/Transmit Buffer
<> 149:156823d33999 14359 * | | |Write Operation:
<> 149:156823d33999 14360 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
<> 149:156823d33999 14361 * | | |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
<> 149:156823d33999 14362 * | | |Read Operation:
<> 149:156823d33999 14363 * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
<> 149:156823d33999 14364 * @var UART_T::INTEN
<> 149:156823d33999 14365 * Offset: 0x04 UART Interrupt Enable Register
<> 149:156823d33999 14366 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14367 * |Bits |Field |Descriptions
<> 149:156823d33999 14368 * | :----: | :----: | :---- |
<> 149:156823d33999 14369 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
<> 149:156823d33999 14370 * | | |0 = Receive data available interrupt Disabled.
<> 149:156823d33999 14371 * | | |1 = Receive data available interrupt Enabled.
<> 149:156823d33999 14372 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
<> 149:156823d33999 14373 * | | |0 = Transmit holding register empty interrupt Disabled.
<> 149:156823d33999 14374 * | | |1 = Transmit holding register empty interrupt Enabled.
<> 149:156823d33999 14375 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
<> 149:156823d33999 14376 * | | |0 = Receive Line Status interrupt Disabled.
<> 149:156823d33999 14377 * | | |1 = Receive Line Status interrupt Enabled.
<> 149:156823d33999 14378 * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
<> 149:156823d33999 14379 * | | |0 = Modem status interrupt Disabled.
<> 149:156823d33999 14380 * | | |1 = Modem status interrupt Enabled.
<> 149:156823d33999 14381 * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Bit
<> 149:156823d33999 14382 * | | |0 = RX time-out interrupt Disabled.
<> 149:156823d33999 14383 * | | |1 = RX time-out interrupt Enabled.
<> 149:156823d33999 14384 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
<> 149:156823d33999 14385 * | | |0 = Buffer error interrupt Disabled.
<> 149:156823d33999 14386 * | | |1 = Buffer error interrupt Enabled.
<> 149:156823d33999 14387 * |[8] |LINIEN |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
<> 149:156823d33999 14388 * | | |0 = LIN bus interrupt Disabled.
<> 149:156823d33999 14389 * | | |1 = LIN bus interrupt Enabled.
<> 149:156823d33999 14390 * | | |Note: This bit is used for LIN function mode.
<> 149:156823d33999 14391 * |[9] |WKCTSIEN |nCTS Wake-Up Interrupt Enable Bit
<> 149:156823d33999 14392 * | | |0 = nCTS wake-up system function Disabled.
<> 149:156823d33999 14393 * | | |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
<> 149:156823d33999 14394 * |[10] |WKDATIEN |Incoming Data Wake-Up Interrupt Enable Bit
<> 149:156823d33999 14395 * | | |0 = Incoming data wake-up system function Disabled.
<> 149:156823d33999 14396 * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
<> 149:156823d33999 14397 * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
<> 149:156823d33999 14398 * |[11] |TOCNTEN |Time-Out Counter Enable Bit
<> 149:156823d33999 14399 * | | |0 = Time-out counter Disabled.
<> 149:156823d33999 14400 * | | |1 = Time-out counter Enabled.
<> 149:156823d33999 14401 * |[12] |ATORTSEN |nRTS Auto-Flow Control Enable Bit
<> 149:156823d33999 14402 * | | |0 = nRTS auto-flow control Disabled.
<> 149:156823d33999 14403 * | | |1 = nRTS auto-flow control Enabled.
<> 149:156823d33999 14404 * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
<> 149:156823d33999 14405 * |[13] |ATOCTSEN |nCTS Auto-Flow Control Enable Bit
<> 149:156823d33999 14406 * | | |0 = nCTS auto-flow control Disabled.
<> 149:156823d33999 14407 * | | |1 = nCTS auto-flow control Enabled.
<> 149:156823d33999 14408 * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
<> 149:156823d33999 14409 * |[14] |TXPDMAEN |TX DMA Enable Bit
<> 149:156823d33999 14410 * | | |This bit can enable or disable TX DMA service.
<> 149:156823d33999 14411 * | | |0 = TX DMA Disabled.
<> 149:156823d33999 14412 * | | |1 = TX DMA Enabled.
<> 149:156823d33999 14413 * |[15] |RXPDMAEN |RX DMA Enable Bit
<> 149:156823d33999 14414 * | | |This bit can enable or disable RX DMA service.
<> 149:156823d33999 14415 * | | |0 = RX DMA Disabled.
<> 149:156823d33999 14416 * | | |1 = RX DMA Enabled.
<> 149:156823d33999 14417 * |[18] |ABRIEN |Auto-Baud Rate Interrupt Enable Bit
<> 149:156823d33999 14418 * | | |0 = Auto-baud rate interrupt Disabled.
<> 149:156823d33999 14419 * | | |1 = Auto-baud rate interrupt Enabled.
<> 149:156823d33999 14420 * @var UART_T::FIFO
<> 149:156823d33999 14421 * Offset: 0x08 UART FIFO Control Register
<> 149:156823d33999 14422 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14423 * |Bits |Field |Descriptions
<> 149:156823d33999 14424 * | :----: | :----: | :---- |
<> 149:156823d33999 14425 * |[1] |RXRST |RX Field Software Reset
<> 149:156823d33999 14426 * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
<> 149:156823d33999 14427 * | | |0 = No effect.
<> 149:156823d33999 14428 * | | |1 = Reset the RX internal state machine and pointers.
<> 149:156823d33999 14429 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
<> 149:156823d33999 14430 * |[2] |TXRST |TX Field Software Reset
<> 149:156823d33999 14431 * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
<> 149:156823d33999 14432 * | | |0 = No effect.
<> 149:156823d33999 14433 * | | |1 = Reset the TX internal state machine and pointers.
<> 149:156823d33999 14434 * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
<> 149:156823d33999 14435 * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
<> 149:156823d33999 14436 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
<> 149:156823d33999 14437 * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
<> 149:156823d33999 14438 * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
<> 149:156823d33999 14439 * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
<> 149:156823d33999 14440 * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
<> 149:156823d33999 14441 * | | |Others = Reserved.
<> 149:156823d33999 14442 * |[8] |RXOFF |Receiver Disable
<> 149:156823d33999 14443 * | | |The receiver is disabled or not (set 1 to disable receiver)
<> 149:156823d33999 14444 * | | |0 = Receiver Enabled.
<> 149:156823d33999 14445 * | | |1 = Receiver Disabled.
<> 149:156823d33999 14446 * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.
<> 149:156823d33999 14447 * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
<> 149:156823d33999 14448 * |[19:16] |RTSTRGLV |nRTS Trigger Level For Auto-Flow Control Use
<> 149:156823d33999 14449 * | | |0000 = nRTS Trigger Level is 1 bytes.
<> 149:156823d33999 14450 * | | |0001 = nRTS Trigger Level is 4bytes.
<> 149:156823d33999 14451 * | | |0010 = nRTS Trigger Level is 8 bytes.
<> 149:156823d33999 14452 * | | |0011 = nRTS Trigger Level is 14 bytes.
<> 149:156823d33999 14453 * | | |Others = Reserved.
<> 149:156823d33999 14454 * | | |Note: This field is used for auto nRTS flow control.
<> 149:156823d33999 14455 * @var UART_T::LINE
<> 149:156823d33999 14456 * Offset: 0x0C UART Line Control Register
<> 149:156823d33999 14457 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14458 * |Bits |Field |Descriptions
<> 149:156823d33999 14459 * | :----: | :----: | :---- |
<> 149:156823d33999 14460 * |[1:0] |WLS |Word Length Selection
<> 149:156823d33999 14461 * | | |This field sets UART word length.
<> 149:156823d33999 14462 * | | |00 = 5 bits.
<> 149:156823d33999 14463 * | | |01 = 6 bits.
<> 149:156823d33999 14464 * | | |10 = 7 bits.
<> 149:156823d33999 14465 * | | |11 = 8 bits.
<> 149:156823d33999 14466 * |[2] |NSB |Number Of "STOP Bit"
<> 149:156823d33999 14467 * | | |0 = One "STOP bit" is generated in the transmitted data.
<> 149:156823d33999 14468 * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
<> 149:156823d33999 14469 * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
<> 149:156823d33999 14470 * |[3] |PBE |Parity Bit Enable Bit
<> 149:156823d33999 14471 * | | |0 = No parity bit generated Disabled.
<> 149:156823d33999 14472 * | | |1 = Parity bit generated Enabled.
<> 149:156823d33999 14473 * | | |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
<> 149:156823d33999 14474 * |[4] |EPE |Even Parity Enable Bit
<> 149:156823d33999 14475 * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
<> 149:156823d33999 14476 * | | |1 = Even number of logic 1's is transmitted and checked in each word.
<> 149:156823d33999 14477 * | | |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
<> 149:156823d33999 14478 * |[5] |SPE |Stick Parity Enable Bit
<> 149:156823d33999 14479 * | | |0 = Stick parity Disabled.
<> 149:156823d33999 14480 * | | |1 = Stick parity Enabled.
<> 149:156823d33999 14481 * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
<> 149:156823d33999 14482 * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
<> 149:156823d33999 14483 * |[6] |BCB |Break Control Bit
<> 149:156823d33999 14484 * | | |0 = Break Control Disabled.
<> 149:156823d33999 14485 * | | |1 = Break Control Enabled.
<> 149:156823d33999 14486 * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
<> 149:156823d33999 14487 * | | |This bit acts only on TX line and has no effect on the transmitter logic.
<> 149:156823d33999 14488 * @var UART_T::MODEM
<> 149:156823d33999 14489 * Offset: 0x10 UART Modem Control Register
<> 149:156823d33999 14490 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14491 * |Bits |Field |Descriptions
<> 149:156823d33999 14492 * | :----: | :----: | :---- |
<> 149:156823d33999 14493 * |[1] |RTS |nRTS (Request-To-Send) Signal Control
<> 149:156823d33999 14494 * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
<> 149:156823d33999 14495 * | | |0 = nRTS signal is active.
<> 149:156823d33999 14496 * | | |1 = nRTS signal is inactive.
<> 149:156823d33999 14497 * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
<> 149:156823d33999 14498 * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
<> 149:156823d33999 14499 * |[9] |RTSACTLV |nRTS Pin Active Level
<> 149:156823d33999 14500 * | | |This bit defines the active level state of nRTS pin output.
<> 149:156823d33999 14501 * | | |0 =n RTS pin output is high level active.
<> 149:156823d33999 14502 * | | |1 = nRTS pin output is low level active. (Default)
<> 149:156823d33999 14503 * | | |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
<> 149:156823d33999 14504 * | | |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
<> 149:156823d33999 14505 * |[13] |RTSSTS |nRTS Pin Status (Read Only)
<> 149:156823d33999 14506 * | | |This bit mirror from nRTS pin output of voltage logic status.
<> 149:156823d33999 14507 * | | |0 = nRTS pin output is low level voltage logic state.
<> 149:156823d33999 14508 * | | |1 = nRTS pin output is high level voltage logic state.
<> 149:156823d33999 14509 * @var UART_T::MODEMSTS
<> 149:156823d33999 14510 * Offset: 0x14 UART Modem Status Register
<> 149:156823d33999 14511 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14512 * |Bits |Field |Descriptions
<> 149:156823d33999 14513 * | :----: | :----: | :---- |
<> 149:156823d33999 14514 * |[0] |CTSDETF |Detect nCTS State Change Flag (Read Only)
<> 149:156823d33999 14515 * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
<> 149:156823d33999 14516 * | | |0 = nCTS input has not change state.
<> 149:156823d33999 14517 * | | |1 = nCTS input has change state.
<> 149:156823d33999 14518 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
<> 149:156823d33999 14519 * |[4] |CTSSTS |nCTS Pin Status (Read Only)
<> 149:156823d33999 14520 * | | |This bit mirror from nCTS pin input of voltage logic status.
<> 149:156823d33999 14521 * | | |0 = nCTS pin input is low level voltage logic state.
<> 149:156823d33999 14522 * | | |1 = nCTS pin input is high level voltage logic state.
<> 149:156823d33999 14523 * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
<> 149:156823d33999 14524 * |[8] |CTSACTLV |nCTS Pin Active Level
<> 149:156823d33999 14525 * | | |This bit defines the active level state of nCTS pin input.
<> 149:156823d33999 14526 * | | |0 = nCTS pin input is high level active.
<> 149:156823d33999 14527 * | | |1 = nCTS pin input is low level active. (Default)
<> 149:156823d33999 14528 * @var UART_T::FIFOSTS
<> 149:156823d33999 14529 * Offset: 0x18 UART FIFO Status Register
<> 149:156823d33999 14530 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14531 * |Bits |Field |Descriptions
<> 149:156823d33999 14532 * | :----: | :----: | :---- |
<> 149:156823d33999 14533 * |[0] |RXOVIF |RX Overflow Error Interrupt Flag (Read Only)
<> 149:156823d33999 14534 * | | |This bit is set when RX FIFO overflow.
<> 149:156823d33999 14535 * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
<> 149:156823d33999 14536 * | | |0 = RX FIFO is not overflow.
<> 149:156823d33999 14537 * | | |1 = RX FIFO is overflow.
<> 149:156823d33999 14538 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
<> 149:156823d33999 14539 * |[1] |ABRDIF |Auto-Baud Rate Detect Interrupt (Read Only)
<> 149:156823d33999 14540 * | | |0 = Auto-baud rate detect function is not finished.
<> 149:156823d33999 14541 * | | |1 = Auto-baud rate detect function is finished.
<> 149:156823d33999 14542 * | | |This bit is set to logic "1" when auto-baud rate detect function is finished.
<> 149:156823d33999 14543 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
<> 149:156823d33999 14544 * |[2] |ABRDTOIF |Auto-Baud Rate Time-Out Interrupt (Read Only)
<> 149:156823d33999 14545 * | | |0 = Auto-baud rate counter is underflow.
<> 149:156823d33999 14546 * | | |1 = Auto-baud rate counter is overflow.
<> 149:156823d33999 14547 * | | |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
<> 149:156823d33999 14548 * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
<> 149:156823d33999 14549 * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag (Read Only)
<> 149:156823d33999 14550 * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
<> 149:156823d33999 14551 * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
<> 149:156823d33999 14552 * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
<> 149:156823d33999 14553 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14554 * |[4] |PEF |Parity Error Flag (Read Only)
<> 149:156823d33999 14555 * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
<> 149:156823d33999 14556 * | | |0 = No parity error is generated.
<> 149:156823d33999 14557 * | | |1 = Parity error is generated.
<> 149:156823d33999 14558 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14559 * |[5] |FEF |Framing Error Flag (Read Only)
<> 149:156823d33999 14560 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
<> 149:156823d33999 14561 * | | |0 = No framing error is generated.
<> 149:156823d33999 14562 * | | |1 = Framing error is generated.
<> 149:156823d33999 14563 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14564 * |[6] |BIF |Break Interrupt Flag (Read Only)
<> 149:156823d33999 14565 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
<> 149:156823d33999 14566 * | | |0 = No Break interrupt is generated.
<> 149:156823d33999 14567 * | | |1 = Break interrupt is generated.
<> 149:156823d33999 14568 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14569 * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
<> 149:156823d33999 14570 * | | |This field indicates the RX FIFO Buffer Pointer.
<> 149:156823d33999 14571 * | | |When UART receives one byte from external device, RXPTR increases one.
<> 149:156823d33999 14572 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
<> 149:156823d33999 14573 * | | |The Maximum value shown in RXPTR is 15.
<> 149:156823d33999 14574 * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
<> 149:156823d33999 14575 * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
<> 149:156823d33999 14576 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
<> 149:156823d33999 14577 * | | |This bit initiate RX FIFO empty or not.
<> 149:156823d33999 14578 * | | |0 = RX FIFO is not empty.
<> 149:156823d33999 14579 * | | |1 = RX FIFO is empty.
<> 149:156823d33999 14580 * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
<> 149:156823d33999 14581 * | | |It will be cleared when UART receives any new data.
<> 149:156823d33999 14582 * |[15] |RXFULL |Receiver FIFO Full (Read Only)
<> 149:156823d33999 14583 * | | |This bit initiates RX FIFO full or not.
<> 149:156823d33999 14584 * | | |0 = RX FIFO is not full.
<> 149:156823d33999 14585 * | | |1 = RX FIFO is full.
<> 149:156823d33999 14586 * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
<> 149:156823d33999 14587 * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
<> 149:156823d33999 14588 * | | |This field indicates the TX FIFO Buffer Pointer.
<> 149:156823d33999 14589 * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
<> 149:156823d33999 14590 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
<> 149:156823d33999 14591 * | | |The Maximum value shown in TXPTR is 15.
<> 149:156823d33999 14592 * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
<> 149:156823d33999 14593 * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
<> 149:156823d33999 14594 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
<> 149:156823d33999 14595 * | | |This bit indicates TX FIFO empty or not.
<> 149:156823d33999 14596 * | | |0 = TX FIFO is not empty.
<> 149:156823d33999 14597 * | | |1 = TX FIFO is empty.
<> 149:156823d33999 14598 * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
<> 149:156823d33999 14599 * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
<> 149:156823d33999 14600 * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
<> 149:156823d33999 14601 * | | |This bit indicates TX FIFO full or not.
<> 149:156823d33999 14602 * | | |0 = TX FIFO is not full.
<> 149:156823d33999 14603 * | | |1 = TX FIFO is full.
<> 149:156823d33999 14604 * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
<> 149:156823d33999 14605 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
<> 149:156823d33999 14606 * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
<> 149:156823d33999 14607 * | | |0 = TX FIFO is not overflow.
<> 149:156823d33999 14608 * | | |1 = TX FIFO is overflow.
<> 149:156823d33999 14609 * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
<> 149:156823d33999 14610 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
<> 149:156823d33999 14611 * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
<> 149:156823d33999 14612 * | | |0 = TX FIFO is not empty.
<> 149:156823d33999 14613 * | | |1 = TX FIFO is empty.
<> 149:156823d33999 14614 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
<> 149:156823d33999 14615 * @var UART_T::INTSTS
<> 149:156823d33999 14616 * Offset: 0x1C UART Interrupt Status Register
<> 149:156823d33999 14617 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14618 * |Bits |Field |Descriptions
<> 149:156823d33999 14619 * | :----: | :----: | :---- |
<> 149:156823d33999 14620 * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
<> 149:156823d33999 14621 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
<> 149:156823d33999 14622 * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
<> 149:156823d33999 14623 * | | |0 = No RDA interrupt flag is generated.
<> 149:156823d33999 14624 * | | |1 = RDA interrupt flag is generated.
<> 149:156823d33999 14625 * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
<> 149:156823d33999 14626 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
<> 149:156823d33999 14627 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
<> 149:156823d33999 14628 * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
<> 149:156823d33999 14629 * | | |0 = No THRE interrupt flag is generated.
<> 149:156823d33999 14630 * | | |1 = THRE interrupt flag is generated.
<> 149:156823d33999 14631 * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
<> 149:156823d33999 14632 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
<> 149:156823d33999 14633 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
<> 149:156823d33999 14634 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
<> 149:156823d33999 14635 * | | |0 = No RLS interrupt flag is generated.
<> 149:156823d33999 14636 * | | |1 = RLS interrupt flag is generated.
<> 149:156823d33999 14637 * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
<> 149:156823d33999 14638 * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
<> 149:156823d33999 14639 * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
<> 149:156823d33999 14640 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
<> 149:156823d33999 14641 * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
<> 149:156823d33999 14642 * | | |0 = No Modem interrupt flag is generated.
<> 149:156823d33999 14643 * | | |1 = Modem interrupt flag is generated.
<> 149:156823d33999 14644 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
<> 149:156823d33999 14645 * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
<> 149:156823d33999 14646 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
<> 149:156823d33999 14647 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
<> 149:156823d33999 14648 * | | |0 = No Time-out interrupt flag is generated.
<> 149:156823d33999 14649 * | | |1 = Time-out interrupt flag is generated.
<> 149:156823d33999 14650 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
<> 149:156823d33999 14651 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
<> 149:156823d33999 14652 * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
<> 149:156823d33999 14653 * | | |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
<> 149:156823d33999 14654 * | | |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
<> 149:156823d33999 14655 * | | |0 = No buffer error interrupt flag is generated.
<> 149:156823d33999 14656 * | | |1 = Buffer error interrupt flag is generated.
<> 149:156823d33999 14657 * | | |Note: This bit is read only.
<> 149:156823d33999 14658 * | | |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
<> 149:156823d33999 14659 * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
<> 149:156823d33999 14660 * | | |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
<> 149:156823d33999 14661 * | | |0 = No DATWKIF and CTSWKIF are generated.
<> 149:156823d33999 14662 * | | |1 = DATWKIF or CTSWKIF.
<> 149:156823d33999 14663 * | | |Note: This bit is read only.
<> 149:156823d33999 14664 * | | |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
<> 149:156823d33999 14665 * |[7] |LINIF |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
<> 149:156823d33999 14666 * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
<> 149:156823d33999 14667 * | | |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
<> 149:156823d33999 14668 * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
<> 149:156823d33999 14669 * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
<> 149:156823d33999 14670 * | | |Note: This bit is read only.
<> 149:156823d33999 14671 * | | |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
<> 149:156823d33999 14672 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
<> 149:156823d33999 14673 * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
<> 149:156823d33999 14674 * | | |0 = No RDA interrupt is generated.
<> 149:156823d33999 14675 * | | |1 = RDA interrupt is generated.
<> 149:156823d33999 14676 * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
<> 149:156823d33999 14677 * | | |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
<> 149:156823d33999 14678 * | | |0 = No DATE interrupt is generated.
<> 149:156823d33999 14679 * | | |1 = DATE interrupt is generated.
<> 149:156823d33999 14680 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
<> 149:156823d33999 14681 * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
<> 149:156823d33999 14682 * | | |0 = No RLS interrupt is generated.
<> 149:156823d33999 14683 * | | |1 = RLS interrupt is generated.
<> 149:156823d33999 14684 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
<> 149:156823d33999 14685 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
<> 149:156823d33999 14686 * | | |0 = No Modem interrupt is generated.
<> 149:156823d33999 14687 * | | |1 = Modem interrupt is generated.
<> 149:156823d33999 14688 * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
<> 149:156823d33999 14689 * | | |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
<> 149:156823d33999 14690 * | | |0 = No Tout interrupt is generated.
<> 149:156823d33999 14691 * | | |1 = Tout interrupt is generated.
<> 149:156823d33999 14692 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
<> 149:156823d33999 14693 * | | |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
<> 149:156823d33999 14694 * | | |0 = No buffer error interrupt is generated.
<> 149:156823d33999 14695 * | | |1 = Buffer error interrupt is generated.
<> 149:156823d33999 14696 * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
<> 149:156823d33999 14697 * | | |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
<> 149:156823d33999 14698 * | | |0 = No LIN Bus interrupt is generated.
<> 149:156823d33999 14699 * | | |1 = The LIN Bus interrupt is generated.
<> 149:156823d33999 14700 * |[16] |CTSWKIF |nCTS Wake-Up Interrupt Flag (Read Only)
<> 149:156823d33999 14701 * | | |0 = Chip stays in power-down state.
<> 149:156823d33999 14702 * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
<> 149:156823d33999 14703 * | | |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
<> 149:156823d33999 14704 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14705 * |[17] |DATWKIF |Data Wake-Up Interrupt Flag (Read Only)
<> 149:156823d33999 14706 * | | |This bit is set if chip wake-up from power-down state by data wake-up.
<> 149:156823d33999 14707 * | | |0 = Chip stays in power-down state.
<> 149:156823d33999 14708 * | | |1 = Chip wake-up from power-down state by data wake-up.
<> 149:156823d33999 14709 * | | |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
<> 149:156823d33999 14710 * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
<> 149:156823d33999 14711 * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
<> 149:156823d33999 14712 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
<> 149:156823d33999 14713 * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
<> 149:156823d33999 14714 * | | |0 = No RLS interrupt flag is generated.
<> 149:156823d33999 14715 * | | |1 = RLS interrupt flag is generated.
<> 149:156823d33999 14716 * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
<> 149:156823d33999 14717 * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
<> 149:156823d33999 14718 * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
<> 149:156823d33999 14719 * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
<> 149:156823d33999 14720 * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
<> 149:156823d33999 14721 * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
<> 149:156823d33999 14722 * | | |0 = No Modem interrupt flag is generated.
<> 149:156823d33999 14723 * | | |1 = Modem interrupt flag is generated.
<> 149:156823d33999 14724 * | | |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
<> 149:156823d33999 14725 * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
<> 149:156823d33999 14726 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
<> 149:156823d33999 14727 * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
<> 149:156823d33999 14728 * | | |0 = No Time-out interrupt flag is generated.
<> 149:156823d33999 14729 * | | |1 = Time-out interrupt flag is generated.
<> 149:156823d33999 14730 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
<> 149:156823d33999 14731 * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
<> 149:156823d33999 14732 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
<> 149:156823d33999 14733 * | | |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
<> 149:156823d33999 14734 * | | |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
<> 149:156823d33999 14735 * | | |0 = No buffer error interrupt flag is generated.
<> 149:156823d33999 14736 * | | |1 = Buffer error interrupt flag is generated.
<> 149:156823d33999 14737 * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
<> 149:156823d33999 14738 * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
<> 149:156823d33999 14739 * | | |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
<> 149:156823d33999 14740 * | | |0 = No RLS interrupt is generated in DMA mode.
<> 149:156823d33999 14741 * | | |1 = RLS interrupt is generated in DMA mode.
<> 149:156823d33999 14742 * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
<> 149:156823d33999 14743 * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
<> 149:156823d33999 14744 * | | |0 = No Modem interrupt is generated in DMA mode.
<> 149:156823d33999 14745 * | | |1 = Modem interrupt is generated in DMA mode.
<> 149:156823d33999 14746 * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
<> 149:156823d33999 14747 * | | |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
<> 149:156823d33999 14748 * | | |0 = No Tout interrupt is generated in DMA mode.
<> 149:156823d33999 14749 * | | |1 = Tout interrupt is generated in DMA mode.
<> 149:156823d33999 14750 * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
<> 149:156823d33999 14751 * | | |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
<> 149:156823d33999 14752 * | | |0 = No buffer error interrupt is generated in DMA mode.
<> 149:156823d33999 14753 * | | |1 = Buffer error interrupt is generated in DMA mode.
<> 149:156823d33999 14754 * @var UART_T::TOUT
<> 149:156823d33999 14755 * Offset: 0x20 UART Time-out Register
<> 149:156823d33999 14756 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14757 * |Bits |Field |Descriptions
<> 149:156823d33999 14758 * | :----: | :----: | :---- |
<> 149:156823d33999 14759 * |[7:0] |TOIC |Time-Out Interrupt Comparator
<> 149:156823d33999 14760 * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
<> 149:156823d33999 14761 * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
<> 149:156823d33999 14762 * | | |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
<> 149:156823d33999 14763 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
<> 149:156823d33999 14764 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
<> 149:156823d33999 14765 * |[15:8] |DLY |TX Delay Time Value
<> 149:156823d33999 14766 * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.
<> 149:156823d33999 14767 * | | |The unit is bit time.
<> 149:156823d33999 14768 * @var UART_T::BAUD
<> 149:156823d33999 14769 * Offset: 0x24 UART Baud Rate Divisor Register
<> 149:156823d33999 14770 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14771 * |Bits |Field |Descriptions
<> 149:156823d33999 14772 * | :----: | :----: | :---- |
<> 149:156823d33999 14773 * |[15:0] |BRD |Baud Rate Divider
<> 149:156823d33999 14774 * | | |The field indicates the baud rate divider.
<> 149:156823d33999 14775 * | | |This filed is used in baud rate calculation.
<> 149:156823d33999 14776 * | | |The detail description is shown in Table 6.21-2.
<> 149:156823d33999 14777 * |[27:24] |EDIVM1 |Extra Divider For BAUD Rate Mode 1
<> 149:156823d33999 14778 * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
<> 149:156823d33999 14779 * | | |The detail description is shown in Table 6.21-2.
<> 149:156823d33999 14780 * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
<> 149:156823d33999 14781 * | | |This bit is baud rate mode selection bit 0.
<> 149:156823d33999 14782 * | | |UART provides three baud rate calculation modes.
<> 149:156823d33999 14783 * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
<> 149:156823d33999 14784 * | | |The detail description is shown in Table 6.21-2.
<> 149:156823d33999 14785 * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
<> 149:156823d33999 14786 * | | |This bit is baud rate mode selection bit 1.
<> 149:156823d33999 14787 * | | |UART provides three baud rate calculation modes.
<> 149:156823d33999 14788 * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
<> 149:156823d33999 14789 * | | |The detail description is shown in Table 6.21-2.
<> 149:156823d33999 14790 * | | |Note: In IrDA mode must be operated in mode 0.
<> 149:156823d33999 14791 * @var UART_T::IRDA
<> 149:156823d33999 14792 * Offset: 0x28 UART IrDA Control Register
<> 149:156823d33999 14793 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14794 * |Bits |Field |Descriptions
<> 149:156823d33999 14795 * | :----: | :----: | :---- |
<> 149:156823d33999 14796 * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
<> 149:156823d33999 14797 * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
<> 149:156823d33999 14798 * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
<> 149:156823d33999 14799 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
<> 149:156823d33999 14800 * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
<> 149:156823d33999 14801 * | | |0 = None inverse transmitting signal. (Default)
<> 149:156823d33999 14802 * | | |1 = Inverse transmitting output signal.
<> 149:156823d33999 14803 * |[6] |RXINV |IrDA Inverse Receive Input Signal
<> 149:156823d33999 14804 * | | |0 = None inverse receiving input signal.
<> 149:156823d33999 14805 * | | |1 = Inverse receiving input signal. (Default)
<> 149:156823d33999 14806 * @var UART_T::ALTCTL
<> 149:156823d33999 14807 * Offset: 0x2C UART Alternate Control/Status Register
<> 149:156823d33999 14808 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14809 * |Bits |Field |Descriptions
<> 149:156823d33999 14810 * | :----: | :----: | :---- |
<> 149:156823d33999 14811 * |[3:0] |BRKFL |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
<> 149:156823d33999 14812 * | | |This field indicates a 4-bit LIN TX break field count.
<> 149:156823d33999 14813 * | | |Note1: This break field length is BRKFL + 1
<> 149:156823d33999 14814 * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
<> 149:156823d33999 14815 * |[6] |LINRXEN |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
<> 149:156823d33999 14816 * | | |0 = LIN RX mode Disabled.
<> 149:156823d33999 14817 * | | |1 = LIN RX mode Enabled.
<> 149:156823d33999 14818 * |[7] |LINTXEN |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
<> 149:156823d33999 14819 * | | |0 = LIN TX Break mode Disabled.
<> 149:156823d33999 14820 * | | |1 = LIN TX Break mode Enabled.
<> 149:156823d33999 14821 * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
<> 149:156823d33999 14822 * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
<> 149:156823d33999 14823 * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
<> 149:156823d33999 14824 * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
<> 149:156823d33999 14825 * | | |Note: It cannot be active with RS-485_AAD operation mode.
<> 149:156823d33999 14826 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
<> 149:156823d33999 14827 * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
<> 149:156823d33999 14828 * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
<> 149:156823d33999 14829 * | | |Note: It cannot be active with RS-485_NMM operation mode.
<> 149:156823d33999 14830 * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
<> 149:156823d33999 14831 * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
<> 149:156823d33999 14832 * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
<> 149:156823d33999 14833 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
<> 149:156823d33999 14834 * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
<> 149:156823d33999 14835 * | | |This bit is used to enable RS-485 Address Detection mode.
<> 149:156823d33999 14836 * | | |0 = Address detection mode Disabled.
<> 149:156823d33999 14837 * | | |1 = Address detection mode Enabled.
<> 149:156823d33999 14838 * | | |Note: This bit is used for RS-485 any operation mode.
<> 149:156823d33999 14839 * |[17] |ABRIF |Auto-Baud Rate Interrupt Flag (Read Only)
<> 149:156823d33999 14840 * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
<> 149:156823d33999 14841 * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
<> 149:156823d33999 14842 * |[18] |ABRDEN |Auto-Baud Rate Detect Enable Bit
<> 149:156823d33999 14843 * | | |0 = Auto-baud rate detect function Disabled.
<> 149:156823d33999 14844 * | | |1 = Auto-baud rate detect function Enabled.
<> 149:156823d33999 14845 * | | |This bit is cleared automatically after auto-baud detection is finished.
<> 149:156823d33999 14846 * |[20:19] |ABRDBITS |Auto-Baud Rate Detect Bit Length
<> 149:156823d33999 14847 * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
<> 149:156823d33999 14848 * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
<> 149:156823d33999 14849 * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
<> 149:156823d33999 14850 * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
<> 149:156823d33999 14851 * | | |Note : The calculation of bit number includes the START bit.
<> 149:156823d33999 14852 * |[31:24] |ADDRMV |Address Match Value
<> 149:156823d33999 14853 * | | |This field contains the RS-485 address match values.
<> 149:156823d33999 14854 * | | |Note: This field is used for RS-485 auto address detection mode.
<> 149:156823d33999 14855 * @var UART_T::FUNCSEL
<> 149:156823d33999 14856 * Offset: 0x30 UART Function Select Register
<> 149:156823d33999 14857 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14858 * |Bits |Field |Descriptions
<> 149:156823d33999 14859 * | :----: | :----: | :---- |
<> 149:156823d33999 14860 * |[1:0] |FUNCSEL |Function Select
<> 149:156823d33999 14861 * | | |00 = UART function.
<> 149:156823d33999 14862 * | | |01 = LIN function (Only Available in UART0/UART1 Channel).
<> 149:156823d33999 14863 * | | |10 = IrDA function.
<> 149:156823d33999 14864 * | | |11 = RS-485 function.
<> 149:156823d33999 14865 * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
<> 149:156823d33999 14866 * @var UART_T::LINCTL
<> 149:156823d33999 14867 * Offset: 0x34 UART LIN Control Register
<> 149:156823d33999 14868 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14869 * |Bits |Field |Descriptions
<> 149:156823d33999 14870 * | :----: | :----: | :---- |
<> 149:156823d33999 14871 * |[0] |SLVEN |LIN Slave Mode Enable Bit
<> 149:156823d33999 14872 * | | |0 = LIN slave mode Disabled.
<> 149:156823d33999 14873 * | | |1 = LIN slave mode Enabled.
<> 149:156823d33999 14874 * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
<> 149:156823d33999 14875 * | | |0 = LIN slave header detection Disabled.
<> 149:156823d33999 14876 * | | |1 = LIN slave header detection Enabled.
<> 149:156823d33999 14877 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
<> 149:156823d33999 14878 * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
<> 149:156823d33999 14879 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
<> 149:156823d33999 14880 * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
<> 149:156823d33999 14881 * | | |0 = LIN automatic resynchronization Disabled.
<> 149:156823d33999 14882 * | | |1 = LIN automatic resynchronization Enabled.
<> 149:156823d33999 14883 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
<> 149:156823d33999 14884 * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
<> 149:156823d33999 14885 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
<> 149:156823d33999 14886 * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
<> 149:156823d33999 14887 * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
<> 149:156823d33999 14888 * | | |1 = UART_BAUD is updated at the next received character.
<> 149:156823d33999 14889 * | | |User must set the bit before checksum reception.
<> 149:156823d33999 14890 * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
<> 149:156823d33999 14891 * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
<> 149:156823d33999 14892 * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
<> 149:156823d33999 14893 * | | |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
<> 149:156823d33999 14894 * |[4] |MUTE |LIN Mute Mode Enable Bit
<> 149:156823d33999 14895 * | | |0 = LIN mute mode Disabled.
<> 149:156823d33999 14896 * | | |1 = LIN mute mode Enabled.
<> 149:156823d33999 14897 * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
<> 149:156823d33999 14898 * |[8] |SENDH |LIN TX Send Header Enable Bit
<> 149:156823d33999 14899 * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
<> 149:156823d33999 14900 * | | |0 = Send LIN TX header Disabled.
<> 149:156823d33999 14901 * | | |1 = Send LIN TX header Enabled.
<> 149:156823d33999 14902 * | | |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
<> 149:156823d33999 14903 * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
<> 149:156823d33999 14904 * |[9] |IDPEN |LIN ID Parity Enable Bit
<> 149:156823d33999 14905 * | | |0 = LIN frame ID parity Disabled.
<> 149:156823d33999 14906 * | | |1 = LIN frame ID parity Enabled.
<> 149:156823d33999 14907 * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
<> 149:156823d33999 14908 * | | |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
<> 149:156823d33999 14909 * |[10] |BRKDETEN |LIN Break Detection Enable Bit
<> 149:156823d33999 14910 * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
<> 149:156823d33999 14911 * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
<> 149:156823d33999 14912 * | | |0 = LIN break detection Disabled .
<> 149:156823d33999 14913 * | | |1 = LIN break detection Enabled.
<> 149:156823d33999 14914 * |[11] |RXOFF |LIN Receiver Disable Bit
<> 149:156823d33999 14915 * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0),
<> 149:156823d33999 14916 * | | |all received byte data will be accepted and stored in the RX-FIFO,
<> 149:156823d33999 14917 * | | |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
<> 149:156823d33999 14918 * | | |0 = LIN receiver Enabled.
<> 149:156823d33999 14919 * | | |1 = LIN receiver Disabled.
<> 149:156823d33999 14920 * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
<> 149:156823d33999 14921 * |[12] |BITERREN |Bit Error Detect Enable Bit
<> 149:156823d33999 14922 * | | |0 = Bit error detection function Disabled.
<> 149:156823d33999 14923 * | | |1 = Bit error detection Enabled.
<> 149:156823d33999 14924 * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
<> 149:156823d33999 14925 * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
<> 149:156823d33999 14926 * |[19:16] |BRKFL |LIN Break Field Length
<> 149:156823d33999 14927 * | | |This field indicates a 4-bit LIN TX break field count.
<> 149:156823d33999 14928 * | | |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
<> 149:156823d33999 14929 * | | |Note2: This break field length is BRKFL + 1.
<> 149:156823d33999 14930 * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
<> 149:156823d33999 14931 * |[21:20] |BSL |LIN Break/Sync Delimiter Length
<> 149:156823d33999 14932 * | | |00 = The LIN break/sync delimiter length is 1-bit time.
<> 149:156823d33999 14933 * | | |01 = The LIN break/sync delimiter length is 2-bit time.
<> 149:156823d33999 14934 * | | |10 = The LIN break/sync delimiter length is 3-bit time.
<> 149:156823d33999 14935 * | | |11 = The LIN break/sync delimiter length is 4-bit time.
<> 149:156823d33999 14936 * | | |Note: This bit used for LIN master to sending header field.
<> 149:156823d33999 14937 * |[23:22] |HSEL |LIN Header Select
<> 149:156823d33999 14938 * | | |00 = The LIN header includes "break field".
<> 149:156823d33999 14939 * | | |01 = The LIN header includes "break field" and "sync field".
<> 149:156823d33999 14940 * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field".
<> 149:156823d33999 14941 * | | |11 = Reserved.
<> 149:156823d33999 14942 * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
<> 149:156823d33999 14943 * |[31:24] |PID |LIN PID Bits
<> 149:156823d33999 14944 * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
<> 149:156823d33999 14945 * | | |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
<> 149:156823d33999 14946 * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
<> 149:156823d33999 14947 * | | |Note2: This field can be used for LIN master mode or slave mode.
<> 149:156823d33999 14948 * @var UART_T::LINSTS
<> 149:156823d33999 14949 * Offset: 0x38 UART LIN Status Register
<> 149:156823d33999 14950 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 14951 * |Bits |Field |Descriptions
<> 149:156823d33999 14952 * | :----: | :----: | :---- |
<> 149:156823d33999 14953 * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
<> 149:156823d33999 14954 * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
<> 149:156823d33999 14955 * | | |0 = LIN header not detected.
<> 149:156823d33999 14956 * | | |1 = LIN header detected (break + sync + frame ID).
<> 149:156823d33999 14957 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14958 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
<> 149:156823d33999 14959 * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
<> 149:156823d33999 14960 * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
<> 149:156823d33999 14961 * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
<> 149:156823d33999 14962 * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
<> 149:156823d33999 14963 * | | |0 = LIN header error not detected.
<> 149:156823d33999 14964 * | | |1 = LIN header error detected.
<> 149:156823d33999 14965 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14966 * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
<> 149:156823d33999 14967 * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
<> 149:156823d33999 14968 * | | |This bit is set by hardware when receipted frame ID parity is not correct.
<> 149:156823d33999 14969 * | | |0 = No active.
<> 149:156823d33999 14970 * | | |1 = Receipted frame ID parity is not correct.
<> 149:156823d33999 14971 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14972 * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
<> 149:156823d33999 14973 * |[3] |SLVSYNCF |LIN Slave Sync Field (Read Only)
<> 149:156823d33999 14974 * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
<> 149:156823d33999 14975 * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
<> 149:156823d33999 14976 * | | |0 = The current character is not at LIN sync state.
<> 149:156823d33999 14977 * | | |1 = The current character is at LIN sync state.
<> 149:156823d33999 14978 * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
<> 149:156823d33999 14979 * | | |Note2: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14980 * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
<> 149:156823d33999 14981 * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
<> 149:156823d33999 14982 * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
<> 149:156823d33999 14983 * | | |0 = LIN break not detected.
<> 149:156823d33999 14984 * | | |1 = LIN break detected.
<> 149:156823d33999 14985 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14986 * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
<> 149:156823d33999 14987 * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
<> 149:156823d33999 14988 * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
<> 149:156823d33999 14989 * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
<> 149:156823d33999 14990 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 149:156823d33999 14991 * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
<> 149:156823d33999 14992 */
<> 149:156823d33999 14993
<> 149:156823d33999 14994 __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
<> 149:156823d33999 14995 __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
<> 149:156823d33999 14996 __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
<> 149:156823d33999 14997 __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
<> 149:156823d33999 14998 __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
<> 149:156823d33999 14999 __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
<> 149:156823d33999 15000 __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
<> 149:156823d33999 15001 __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
<> 149:156823d33999 15002 __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
<> 149:156823d33999 15003 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
<> 149:156823d33999 15004 __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
<> 149:156823d33999 15005 __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
<> 149:156823d33999 15006 __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
<> 149:156823d33999 15007 __IO uint32_t LINCTL; /* Offset: 0x34 UART LIN Control Register */
<> 149:156823d33999 15008 __IO uint32_t LINSTS; /* Offset: 0x38 UART LIN Status Register */
<> 149:156823d33999 15009
<> 149:156823d33999 15010 } UART_T;
<> 149:156823d33999 15011
<> 149:156823d33999 15012
<> 149:156823d33999 15013
<> 149:156823d33999 15014 /**
<> 149:156823d33999 15015 @addtogroup UART_CONST UART Bit Field Definition
<> 149:156823d33999 15016 Constant Definitions for UART Controller
<> 149:156823d33999 15017 @{ */
<> 149:156823d33999 15018
<> 149:156823d33999 15019 #define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
<> 149:156823d33999 15020 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
<> 149:156823d33999 15021
<> 149:156823d33999 15022 #define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
<> 149:156823d33999 15023 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
<> 149:156823d33999 15024
<> 149:156823d33999 15025 #define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
<> 149:156823d33999 15026 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
<> 149:156823d33999 15027
<> 149:156823d33999 15028 #define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
<> 149:156823d33999 15029 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
<> 149:156823d33999 15030
<> 149:156823d33999 15031 #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
<> 149:156823d33999 15032 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
<> 149:156823d33999 15033
<> 149:156823d33999 15034 #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
<> 149:156823d33999 15035 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
<> 149:156823d33999 15036
<> 149:156823d33999 15037 #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
<> 149:156823d33999 15038 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
<> 149:156823d33999 15039
<> 149:156823d33999 15040 #define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
<> 149:156823d33999 15041 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
<> 149:156823d33999 15042
<> 149:156823d33999 15043 #define UART_INTEN_WKCTSIEN_Pos (9) /*!< UART_T::INTEN: WKCTSIEN Position */
<> 149:156823d33999 15044 #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART_T::INTEN: WKCTSIEN Mask */
<> 149:156823d33999 15045
<> 149:156823d33999 15046 #define UART_INTEN_WKDATIEN_Pos (10) /*!< UART_T::INTEN: WKDATIEN Position */
<> 149:156823d33999 15047 #define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) /*!< UART_T::INTEN: WKDATIEN Mask */
<> 149:156823d33999 15048
<> 149:156823d33999 15049 #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
<> 149:156823d33999 15050 #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
<> 149:156823d33999 15051
<> 149:156823d33999 15052 #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
<> 149:156823d33999 15053 #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
<> 149:156823d33999 15054
<> 149:156823d33999 15055 #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
<> 149:156823d33999 15056 #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
<> 149:156823d33999 15057
<> 149:156823d33999 15058 #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
<> 149:156823d33999 15059 #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
<> 149:156823d33999 15060
<> 149:156823d33999 15061 #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
<> 149:156823d33999 15062 #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
<> 149:156823d33999 15063
<> 149:156823d33999 15064 #define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
<> 149:156823d33999 15065 #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
<> 149:156823d33999 15066
<> 149:156823d33999 15067 #define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
<> 149:156823d33999 15068 #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
<> 149:156823d33999 15069
<> 149:156823d33999 15070 #define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
<> 149:156823d33999 15071 #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
<> 149:156823d33999 15072
<> 149:156823d33999 15073 #define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
<> 149:156823d33999 15074 #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
<> 149:156823d33999 15075
<> 149:156823d33999 15076 #define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
<> 149:156823d33999 15077 #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
<> 149:156823d33999 15078
<> 149:156823d33999 15079 #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
<> 149:156823d33999 15080 #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
<> 149:156823d33999 15081
<> 149:156823d33999 15082 #define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
<> 149:156823d33999 15083 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
<> 149:156823d33999 15084
<> 149:156823d33999 15085 #define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
<> 149:156823d33999 15086 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
<> 149:156823d33999 15087
<> 149:156823d33999 15088 #define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
<> 149:156823d33999 15089 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
<> 149:156823d33999 15090
<> 149:156823d33999 15091 #define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
<> 149:156823d33999 15092 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
<> 149:156823d33999 15093
<> 149:156823d33999 15094 #define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
<> 149:156823d33999 15095 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
<> 149:156823d33999 15096
<> 149:156823d33999 15097 #define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
<> 149:156823d33999 15098 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
<> 149:156823d33999 15099
<> 149:156823d33999 15100 #define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
<> 149:156823d33999 15101 #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
<> 149:156823d33999 15102
<> 149:156823d33999 15103 #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
<> 149:156823d33999 15104 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
<> 149:156823d33999 15105
<> 149:156823d33999 15106 #define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
<> 149:156823d33999 15107 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
<> 149:156823d33999 15108
<> 149:156823d33999 15109 #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
<> 149:156823d33999 15110 #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
<> 149:156823d33999 15111
<> 149:156823d33999 15112 #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
<> 149:156823d33999 15113 #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
<> 149:156823d33999 15114
<> 149:156823d33999 15115 #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
<> 149:156823d33999 15116 #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
<> 149:156823d33999 15117
<> 149:156823d33999 15118 #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
<> 149:156823d33999 15119 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
<> 149:156823d33999 15120
<> 149:156823d33999 15121 #define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
<> 149:156823d33999 15122 #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
<> 149:156823d33999 15123
<> 149:156823d33999 15124 #define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
<> 149:156823d33999 15125 #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
<> 149:156823d33999 15126
<> 149:156823d33999 15127 #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
<> 149:156823d33999 15128 #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
<> 149:156823d33999 15129
<> 149:156823d33999 15130 #define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
<> 149:156823d33999 15131 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
<> 149:156823d33999 15132
<> 149:156823d33999 15133 #define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
<> 149:156823d33999 15134 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
<> 149:156823d33999 15135
<> 149:156823d33999 15136 #define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
<> 149:156823d33999 15137 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
<> 149:156823d33999 15138
<> 149:156823d33999 15139 #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
<> 149:156823d33999 15140 #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
<> 149:156823d33999 15141
<> 149:156823d33999 15142 #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
<> 149:156823d33999 15143 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
<> 149:156823d33999 15144
<> 149:156823d33999 15145 #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
<> 149:156823d33999 15146 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
<> 149:156823d33999 15147
<> 149:156823d33999 15148 #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
<> 149:156823d33999 15149 #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
<> 149:156823d33999 15150
<> 149:156823d33999 15151 #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
<> 149:156823d33999 15152 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
<> 149:156823d33999 15153
<> 149:156823d33999 15154 #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
<> 149:156823d33999 15155 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
<> 149:156823d33999 15156
<> 149:156823d33999 15157 #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
<> 149:156823d33999 15158 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
<> 149:156823d33999 15159
<> 149:156823d33999 15160 #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
<> 149:156823d33999 15161 #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
<> 149:156823d33999 15162
<> 149:156823d33999 15163 #define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
<> 149:156823d33999 15164 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
<> 149:156823d33999 15165
<> 149:156823d33999 15166 #define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
<> 149:156823d33999 15167 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
<> 149:156823d33999 15168
<> 149:156823d33999 15169 #define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
<> 149:156823d33999 15170 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
<> 149:156823d33999 15171
<> 149:156823d33999 15172 #define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
<> 149:156823d33999 15173 #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
<> 149:156823d33999 15174
<> 149:156823d33999 15175 #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
<> 149:156823d33999 15176 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
<> 149:156823d33999 15177
<> 149:156823d33999 15178 #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
<> 149:156823d33999 15179 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
<> 149:156823d33999 15180
<> 149:156823d33999 15181 #define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
<> 149:156823d33999 15182 #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
<> 149:156823d33999 15183
<> 149:156823d33999 15184 #define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
<> 149:156823d33999 15185 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
<> 149:156823d33999 15186
<> 149:156823d33999 15187 #define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
<> 149:156823d33999 15188 #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
<> 149:156823d33999 15189
<> 149:156823d33999 15190 #define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
<> 149:156823d33999 15191 #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
<> 149:156823d33999 15192
<> 149:156823d33999 15193 #define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
<> 149:156823d33999 15194 #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
<> 149:156823d33999 15195
<> 149:156823d33999 15196 #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
<> 149:156823d33999 15197 #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
<> 149:156823d33999 15198
<> 149:156823d33999 15199 #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
<> 149:156823d33999 15200 #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
<> 149:156823d33999 15201
<> 149:156823d33999 15202 #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
<> 149:156823d33999 15203 #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
<> 149:156823d33999 15204
<> 149:156823d33999 15205 #define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
<> 149:156823d33999 15206 #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
<> 149:156823d33999 15207
<> 149:156823d33999 15208 #define UART_INTSTS_CTSWKIF_Pos (16) /*!< UART_T::INTSTS: CTSWKIF Position */
<> 149:156823d33999 15209 #define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) /*!< UART_T::INTSTS: CTSWKIF Mask */
<> 149:156823d33999 15210
<> 149:156823d33999 15211 #define UART_INTSTS_DATWKIF_Pos (17) /*!< UART_T::INTSTS: DATWKIF Position */
<> 149:156823d33999 15212 #define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) /*!< UART_T::INTSTS: DATWKIF Mask */
<> 149:156823d33999 15213
<> 149:156823d33999 15214 #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
<> 149:156823d33999 15215 #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
<> 149:156823d33999 15216
<> 149:156823d33999 15217 #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
<> 149:156823d33999 15218 #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
<> 149:156823d33999 15219
<> 149:156823d33999 15220 #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
<> 149:156823d33999 15221 #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
<> 149:156823d33999 15222
<> 149:156823d33999 15223 #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
<> 149:156823d33999 15224 #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
<> 149:156823d33999 15225
<> 149:156823d33999 15226 #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
<> 149:156823d33999 15227 #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
<> 149:156823d33999 15228
<> 149:156823d33999 15229 #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
<> 149:156823d33999 15230 #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
<> 149:156823d33999 15231
<> 149:156823d33999 15232 #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
<> 149:156823d33999 15233 #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
<> 149:156823d33999 15234
<> 149:156823d33999 15235 #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
<> 149:156823d33999 15236 #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
<> 149:156823d33999 15237
<> 149:156823d33999 15238 #define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
<> 149:156823d33999 15239 #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
<> 149:156823d33999 15240
<> 149:156823d33999 15241 #define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
<> 149:156823d33999 15242 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
<> 149:156823d33999 15243
<> 149:156823d33999 15244 #define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
<> 149:156823d33999 15245 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
<> 149:156823d33999 15246
<> 149:156823d33999 15247 #define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
<> 149:156823d33999 15248 #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
<> 149:156823d33999 15249
<> 149:156823d33999 15250 #define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
<> 149:156823d33999 15251 #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
<> 149:156823d33999 15252
<> 149:156823d33999 15253 #define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
<> 149:156823d33999 15254 #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
<> 149:156823d33999 15255
<> 149:156823d33999 15256 #define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
<> 149:156823d33999 15257 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
<> 149:156823d33999 15258
<> 149:156823d33999 15259 #define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
<> 149:156823d33999 15260 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
<> 149:156823d33999 15261
<> 149:156823d33999 15262 #define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
<> 149:156823d33999 15263 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
<> 149:156823d33999 15264
<> 149:156823d33999 15265 #define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
<> 149:156823d33999 15266 #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
<> 149:156823d33999 15267
<> 149:156823d33999 15268 #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
<> 149:156823d33999 15269 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
<> 149:156823d33999 15270
<> 149:156823d33999 15271 #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
<> 149:156823d33999 15272 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
<> 149:156823d33999 15273
<> 149:156823d33999 15274 #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
<> 149:156823d33999 15275 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
<> 149:156823d33999 15276
<> 149:156823d33999 15277 #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
<> 149:156823d33999 15278 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
<> 149:156823d33999 15279
<> 149:156823d33999 15280 #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
<> 149:156823d33999 15281 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
<> 149:156823d33999 15282
<> 149:156823d33999 15283 #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
<> 149:156823d33999 15284 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
<> 149:156823d33999 15285
<> 149:156823d33999 15286 #define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
<> 149:156823d33999 15287 #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
<> 149:156823d33999 15288
<> 149:156823d33999 15289 #define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
<> 149:156823d33999 15290 #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
<> 149:156823d33999 15291
<> 149:156823d33999 15292 #define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
<> 149:156823d33999 15293 #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
<> 149:156823d33999 15294
<> 149:156823d33999 15295 #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
<> 149:156823d33999 15296 #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
<> 149:156823d33999 15297
<> 149:156823d33999 15298 #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
<> 149:156823d33999 15299 #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
<> 149:156823d33999 15300
<> 149:156823d33999 15301 #define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
<> 149:156823d33999 15302 #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
<> 149:156823d33999 15303
<> 149:156823d33999 15304 #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
<> 149:156823d33999 15305 #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
<> 149:156823d33999 15306
<> 149:156823d33999 15307 #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
<> 149:156823d33999 15308 #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
<> 149:156823d33999 15309
<> 149:156823d33999 15310 #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
<> 149:156823d33999 15311 #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
<> 149:156823d33999 15312
<> 149:156823d33999 15313 #define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
<> 149:156823d33999 15314 #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
<> 149:156823d33999 15315
<> 149:156823d33999 15316 #define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
<> 149:156823d33999 15317 #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
<> 149:156823d33999 15318
<> 149:156823d33999 15319 #define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
<> 149:156823d33999 15320 #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
<> 149:156823d33999 15321
<> 149:156823d33999 15322 #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
<> 149:156823d33999 15323 #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
<> 149:156823d33999 15324
<> 149:156823d33999 15325 #define UART_LINCTL_RXOFF_Pos (11) /*!< UART_T::LINCTL: RXOFF Position */
<> 149:156823d33999 15326 #define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART_T::LINCTL: RXOFF Mask */
<> 149:156823d33999 15327
<> 149:156823d33999 15328 #define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
<> 149:156823d33999 15329 #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
<> 149:156823d33999 15330
<> 149:156823d33999 15331 #define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
<> 149:156823d33999 15332 #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
<> 149:156823d33999 15333
<> 149:156823d33999 15334 #define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
<> 149:156823d33999 15335 #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
<> 149:156823d33999 15336
<> 149:156823d33999 15337 #define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
<> 149:156823d33999 15338 #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
<> 149:156823d33999 15339
<> 149:156823d33999 15340 #define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
<> 149:156823d33999 15341 #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
<> 149:156823d33999 15342
<> 149:156823d33999 15343 #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
<> 149:156823d33999 15344 #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
<> 149:156823d33999 15345
<> 149:156823d33999 15346 #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
<> 149:156823d33999 15347 #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
<> 149:156823d33999 15348
<> 149:156823d33999 15349 #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
<> 149:156823d33999 15350 #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
<> 149:156823d33999 15351
<> 149:156823d33999 15352 #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
<> 149:156823d33999 15353 #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
<> 149:156823d33999 15354
<> 149:156823d33999 15355 #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
<> 149:156823d33999 15356 #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
<> 149:156823d33999 15357
<> 149:156823d33999 15358 #define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
<> 149:156823d33999 15359 #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
<> 149:156823d33999 15360
<> 149:156823d33999 15361
<> 149:156823d33999 15362 /**@}*/ /* UART_CONST */
<> 149:156823d33999 15363 /**@}*/ /* end of UART register group */
<> 149:156823d33999 15364
<> 149:156823d33999 15365
<> 149:156823d33999 15366 /*---------------------- Universal Serial Bus Controller -------------------------*/
<> 149:156823d33999 15367 /**
<> 149:156823d33999 15368 @addtogroup USB Universal Serial Bus Controller(USB)
<> 149:156823d33999 15369 Memory Mapped Structure for USB Controller
<> 149:156823d33999 15370 @{ */
<> 149:156823d33999 15371
<> 149:156823d33999 15372 /**
<> 149:156823d33999 15373 * @brief USBD endpoints register
<> 149:156823d33999 15374 */
<> 149:156823d33999 15375
<> 149:156823d33999 15376 typedef struct
<> 149:156823d33999 15377 {
<> 149:156823d33999 15378
<> 149:156823d33999 15379
<> 149:156823d33999 15380 /**
<> 149:156823d33999 15381 * @var USBD_EP_T::BUFSEG
<> 149:156823d33999 15382 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register
<> 149:156823d33999 15383 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15384 * |Bits |Field |Descriptions
<> 149:156823d33999 15385 * | :----: | :----: | :---- |
<> 149:156823d33999 15386 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
<> 149:156823d33999 15387 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
<> 149:156823d33999 15388 * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000}
<> 149:156823d33999 15389 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
<> 149:156823d33999 15390 * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
<> 149:156823d33999 15391 * @var USBD_EP_T::MXPLD
<> 149:156823d33999 15392 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register
<> 149:156823d33999 15393 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15394 * |Bits |Field |Descriptions
<> 149:156823d33999 15395 * | :----: | :----: | :---- |
<> 149:156823d33999 15396 * |[8:0] |MXPLD |Maximal Payload
<> 149:156823d33999 15397 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
<> 149:156823d33999 15398 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
<> 149:156823d33999 15399 * | | |(1) When the register is written by CPU,
<> 149:156823d33999 15400 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
<> 149:156823d33999 15401 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
<> 149:156823d33999 15402 * | | |(2) When the register is read by CPU,
<> 149:156823d33999 15403 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
<> 149:156823d33999 15404 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
<> 149:156823d33999 15405 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
<> 149:156823d33999 15406 * @var USBD_EP_T::CFG
<> 149:156823d33999 15407 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register
<> 149:156823d33999 15408 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15409 * |Bits |Field |Descriptions
<> 149:156823d33999 15410 * | :----: | :----: | :---- |
<> 149:156823d33999 15411 * |[3:0] |EPNUM |Endpoint Number
<> 149:156823d33999 15412 * | | |These bits are used to define the endpoint number of the current endpoint.
<> 149:156823d33999 15413 * |[4] |ISOCH |Isochronous Endpoint
<> 149:156823d33999 15414 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
<> 149:156823d33999 15415 * | | |0 = No Isochronous endpoint.
<> 149:156823d33999 15416 * | | |1 = Isochronous endpoint.
<> 149:156823d33999 15417 * |[6:5] |STATE |Endpoint STATE
<> 149:156823d33999 15418 * | | |00 = Endpoint is Disabled.
<> 149:156823d33999 15419 * | | |01 = Out endpoint.
<> 149:156823d33999 15420 * | | |10 = IN endpoint.
<> 149:156823d33999 15421 * | | |11 = Undefined.
<> 149:156823d33999 15422 * |[7] |DSQSYNC |Data Sequence Synchronization
<> 149:156823d33999 15423 * | | |0 = DATA0 PID.
<> 149:156823d33999 15424 * | | |1 = DATA1 PID.
<> 149:156823d33999 15425 * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
<> 149:156823d33999 15426 * | | |Hardware will toggle automatically in IN token base on the bit.
<> 149:156823d33999 15427 * |[9] |CSTALL |Clear STALL Response
<> 149:156823d33999 15428 * | | |0 = Disable the device to clear the STALL handshake in setup stage.
<> 149:156823d33999 15429 * | | |1 = Clear the device to response STALL handshake in setup stage.
<> 149:156823d33999 15430 * @var USBD_EP_T::CFGP
<> 149:156823d33999 15431 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
<> 149:156823d33999 15432 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15433 * |Bits |Field |Descriptions
<> 149:156823d33999 15434 * | :----: | :----: | :---- |
<> 149:156823d33999 15435 * |[0] |CLRRDY |Clear Ready
<> 149:156823d33999 15436 * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
<> 149:156823d33999 15437 * | | |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
<> 149:156823d33999 15438 * | | |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
<> 149:156823d33999 15439 * | | |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
<> 149:156823d33999 15440 * | | |This bit is write 1 only and is always 0 when it is read back.
<> 149:156823d33999 15441 * |[1] |SSTALL |Set STALL
<> 149:156823d33999 15442 * | | |0 = Disable the device to response STALL.
<> 149:156823d33999 15443 * | | |1 = Set the device to respond STALL automatically.
<> 149:156823d33999 15444 */
<> 149:156823d33999 15445
<> 149:156823d33999 15446 __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
<> 149:156823d33999 15447 __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
<> 149:156823d33999 15448 __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
<> 149:156823d33999 15449 __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
<> 149:156823d33999 15450
<> 149:156823d33999 15451 } USBD_EP_T;
<> 149:156823d33999 15452
<> 149:156823d33999 15453
<> 149:156823d33999 15454
<> 149:156823d33999 15455
<> 149:156823d33999 15456
<> 149:156823d33999 15457 typedef struct
<> 149:156823d33999 15458 {
<> 149:156823d33999 15459
<> 149:156823d33999 15460
<> 149:156823d33999 15461 /**
<> 149:156823d33999 15462 * @var USBD_T::INTEN
<> 149:156823d33999 15463 * Offset: 0x00 USB Interrupt Enable Register
<> 149:156823d33999 15464 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15465 * |Bits |Field |Descriptions
<> 149:156823d33999 15466 * | :----: | :----: | :---- |
<> 149:156823d33999 15467 * |[0] |BUSIEN |Bus Event Interrupt Enable
<> 149:156823d33999 15468 * | | |0 = BUS event interrupt Disabled.
<> 149:156823d33999 15469 * | | |1 = BUS event interrupt Enabled.
<> 149:156823d33999 15470 * |[1] |USBIEN |USB Event Interrupt Enable
<> 149:156823d33999 15471 * | | |0 = USB event interrupt Disabled.
<> 149:156823d33999 15472 * | | |1 = USB event interrupt Enabled.
<> 149:156823d33999 15473 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable
<> 149:156823d33999 15474 * | | |0 = Floating detection Interrupt Disabled.
<> 149:156823d33999 15475 * | | |1 = Floating detection Interrupt Enabled.
<> 149:156823d33999 15476 * |[3] |NEVWKIEN |USB No-Event-Wake-Up Interrupt Enable
<> 149:156823d33999 15477 * | | |0 = No-Event-Wake-up Interrupt Disabled.
<> 149:156823d33999 15478 * | | |1 = No-Event-Wake-up Interrupt Enabled.
<> 149:156823d33999 15479 * |[8] |WKEN |Wake-Up Function Enable
<> 149:156823d33999 15480 * | | |0 = USB wake-up function Disabled.
<> 149:156823d33999 15481 * | | |1 = USB wake-up function Enabled.
<> 149:156823d33999 15482 * |[15] |INNAKEN |Active NAK Function And Its Status In IN Token
<> 149:156823d33999 15483 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be
<> 149:156823d33999 15484 * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
<> 149:156823d33999 15485 * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
<> 149:156823d33999 15486 * | | | will be asserted, when the device responds NAK after receiving IN token.
<> 149:156823d33999 15487 * @var USBD_T::INTSTS
<> 149:156823d33999 15488 * Offset: 0x04 USB Interrupt Event Status Register
<> 149:156823d33999 15489 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15490 * |Bits |Field |Descriptions
<> 149:156823d33999 15491 * | :----: | :----: | :---- |
<> 149:156823d33999 15492 * |[0] |BUSIF |BUS Interrupt Status
<> 149:156823d33999 15493 * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
<> 149:156823d33999 15494 * | | |0 = No BUS event occurred.
<> 149:156823d33999 15495 * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
<> 149:156823d33999 15496 * |[1] |USBIF |USB Event Interrupt Status
<> 149:156823d33999 15497 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
<> 149:156823d33999 15498 * | | |0 = No USB event occurred.
<> 149:156823d33999 15499 * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
<> 149:156823d33999 15500 * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
<> 149:156823d33999 15501 * |[2] |VBDETIF |VBUS Detection Interrupt Status
<> 149:156823d33999 15502 * | | |0 = There is not attached/detached event in the USB.
<> 149:156823d33999 15503 * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
<> 149:156823d33999 15504 * |[3] |NEVWKIF |USB No-Event-Wake-Up Interrupt Status
<> 149:156823d33999 15505 * | | |0 = No Wake-up event occurred.
<> 149:156823d33999 15506 * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
<> 149:156823d33999 15507 * |[16] |EPEVT0 |Endpoint 0's USB Event Status
<> 149:156823d33999 15508 * | | |0 = No event occurred on endpoint 0.
<> 149:156823d33999 15509 * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
<> 149:156823d33999 15510 * |[17] |EPEVT1 |Endpoint 1's USB Event Status
<> 149:156823d33999 15511 * | | |0 = No event occurred on endpoint 1.
<> 149:156823d33999 15512 * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
<> 149:156823d33999 15513 * |[18] |EPEVT2 |Endpoint 2's USB Event Status
<> 149:156823d33999 15514 * | | |0 = No event occurred on endpoint 2.
<> 149:156823d33999 15515 * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
<> 149:156823d33999 15516 * |[19] |EPEVT3 |Endpoint 3's USB Event Status
<> 149:156823d33999 15517 * | | |0 = No event occurred on endpoint 3.
<> 149:156823d33999 15518 * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
<> 149:156823d33999 15519 * |[20] |EPEVT4 |Endpoint 4's USB Event Status
<> 149:156823d33999 15520 * | | |0 = No event occurred on endpoint 4.
<> 149:156823d33999 15521 * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
<> 149:156823d33999 15522 * |[21] |EPEVT5 |Endpoint 5's USB Event Status
<> 149:156823d33999 15523 * | | |0 = No event occurred on endpoint 5.
<> 149:156823d33999 15524 * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
<> 149:156823d33999 15525 * |[22] |EPEVT6 |Endpoint 6's USB Event Status
<> 149:156823d33999 15526 * | | |0 = No event occurred on endpoint 6.
<> 149:156823d33999 15527 * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
<> 149:156823d33999 15528 * |[23] |EPEVT7 |Endpoint 7's USB Event Status
<> 149:156823d33999 15529 * | | |0 = No event occurred on endpoint 7.
<> 149:156823d33999 15530 * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
<> 149:156823d33999 15531 * |[31] |SETUP |Setup Event Status
<> 149:156823d33999 15532 * | | |0 = No Setup event.
<> 149:156823d33999 15533 * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
<> 149:156823d33999 15534 * @var USBD_T::FADDR
<> 149:156823d33999 15535 * Offset: 0x08 USB Device Function Address Register
<> 149:156823d33999 15536 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15537 * |Bits |Field |Descriptions
<> 149:156823d33999 15538 * | :----: | :----: | :---- |
<> 149:156823d33999 15539 * |[6:0] |FADDR |USB Device Function Address
<> 149:156823d33999 15540 * @var USBD_T::EPSTS
<> 149:156823d33999 15541 * Offset: 0x0C USB Endpoint Status Register
<> 149:156823d33999 15542 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15543 * |Bits |Field |Descriptions
<> 149:156823d33999 15544 * | :----: | :----: | :---- |
<> 149:156823d33999 15545 * |[7] |OV |Overrun
<> 149:156823d33999 15546 * | | |It indicates that the received data is over the maximum payload number or not.
<> 149:156823d33999 15547 * | | |0 = No overrun.
<> 149:156823d33999 15548 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
<> 149:156823d33999 15549 * |[10:8] |EPSTS0 |Endpoint 0 Bus Status
<> 149:156823d33999 15550 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15551 * | | |000 = In ACK.
<> 149:156823d33999 15552 * | | |001 = In NAK.
<> 149:156823d33999 15553 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15554 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15555 * | | |011 = Setup ACK.
<> 149:156823d33999 15556 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15557 * |[13:11] |EPSTS1 |Endpoint 1 Bus Status
<> 149:156823d33999 15558 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15559 * | | |000 = In ACK.
<> 149:156823d33999 15560 * | | |001 = In NAK.
<> 149:156823d33999 15561 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15562 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15563 * | | |011 = Setup ACK.
<> 149:156823d33999 15564 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15565 * |[16:14] |EPSTS2 |Endpoint 2 Bus Status
<> 149:156823d33999 15566 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15567 * | | |000 = In ACK.
<> 149:156823d33999 15568 * | | |001 = In NAK.
<> 149:156823d33999 15569 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15570 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15571 * | | |011 = Setup ACK.
<> 149:156823d33999 15572 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15573 * |[19:17] |EPSTS3 |Endpoint 3 Bus Status
<> 149:156823d33999 15574 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15575 * | | |000 = In ACK.
<> 149:156823d33999 15576 * | | |001 = In NAK.
<> 149:156823d33999 15577 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15578 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15579 * | | |011 = Setup ACK.
<> 149:156823d33999 15580 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15581 * |[22:20] |EPSTS4 |Endpoint 4 Bus Status
<> 149:156823d33999 15582 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15583 * | | |000 = In ACK.
<> 149:156823d33999 15584 * | | |001 = In NAK.
<> 149:156823d33999 15585 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15586 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15587 * | | |011 = Setup ACK.
<> 149:156823d33999 15588 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15589 * |[25:23] |EPSTS5 |Endpoint 5 Bus Status
<> 149:156823d33999 15590 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15591 * | | |000 = In ACK.
<> 149:156823d33999 15592 * | | |001 = In NAK.
<> 149:156823d33999 15593 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15594 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15595 * | | |011 = Setup ACK.
<> 149:156823d33999 15596 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15597 * |[28:26] |EPSTS6 |Endpoint 6 Bus Status
<> 149:156823d33999 15598 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15599 * | | |000 = In ACK.
<> 149:156823d33999 15600 * | | |001 = In NAK.
<> 149:156823d33999 15601 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15602 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15603 * | | |011 = Setup ACK.
<> 149:156823d33999 15604 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15605 * |[31:29] |EPSTS7 |Endpoint 7 Bus Status
<> 149:156823d33999 15606 * | | |These bits are used to indicate the current status of this endpoint
<> 149:156823d33999 15607 * | | |000 = In ACK.
<> 149:156823d33999 15608 * | | |001 = In NAK.
<> 149:156823d33999 15609 * | | |010 = Out Packet Data0 ACK.
<> 149:156823d33999 15610 * | | |110 = Out Packet Data1 ACK.
<> 149:156823d33999 15611 * | | |011 = Setup ACK.
<> 149:156823d33999 15612 * | | |111 = Isochronous transfer end.
<> 149:156823d33999 15613 * @var USBD_T::ATTR
<> 149:156823d33999 15614 * Offset: 0x10 USB Bus Status and Attribution Register
<> 149:156823d33999 15615 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15616 * |Bits |Field |Descriptions
<> 149:156823d33999 15617 * | :----: | :----: | :---- |
<> 149:156823d33999 15618 * |[0] |USBRST |USB Reset Status
<> 149:156823d33999 15619 * | | |0 = Bus no reset.
<> 149:156823d33999 15620 * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
<> 149:156823d33999 15621 * | | |Note: This bit is read only.
<> 149:156823d33999 15622 * |[1] |SUSPEND |Suspend Status
<> 149:156823d33999 15623 * | | |0 = Bus no suspend.
<> 149:156823d33999 15624 * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
<> 149:156823d33999 15625 * | | |Note: This bit is read only.
<> 149:156823d33999 15626 * |[2] |RESUME |Resume Status
<> 149:156823d33999 15627 * | | |0 = No bus resume.
<> 149:156823d33999 15628 * | | |1 = Resume from suspend.
<> 149:156823d33999 15629 * | | |Note: This bit is read only.
<> 149:156823d33999 15630 * |[3] |TOUT |Time-Out Status
<> 149:156823d33999 15631 * | | |0 = No time-out.
<> 149:156823d33999 15632 * | | |1 = No Bus response more than 18 bits time.
<> 149:156823d33999 15633 * | | |Note: This bit is read only.
<> 149:156823d33999 15634 * |[4] |PHYEN |PHY Transceiver Function Enable
<> 149:156823d33999 15635 * | | |0 = PHY transceiver function Disabled.
<> 149:156823d33999 15636 * | | |1 = PHY transceiver function Enabled.
<> 149:156823d33999 15637 * |[5] |RWAKEUP |Remote Wake-Up
<> 149:156823d33999 15638 * | | |0 = Release the USB bus from K state.
<> 149:156823d33999 15639 * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
<> 149:156823d33999 15640 * |[7] |USBEN |USB Controller Enable
<> 149:156823d33999 15641 * | | |0 = USB Controller Disabled.
<> 149:156823d33999 15642 * | | |1 = USB Controller Enabled.
<> 149:156823d33999 15643 * |[8] |DPPUEN |Pull-Up Resistor On USB_D+ Enable
<> 149:156823d33999 15644 * | | |0 = Pull-up resistor in USB_D+ pin Disabled.
<> 149:156823d33999 15645 * | | |1 = Pull-up resistor in USB_D+ pin Enabled.
<> 149:156823d33999 15646 * |[9] |PWRDN |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
<> 149:156823d33999 15647 * | | |0 = Power down related circuits of PHY transceiver.
<> 149:156823d33999 15648 * | | |1 = Turn on related circuits of PHY transceiver.
<> 149:156823d33999 15649 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
<> 149:156823d33999 15650 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
<> 149:156823d33999 15651 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
<> 149:156823d33999 15652 * @var USBD_T::VBUSDET
<> 149:156823d33999 15653 * Offset: 0x14 USB Device VBUS Detection Register
<> 149:156823d33999 15654 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15655 * |Bits |Field |Descriptions
<> 149:156823d33999 15656 * | :----: | :----: | :---- |
<> 149:156823d33999 15657 * |[0] |FLDET |Device VBUS Detected
<> 149:156823d33999 15658 * | | |0 = Controller is not attached into the USB host.
<> 149:156823d33999 15659 * | | |1 =Controller is attached into the BUS.
<> 149:156823d33999 15660 * @var USBD_T::STBUFSEG
<> 149:156823d33999 15661 * Offset: 0x18 Setup Token Buffer Segmentation Register
<> 149:156823d33999 15662 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15663 * |Bits |Field |Descriptions
<> 149:156823d33999 15664 * | :----: | :----: | :---- |
<> 149:156823d33999 15665 * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation
<> 149:156823d33999 15666 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
<> 149:156823d33999 15667 * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
<> 149:156823d33999 15668 * | | |Where the USB_SRAM address = USBD_BA+0x100h.
<> 149:156823d33999 15669 * | | |Note: It is used for SETUP token only.
<> 149:156823d33999 15670 * @var USBD_T::SE0
<> 149:156823d33999 15671 * Offset: 0x90 USB Drive SE0 Control Register
<> 149:156823d33999 15672 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15673 * |Bits |Field |Descriptions
<> 149:156823d33999 15674 * | :----: | :----: | :---- |
<> 149:156823d33999 15675 * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus
<> 149:156823d33999 15676 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
<> 149:156823d33999 15677 * | | |0 = None.
<> 149:156823d33999 15678 * | | |1 = Force USB PHY transceiver to drive SE0.
<> 149:156823d33999 15679 * @var USBD_T::EP
<> 149:156823d33999 15680 * Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register
<> 149:156823d33999 15681 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15682 */
<> 149:156823d33999 15683
<> 149:156823d33999 15684 __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
<> 149:156823d33999 15685 __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
<> 149:156823d33999 15686 __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
<> 149:156823d33999 15687 __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
<> 149:156823d33999 15688 __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
<> 149:156823d33999 15689 __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
<> 149:156823d33999 15690 __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
<> 149:156823d33999 15691 __I uint32_t RESERVE0[29];
<> 149:156823d33999 15692 __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
<> 149:156823d33999 15693 __I uint32_t RESERVE1[283];
<> 149:156823d33999 15694 USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
<> 149:156823d33999 15695
<> 149:156823d33999 15696 } USBD_T;
<> 149:156823d33999 15697
<> 149:156823d33999 15698
<> 149:156823d33999 15699
<> 149:156823d33999 15700 /**
<> 149:156823d33999 15701 @addtogroup USB_CONST USB Bit Field Definition
<> 149:156823d33999 15702 Constant Definitions for USB Controller
<> 149:156823d33999 15703 @{ */
<> 149:156823d33999 15704
<> 149:156823d33999 15705 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
<> 149:156823d33999 15706 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
<> 149:156823d33999 15707
<> 149:156823d33999 15708 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
<> 149:156823d33999 15709 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
<> 149:156823d33999 15710
<> 149:156823d33999 15711 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
<> 149:156823d33999 15712 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
<> 149:156823d33999 15713
<> 149:156823d33999 15714 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
<> 149:156823d33999 15715 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
<> 149:156823d33999 15716
<> 149:156823d33999 15717 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
<> 149:156823d33999 15718 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
<> 149:156823d33999 15719
<> 149:156823d33999 15720 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
<> 149:156823d33999 15721 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
<> 149:156823d33999 15722
<> 149:156823d33999 15723 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
<> 149:156823d33999 15724 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
<> 149:156823d33999 15725
<> 149:156823d33999 15726 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
<> 149:156823d33999 15727 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
<> 149:156823d33999 15728
<> 149:156823d33999 15729 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
<> 149:156823d33999 15730 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
<> 149:156823d33999 15731
<> 149:156823d33999 15732 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
<> 149:156823d33999 15733 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
<> 149:156823d33999 15734
<> 149:156823d33999 15735 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
<> 149:156823d33999 15736 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
<> 149:156823d33999 15737
<> 149:156823d33999 15738 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
<> 149:156823d33999 15739 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
<> 149:156823d33999 15740
<> 149:156823d33999 15741 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
<> 149:156823d33999 15742 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
<> 149:156823d33999 15743
<> 149:156823d33999 15744 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
<> 149:156823d33999 15745 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
<> 149:156823d33999 15746
<> 149:156823d33999 15747 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
<> 149:156823d33999 15748 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
<> 149:156823d33999 15749
<> 149:156823d33999 15750 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
<> 149:156823d33999 15751 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
<> 149:156823d33999 15752
<> 149:156823d33999 15753 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
<> 149:156823d33999 15754 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
<> 149:156823d33999 15755
<> 149:156823d33999 15756 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
<> 149:156823d33999 15757 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
<> 149:156823d33999 15758
<> 149:156823d33999 15759 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
<> 149:156823d33999 15760 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
<> 149:156823d33999 15761
<> 149:156823d33999 15762 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
<> 149:156823d33999 15763 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
<> 149:156823d33999 15764
<> 149:156823d33999 15765 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
<> 149:156823d33999 15766 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
<> 149:156823d33999 15767
<> 149:156823d33999 15768 #define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
<> 149:156823d33999 15769 #define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
<> 149:156823d33999 15770
<> 149:156823d33999 15771 #define USBD_EPSTS_EPSTS1_Pos (11) /*!< USBD_T::EPSTS: EPSTS1 Position */
<> 149:156823d33999 15772 #define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
<> 149:156823d33999 15773
<> 149:156823d33999 15774 #define USBD_EPSTS_EPSTS2_Pos (14) /*!< USBD_T::EPSTS: EPSTS2 Position */
<> 149:156823d33999 15775 #define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
<> 149:156823d33999 15776
<> 149:156823d33999 15777 #define USBD_EPSTS_EPSTS3_Pos (17) /*!< USBD_T::EPSTS: EPSTS3 Position */
<> 149:156823d33999 15778 #define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
<> 149:156823d33999 15779
<> 149:156823d33999 15780 #define USBD_EPSTS_EPSTS4_Pos (20) /*!< USBD_T::EPSTS: EPSTS4 Position */
<> 149:156823d33999 15781 #define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
<> 149:156823d33999 15782
<> 149:156823d33999 15783 #define USBD_EPSTS_EPSTS5_Pos (23) /*!< USBD_T::EPSTS: EPSTS5 Position */
<> 149:156823d33999 15784 #define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
<> 149:156823d33999 15785
<> 149:156823d33999 15786 #define USBD_EPSTS_EPSTS6_Pos (26) /*!< USBD_T::EPSTS: EPSTS6 Position */
<> 149:156823d33999 15787 #define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) /*!< USBD_T::EPSTS: EPSTS6 Mask */
<> 149:156823d33999 15788
<> 149:156823d33999 15789 #define USBD_EPSTS_EPSTS7_Pos (29) /*!< USBD_T::EPSTS: EPSTS7 Position */
<> 149:156823d33999 15790 #define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) /*!< USBD_T::EPSTS: EPSTS7 Mask */
<> 149:156823d33999 15791
<> 149:156823d33999 15792 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
<> 149:156823d33999 15793 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
<> 149:156823d33999 15794
<> 149:156823d33999 15795 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
<> 149:156823d33999 15796 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
<> 149:156823d33999 15797
<> 149:156823d33999 15798 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
<> 149:156823d33999 15799 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
<> 149:156823d33999 15800
<> 149:156823d33999 15801 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
<> 149:156823d33999 15802 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
<> 149:156823d33999 15803
<> 149:156823d33999 15804 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
<> 149:156823d33999 15805 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
<> 149:156823d33999 15806
<> 149:156823d33999 15807 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
<> 149:156823d33999 15808 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
<> 149:156823d33999 15809
<> 149:156823d33999 15810 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
<> 149:156823d33999 15811 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
<> 149:156823d33999 15812
<> 149:156823d33999 15813 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
<> 149:156823d33999 15814 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
<> 149:156823d33999 15815
<> 149:156823d33999 15816 #define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
<> 149:156823d33999 15817 #define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
<> 149:156823d33999 15818
<> 149:156823d33999 15819 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
<> 149:156823d33999 15820 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
<> 149:156823d33999 15821
<> 149:156823d33999 15822 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
<> 149:156823d33999 15823 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
<> 149:156823d33999 15824
<> 149:156823d33999 15825 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
<> 149:156823d33999 15826 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
<> 149:156823d33999 15827
<> 149:156823d33999 15828 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
<> 149:156823d33999 15829 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
<> 149:156823d33999 15830
<> 149:156823d33999 15831 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
<> 149:156823d33999 15832 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
<> 149:156823d33999 15833
<> 149:156823d33999 15834 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
<> 149:156823d33999 15835 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
<> 149:156823d33999 15836
<> 149:156823d33999 15837 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
<> 149:156823d33999 15838 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
<> 149:156823d33999 15839
<> 149:156823d33999 15840 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
<> 149:156823d33999 15841 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
<> 149:156823d33999 15842
<> 149:156823d33999 15843 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
<> 149:156823d33999 15844 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
<> 149:156823d33999 15845
<> 149:156823d33999 15846 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
<> 149:156823d33999 15847 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
<> 149:156823d33999 15848
<> 149:156823d33999 15849 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
<> 149:156823d33999 15850 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
<> 149:156823d33999 15851
<> 149:156823d33999 15852 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
<> 149:156823d33999 15853 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
<> 149:156823d33999 15854
<> 149:156823d33999 15855 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
<> 149:156823d33999 15856 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
<> 149:156823d33999 15857
<> 149:156823d33999 15858 /**@}*/ /* USB_CONST */
<> 149:156823d33999 15859 /**@}*/ /* end of USB register group */
<> 149:156823d33999 15860
<> 149:156823d33999 15861
<> 149:156823d33999 15862 /*---------------------- USB Host Controller -------------------------*/
<> 149:156823d33999 15863 /**
<> 149:156823d33999 15864 @addtogroup USBH USB Host Controller(USBH)
<> 149:156823d33999 15865 Memory Mapped Structure for USBH Controller
<> 149:156823d33999 15866 @{ */
<> 149:156823d33999 15867
<> 149:156823d33999 15868
<> 149:156823d33999 15869 typedef struct
<> 149:156823d33999 15870 {
<> 149:156823d33999 15871
<> 149:156823d33999 15872
<> 149:156823d33999 15873
<> 149:156823d33999 15874
<> 149:156823d33999 15875 /**
<> 149:156823d33999 15876 * @var USBH_T::HcRevision
<> 149:156823d33999 15877 * Offset: 0x00 Host Controller Revision Register
<> 149:156823d33999 15878 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15879 * |Bits |Field |Descriptions
<> 149:156823d33999 15880 * | :----: | :----: | :---- |
<> 149:156823d33999 15881 * |[7:0] |REV |Revision Number
<> 149:156823d33999 15882 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
<> 149:156823d33999 15883 * | | |Host Controller supports 1.1 specification.
<> 149:156823d33999 15884 * | | |(X.Y = XYh).
<> 149:156823d33999 15885 * @var USBH_T::HcControl
<> 149:156823d33999 15886 * Offset: 0x04 Host Controller Control Register
<> 149:156823d33999 15887 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15888 * |Bits |Field |Descriptions
<> 149:156823d33999 15889 * | :----: | :----: | :---- |
<> 149:156823d33999 15890 * |[1:0] |CBSR |Control Bulk Service Ratio
<> 149:156823d33999 15891 * | | |This specifies the service ratio between Control and Bulk EDs.
<> 149:156823d33999 15892 * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
<> 149:156823d33999 15893 * | | |The internal count will be retained when crossing the frame boundary.
<> 149:156823d33999 15894 * | | |In case of reset, HCD is responsible for restoring this.
<> 149:156823d33999 15895 * | | |Value.
<> 149:156823d33999 15896 * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
<> 149:156823d33999 15897 * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
<> 149:156823d33999 15898 * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
<> 149:156823d33999 15899 * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
<> 149:156823d33999 15900 * |[2] |PLE |Periodic List Enable Bit
<> 149:156823d33999 15901 * | | |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
<> 149:156823d33999 15902 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
<> 149:156823d33999 15903 * | | |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
<> 149:156823d33999 15904 * | | |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
<> 149:156823d33999 15905 * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
<> 149:156823d33999 15906 * |[3] |IE |Isochronous List Enable Bit
<> 149:156823d33999 15907 * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
<> 149:156823d33999 15908 * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
<> 149:156823d33999 15909 * | | |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
<> 149:156823d33999 15910 * | | |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
<> 149:156823d33999 15911 * |[4] |CLE |Control List Enable Bit
<> 149:156823d33999 15912 * | | |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
<> 149:156823d33999 15913 * | | |1 = Enable processing of the Control list in the next frame.
<> 149:156823d33999 15914 * |[5] |BLE |Bulk List Enable Bit
<> 149:156823d33999 15915 * | | |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
<> 149:156823d33999 15916 * | | |1 = Enable processing of the Bulk list in the next frame.
<> 149:156823d33999 15917 * |[7:6] |HCFS |Host Controller Functional State
<> 149:156823d33999 15918 * | | |This field sets the Host Controller state.
<> 149:156823d33999 15919 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
<> 149:156823d33999 15920 * | | |States are:
<> 149:156823d33999 15921 * | | |00 = USBSUSPEND.
<> 149:156823d33999 15922 * | | |01 = USBRESUME.
<> 149:156823d33999 15923 * | | |10 = USBOPERATIONAL.
<> 149:156823d33999 15924 * | | |11 = USBRESET.
<> 149:156823d33999 15925 * @var USBH_T::HcCommandStatus
<> 149:156823d33999 15926 * Offset: 0x08 Host Controller CMD Status Register
<> 149:156823d33999 15927 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15928 * |Bits |Field |Descriptions
<> 149:156823d33999 15929 * | :----: | :----: | :---- |
<> 149:156823d33999 15930 * |[0] |HCR |Host Controller Reset
<> 149:156823d33999 15931 * | | |This bit is set to initiate the software reset of Host Controller.
<> 149:156823d33999 15932 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
<> 149:156823d33999 15933 * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
<> 149:156823d33999 15934 * | | |0 = Host Controller is not in software reset state.
<> 149:156823d33999 15935 * | | |1 = Host Controller is in software reset state.
<> 149:156823d33999 15936 * |[1] |CLF |Control List Filled
<> 149:156823d33999 15937 * | | |Set high to indicate there is an active TD on the Control List.
<> 149:156823d33999 15938 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
<> 149:156823d33999 15939 * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
<> 149:156823d33999 15940 * | | |1 = An active TD added or found on the Control list.
<> 149:156823d33999 15941 * |[2] |BLF |Bulk List Filled
<> 149:156823d33999 15942 * | | |Set high to indicate there is an active TD on the Bulk list.
<> 149:156823d33999 15943 * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
<> 149:156823d33999 15944 * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
<> 149:156823d33999 15945 * | | |1 = An active TD added or found on the Bulk list.
<> 149:156823d33999 15946 * |[17:16] |SOC |Schedule Overrun Count
<> 149:156823d33999 15947 * | | |These bits are incremented on each scheduling overrun error.
<> 149:156823d33999 15948 * | | |It is initialized to 00b and wraps around at 11b.
<> 149:156823d33999 15949 * | | |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
<> 149:156823d33999 15950 * @var USBH_T::HcInterruptStatus
<> 149:156823d33999 15951 * Offset: 0x0C Host Controller Interrupt Status Register
<> 149:156823d33999 15952 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15953 * |Bits |Field |Descriptions
<> 149:156823d33999 15954 * | :----: | :----: | :---- |
<> 149:156823d33999 15955 * |[0] |SO |Scheduling Overrun
<> 149:156823d33999 15956 * | | |Set when the List Processor determines a Schedule Overrun has occurred.
<> 149:156823d33999 15957 * | | |0 = Schedule Overrun didn't occur.
<> 149:156823d33999 15958 * | | |1 = Schedule Overrun has occurred.
<> 149:156823d33999 15959 * |[1] |WDH |Write Back Done Head
<> 149:156823d33999 15960 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
<> 149:156823d33999 15961 * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
<> 149:156823d33999 15962 * | | |0 =.Host Controller didn't update HccaDoneHead.
<> 149:156823d33999 15963 * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
<> 149:156823d33999 15964 * |[2] |SF |Start Of Frame
<> 149:156823d33999 15965 * | | |Set when the Frame Management functional block signals a 'Start of Frame' event.
<> 149:156823d33999 15966 * | | |Host Control generates a SOF token at the same time.
<> 149:156823d33999 15967 * | | |0 =.Not the start of a frame.
<> 149:156823d33999 15968 * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
<> 149:156823d33999 15969 * |[3] |RD |Resume Detected
<> 149:156823d33999 15970 * | | |Set when Host Controller detects resume signaling on a downstream port.
<> 149:156823d33999 15971 * | | |0 = No resume signaling detected on a downstream port.
<> 149:156823d33999 15972 * | | |1 = Resume signaling detected on a downstream port.
<> 149:156823d33999 15973 * |[5] |FNO |Frame Number Overflow
<> 149:156823d33999 15974 * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
<> 149:156823d33999 15975 * | | |0 = The bit 15 of Frame Number didn't change.
<> 149:156823d33999 15976 * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
<> 149:156823d33999 15977 * |[6] |RHSC |Root Hub Status Change
<> 149:156823d33999 15978 * | | |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
<> 149:156823d33999 15979 * | | |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
<> 149:156823d33999 15980 * | | |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
<> 149:156823d33999 15981 * @var USBH_T::HcInterruptEnable
<> 149:156823d33999 15982 * Offset: 0x10 Host Controller Interrupt Enable Register
<> 149:156823d33999 15983 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 15984 * |Bits |Field |Descriptions
<> 149:156823d33999 15985 * | :----: | :----: | :---- |
<> 149:156823d33999 15986 * |[0] |SO |Scheduling Overrun Enable Bit
<> 149:156823d33999 15987 * | | |Write Operation:
<> 149:156823d33999 15988 * | | |0 = No effect.
<> 149:156823d33999 15989 * | | |1 = Enable interrupt generation due to SO (HcIntSts[0]).
<> 149:156823d33999 15990 * | | |Read Operation:
<> 149:156823d33999 15991 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
<> 149:156823d33999 15992 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
<> 149:156823d33999 15993 * |[1] |WDH |Write Back Done Head Enable Bit
<> 149:156823d33999 15994 * | | |Write Operation:
<> 149:156823d33999 15995 * | | |0 = No effect.
<> 149:156823d33999 15996 * | | |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
<> 149:156823d33999 15997 * | | |Read Operation:
<> 149:156823d33999 15998 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
<> 149:156823d33999 15999 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
<> 149:156823d33999 16000 * |[2] |SF |Start Of Frame Enable Bit
<> 149:156823d33999 16001 * | | |Write Operation:
<> 149:156823d33999 16002 * | | |0 = No effect.
<> 149:156823d33999 16003 * | | |1 = Enable interrupt generation due to SF (HcIntSts[2]).
<> 149:156823d33999 16004 * | | |Read Operation:
<> 149:156823d33999 16005 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
<> 149:156823d33999 16006 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
<> 149:156823d33999 16007 * |[3] |RD |Resume Detected Enable Bit
<> 149:156823d33999 16008 * | | |Write Operation:
<> 149:156823d33999 16009 * | | |0 = No effect.
<> 149:156823d33999 16010 * | | |1 = Enable interrupt generation due to RD (HcIntSts[3]).
<> 149:156823d33999 16011 * | | |Read Operation:
<> 149:156823d33999 16012 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
<> 149:156823d33999 16013 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
<> 149:156823d33999 16014 * |[5] |FNO |Frame Number Overflow Enable Bit
<> 149:156823d33999 16015 * | | |Write Operation:
<> 149:156823d33999 16016 * | | |0 = No effect.
<> 149:156823d33999 16017 * | | |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
<> 149:156823d33999 16018 * | | |Read Operation:
<> 149:156823d33999 16019 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
<> 149:156823d33999 16020 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
<> 149:156823d33999 16021 * |[6] |RHSC |Root Hub Status Change Enable Bit
<> 149:156823d33999 16022 * | | |Write Operation:
<> 149:156823d33999 16023 * | | |0 = No effect.
<> 149:156823d33999 16024 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
<> 149:156823d33999 16025 * | | |Read Operation:
<> 149:156823d33999 16026 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
<> 149:156823d33999 16027 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
<> 149:156823d33999 16028 * |[31] |MIE |Master Interrupt Enable Bit
<> 149:156823d33999 16029 * | | |This bit is a global interrupt enable.
<> 149:156823d33999 16030 * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
<> 149:156823d33999 16031 * | | |Write Operation:
<> 149:156823d33999 16032 * | | |0 = No effect.
<> 149:156823d33999 16033 * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16034 * | | |Read Operation:
<> 149:156823d33999 16035 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16036 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16037 * @var USBH_T::HcInterruptDisable
<> 149:156823d33999 16038 * Offset: 0x14 Host Controller Interrupt Disable Register
<> 149:156823d33999 16039 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16040 * |Bits |Field |Descriptions
<> 149:156823d33999 16041 * | :----: | :----: | :---- |
<> 149:156823d33999 16042 * |[0] |SO |Scheduling Overrun Disable Bit
<> 149:156823d33999 16043 * | | |Write Operation:
<> 149:156823d33999 16044 * | | |0 = No effect.
<> 149:156823d33999 16045 * | | |1 = Disable interrupt generation due to SO (HcIntSts[0]).
<> 149:156823d33999 16046 * | | |Read Operation:
<> 149:156823d33999 16047 * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
<> 149:156823d33999 16048 * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
<> 149:156823d33999 16049 * |[1] |WDH |Write Back Done Head Disable Bit
<> 149:156823d33999 16050 * | | |Write Operation:
<> 149:156823d33999 16051 * | | |0 = No effect.
<> 149:156823d33999 16052 * | | |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
<> 149:156823d33999 16053 * | | |Read Operation:
<> 149:156823d33999 16054 * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
<> 149:156823d33999 16055 * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
<> 149:156823d33999 16056 * |[2] |SF |Start Of Frame Disable Bit
<> 149:156823d33999 16057 * | | |Write Operation:
<> 149:156823d33999 16058 * | | |0 = No effect.
<> 149:156823d33999 16059 * | | |1 = Disable interrupt generation due to SF (HcIntSts[2]).
<> 149:156823d33999 16060 * | | |Read Operation:
<> 149:156823d33999 16061 * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
<> 149:156823d33999 16062 * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
<> 149:156823d33999 16063 * |[3] |RD |Resume Detected Disable Bit
<> 149:156823d33999 16064 * | | |Write Operation:
<> 149:156823d33999 16065 * | | |0 = No effect.
<> 149:156823d33999 16066 * | | |1 = Disable interrupt generation due to RD (HcIntSts[3]).
<> 149:156823d33999 16067 * | | |Read Operation:
<> 149:156823d33999 16068 * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
<> 149:156823d33999 16069 * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
<> 149:156823d33999 16070 * |[5] |FNO |Frame Number Overflow Disable Bit
<> 149:156823d33999 16071 * | | |Write Operation:
<> 149:156823d33999 16072 * | | |0 = No effect.
<> 149:156823d33999 16073 * | | |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
<> 149:156823d33999 16074 * | | |Read Operation:
<> 149:156823d33999 16075 * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
<> 149:156823d33999 16076 * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
<> 149:156823d33999 16077 * |[6] |RHSC |Root Hub Status Change Disable Bit
<> 149:156823d33999 16078 * | | |Write Operation:
<> 149:156823d33999 16079 * | | |0 = No effect.
<> 149:156823d33999 16080 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
<> 149:156823d33999 16081 * | | |Read Operation:
<> 149:156823d33999 16082 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
<> 149:156823d33999 16083 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
<> 149:156823d33999 16084 * |[31] |MIE |Master Interrupt Disable Bit
<> 149:156823d33999 16085 * | | |Global interrupt disable. Writing '1' to disable all interrupts.
<> 149:156823d33999 16086 * | | |Write Operation:
<> 149:156823d33999 16087 * | | |0 = No effect.
<> 149:156823d33999 16088 * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16089 * | | |Read Operation:
<> 149:156823d33999 16090 * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16091 * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
<> 149:156823d33999 16092 * @var USBH_T::HcHCCA
<> 149:156823d33999 16093 * Offset: 0x18 Host Controller Communication Area Register
<> 149:156823d33999 16094 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16095 * |Bits |Field |Descriptions
<> 149:156823d33999 16096 * | :----: | :----: | :---- |
<> 149:156823d33999 16097 * |[31:8] |HCCA |Host Controller Communication Area
<> 149:156823d33999 16098 * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
<> 149:156823d33999 16099 * @var USBH_T::HcPeriodCurrentED
<> 149:156823d33999 16100 * Offset: 0x1C Host Controller Period Current ED Register
<> 149:156823d33999 16101 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16102 * |Bits |Field |Descriptions
<> 149:156823d33999 16103 * | :----: | :----: | :---- |
<> 149:156823d33999 16104 * |[31:4] |PCED |Periodic Current ED
<> 149:156823d33999 16105 * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
<> 149:156823d33999 16106 * @var USBH_T::HcControlHeadED
<> 149:156823d33999 16107 * Offset: 0x20 Host Controller Control Head ED Register
<> 149:156823d33999 16108 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16109 * |Bits |Field |Descriptions
<> 149:156823d33999 16110 * | :----: | :----: | :---- |
<> 149:156823d33999 16111 * |[31:4] |CHED |Control Head ED
<> 149:156823d33999 16112 * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
<> 149:156823d33999 16113 * @var USBH_T::HcControlCurrentED
<> 149:156823d33999 16114 * Offset: 0x24 Host Controller Control Current ED Register
<> 149:156823d33999 16115 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16116 * |Bits |Field |Descriptions
<> 149:156823d33999 16117 * | :----: | :----: | :---- |
<> 149:156823d33999 16118 * |[31:4] |CCED |Control Current Head ED
<> 149:156823d33999 16119 * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
<> 149:156823d33999 16120 * @var USBH_T::HcBulkHeadED
<> 149:156823d33999 16121 * Offset: 0x28 Host Controller Bulk Head ED Register
<> 149:156823d33999 16122 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16123 * |Bits |Field |Descriptions
<> 149:156823d33999 16124 * | :----: | :----: | :---- |
<> 149:156823d33999 16125 * |[31:4] |BHED |Bulk Head ED
<> 149:156823d33999 16126 * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
<> 149:156823d33999 16127 * @var USBH_T::HcBulkCurrentED
<> 149:156823d33999 16128 * Offset: 0x2C Host Controller Bulk Current ED Register
<> 149:156823d33999 16129 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16130 * |Bits |Field |Descriptions
<> 149:156823d33999 16131 * | :----: | :----: | :---- |
<> 149:156823d33999 16132 * |[31:4] |BCED |Bulk Current Head ED
<> 149:156823d33999 16133 * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
<> 149:156823d33999 16134 * @var USBH_T::HcDoneHead
<> 149:156823d33999 16135 * Offset: 0x30 Host Controller Done Head Register
<> 149:156823d33999 16136 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16137 * |Bits |Field |Descriptions
<> 149:156823d33999 16138 * | :----: | :----: | :---- |
<> 149:156823d33999 16139 * |[31:4] |DH |Done Head
<> 149:156823d33999 16140 * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
<> 149:156823d33999 16141 * @var USBH_T::HcFmInterval
<> 149:156823d33999 16142 * Offset: 0x34 Host Controller Frame Interval Register
<> 149:156823d33999 16143 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16144 * |Bits |Field |Descriptions
<> 149:156823d33999 16145 * | :----: | :----: | :---- |
<> 149:156823d33999 16146 * |[13:0] |FI |Frame Interval
<> 149:156823d33999 16147 * | | |This field specifies the length of a frame as (bit times - 1).
<> 149:156823d33999 16148 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
<> 149:156823d33999 16149 * |[30:16] |FSMPS |FS Largest Data Packet
<> 149:156823d33999 16150 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
<> 149:156823d33999 16151 * |[31] |FIT |Frame Interval Toggle
<> 149:156823d33999 16152 * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
<> 149:156823d33999 16153 * | | |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
<> 149:156823d33999 16154 * | | |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
<> 149:156823d33999 16155 * @var USBH_T::HcFmRemaining
<> 149:156823d33999 16156 * Offset: 0x38 Host Controller Frame Remaining Register
<> 149:156823d33999 16157 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16158 * |Bits |Field |Descriptions
<> 149:156823d33999 16159 * | :----: | :----: | :---- |
<> 149:156823d33999 16160 * |[13:0] |FR |Frame Remaining
<> 149:156823d33999 16161 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
<> 149:156823d33999 16162 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
<> 149:156823d33999 16163 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
<> 149:156823d33999 16164 * |[31] |FRT |Frame Remaining Toggle
<> 149:156823d33999 16165 * | | |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
<> 149:156823d33999 16166 * @var USBH_T::HcFmNumber
<> 149:156823d33999 16167 * Offset: 0x3C Host Controller Frame Number Register
<> 149:156823d33999 16168 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16169 * |Bits |Field |Descriptions
<> 149:156823d33999 16170 * | :----: | :----: | :---- |
<> 149:156823d33999 16171 * |[15:0] |FN |Frame Number
<> 149:156823d33999 16172 * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
<> 149:156823d33999 16173 * | | |The count rolls over from 'FFFFh' to '0h.'.
<> 149:156823d33999 16174 * @var USBH_T::HcPeriodicStart
<> 149:156823d33999 16175 * Offset: 0x40 Host Controller Periodic Start Register
<> 149:156823d33999 16176 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16177 * |Bits |Field |Descriptions
<> 149:156823d33999 16178 * | :----: | :----: | :---- |
<> 149:156823d33999 16179 * |[13:0] |PS |Periodic Start
<> 149:156823d33999 16180 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
<> 149:156823d33999 16181 * @var USBH_T::HcLSThreshold
<> 149:156823d33999 16182 * Offset: 0x44 Host Controller Low-speed Threshold Register
<> 149:156823d33999 16183 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16184 * |Bits |Field |Descriptions
<> 149:156823d33999 16185 * | :----: | :----: | :---- |
<> 149:156823d33999 16186 * |[11:0] |LST |Low-Speed Threshold
<> 149:156823d33999 16187 * | | |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
<> 149:156823d33999 16188 * | | |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
<> 149:156823d33999 16189 * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
<> 149:156823d33999 16190 * @var USBH_T::HcRhDescriptorA
<> 149:156823d33999 16191 * Offset: 0x48 Host Controller Root Hub Descriptor A Register
<> 149:156823d33999 16192 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16193 * |Bits |Field |Descriptions
<> 149:156823d33999 16194 * | :----: | :----: | :---- |
<> 149:156823d33999 16195 * |[7:0] |NDP |Number Downstream Ports
<> 149:156823d33999 16196 * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
<> 149:156823d33999 16197 * |[8] |PSM |Power Switching Mode
<> 149:156823d33999 16198 * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
<> 149:156823d33999 16199 * | | |0 = Global Switching.
<> 149:156823d33999 16200 * | | |1 = Individual Switching.
<> 149:156823d33999 16201 * |[11] |OCPM |Over Current Protection Mode
<> 149:156823d33999 16202 * | | |This bit describes how the over current status for the Root Hub ports reported.
<> 149:156823d33999 16203 * | | |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
<> 149:156823d33999 16204 * | | |0 = Global Over current.
<> 149:156823d33999 16205 * | | |1 = Individual Over current.
<> 149:156823d33999 16206 * |[12] |NOCP |No Over Current Protection
<> 149:156823d33999 16207 * | | |This bit describes how the over current status for the Root Hub ports reported.
<> 149:156823d33999 16208 * | | |0 = Over current status is reported.
<> 149:156823d33999 16209 * | | |1 = Over current status is not reported.
<> 149:156823d33999 16210 * @var USBH_T::HcRhDescriptorB
<> 149:156823d33999 16211 * Offset: 0x4C Host Controller Root Hub Descriptor B Register
<> 149:156823d33999 16212 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16213 * |Bits |Field |Descriptions
<> 149:156823d33999 16214 * | :----: | :----: | :---- |
<> 149:156823d33999 16215 * |[31:16] |PPCM |Port Power Control Mask
<> 149:156823d33999 16216 * | | |Global power switching.
<> 149:156823d33999 16217 * | | |This field is only valid if PowerSwitchingMode is set (individual port switching).
<> 149:156823d33999 16218 * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
<> 149:156823d33999 16219 * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
<> 149:156823d33999 16220 * | | |0 = Port power controlled by global power switching.
<> 149:156823d33999 16221 * | | |1 = Port power controlled by port power switching.
<> 149:156823d33999 16222 * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
<> 149:156823d33999 16223 * @var USBH_T::HcRhStatus
<> 149:156823d33999 16224 * Offset: 0x50 Host Controller Root Hub Status Register
<> 149:156823d33999 16225 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16226 * |Bits |Field |Descriptions
<> 149:156823d33999 16227 * | :----: | :----: | :---- |
<> 149:156823d33999 16228 * |[0] |LPS |Clear Global Power
<> 149:156823d33999 16229 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
<> 149:156823d33999 16230 * | | |This bit always read as zero.
<> 149:156823d33999 16231 * | | |Write Operation:
<> 149:156823d33999 16232 * | | |0 = No effect.
<> 149:156823d33999 16233 * | | |1 = Clear global power.
<> 149:156823d33999 16234 * |[1] |OCI |Over Current Indicator
<> 149:156823d33999 16235 * | | |This bit reflects the state of the over current status pin.
<> 149:156823d33999 16236 * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
<> 149:156823d33999 16237 * | | |0 = No over current condition.
<> 149:156823d33999 16238 * | | |1 = Over current condition.
<> 149:156823d33999 16239 * |[15] |DRWE |Device Remote Wakeup Enable Bit
<> 149:156823d33999 16240 * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
<> 149:156823d33999 16241 * | | |Write Operation:
<> 149:156823d33999 16242 * | | |0 = No effect.
<> 149:156823d33999 16243 * | | |1 = Enable Connect Status Change as a remote wake-up event.
<> 149:156823d33999 16244 * | | |Read Operation:
<> 149:156823d33999 16245 * | | |0 = Connect Status Change as a remote wake-up event disabled.
<> 149:156823d33999 16246 * | | |1 = Connect Status Change as a remote wake-up event enabled.
<> 149:156823d33999 16247 * |[16] |LPSC |Set Global Power
<> 149:156823d33999 16248 * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
<> 149:156823d33999 16249 * | | |This bit always read as zero.
<> 149:156823d33999 16250 * | | |Write Operation:
<> 149:156823d33999 16251 * | | |0 = No effect.
<> 149:156823d33999 16252 * | | |1 = Set global power.
<> 149:156823d33999 16253 * |[17] |OCIC |Over Current Indicator Change
<> 149:156823d33999 16254 * | | |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
<> 149:156823d33999 16255 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16256 * | | |0 = OCI (HcRhSts[1]) didn't change.
<> 149:156823d33999 16257 * | | |1 = OCI (HcRhSts[1]) change.
<> 149:156823d33999 16258 * |[31] |CRWE |Clear Remote Wake-up Enable Bit
<> 149:156823d33999 16259 * | | |This bit is use to clear DRWE (HcRhSts[15]).
<> 149:156823d33999 16260 * | | |This bit always read as zero.
<> 149:156823d33999 16261 * | | |Write Operation:
<> 149:156823d33999 16262 * | | |0 = No effect.
<> 149:156823d33999 16263 * | | |1 = Clear DRWE (HcRhSts[15]).
<> 149:156823d33999 16264 * @var USBH_T::HcRhPortStatus
<> 149:156823d33999 16265 * Offset: 0x54 Host Controller Root Hub Port Status [1]
<> 149:156823d33999 16266 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16267 * |Bits |Field |Descriptions
<> 149:156823d33999 16268 * | :----: | :----: | :---- |
<> 149:156823d33999 16269 * |[0] |CCS |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
<> 149:156823d33999 16270 * | | |Write Operation:
<> 149:156823d33999 16271 * | | |0 = No effect.
<> 149:156823d33999 16272 * | | |1 = Clear port enable.
<> 149:156823d33999 16273 * | | |Read Operation:
<> 149:156823d33999 16274 * | | |0 = No device connected.
<> 149:156823d33999 16275 * | | |1 = Device connected.
<> 149:156823d33999 16276 * |[1] |PES |Port Enable Status
<> 149:156823d33999 16277 * | | |Write Operation:
<> 149:156823d33999 16278 * | | |0 = No effect.
<> 149:156823d33999 16279 * | | |1 = Set port enable.
<> 149:156823d33999 16280 * | | |Read Operation:
<> 149:156823d33999 16281 * | | |0 = Port Disabled.
<> 149:156823d33999 16282 * | | |1 = Port Enabled.
<> 149:156823d33999 16283 * |[2] |PSS |Port Suspend Status
<> 149:156823d33999 16284 * | | |This bit indicates the port is suspended
<> 149:156823d33999 16285 * | | |Write Operation:
<> 149:156823d33999 16286 * | | |0 = No effect.
<> 149:156823d33999 16287 * | | |1 = Set port suspend.
<> 149:156823d33999 16288 * | | |Read Operation:
<> 149:156823d33999 16289 * | | |0 = Port is not suspended.
<> 149:156823d33999 16290 * | | |1 = Port is selectively suspended.
<> 149:156823d33999 16291 * |[3] |POCI |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
<> 149:156823d33999 16292 * | | |This bit reflects the state of the over current status pin dedicated to this port.
<> 149:156823d33999 16293 * | | |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
<> 149:156823d33999 16294 * | | |This bit is also used to initiate the selective result sequence for the port.
<> 149:156823d33999 16295 * | | |Write Operation:
<> 149:156823d33999 16296 * | | |0 = No effect.
<> 149:156823d33999 16297 * | | |1 = Clear port suspend.
<> 149:156823d33999 16298 * | | |Read Operation:
<> 149:156823d33999 16299 * | | |0 = No over current condition.
<> 149:156823d33999 16300 * | | |1 = Over current condition.
<> 149:156823d33999 16301 * |[4] |PRS |Port Reset Status
<> 149:156823d33999 16302 * | | |This bit reflects the reset state of the port.
<> 149:156823d33999 16303 * | | |Write Operation:
<> 149:156823d33999 16304 * | | |0 = No effect.
<> 149:156823d33999 16305 * | | |1 = Set port reset.
<> 149:156823d33999 16306 * | | |Read Operation
<> 149:156823d33999 16307 * | | |0 = Port reset signal is not active.
<> 149:156823d33999 16308 * | | |1 = Port reset signal is active.
<> 149:156823d33999 16309 * |[8] |PPS |Port Power Status
<> 149:156823d33999 16310 * | | |This bit reflects the power state of the port regardless of the power switching mode.
<> 149:156823d33999 16311 * | | |Write Operation:
<> 149:156823d33999 16312 * | | |0 = No effect.
<> 149:156823d33999 16313 * | | |1 = Port Power Enabled.
<> 149:156823d33999 16314 * | | |Read Operation:
<> 149:156823d33999 16315 * | | |0 = Port power is Disabled.
<> 149:156823d33999 16316 * | | |1 = Port power is Enabled.
<> 149:156823d33999 16317 * |[9] |LSDA |Low Speed Device Attached (Read) Or Clear Port Power (Write)
<> 149:156823d33999 16318 * | | |This bit defines the speed (and bud idle) of the attached device.
<> 149:156823d33999 16319 * | | |It is only valid when CCS (HcRhPrt1[0]) is set.
<> 149:156823d33999 16320 * | | |This bit is also used to clear port power.
<> 149:156823d33999 16321 * | | |Write Operation:
<> 149:156823d33999 16322 * | | |0 = No effect.
<> 149:156823d33999 16323 * | | |1 = Clear PPS (HcRhPrt1[8]).
<> 149:156823d33999 16324 * | | |Read Operation:
<> 149:156823d33999 16325 * | | |0 = Full Speed device.
<> 149:156823d33999 16326 * | | |1 = Low-speed device.
<> 149:156823d33999 16327 * |[16] |CSC |Connect Status Change
<> 149:156823d33999 16328 * | | |This bit indicates connect or disconnect event has been detected (CCS
<> 149:156823d33999 16329 * | | |(HcRhPrt1[0]) changed).
<> 149:156823d33999 16330 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16331 * | | |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
<> 149:156823d33999 16332 * | | |1 = Hardware detection of connect/disconnect event (CCS
<> 149:156823d33999 16333 * | | |(HcRhPrt1[0]) changed).
<> 149:156823d33999 16334 * |[17] |PESC |Port Enable Status Change
<> 149:156823d33999 16335 * | | |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
<> 149:156823d33999 16336 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16337 * | | |0 = PES (HcRhPrt1[1]) didn't change.
<> 149:156823d33999 16338 * | | |1 = PES (HcRhPrt1[1]) changed.
<> 149:156823d33999 16339 * |[18] |PSSC |Port Suspend Status Change
<> 149:156823d33999 16340 * | | |This bit indicates the completion of the selective resume sequence for the port.
<> 149:156823d33999 16341 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16342 * | | |0 = Port resume is not completed.
<> 149:156823d33999 16343 * | | |1 = Port resume completed.
<> 149:156823d33999 16344 * |[19] |OCIC |Port Over Current Indicator Change
<> 149:156823d33999 16345 * | | |This bit is set when POCI (HcRhPrt1[3]) changes.
<> 149:156823d33999 16346 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16347 * | | |0 = POCI (HcRhPrt1[3]) didn't change.
<> 149:156823d33999 16348 * | | |1 = POCI (HcRhPrt1[3]) changes.
<> 149:156823d33999 16349 * |[20] |PRSC |Port Reset Status Change
<> 149:156823d33999 16350 * | | |This bit indicates that the port reset signal has completed.
<> 149:156823d33999 16351 * | | |Write 1 to clear this bit to zero.
<> 149:156823d33999 16352 * | | |0 = Port reset is not complete.
<> 149:156823d33999 16353 * | | |1 = Port reset is complete.
<> 149:156823d33999 16354 * @var USBH_T::HcPhyControl
<> 149:156823d33999 16355 * Offset: 0x200 USB Host Controller PHY Control Register
<> 149:156823d33999 16356 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16357 * |Bits |Field |Descriptions
<> 149:156823d33999 16358 * | :----: | :----: | :---- |
<> 149:156823d33999 16359 * |[27] |STBYEN |USB Transceiver Standby Enable Bit
<> 149:156823d33999 16360 * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
<> 149:156823d33999 16361 * | | |0 = The USB transceiver would never enter the standby mode.
<> 149:156823d33999 16362 * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
<> 149:156823d33999 16363 * @var USBH_T::HcMiscControl
<> 149:156823d33999 16364 * Offset: 0x204 USB Host Controller Miscellaneous Control Register
<> 149:156823d33999 16365 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16366 * |Bits |Field |Descriptions
<> 149:156823d33999 16367 * | :----: | :----: | :---- |
<> 149:156823d33999 16368 * |[1] |ABORT |AHB Bus ERROR Response
<> 149:156823d33999 16369 * | | |This bit indicates there is an ERROR response received in AHB bus.
<> 149:156823d33999 16370 * | | |0 = No ERROR response received.
<> 149:156823d33999 16371 * | | |1 = ERROR response received.
<> 149:156823d33999 16372 * |[3] |OCAL |Over Current Active Low
<> 149:156823d33999 16373 * | | |This bit controls the polarity of over current flag from external power IC.
<> 149:156823d33999 16374 * | | |0 = Over current flag is high active.
<> 149:156823d33999 16375 * | | |1 = Over current flag is low active.
<> 149:156823d33999 16376 * |[16] |DPRT1 |Disable Port 1
<> 149:156823d33999 16377 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
<> 149:156823d33999 16378 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
<> 149:156823d33999 16379 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
<> 149:156823d33999 16380 * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
<> 149:156823d33999 16381 * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
<> 149:156823d33999 16382 */
<> 149:156823d33999 16383
<> 149:156823d33999 16384 __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
<> 149:156823d33999 16385 __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
<> 149:156823d33999 16386 __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
<> 149:156823d33999 16387 __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
<> 149:156823d33999 16388 __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
<> 149:156823d33999 16389 __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
<> 149:156823d33999 16390 __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
<> 149:156823d33999 16391 __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
<> 149:156823d33999 16392 __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
<> 149:156823d33999 16393 __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
<> 149:156823d33999 16394 __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
<> 149:156823d33999 16395 __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
<> 149:156823d33999 16396 __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
<> 149:156823d33999 16397 __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
<> 149:156823d33999 16398 __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
<> 149:156823d33999 16399 __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
<> 149:156823d33999 16400 __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
<> 149:156823d33999 16401 __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
<> 149:156823d33999 16402 __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
<> 149:156823d33999 16403 __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
<> 149:156823d33999 16404 __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
<> 149:156823d33999 16405 __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
<> 149:156823d33999 16406 __I uint32_t RESERVE0[105];
<> 149:156823d33999 16407 __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
<> 149:156823d33999 16408 __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
<> 149:156823d33999 16409
<> 149:156823d33999 16410 } USBH_T;
<> 149:156823d33999 16411
<> 149:156823d33999 16412
<> 149:156823d33999 16413
<> 149:156823d33999 16414
<> 149:156823d33999 16415 /**
<> 149:156823d33999 16416 @addtogroup USBH_CONST USBH Bit Field Definition
<> 149:156823d33999 16417 Constant Definitions for USBH Controller
<> 149:156823d33999 16418 @{ */
<> 149:156823d33999 16419
<> 149:156823d33999 16420 #define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
<> 149:156823d33999 16421 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
<> 149:156823d33999 16422
<> 149:156823d33999 16423 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
<> 149:156823d33999 16424 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
<> 149:156823d33999 16425
<> 149:156823d33999 16426 #define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: CBSR Position */
<> 149:156823d33999 16427 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: CBSR Mask */
<> 149:156823d33999 16428
<> 149:156823d33999 16429 #define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
<> 149:156823d33999 16430 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
<> 149:156823d33999 16431
<> 149:156823d33999 16432 #define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
<> 149:156823d33999 16433 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
<> 149:156823d33999 16434
<> 149:156823d33999 16435 #define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
<> 149:156823d33999 16436 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
<> 149:156823d33999 16437
<> 149:156823d33999 16438 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
<> 149:156823d33999 16439 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
<> 149:156823d33999 16440
<> 149:156823d33999 16441 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
<> 149:156823d33999 16442 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
<> 149:156823d33999 16443
<> 149:156823d33999 16444 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
<> 149:156823d33999 16445 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
<> 149:156823d33999 16446
<> 149:156823d33999 16447 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
<> 149:156823d33999 16448 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
<> 149:156823d33999 16449
<> 149:156823d33999 16450 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
<> 149:156823d33999 16451 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
<> 149:156823d33999 16452
<> 149:156823d33999 16453 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
<> 149:156823d33999 16454 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
<> 149:156823d33999 16455
<> 149:156823d33999 16456 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position */
<> 149:156823d33999 16457 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
<> 149:156823d33999 16458
<> 149:156823d33999 16459 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
<> 149:156823d33999 16460 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
<> 149:156823d33999 16461
<> 149:156823d33999 16462 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
<> 149:156823d33999 16463 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
<> 149:156823d33999 16464
<> 149:156823d33999 16465 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position */
<> 149:156823d33999 16466 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
<> 149:156823d33999 16467
<> 149:156823d33999 16468 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position */
<> 149:156823d33999 16469 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
<> 149:156823d33999 16470
<> 149:156823d33999 16471 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
<> 149:156823d33999 16472 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
<> 149:156823d33999 16473
<> 149:156823d33999 16474 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position */
<> 149:156823d33999 16475 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
<> 149:156823d33999 16476
<> 149:156823d33999 16477 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
<> 149:156823d33999 16478 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
<> 149:156823d33999 16479
<> 149:156823d33999 16480 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
<> 149:156823d33999 16481 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
<> 149:156823d33999 16482
<> 149:156823d33999 16483 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position */
<> 149:156823d33999 16484 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
<> 149:156823d33999 16485
<> 149:156823d33999 16486 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position */
<> 149:156823d33999 16487 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
<> 149:156823d33999 16488
<> 149:156823d33999 16489 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position */
<> 149:156823d33999 16490 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
<> 149:156823d33999 16491
<> 149:156823d33999 16492 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position */
<> 149:156823d33999 16493 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
<> 149:156823d33999 16494
<> 149:156823d33999 16495 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position */
<> 149:156823d33999 16496 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
<> 149:156823d33999 16497
<> 149:156823d33999 16498 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position */
<> 149:156823d33999 16499 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
<> 149:156823d33999 16500
<> 149:156823d33999 16501 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position */
<> 149:156823d33999 16502 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
<> 149:156823d33999 16503
<> 149:156823d33999 16504 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position */
<> 149:156823d33999 16505 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
<> 149:156823d33999 16506
<> 149:156823d33999 16507 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position */
<> 149:156823d33999 16508 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
<> 149:156823d33999 16509
<> 149:156823d33999 16510 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position */
<> 149:156823d33999 16511 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
<> 149:156823d33999 16512
<> 149:156823d33999 16513 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
<> 149:156823d33999 16514 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
<> 149:156823d33999 16515
<> 149:156823d33999 16516 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position */
<> 149:156823d33999 16517 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
<> 149:156823d33999 16518
<> 149:156823d33999 16519 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
<> 149:156823d33999 16520 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
<> 149:156823d33999 16521
<> 149:156823d33999 16522 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position */
<> 149:156823d33999 16523 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
<> 149:156823d33999 16524
<> 149:156823d33999 16525 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
<> 149:156823d33999 16526 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
<> 149:156823d33999 16527
<> 149:156823d33999 16528 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
<> 149:156823d33999 16529 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
<> 149:156823d33999 16530
<> 149:156823d33999 16531 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
<> 149:156823d33999 16532 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
<> 149:156823d33999 16533
<> 149:156823d33999 16534 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
<> 149:156823d33999 16535 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
<> 149:156823d33999 16536
<> 149:156823d33999 16537 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
<> 149:156823d33999 16538 #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
<> 149:156823d33999 16539
<> 149:156823d33999 16540 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
<> 149:156823d33999 16541 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
<> 149:156823d33999 16542
<> 149:156823d33999 16543 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
<> 149:156823d33999 16544 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
<> 149:156823d33999 16545
<> 149:156823d33999 16546 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
<> 149:156823d33999 16547 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
<> 149:156823d33999 16548
<> 149:156823d33999 16549 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
<> 149:156823d33999 16550 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
<> 149:156823d33999 16551
<> 149:156823d33999 16552 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
<> 149:156823d33999 16553 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
<> 149:156823d33999 16554
<> 149:156823d33999 16555 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
<> 149:156823d33999 16556 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
<> 149:156823d33999 16557
<> 149:156823d33999 16558 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
<> 149:156823d33999 16559 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
<> 149:156823d33999 16560
<> 149:156823d33999 16561 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
<> 149:156823d33999 16562 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
<> 149:156823d33999 16563
<> 149:156823d33999 16564 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
<> 149:156823d33999 16565 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
<> 149:156823d33999 16566
<> 149:156823d33999 16567 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
<> 149:156823d33999 16568 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
<> 149:156823d33999 16569
<> 149:156823d33999 16570 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
<> 149:156823d33999 16571 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
<> 149:156823d33999 16572
<> 149:156823d33999 16573 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
<> 149:156823d33999 16574 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
<> 149:156823d33999 16575
<> 149:156823d33999 16576 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
<> 149:156823d33999 16577 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
<> 149:156823d33999 16578
<> 149:156823d33999 16579 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
<> 149:156823d33999 16580 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
<> 149:156823d33999 16581
<> 149:156823d33999 16582 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
<> 149:156823d33999 16583 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
<> 149:156823d33999 16584
<> 149:156823d33999 16585 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
<> 149:156823d33999 16586 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
<> 149:156823d33999 16587
<> 149:156823d33999 16588 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
<> 149:156823d33999 16589 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
<> 149:156823d33999 16590
<> 149:156823d33999 16591 #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
<> 149:156823d33999 16592 #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
<> 149:156823d33999 16593
<> 149:156823d33999 16594 #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
<> 149:156823d33999 16595 #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
<> 149:156823d33999 16596
<> 149:156823d33999 16597 #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
<> 149:156823d33999 16598 #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
<> 149:156823d33999 16599
<> 149:156823d33999 16600 #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
<> 149:156823d33999 16601 #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
<> 149:156823d33999 16602
<> 149:156823d33999 16603 #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
<> 149:156823d33999 16604 #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
<> 149:156823d33999 16605
<> 149:156823d33999 16606 #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
<> 149:156823d33999 16607 #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
<> 149:156823d33999 16608
<> 149:156823d33999 16609 #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
<> 149:156823d33999 16610 #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
<> 149:156823d33999 16611
<> 149:156823d33999 16612 #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
<> 149:156823d33999 16613 #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
<> 149:156823d33999 16614
<> 149:156823d33999 16615 #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
<> 149:156823d33999 16616 #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
<> 149:156823d33999 16617
<> 149:156823d33999 16618 #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
<> 149:156823d33999 16619 #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
<> 149:156823d33999 16620
<> 149:156823d33999 16621 #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
<> 149:156823d33999 16622 #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
<> 149:156823d33999 16623
<> 149:156823d33999 16624 #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
<> 149:156823d33999 16625 #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
<> 149:156823d33999 16626
<> 149:156823d33999 16627 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
<> 149:156823d33999 16628 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
<> 149:156823d33999 16629
<> 149:156823d33999 16630 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
<> 149:156823d33999 16631 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
<> 149:156823d33999 16632
<> 149:156823d33999 16633 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
<> 149:156823d33999 16634 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
<> 149:156823d33999 16635
<> 149:156823d33999 16636 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
<> 149:156823d33999 16637 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
<> 149:156823d33999 16638
<> 149:156823d33999 16639 /**@}*/ /* USBH_CONST */
<> 149:156823d33999 16640 /**@}*/ /* end of USBH register group */
<> 149:156823d33999 16641
<> 149:156823d33999 16642
<> 149:156823d33999 16643 /*---------------------- Watch Dog Timer Controller -------------------------*/
<> 149:156823d33999 16644 /**
<> 149:156823d33999 16645 @addtogroup WDT Watch Dog Timer Controller(WDT)
<> 149:156823d33999 16646 Memory Mapped Structure for WDT Controller
<> 149:156823d33999 16647 @{ */
<> 149:156823d33999 16648
<> 149:156823d33999 16649
<> 149:156823d33999 16650 typedef struct
<> 149:156823d33999 16651 {
<> 149:156823d33999 16652
<> 149:156823d33999 16653
<> 149:156823d33999 16654
<> 149:156823d33999 16655
<> 149:156823d33999 16656 /**
<> 149:156823d33999 16657 * @var WDT_T::CTL
<> 149:156823d33999 16658 * Offset: 0x00 WDT Control Register
<> 149:156823d33999 16659 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16660 * |Bits |Field |Descriptions
<> 149:156823d33999 16661 * | :----: | :----: | :---- |
<> 149:156823d33999 16662 * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
<> 149:156823d33999 16663 * | | |0 = No effect.
<> 149:156823d33999 16664 * | | |1 = Reset the internal 18-bit WDT up counter value.
<> 149:156823d33999 16665 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16666 * | | |Note2: This bit will be automatically cleared by hardware.
<> 149:156823d33999 16667 * |[1] |RSTEN |WDT Time-Out Reset Enable Control (Write Protect)
<> 149:156823d33999 16668 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
<> 149:156823d33999 16669 * | | |0 = WDT time-out reset function Disabled.
<> 149:156823d33999 16670 * | | |1 = WDT time-out reset function Enabled.
<> 149:156823d33999 16671 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16672 * |[2] |RSTF |WDT Time-Out Reset Flag
<> 149:156823d33999 16673 * | | |This bit indicates the system has been reset by WDT time-out reset or not.
<> 149:156823d33999 16674 * | | |0 = WDT time-out reset did not occur.
<> 149:156823d33999 16675 * | | |1 = WDT time-out reset occurred.
<> 149:156823d33999 16676 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 16677 * |[3] |IF |WDT Time-Out Interrupt Flag
<> 149:156823d33999 16678 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
<> 149:156823d33999 16679 * | | |0 = WDT time-out interrupt did not occur.
<> 149:156823d33999 16680 * | | |1 = WDT time-out interrupt occurred.
<> 149:156823d33999 16681 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 16682 * |[4] |WKEN |WDT Time-Out Wake-Up Function Control (Write Protect)
<> 149:156823d33999 16683 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
<> 149:156823d33999 16684 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
<> 149:156823d33999 16685 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
<> 149:156823d33999 16686 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16687 * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
<> 149:156823d33999 16688 * |[5] |WKF |WDT Time-Out Wake-Up Flag
<> 149:156823d33999 16689 * | | |This bit indicates the interrupt wake-up flag status of WDT
<> 149:156823d33999 16690 * | | |0 = WDT does not cause chip wake-up.
<> 149:156823d33999 16691 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
<> 149:156823d33999 16692 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16693 * | | |Note2: This bit is cleared by writing 1 to it.
<> 149:156823d33999 16694 * |[6] |INTEN |WDT Time-Out Interrupt Enable Control (Write Protect)
<> 149:156823d33999 16695 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
<> 149:156823d33999 16696 * | | |0 = WDT time-out interrupt Disabled.
<> 149:156823d33999 16697 * | | |1 = WDT time-out interrupt Enabled.
<> 149:156823d33999 16698 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16699 * |[7] |WDTEN |WDT Enable Control (Write Protect)
<> 149:156823d33999 16700 * | | |0 = WDT Disabled (This action will reset the internal up counter value).
<> 149:156823d33999 16701 * | | |1 = WDT Enabled.
<> 149:156823d33999 16702 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16703 * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
<> 149:156823d33999 16704 * |[10:8] |TOUTSEL |WDT Time-Out Interval Selection (Write Protect)
<> 149:156823d33999 16705 * | | |These three bits select the time-out interval period for the WDT.
<> 149:156823d33999 16706 * | | |000 = (2^4)*TWDT.
<> 149:156823d33999 16707 * | | |001 = (2^6)*TWDT.
<> 149:156823d33999 16708 * | | |010 = (2^8)*TWDT.
<> 149:156823d33999 16709 * | | |011 = (2^10)*TWDT.
<> 149:156823d33999 16710 * | | |100 = (2^12)*TWDT.
<> 149:156823d33999 16711 * | | |101 = (2^14)*TWDT.
<> 149:156823d33999 16712 * | | |110 = (2^16)*TWDT.
<> 149:156823d33999 16713 * | | |111 = (2^18)*TWDT.
<> 149:156823d33999 16714 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16715 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
<> 149:156823d33999 16716 * | | |0 = ICE debug mode acknowledgement affects WDT counting.
<> 149:156823d33999 16717 * | | |WDT up counter will be held while CPU is held by ICE.
<> 149:156823d33999 16718 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 149:156823d33999 16719 * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
<> 149:156823d33999 16720 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16721 * @var WDT_T::ALTCTL
<> 149:156823d33999 16722 * Offset: 0x04 WDT Alternative Control Register
<> 149:156823d33999 16723 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16724 * |Bits |Field |Descriptions
<> 149:156823d33999 16725 * | :----: | :----: | :---- |
<> 149:156823d33999 16726 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
<> 149:156823d33999 16727 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
<> 149:156823d33999 16728 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
<> 149:156823d33999 16729 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
<> 149:156823d33999 16730 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
<> 149:156823d33999 16731 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
<> 149:156823d33999 16732 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
<> 149:156823d33999 16733 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
<> 149:156823d33999 16734 * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
<> 149:156823d33999 16735 */
<> 149:156823d33999 16736
<> 149:156823d33999 16737 __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
<> 149:156823d33999 16738 __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
<> 149:156823d33999 16739
<> 149:156823d33999 16740 } WDT_T;
<> 149:156823d33999 16741
<> 149:156823d33999 16742
<> 149:156823d33999 16743
<> 149:156823d33999 16744 /**
<> 149:156823d33999 16745 @addtogroup WDT_CONST WDT Bit Field Definition
<> 149:156823d33999 16746 Constant Definitions for WDT Controller
<> 149:156823d33999 16747 @{ */
<> 149:156823d33999 16748
<> 149:156823d33999 16749 #define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
<> 149:156823d33999 16750 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
<> 149:156823d33999 16751
<> 149:156823d33999 16752 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
<> 149:156823d33999 16753 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
<> 149:156823d33999 16754
<> 149:156823d33999 16755 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
<> 149:156823d33999 16756 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
<> 149:156823d33999 16757
<> 149:156823d33999 16758 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
<> 149:156823d33999 16759 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
<> 149:156823d33999 16760
<> 149:156823d33999 16761 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
<> 149:156823d33999 16762 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
<> 149:156823d33999 16763
<> 149:156823d33999 16764 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
<> 149:156823d33999 16765 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
<> 149:156823d33999 16766
<> 149:156823d33999 16767 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
<> 149:156823d33999 16768 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
<> 149:156823d33999 16769
<> 149:156823d33999 16770 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
<> 149:156823d33999 16771 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
<> 149:156823d33999 16772
<> 149:156823d33999 16773 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
<> 149:156823d33999 16774 #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
<> 149:156823d33999 16775
<> 149:156823d33999 16776 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
<> 149:156823d33999 16777 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
<> 149:156823d33999 16778
<> 149:156823d33999 16779 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
<> 149:156823d33999 16780 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
<> 149:156823d33999 16781
<> 149:156823d33999 16782 /**@}*/ /* WDT_CONST */
<> 149:156823d33999 16783 /**@}*/ /* end of WDT register group */
<> 149:156823d33999 16784
<> 149:156823d33999 16785
<> 149:156823d33999 16786 /*---------------------- Window Watchdog Timer -------------------------*/
<> 149:156823d33999 16787 /**
<> 149:156823d33999 16788 @addtogroup WWDT Window Watchdog Timer(WWDT)
<> 149:156823d33999 16789 Memory Mapped Structure for WWDT Controller
<> 149:156823d33999 16790 @{ */
<> 149:156823d33999 16791
<> 149:156823d33999 16792
<> 149:156823d33999 16793 typedef struct
<> 149:156823d33999 16794 {
<> 149:156823d33999 16795
<> 149:156823d33999 16796
<> 149:156823d33999 16797
<> 149:156823d33999 16798
<> 149:156823d33999 16799 /**
<> 149:156823d33999 16800 * @var WWDT_T::RLDCNT
<> 149:156823d33999 16801 * Offset: 0x00 WWDT Reload Counter Register
<> 149:156823d33999 16802 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16803 * |Bits |Field |Descriptions
<> 149:156823d33999 16804 * | :----: | :----: | :---- |
<> 149:156823d33999 16805 * |[31:0] |WWDT_RLDCNT|WWDT Reload Counter Register
<> 149:156823d33999 16806 * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
<> 149:156823d33999 16807 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
<> 149:156823d33999 16808 * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
<> 149:156823d33999 16809 * @var WWDT_T::CTL
<> 149:156823d33999 16810 * Offset: 0x04 WWDT Control Register
<> 149:156823d33999 16811 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16812 * |Bits |Field |Descriptions
<> 149:156823d33999 16813 * | :----: | :----: | :---- |
<> 149:156823d33999 16814 * |[0] |WWDTEN |WWDT Enable Control Bit
<> 149:156823d33999 16815 * | | |Set this bit to enable WWDT counter counting.
<> 149:156823d33999 16816 * | | |0 = WWDT counter is stopped.
<> 149:156823d33999 16817 * | | |1 = WWDT counter is starting counting.
<> 149:156823d33999 16818 * |[1] |INTEN |WWDT Interrupt Enable Control Bit
<> 149:156823d33999 16819 * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
<> 149:156823d33999 16820 * | | |0 = WWDT counter compare match interrupt Disabled.
<> 149:156823d33999 16821 * | | |1 = WWDT counter compare match interrupt Enabled.
<> 149:156823d33999 16822 * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
<> 149:156823d33999 16823 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
<> 149:156823d33999 16824 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
<> 149:156823d33999 16825 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
<> 149:156823d33999 16826 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
<> 149:156823d33999 16827 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
<> 149:156823d33999 16828 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
<> 149:156823d33999 16829 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
<> 149:156823d33999 16830 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
<> 149:156823d33999 16831 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
<> 149:156823d33999 16832 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
<> 149:156823d33999 16833 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
<> 149:156823d33999 16834 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
<> 149:156823d33999 16835 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
<> 149:156823d33999 16836 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
<> 149:156823d33999 16837 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
<> 149:156823d33999 16838 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
<> 149:156823d33999 16839 * |[21:16] |CMPDAT |WWDT Window Compare Register
<> 149:156823d33999 16840 * | | |Set this register to adjust the valid reload window.
<> 149:156823d33999 16841 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
<> 149:156823d33999 16842 * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
<> 149:156823d33999 16843 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
<> 149:156823d33999 16844 * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
<> 149:156823d33999 16845 * | | |WWDT down counter will be held while CPU is held by ICE.
<> 149:156823d33999 16846 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 149:156823d33999 16847 * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
<> 149:156823d33999 16848 * @var WWDT_T::STATUS
<> 149:156823d33999 16849 * Offset: 0x08 WWDT Status Register
<> 149:156823d33999 16850 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16851 * |Bits |Field |Descriptions
<> 149:156823d33999 16852 * | :----: | :----: | :---- |
<> 149:156823d33999 16853 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
<> 149:156823d33999 16854 * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
<> 149:156823d33999 16855 * | | |0 = No effect.
<> 149:156823d33999 16856 * | | |1 = WWDT counter value matches CMPDAT.
<> 149:156823d33999 16857 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 16858 * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
<> 149:156823d33999 16859 * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
<> 149:156823d33999 16860 * | | |0 = WWDT time-out reset did not occur.
<> 149:156823d33999 16861 * | | |1 = WWDT time-out reset occurred.
<> 149:156823d33999 16862 * | | |Note: This bit is cleared by writing 1 to it.
<> 149:156823d33999 16863 * @var WWDT_T::CNT
<> 149:156823d33999 16864 * Offset: 0x0C WWDT Counter Value Register
<> 149:156823d33999 16865 * ---------------------------------------------------------------------------------------------------
<> 149:156823d33999 16866 * |Bits |Field |Descriptions
<> 149:156823d33999 16867 * | :----: | :----: | :---- |
<> 149:156823d33999 16868 * |[5:0] |CNTDAT |WWDT Counter Value
<> 149:156823d33999 16869 * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
<> 149:156823d33999 16870 */
<> 149:156823d33999 16871
<> 149:156823d33999 16872 __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
<> 149:156823d33999 16873 __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
<> 149:156823d33999 16874 __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
<> 149:156823d33999 16875 __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
<> 149:156823d33999 16876
<> 149:156823d33999 16877 } WWDT_T;
<> 149:156823d33999 16878
<> 149:156823d33999 16879
<> 149:156823d33999 16880
<> 149:156823d33999 16881 /**
<> 149:156823d33999 16882 @addtogroup WWDT_CONST WWDT Bit Field Definition
<> 149:156823d33999 16883 Constant Definitions for WWDT Controller
<> 149:156823d33999 16884 @{ */
<> 149:156823d33999 16885
<> 149:156823d33999 16886 #define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position */
<> 149:156823d33999 16887 #define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask */
<> 149:156823d33999 16888
<> 149:156823d33999 16889 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
<> 149:156823d33999 16890 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
<> 149:156823d33999 16891
<> 149:156823d33999 16892 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
<> 149:156823d33999 16893 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
<> 149:156823d33999 16894
<> 149:156823d33999 16895 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
<> 149:156823d33999 16896 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
<> 149:156823d33999 16897
<> 149:156823d33999 16898 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
<> 149:156823d33999 16899 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
<> 149:156823d33999 16900
<> 149:156823d33999 16901 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
<> 149:156823d33999 16902 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
<> 149:156823d33999 16903
<> 149:156823d33999 16904 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
<> 149:156823d33999 16905 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
<> 149:156823d33999 16906
<> 149:156823d33999 16907 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
<> 149:156823d33999 16908 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
<> 149:156823d33999 16909
<> 149:156823d33999 16910 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
<> 149:156823d33999 16911 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
<> 149:156823d33999 16912
<> 149:156823d33999 16913 /**@}*/ /* WWDT_CONST */
<> 149:156823d33999 16914 /**@}*/ /* end of WWDT register group */
<> 149:156823d33999 16915
<> 149:156823d33999 16916
<> 149:156823d33999 16917 /**@}*/ /* end of REGISTER group */
<> 149:156823d33999 16918
<> 149:156823d33999 16919
<> 149:156823d33999 16920 /******************************************************************************/
<> 149:156823d33999 16921 /* Peripheral memory map */
<> 149:156823d33999 16922 /******************************************************************************/
<> 149:156823d33999 16923 /** @addtogroup MemoryMap Memory Mapping
<> 149:156823d33999 16924 @{
<> 149:156823d33999 16925 */
<> 149:156823d33999 16926
<> 149:156823d33999 16927 /* Peripheral and SRAM base address */
<> 149:156823d33999 16928 #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
<> 149:156823d33999 16929 #define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
<> 149:156823d33999 16930
<> 149:156823d33999 16931
<> 149:156823d33999 16932 /* Peripheral memory map */
<> 149:156823d33999 16933 #define AHBPERIPH_BASE PERIPH_BASE
<> 149:156823d33999 16934 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
<> 149:156823d33999 16935
<> 149:156823d33999 16936 /*!< AHB peripherals */
<> 149:156823d33999 16937 #define GCR_BASE (AHBPERIPH_BASE + 0x00000)
<> 149:156823d33999 16938 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
<> 149:156823d33999 16939 #define INT_BASE (AHBPERIPH_BASE + 0x00300)
<> 149:156823d33999 16940 #define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
<> 149:156823d33999 16941 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
<> 149:156823d33999 16942 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
<> 149:156823d33999 16943 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
<> 149:156823d33999 16944 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
<> 149:156823d33999 16945 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
<> 149:156823d33999 16946 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
<> 149:156823d33999 16947 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
<> 149:156823d33999 16948 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
<> 149:156823d33999 16949 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
<> 149:156823d33999 16950 #define USBH_BASE (AHBPERIPH_BASE + 0x09000)
<> 149:156823d33999 16951 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
<> 149:156823d33999 16952 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
<> 149:156823d33999 16953 #define CRC_BASE (AHBPERIPH_BASE + 0x31000)
<> 149:156823d33999 16954
<> 149:156823d33999 16955 /*!< APB0 peripherals */
<> 149:156823d33999 16956 #define WDT_BASE (APBPERIPH_BASE + 0x00000)
<> 149:156823d33999 16957 #define WWDT_BASE (APBPERIPH_BASE + 0x00100)
<> 149:156823d33999 16958 #define TMR01_BASE (APBPERIPH_BASE + 0x10000)
<> 149:156823d33999 16959 #define PWM0_BASE (APBPERIPH_BASE + 0x18000)
<> 149:156823d33999 16960 #define SPI0_BASE (APBPERIPH_BASE + 0x20000)
<> 149:156823d33999 16961 #define SPI2_BASE (APBPERIPH_BASE + 0x22000)
<> 149:156823d33999 16962 #define UART0_BASE (APBPERIPH_BASE + 0x30000)
<> 149:156823d33999 16963 #define UART2_BASE (APBPERIPH_BASE + 0x32000)
<> 149:156823d33999 16964 #define I2C0_BASE (APBPERIPH_BASE + 0x40000)
<> 149:156823d33999 16965 #define SC0_BASE (APBPERIPH_BASE + 0x50000)
<> 149:156823d33999 16966 #define CAN0_BASE (APBPERIPH_BASE + 0x60000)
<> 149:156823d33999 16967 #define USBD_BASE (APBPERIPH_BASE + 0x80000)
<> 149:156823d33999 16968 #define TK_BASE (APBPERIPH_BASE + 0xA2000)
<> 149:156823d33999 16969
<> 149:156823d33999 16970 /*!< APB1 peripherals */
<> 149:156823d33999 16971 #define RTC_BASE (APBPERIPH_BASE + 0x01000)
<> 149:156823d33999 16972 #define EADC0_BASE (APBPERIPH_BASE + 0x03000)
<> 149:156823d33999 16973 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
<> 149:156823d33999 16974 #define DAC_BASE (APBPERIPH_BASE + 0x07000)
<> 149:156823d33999 16975 #define OTG_BASE (APBPERIPH_BASE + 0x0D000)
<> 149:156823d33999 16976 #define TMR23_BASE (APBPERIPH_BASE + 0x11000)
<> 149:156823d33999 16977 #define PWM1_BASE (APBPERIPH_BASE + 0x19000)
<> 149:156823d33999 16978 #define SPI1_BASE (APBPERIPH_BASE + 0x21000)
<> 149:156823d33999 16979 #define UART1_BASE (APBPERIPH_BASE + 0x31000)
<> 149:156823d33999 16980 #define UART3_BASE (APBPERIPH_BASE + 0x33000)
<> 149:156823d33999 16981 #define I2C1_BASE (APBPERIPH_BASE + 0x41000)
<> 149:156823d33999 16982 /*@}*/ /* end of group MemoryMap */
<> 149:156823d33999 16983
<> 149:156823d33999 16984
<> 149:156823d33999 16985 /******************************************************************************/
<> 149:156823d33999 16986 /* Peripheral declaration */
<> 149:156823d33999 16987 /******************************************************************************/
<> 149:156823d33999 16988 /** @addtogroup PeripheralDecl Peripheral Declaration
<> 149:156823d33999 16989 @{
<> 149:156823d33999 16990 */
<> 149:156823d33999 16991
<> 149:156823d33999 16992
<> 149:156823d33999 16993 #define SYS ((SYS_T *) GCR_BASE)
<> 149:156823d33999 16994 #define SYSINT ((SYS_INT_T *) INT_BASE)
<> 149:156823d33999 16995 #define CLK ((CLK_T *) CLK_BASE)
<> 149:156823d33999 16996 #define PA ((GPIO_T *) GPIOA_BASE)
<> 149:156823d33999 16997 #define PB ((GPIO_T *) GPIOB_BASE)
<> 149:156823d33999 16998 #define PC ((GPIO_T *) GPIOC_BASE)
<> 149:156823d33999 16999 #define PD ((GPIO_T *) GPIOD_BASE)
<> 149:156823d33999 17000 #define PE ((GPIO_T *) GPIOE_BASE)
<> 149:156823d33999 17001 #define PF ((GPIO_T *) GPIOF_BASE)
<> 149:156823d33999 17002 #define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
<> 149:156823d33999 17003 #define PDMA ((PDMA_T *) PDMA_BASE)
<> 149:156823d33999 17004 #define USBH ((USBH_T *) USBH_BASE)
<> 149:156823d33999 17005 #define FMC ((FMC_T *) FMC_BASE)
<> 149:156823d33999 17006 #define EBI ((EBI_T *) EBI_BASE)
<> 149:156823d33999 17007 #define CRC ((CRC_T *) CRC_BASE)
<> 149:156823d33999 17008
<> 149:156823d33999 17009 #define WDT ((WDT_T *) WDT_BASE)
<> 149:156823d33999 17010 #define WWDT ((WWDT_T *) WWDT_BASE)
<> 149:156823d33999 17011 #define RTC ((RTC_T *) RTC_BASE)
<> 149:156823d33999 17012 #define EADC ((EADC_T *) EADC0_BASE)
<> 149:156823d33999 17013 #define ACMP01 ((ACMP_T *) ACMP01_BASE)
<> 149:156823d33999 17014
<> 149:156823d33999 17015 #define USBD ((USBD_T *) USBD_BASE)
<> 149:156823d33999 17016 #define OTG ((OTG_T *) OTG_BASE)
<> 149:156823d33999 17017 #define TIMER0 ((TIMER_T *) TMR01_BASE)
<> 149:156823d33999 17018 #define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
<> 149:156823d33999 17019 #define TIMER2 ((TIMER_T *) TMR23_BASE)
<> 149:156823d33999 17020 #define TIMER3 ((TIMER_T *) (TMR23_BASE+ 0x20))
<> 149:156823d33999 17021 #define PWM0 ((PWM_T *) PWM0_BASE)
<> 149:156823d33999 17022 #define PWM1 ((PWM_T *) PWM1_BASE)
<> 149:156823d33999 17023 #define DAC ((DAC_T *) DAC_BASE)
<> 149:156823d33999 17024 #define SPI0 ((SPI_T *) SPI0_BASE)
<> 149:156823d33999 17025 #define SPI1 ((SPI_T *) SPI1_BASE)
<> 149:156823d33999 17026 #define SPI2 ((SPI_T *) SPI2_BASE)
<> 149:156823d33999 17027 #define UART0 ((UART_T *) UART0_BASE)
<> 149:156823d33999 17028 #define UART1 ((UART_T *) UART1_BASE)
<> 149:156823d33999 17029 #define UART2 ((UART_T *) UART2_BASE)
<> 149:156823d33999 17030 #define UART3 ((UART_T *) UART3_BASE)
<> 149:156823d33999 17031 #define I2C0 ((I2C_T *) I2C0_BASE)
<> 149:156823d33999 17032 #define I2C1 ((I2C_T *) I2C1_BASE)
<> 149:156823d33999 17033 #define SC0 ((SC_T *) SC0_BASE)
<> 149:156823d33999 17034 #define CAN0 ((CAN_T *) CAN0_BASE)
<> 149:156823d33999 17035 #define TK ((TK_T *) TK_BASE)
<> 149:156823d33999 17036
<> 149:156823d33999 17037 /* One Bit Mask Definitions */
<> 149:156823d33999 17038 #define BIT0 0x00000001
<> 149:156823d33999 17039 #define BIT1 0x00000002
<> 149:156823d33999 17040 #define BIT2 0x00000004
<> 149:156823d33999 17041 #define BIT3 0x00000008
<> 149:156823d33999 17042 #define BIT4 0x00000010
<> 149:156823d33999 17043 #define BIT5 0x00000020
<> 149:156823d33999 17044 #define BIT6 0x00000040
<> 149:156823d33999 17045 #define BIT7 0x00000080
<> 149:156823d33999 17046 #define BIT8 0x00000100
<> 149:156823d33999 17047 #define BIT9 0x00000200
<> 149:156823d33999 17048 #define BIT10 0x00000400
<> 149:156823d33999 17049 #define BIT11 0x00000800
<> 149:156823d33999 17050 #define BIT12 0x00001000
<> 149:156823d33999 17051 #define BIT13 0x00002000
<> 149:156823d33999 17052 #define BIT14 0x00004000
<> 149:156823d33999 17053 #define BIT15 0x00008000
<> 149:156823d33999 17054 #define BIT16 0x00010000
<> 149:156823d33999 17055 #define BIT17 0x00020000
<> 149:156823d33999 17056 #define BIT18 0x00040000
<> 149:156823d33999 17057 #define BIT19 0x00080000
<> 149:156823d33999 17058 #define BIT20 0x00100000
<> 149:156823d33999 17059 #define BIT21 0x00200000
<> 149:156823d33999 17060 #define BIT22 0x00400000
<> 149:156823d33999 17061 #define BIT23 0x00800000
<> 149:156823d33999 17062 #define BIT24 0x01000000
<> 149:156823d33999 17063 #define BIT25 0x02000000
<> 149:156823d33999 17064 #define BIT26 0x04000000
<> 149:156823d33999 17065 #define BIT27 0x08000000
<> 149:156823d33999 17066 #define BIT28 0x10000000
<> 149:156823d33999 17067 #define BIT29 0x20000000
<> 149:156823d33999 17068 #define BIT30 0x40000000
<> 149:156823d33999 17069 #define BIT31 0x80000000
<> 149:156823d33999 17070
<> 149:156823d33999 17071 /* Byte Mask Definitions */
<> 149:156823d33999 17072 #define BYTE0_Msk (0x000000FF)
<> 149:156823d33999 17073 #define BYTE1_Msk (0x0000FF00)
<> 149:156823d33999 17074 #define BYTE2_Msk (0x00FF0000)
<> 149:156823d33999 17075 #define BYTE3_Msk (0xFF000000)
<> 149:156823d33999 17076
<> 149:156823d33999 17077 #define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
<> 149:156823d33999 17078 #define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
<> 149:156823d33999 17079 #define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
<> 149:156823d33999 17080 #define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
<> 149:156823d33999 17081
<> 149:156823d33999 17082 #ifndef TRUE
<> 149:156823d33999 17083 # define TRUE 1
<> 149:156823d33999 17084 #endif
<> 149:156823d33999 17085 #ifndef FALSE
<> 149:156823d33999 17086 # define FALSE 0
<> 149:156823d33999 17087 #endif
<> 149:156823d33999 17088
<> 149:156823d33999 17089 #ifndef NULL
<> 149:156823d33999 17090 #define NULL 0
<> 149:156823d33999 17091 #endif
<> 149:156823d33999 17092
<> 149:156823d33999 17093 #include "m451_sys.h"
<> 149:156823d33999 17094 #include "m451_clk.h"
<> 149:156823d33999 17095 #include "m451_gpio.h"
<> 149:156823d33999 17096 #include "m451_i2c.h"
<> 149:156823d33999 17097 #include "m451_crc.h"
<> 149:156823d33999 17098 #include "m451_ebi.h"
<> 149:156823d33999 17099 #include "m451_rtc.h"
<> 149:156823d33999 17100 #include "m451_timer.h"
<> 149:156823d33999 17101 #include "m451_wdt.h"
<> 149:156823d33999 17102 #include "m451_wwdt.h"
<> 149:156823d33999 17103 #include "m451_spi.h"
<> 149:156823d33999 17104 #include "m451_sc.h"
<> 149:156823d33999 17105 #include "m451_scuart.h"
<> 149:156823d33999 17106 #include "m451_acmp.h"
<> 149:156823d33999 17107 #include "m451_eadc.h"
<> 149:156823d33999 17108 #include "m451_dac.h"
<> 149:156823d33999 17109 #include "m451_can.h"
<> 149:156823d33999 17110 #include "m451_usbd.h"
<> 149:156823d33999 17111 #include "m451_fmc.h"
<> 149:156823d33999 17112 #include "m451_uart.h"
<> 149:156823d33999 17113 #include "m451_pwm.h"
<> 149:156823d33999 17114 #include "m451_pdma.h"
<> 149:156823d33999 17115 #include "m451_tk.h"
<> 149:156823d33999 17116 #include "m451_otg.h"
<> 149:156823d33999 17117
<> 149:156823d33999 17118 typedef volatile unsigned char vu8;
<> 149:156823d33999 17119 typedef volatile unsigned long vu32;
<> 149:156823d33999 17120 typedef volatile unsigned short vu16;
<> 149:156823d33999 17121 #define M8(adr) (*((vu8 *) (adr)))
<> 149:156823d33999 17122 #define M16(adr) (*((vu16 *) (adr)))
<> 149:156823d33999 17123 #define M32(adr) (*((vu32 *) (adr)))
<> 149:156823d33999 17124
<> 149:156823d33999 17125 #define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
<> 149:156823d33999 17126 #define inpw(port) (*((volatile unsigned int *)(port)))
<> 149:156823d33999 17127 #define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
<> 149:156823d33999 17128 #define inpb(port) (*((volatile unsigned char *)(port)))
<> 149:156823d33999 17129 #define outps(port,value) (*((volatile unsigned short *)(port))=(value))
<> 149:156823d33999 17130 #define inps(port) (*((volatile unsigned short *)(port)))
<> 149:156823d33999 17131
<> 149:156823d33999 17132 #define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
<> 149:156823d33999 17133 #define inp32(port) (*((volatile unsigned int *)(port)))
<> 149:156823d33999 17134 #define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
<> 149:156823d33999 17135 #define inp8(port) (*((volatile unsigned char *)(port)))
<> 149:156823d33999 17136 #define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
<> 149:156823d33999 17137 #define inp16(port) (*((volatile unsigned short *)(port)))
<> 149:156823d33999 17138
<> 149:156823d33999 17139 /*@}*/ /* end of group PeripheralDecl */
<> 149:156823d33999 17140
<> 149:156823d33999 17141 #ifdef __cplusplus
<> 149:156823d33999 17142 }
<> 149:156823d33999 17143 #endif
<> 149:156823d33999 17144
<> 149:156823d33999 17145 #endif /* __M451SERIES_H__ */
<> 149:156823d33999 17146
<> 149:156823d33999 17147 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
<> 149:156823d33999 17148
<> 149:156823d33999 17149
<> 149:156823d33999 17150