shao ziyang / mbed-dev

mbed library sources. Supersedes mbed-src. Add PORTG support for STM32L476JG (SensorTile kit)

Dependents:   SensorTileTest

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/crossbar_map.h@154:1375a99fb16d, 2017-01-02 (annotated)

Committer:
shaoziyang
Date:
Mon Jan 02 15:52:04 2017 +0000
Revision:
154:1375a99fb16d
Parent:
149:156823d33999 
Mbed for ST SensorTile kit, fixed GPIOG bug, add PORTG support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file crossbar_map.h
<> 144:ef7eb2e8f9f7 4 * @brief CROSSBAR hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3318 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-03-27 16:29:34 +0530 (Fri, 27 Mar 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup crossbar
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #ifndef CROSSB_MAP_H_
<> 144:ef7eb2e8f9f7 33 #define CROSSB_MAP_H_
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 36 * *
<> 144:ef7eb2e8f9f7 37 * Header files *
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include "architecture.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 44 * *
<> 144:ef7eb2e8f9f7 45 * Type definitions *
<> 144:ef7eb2e8f9f7 46 * *
<> 144:ef7eb2e8f9f7 47 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Crossbar Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 50 typedef struct {
<> 144:ef7eb2e8f9f7 51 __IO uint32_t DIOCTRL0; /**< Switch IO0 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t DIOCTRL1; /**< Switch IO1 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t DIOCTRL2; /**< Switch IO2 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t DIOCTRL3; /**< Switch IO3 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t DIOCTRL4; /**< Switch IO4 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t DIOCTRL5; /**< Switch IO5 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t DIOCTRL6; /**< Switch IO6 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t DIOCTRL7; /**< Switch IO7 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t DIOCTRL8; /**< Switch IO8 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t DIOCTRL9; /**< Switch IO9 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t DIOCTRL10; /**< Switch IO10 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 62 __IO uint32_t DIOCTRL11; /**< Switch IO11 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t DIOCTRL12; /**< Switch IO12 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t DIOCTRL13; /**< Switch IO13 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t DIOCTRL14; /**< Switch IO14 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t DIOCTRL15; /**< Switch IO15 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t DIOCTRL16; /**< Switch IO16 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t DIOCTRL17; /**< Switch IO17 to GPIO(default) or peripheral device */
<> 144:ef7eb2e8f9f7 69 } CrossbReg_t, *CrossbReg_pt;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #endif /* CROSSB_MAP_H_ */