hello
VL53L0X.h@0:69ce6d469c71, 2019-10-01 (annotated)
- Committer:
- shalutha
- Date:
- Tue Oct 01 14:08:33 2019 +0000
- Revision:
- 0:69ce6d469c71
hello
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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shalutha | 0:69ce6d469c71 | 1 | #ifndef VL53L0X_h |
shalutha | 0:69ce6d469c71 | 2 | #define VL53L0X_h |
shalutha | 0:69ce6d469c71 | 3 | |
shalutha | 0:69ce6d469c71 | 4 | #include <mbed.h> |
shalutha | 0:69ce6d469c71 | 5 | |
shalutha | 0:69ce6d469c71 | 6 | class VL53L0X |
shalutha | 0:69ce6d469c71 | 7 | { |
shalutha | 0:69ce6d469c71 | 8 | public: |
shalutha | 0:69ce6d469c71 | 9 | // register addresses from API vl53l0x_device.h (ordered as listed there) |
shalutha | 0:69ce6d469c71 | 10 | enum regAddr |
shalutha | 0:69ce6d469c71 | 11 | { |
shalutha | 0:69ce6d469c71 | 12 | SYSRANGE_START = 0x00, |
shalutha | 0:69ce6d469c71 | 13 | |
shalutha | 0:69ce6d469c71 | 14 | SYSTEM_THRESH_HIGH = 0x0C, |
shalutha | 0:69ce6d469c71 | 15 | SYSTEM_THRESH_LOW = 0x0E, |
shalutha | 0:69ce6d469c71 | 16 | |
shalutha | 0:69ce6d469c71 | 17 | SYSTEM_SEQUENCE_CONFIG = 0x01, |
shalutha | 0:69ce6d469c71 | 18 | SYSTEM_RANGE_CONFIG = 0x09, |
shalutha | 0:69ce6d469c71 | 19 | SYSTEM_INTERMEASUREMENT_PERIOD = 0x04, |
shalutha | 0:69ce6d469c71 | 20 | |
shalutha | 0:69ce6d469c71 | 21 | SYSTEM_INTERRUPT_CONFIG_GPIO = 0x0A, |
shalutha | 0:69ce6d469c71 | 22 | |
shalutha | 0:69ce6d469c71 | 23 | GPIO_HV_MUX_ACTIVE_HIGH = 0x84, |
shalutha | 0:69ce6d469c71 | 24 | |
shalutha | 0:69ce6d469c71 | 25 | SYSTEM_INTERRUPT_CLEAR = 0x0B, |
shalutha | 0:69ce6d469c71 | 26 | |
shalutha | 0:69ce6d469c71 | 27 | RESULT_INTERRUPT_STATUS = 0x13, |
shalutha | 0:69ce6d469c71 | 28 | RESULT_RANGE_STATUS = 0x14, |
shalutha | 0:69ce6d469c71 | 29 | |
shalutha | 0:69ce6d469c71 | 30 | RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN = 0xBC, |
shalutha | 0:69ce6d469c71 | 31 | RESULT_CORE_RANGING_TOTAL_EVENTS_RTN = 0xC0, |
shalutha | 0:69ce6d469c71 | 32 | RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF = 0xD0, |
shalutha | 0:69ce6d469c71 | 33 | RESULT_CORE_RANGING_TOTAL_EVENTS_REF = 0xD4, |
shalutha | 0:69ce6d469c71 | 34 | RESULT_PEAK_SIGNAL_RATE_REF = 0xB6, |
shalutha | 0:69ce6d469c71 | 35 | |
shalutha | 0:69ce6d469c71 | 36 | ALGO_PART_TO_PART_RANGE_OFFSET_MM = 0x28, |
shalutha | 0:69ce6d469c71 | 37 | |
shalutha | 0:69ce6d469c71 | 38 | I2C_SLAVE_DEVICE_ADDRESS = 0x8A, |
shalutha | 0:69ce6d469c71 | 39 | |
shalutha | 0:69ce6d469c71 | 40 | MSRC_CONFIG_CONTROL = 0x60, |
shalutha | 0:69ce6d469c71 | 41 | |
shalutha | 0:69ce6d469c71 | 42 | PRE_RANGE_CONFIG_MIN_SNR = 0x27, |
shalutha | 0:69ce6d469c71 | 43 | PRE_RANGE_CONFIG_VALID_PHASE_LOW = 0x56, |
shalutha | 0:69ce6d469c71 | 44 | PRE_RANGE_CONFIG_VALID_PHASE_HIGH = 0x57, |
shalutha | 0:69ce6d469c71 | 45 | PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT = 0x64, |
shalutha | 0:69ce6d469c71 | 46 | |
shalutha | 0:69ce6d469c71 | 47 | FINAL_RANGE_CONFIG_MIN_SNR = 0x67, |
shalutha | 0:69ce6d469c71 | 48 | FINAL_RANGE_CONFIG_VALID_PHASE_LOW = 0x47, |
shalutha | 0:69ce6d469c71 | 49 | FINAL_RANGE_CONFIG_VALID_PHASE_HIGH = 0x48, |
shalutha | 0:69ce6d469c71 | 50 | FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT = 0x44, |
shalutha | 0:69ce6d469c71 | 51 | |
shalutha | 0:69ce6d469c71 | 52 | PRE_RANGE_CONFIG_SIGMA_THRESH_HI = 0x61, |
shalutha | 0:69ce6d469c71 | 53 | PRE_RANGE_CONFIG_SIGMA_THRESH_LO = 0x62, |
shalutha | 0:69ce6d469c71 | 54 | |
shalutha | 0:69ce6d469c71 | 55 | PRE_RANGE_CONFIG_VCSEL_PERIOD = 0x50, |
shalutha | 0:69ce6d469c71 | 56 | PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x51, |
shalutha | 0:69ce6d469c71 | 57 | PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x52, |
shalutha | 0:69ce6d469c71 | 58 | |
shalutha | 0:69ce6d469c71 | 59 | SYSTEM_HISTOGRAM_BIN = 0x81, |
shalutha | 0:69ce6d469c71 | 60 | HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT = 0x33, |
shalutha | 0:69ce6d469c71 | 61 | HISTOGRAM_CONFIG_READOUT_CTRL = 0x55, |
shalutha | 0:69ce6d469c71 | 62 | |
shalutha | 0:69ce6d469c71 | 63 | FINAL_RANGE_CONFIG_VCSEL_PERIOD = 0x70, |
shalutha | 0:69ce6d469c71 | 64 | FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x71, |
shalutha | 0:69ce6d469c71 | 65 | FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x72, |
shalutha | 0:69ce6d469c71 | 66 | CROSSTALK_COMPENSATION_PEAK_RATE_MCPS = 0x20, |
shalutha | 0:69ce6d469c71 | 67 | |
shalutha | 0:69ce6d469c71 | 68 | MSRC_CONFIG_TIMEOUT_MACROP = 0x46, |
shalutha | 0:69ce6d469c71 | 69 | |
shalutha | 0:69ce6d469c71 | 70 | SOFT_RESET_GO2_SOFT_RESET_N = 0xBF, |
shalutha | 0:69ce6d469c71 | 71 | IDENTIFICATION_MODEL_ID = 0xC0, |
shalutha | 0:69ce6d469c71 | 72 | IDENTIFICATION_REVISION_ID = 0xC2, |
shalutha | 0:69ce6d469c71 | 73 | |
shalutha | 0:69ce6d469c71 | 74 | OSC_CALIBRATE_VAL = 0xF8, |
shalutha | 0:69ce6d469c71 | 75 | |
shalutha | 0:69ce6d469c71 | 76 | GLOBAL_CONFIG_VCSEL_WIDTH = 0x32, |
shalutha | 0:69ce6d469c71 | 77 | GLOBAL_CONFIG_SPAD_ENABLES_REF_0 = 0xB0, |
shalutha | 0:69ce6d469c71 | 78 | GLOBAL_CONFIG_SPAD_ENABLES_REF_1 = 0xB1, |
shalutha | 0:69ce6d469c71 | 79 | GLOBAL_CONFIG_SPAD_ENABLES_REF_2 = 0xB2, |
shalutha | 0:69ce6d469c71 | 80 | GLOBAL_CONFIG_SPAD_ENABLES_REF_3 = 0xB3, |
shalutha | 0:69ce6d469c71 | 81 | GLOBAL_CONFIG_SPAD_ENABLES_REF_4 = 0xB4, |
shalutha | 0:69ce6d469c71 | 82 | GLOBAL_CONFIG_SPAD_ENABLES_REF_5 = 0xB5, |
shalutha | 0:69ce6d469c71 | 83 | |
shalutha | 0:69ce6d469c71 | 84 | GLOBAL_CONFIG_REF_EN_START_SELECT = 0xB6, |
shalutha | 0:69ce6d469c71 | 85 | DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD = 0x4E, |
shalutha | 0:69ce6d469c71 | 86 | DYNAMIC_SPAD_REF_EN_START_OFFSET = 0x4F, |
shalutha | 0:69ce6d469c71 | 87 | POWER_MANAGEMENT_GO1_POWER_FORCE = 0x80, |
shalutha | 0:69ce6d469c71 | 88 | |
shalutha | 0:69ce6d469c71 | 89 | VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV = 0x89, |
shalutha | 0:69ce6d469c71 | 90 | |
shalutha | 0:69ce6d469c71 | 91 | ALGO_PHASECAL_LIM = 0x30, |
shalutha | 0:69ce6d469c71 | 92 | ALGO_PHASECAL_CONFIG_TIMEOUT = 0x30, |
shalutha | 0:69ce6d469c71 | 93 | }; |
shalutha | 0:69ce6d469c71 | 94 | |
shalutha | 0:69ce6d469c71 | 95 | enum vcselPeriodType { VcselPeriodPreRange, VcselPeriodFinalRange }; |
shalutha | 0:69ce6d469c71 | 96 | |
shalutha | 0:69ce6d469c71 | 97 | uint8_t last_status; // status of last I2C transmission |
shalutha | 0:69ce6d469c71 | 98 | |
shalutha | 0:69ce6d469c71 | 99 | VL53L0X(I2C*, Timer*); |
shalutha | 0:69ce6d469c71 | 100 | |
shalutha | 0:69ce6d469c71 | 101 | void setAddress(uint8_t new_addr); |
shalutha | 0:69ce6d469c71 | 102 | inline uint8_t getAddress(void) { return address; } |
shalutha | 0:69ce6d469c71 | 103 | |
shalutha | 0:69ce6d469c71 | 104 | bool init(bool io_2v8 = true); |
shalutha | 0:69ce6d469c71 | 105 | |
shalutha | 0:69ce6d469c71 | 106 | void writeReg(uint8_t reg, uint8_t value); |
shalutha | 0:69ce6d469c71 | 107 | void writeReg16Bit(uint8_t reg, uint16_t value); |
shalutha | 0:69ce6d469c71 | 108 | void writeReg32Bit(uint8_t reg, uint32_t value); |
shalutha | 0:69ce6d469c71 | 109 | uint8_t readReg(uint8_t reg); |
shalutha | 0:69ce6d469c71 | 110 | uint16_t readReg16Bit(uint8_t reg); |
shalutha | 0:69ce6d469c71 | 111 | uint32_t readReg32Bit(uint8_t reg); |
shalutha | 0:69ce6d469c71 | 112 | |
shalutha | 0:69ce6d469c71 | 113 | void writeMulti(uint8_t reg, uint8_t const * src, uint8_t count); |
shalutha | 0:69ce6d469c71 | 114 | void readMulti(uint8_t reg, uint8_t * dst, uint8_t count); |
shalutha | 0:69ce6d469c71 | 115 | |
shalutha | 0:69ce6d469c71 | 116 | bool setSignalRateLimit(float limit_Mcps); |
shalutha | 0:69ce6d469c71 | 117 | float getSignalRateLimit(void); |
shalutha | 0:69ce6d469c71 | 118 | |
shalutha | 0:69ce6d469c71 | 119 | bool setMeasurementTimingBudget(uint32_t budget_us); |
shalutha | 0:69ce6d469c71 | 120 | uint32_t getMeasurementTimingBudget(void); |
shalutha | 0:69ce6d469c71 | 121 | |
shalutha | 0:69ce6d469c71 | 122 | bool setVcselPulsePeriod(vcselPeriodType type, uint8_t period_pclks); |
shalutha | 0:69ce6d469c71 | 123 | uint8_t getVcselPulsePeriod(vcselPeriodType type); |
shalutha | 0:69ce6d469c71 | 124 | |
shalutha | 0:69ce6d469c71 | 125 | void startContinuous(uint32_t period_ms = 0); |
shalutha | 0:69ce6d469c71 | 126 | void stopContinuous(void); |
shalutha | 0:69ce6d469c71 | 127 | uint16_t readRangeContinuousMillimeters(void); |
shalutha | 0:69ce6d469c71 | 128 | uint16_t readRangeSingleMillimeters(void); |
shalutha | 0:69ce6d469c71 | 129 | |
shalutha | 0:69ce6d469c71 | 130 | inline void setTimeout(uint16_t timeout) { io_timeout = timeout; } |
shalutha | 0:69ce6d469c71 | 131 | inline uint16_t getTimeout(void) { return io_timeout; } |
shalutha | 0:69ce6d469c71 | 132 | bool timeoutOccurred(void); |
shalutha | 0:69ce6d469c71 | 133 | |
shalutha | 0:69ce6d469c71 | 134 | private: |
shalutha | 0:69ce6d469c71 | 135 | // TCC: Target CentreCheck |
shalutha | 0:69ce6d469c71 | 136 | // MSRC: Minimum Signal Rate Check |
shalutha | 0:69ce6d469c71 | 137 | // DSS: Dynamic Spad Selection |
shalutha | 0:69ce6d469c71 | 138 | |
shalutha | 0:69ce6d469c71 | 139 | struct SequenceStepEnables |
shalutha | 0:69ce6d469c71 | 140 | { |
shalutha | 0:69ce6d469c71 | 141 | bool tcc, msrc, dss, pre_range, final_range; |
shalutha | 0:69ce6d469c71 | 142 | }; |
shalutha | 0:69ce6d469c71 | 143 | |
shalutha | 0:69ce6d469c71 | 144 | struct SequenceStepTimeouts |
shalutha | 0:69ce6d469c71 | 145 | { |
shalutha | 0:69ce6d469c71 | 146 | uint16_t pre_range_vcsel_period_pclks, final_range_vcsel_period_pclks; |
shalutha | 0:69ce6d469c71 | 147 | |
shalutha | 0:69ce6d469c71 | 148 | uint16_t msrc_dss_tcc_mclks, pre_range_mclks, final_range_mclks; |
shalutha | 0:69ce6d469c71 | 149 | uint32_t msrc_dss_tcc_us, pre_range_us, final_range_us; |
shalutha | 0:69ce6d469c71 | 150 | }; |
shalutha | 0:69ce6d469c71 | 151 | |
shalutha | 0:69ce6d469c71 | 152 | uint8_t address; |
shalutha | 0:69ce6d469c71 | 153 | uint16_t io_timeout; |
shalutha | 0:69ce6d469c71 | 154 | bool did_timeout; |
shalutha | 0:69ce6d469c71 | 155 | uint16_t timeout_start_ms; |
shalutha | 0:69ce6d469c71 | 156 | |
shalutha | 0:69ce6d469c71 | 157 | uint8_t stop_variable; // read by init and used when starting measurement; is StopVariable field of VL53L0X_DevData_t structure in API |
shalutha | 0:69ce6d469c71 | 158 | uint32_t measurement_timing_budget_us; |
shalutha | 0:69ce6d469c71 | 159 | |
shalutha | 0:69ce6d469c71 | 160 | bool getSpadInfo(uint8_t * count, bool * type_is_aperture); |
shalutha | 0:69ce6d469c71 | 161 | |
shalutha | 0:69ce6d469c71 | 162 | void getSequenceStepEnables(SequenceStepEnables * enables); |
shalutha | 0:69ce6d469c71 | 163 | void getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts); |
shalutha | 0:69ce6d469c71 | 164 | |
shalutha | 0:69ce6d469c71 | 165 | bool performSingleRefCalibration(uint8_t vhv_init_byte); |
shalutha | 0:69ce6d469c71 | 166 | |
shalutha | 0:69ce6d469c71 | 167 | static uint16_t decodeTimeout(uint16_t value); |
shalutha | 0:69ce6d469c71 | 168 | static uint16_t encodeTimeout(uint16_t timeout_mclks); |
shalutha | 0:69ce6d469c71 | 169 | static uint32_t timeoutMclksToMicroseconds(uint16_t timeout_period_mclks, uint8_t vcsel_period_pclks); |
shalutha | 0:69ce6d469c71 | 170 | static uint32_t timeoutMicrosecondsToMclks(uint32_t timeout_period_us, uint8_t vcsel_period_pclks); |
shalutha | 0:69ce6d469c71 | 171 | |
shalutha | 0:69ce6d469c71 | 172 | // mbed members |
shalutha | 0:69ce6d469c71 | 173 | I2C* i2c; |
shalutha | 0:69ce6d469c71 | 174 | Timer* timer; |
shalutha | 0:69ce6d469c71 | 175 | }; |
shalutha | 0:69ce6d469c71 | 176 | |
shalutha | 0:69ce6d469c71 | 177 | #endif |