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targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h@18:da299f395b9e, 2015-11-09 (annotated)

Committer:: mbed_official
Date:: Mon Nov 09 13:30:11 2015 +0000
Revision:: 18:da299f395b9e
Parent:: targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/clock_samd21_r21/clock_feature.h@15:a81a8d6c1dfe

Synchronized with git revision f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3

Full URL: https://github.com/mbedmicro/mbed/commit/f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3/

Added support for SAML21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	15:a81a8d6c1dfe	1	/**
mbed_official	15:a81a8d6c1dfe	2	* \file
mbed_official	15:a81a8d6c1dfe	3	*
mbed_official	15:a81a8d6c1dfe	4	* \brief SAM Clock Driver
mbed_official	15:a81a8d6c1dfe	5	*
mbed_official	15:a81a8d6c1dfe	6	* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
mbed_official	15:a81a8d6c1dfe	7	*
mbed_official	15:a81a8d6c1dfe	8	* \asf_license_start
mbed_official	15:a81a8d6c1dfe	9	*
mbed_official	15:a81a8d6c1dfe	10	* \page License
mbed_official	15:a81a8d6c1dfe	11	*
mbed_official	15:a81a8d6c1dfe	12	* Redistribution and use in source and binary forms, with or without
mbed_official	15:a81a8d6c1dfe	13	* modification, are permitted provided that the following conditions are met:
mbed_official	15:a81a8d6c1dfe	14	*
mbed_official	15:a81a8d6c1dfe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	15:a81a8d6c1dfe	16	* this list of conditions and the following disclaimer.
mbed_official	15:a81a8d6c1dfe	17	*
mbed_official	15:a81a8d6c1dfe	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	15:a81a8d6c1dfe	19	* this list of conditions and the following disclaimer in the documentation
mbed_official	15:a81a8d6c1dfe	20	* and/or other materials provided with the distribution.
mbed_official	15:a81a8d6c1dfe	21	*
mbed_official	15:a81a8d6c1dfe	22	* 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official	15:a81a8d6c1dfe	23	* from this software without specific prior written permission.
mbed_official	15:a81a8d6c1dfe	24	*
mbed_official	15:a81a8d6c1dfe	25	* 4. This software may only be redistributed and used in connection with an
mbed_official	15:a81a8d6c1dfe	26	* Atmel microcontroller product.
mbed_official	15:a81a8d6c1dfe	27	*
mbed_official	15:a81a8d6c1dfe	28	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	15:a81a8d6c1dfe	29	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	15:a81a8d6c1dfe	30	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official	15:a81a8d6c1dfe	31	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official	15:a81a8d6c1dfe	32	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	15:a81a8d6c1dfe	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official	15:a81a8d6c1dfe	34	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official	15:a81a8d6c1dfe	35	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official	15:a81a8d6c1dfe	36	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official	15:a81a8d6c1dfe	37	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official	15:a81a8d6c1dfe	38	* POSSIBILITY OF SUCH DAMAGE.
mbed_official	15:a81a8d6c1dfe	39	*
mbed_official	15:a81a8d6c1dfe	40	* \asf_license_stop
mbed_official	15:a81a8d6c1dfe	41	*
mbed_official	15:a81a8d6c1dfe	42	*/
mbed_official	15:a81a8d6c1dfe	43	/*
mbed_official	15:a81a8d6c1dfe	44	* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official	15:a81a8d6c1dfe	45	*/
mbed_official	15:a81a8d6c1dfe	46	#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	15:a81a8d6c1dfe	47	#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	15:a81a8d6c1dfe	48
mbed_official	15:a81a8d6c1dfe	49	#ifdef __cplusplus
mbed_official	15:a81a8d6c1dfe	50	extern "C" {
mbed_official	15:a81a8d6c1dfe	51	#endif
mbed_official	15:a81a8d6c1dfe	52
mbed_official	15:a81a8d6c1dfe	53	/**
mbed_official	15:a81a8d6c1dfe	54	* \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
mbed_official	15:a81a8d6c1dfe	55	*
mbed_official	15:a81a8d6c1dfe	56	* This driver for Atmel® \| SMART ARM®-based microcontrollers provides an interface for the configuration
mbed_official	15:a81a8d6c1dfe	57	* and management of the device's clocking related functions. This includes
mbed_official	15:a81a8d6c1dfe	58	* the various clock sources, bus clocks, and generic clocks within the device,
mbed_official	15:a81a8d6c1dfe	59	* with functions to manage the enabling, disabling, source selection, and
mbed_official	15:a81a8d6c1dfe	60	* prescaling of clocks to various internal peripherals.
mbed_official	15:a81a8d6c1dfe	61	*
mbed_official	15:a81a8d6c1dfe	62	* The following peripherals are used by this module:
mbed_official	15:a81a8d6c1dfe	63	*
mbed_official	15:a81a8d6c1dfe	64	* - GCLK (Generic Clock Management)
mbed_official	15:a81a8d6c1dfe	65	* - PM (Power Management)
mbed_official	15:a81a8d6c1dfe	66	* - SYSCTRL (Clock Source Control)
mbed_official	15:a81a8d6c1dfe	67	*
mbed_official	15:a81a8d6c1dfe	68	* The following devices can use this module:
mbed_official	15:a81a8d6c1dfe	69	* - Atmel \| SMART SAM D20/D21
mbed_official	15:a81a8d6c1dfe	70	* - Atmel \| SMART SAM R21
mbed_official	15:a81a8d6c1dfe	71	* - Atmel \| SMART SAM D10/D11
mbed_official	15:a81a8d6c1dfe	72	* - Atmel \| SMART SAM DA0/DA1
mbed_official	15:a81a8d6c1dfe	73	*
mbed_official	15:a81a8d6c1dfe	74	* The outline of this documentation is as follows:
mbed_official	15:a81a8d6c1dfe	75	* - \ref asfdoc_sam0_system_clock_prerequisites
mbed_official	15:a81a8d6c1dfe	76	* - \ref asfdoc_sam0_system_clock_module_overview
mbed_official	15:a81a8d6c1dfe	77	* - \ref asfdoc_sam0_system_clock_special_considerations
mbed_official	15:a81a8d6c1dfe	78	* - \ref asfdoc_sam0_system_clock_extra_info
mbed_official	15:a81a8d6c1dfe	79	* - \ref asfdoc_sam0_system_clock_examples
mbed_official	15:a81a8d6c1dfe	80	* - \ref asfdoc_sam0_system_clock_api_overview
mbed_official	15:a81a8d6c1dfe	81	*
mbed_official	15:a81a8d6c1dfe	82	*
mbed_official	15:a81a8d6c1dfe	83	* \section asfdoc_sam0_system_clock_prerequisites Prerequisites
mbed_official	15:a81a8d6c1dfe	84	*
mbed_official	15:a81a8d6c1dfe	85	* There are no prerequisites for this module.
mbed_official	15:a81a8d6c1dfe	86	*
mbed_official	15:a81a8d6c1dfe	87	*
mbed_official	15:a81a8d6c1dfe	88	* \section asfdoc_sam0_system_clock_module_overview Module Overview
mbed_official	15:a81a8d6c1dfe	89	* The SAM devices contain a sophisticated clocking system, which is designed
mbed_official	15:a81a8d6c1dfe	90	* to give the maximum flexibility to the user application. This system allows
mbed_official	15:a81a8d6c1dfe	91	* a system designer to tune the performance and power consumption of the device
mbed_official	15:a81a8d6c1dfe	92	* in a dynamic manner, to achieve the best trade-off between the two for a
mbed_official	15:a81a8d6c1dfe	93	* particular application.
mbed_official	15:a81a8d6c1dfe	94	*
mbed_official	15:a81a8d6c1dfe	95	* This driver provides a set of functions for the configuration and management
mbed_official	15:a81a8d6c1dfe	96	* of the various clock related functionality within the device.
mbed_official	15:a81a8d6c1dfe	97	*
mbed_official	15:a81a8d6c1dfe	98	* \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
mbed_official	15:a81a8d6c1dfe	99	* <table>
mbed_official	15:a81a8d6c1dfe	100	* <tr>
mbed_official	15:a81a8d6c1dfe	101	* <th>Driver Feature Macro</th>
mbed_official	15:a81a8d6c1dfe	102	* <th>Supported devices</th>
mbed_official	15:a81a8d6c1dfe	103	* </tr>
mbed_official	15:a81a8d6c1dfe	104	* <tr>
mbed_official	15:a81a8d6c1dfe	105	* <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
mbed_official	15:a81a8d6c1dfe	106	* <td>SAMD21, SAMR21, SAMD10, SAMD11, SAMDAx</td>
mbed_official	15:a81a8d6c1dfe	107	* </tr>
mbed_official	15:a81a8d6c1dfe	108	* </table>
mbed_official	15:a81a8d6c1dfe	109	* \note The specific features are only available in the driver when the
mbed_official	15:a81a8d6c1dfe	110	* selected device supports those features.
mbed_official	15:a81a8d6c1dfe	111	*
mbed_official	15:a81a8d6c1dfe	112	* \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
mbed_official	15:a81a8d6c1dfe	113	* The SAM devices have a number of master clock source modules, each of
mbed_official	15:a81a8d6c1dfe	114	* which being capable of producing a stabilized output frequency, which can then
mbed_official	15:a81a8d6c1dfe	115	* be fed into the various peripherals and modules within the device.
mbed_official	15:a81a8d6c1dfe	116	*
mbed_official	15:a81a8d6c1dfe	117	* Possible clock source modules include internal R/C oscillators, internal
mbed_official	15:a81a8d6c1dfe	118	* DFLL modules, as well as external crystal oscillators and/or clock inputs.
mbed_official	15:a81a8d6c1dfe	119	*
mbed_official	15:a81a8d6c1dfe	120	* \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
mbed_official	15:a81a8d6c1dfe	121	* The CPU and AHB/APBx buses are clocked by the same physical clock source
mbed_official	15:a81a8d6c1dfe	122	* (referred in this module as the Main Clock), however the APBx buses may
mbed_official	15:a81a8d6c1dfe	123	* have additional prescaler division ratios set to give each peripheral bus a
mbed_official	15:a81a8d6c1dfe	124	* different clock speed.
mbed_official	15:a81a8d6c1dfe	125	*
mbed_official	15:a81a8d6c1dfe	126	* The general main clock tree for the CPU and associated buses is shown in
mbed_official	15:a81a8d6c1dfe	127	* \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
mbed_official	15:a81a8d6c1dfe	128	*
mbed_official	15:a81a8d6c1dfe	129	* \anchor asfdoc_sam0_system_clock_module_clock_tree
mbed_official	15:a81a8d6c1dfe	130	* \dot
mbed_official	15:a81a8d6c1dfe	131	* digraph overview {
mbed_official	15:a81a8d6c1dfe	132	* rankdir=LR;
mbed_official	15:a81a8d6c1dfe	133	* clk_src [label="Clock Sources", shape=none, height=0];
mbed_official	15:a81a8d6c1dfe	134	* node [label="CPU Bus" shape=ellipse] cpu_bus;
mbed_official	15:a81a8d6c1dfe	135	* node [label="AHB Bus" shape=ellipse] ahb_bus;
mbed_official	15:a81a8d6c1dfe	136	* node [label="APBA Bus" shape=ellipse] apb_a_bus;
mbed_official	15:a81a8d6c1dfe	137	* node [label="APBB Bus" shape=ellipse] apb_b_bus;
mbed_official	15:a81a8d6c1dfe	138	* node [label="APBC Bus" shape=ellipse] apb_c_bus;
mbed_official	15:a81a8d6c1dfe	139	* node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
mbed_official	15:a81a8d6c1dfe	140	* node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
mbed_official	15:a81a8d6c1dfe	141	* node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
mbed_official	15:a81a8d6c1dfe	142	* node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
mbed_official	15:a81a8d6c1dfe	143	* node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
mbed_official	15:a81a8d6c1dfe	144	*
mbed_official	15:a81a8d6c1dfe	145	* clk_src -> main_clock_mux;
mbed_official	15:a81a8d6c1dfe	146	* main_clock_mux -> main_prescaler;
mbed_official	15:a81a8d6c1dfe	147	* main_prescaler -> cpu_bus;
mbed_official	15:a81a8d6c1dfe	148	* main_prescaler -> ahb_bus;
mbed_official	15:a81a8d6c1dfe	149	* main_prescaler -> apb_a_prescaler;
mbed_official	15:a81a8d6c1dfe	150	* main_prescaler -> apb_b_prescaler;
mbed_official	15:a81a8d6c1dfe	151	* main_prescaler -> apb_c_prescaler;
mbed_official	15:a81a8d6c1dfe	152	* apb_a_prescaler -> apb_a_bus;
mbed_official	15:a81a8d6c1dfe	153	* apb_b_prescaler -> apb_b_bus;
mbed_official	15:a81a8d6c1dfe	154	* apb_c_prescaler -> apb_c_bus;
mbed_official	15:a81a8d6c1dfe	155	* }
mbed_official	15:a81a8d6c1dfe	156	* \enddot
mbed_official	15:a81a8d6c1dfe	157	*
mbed_official	15:a81a8d6c1dfe	158	* \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
mbed_official	15:a81a8d6c1dfe	159	* To save power, the input clock to one or more peripherals on the AHB and APBx
mbed_official	15:a81a8d6c1dfe	160	* buses can be masked away - when masked, no clock is passed into the module.
mbed_official	15:a81a8d6c1dfe	161	* Disabling of clocks of unused modules will prevent all access to the masked
mbed_official	15:a81a8d6c1dfe	162	* module, but will reduce the overall device power consumption.
mbed_official	15:a81a8d6c1dfe	163	*
mbed_official	15:a81a8d6c1dfe	164	* \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
mbed_official	15:a81a8d6c1dfe	165	* Within the SAM devices there are a number of Generic Clocks; these are used to
mbed_official	15:a81a8d6c1dfe	166	* provide clocks to the various peripheral clock domains in the device in a
mbed_official	15:a81a8d6c1dfe	167	* standardized manner. One or more master source clocks can be selected as the
mbed_official	15:a81a8d6c1dfe	168	* input clock to a Generic Clock Generator, which can prescale down the input
mbed_official	15:a81a8d6c1dfe	169	* frequency to a slower rate for use in a peripheral.
mbed_official	15:a81a8d6c1dfe	170	*
mbed_official	15:a81a8d6c1dfe	171	* Additionally, a number of individually selectable Generic Clock Channels are
mbed_official	15:a81a8d6c1dfe	172	* provided, which multiplex and gate the various generator outputs for one or
mbed_official	15:a81a8d6c1dfe	173	* more peripherals within the device. This setup allows for a single common
mbed_official	15:a81a8d6c1dfe	174	* generator to feed one or more channels, which can then be enabled or disabled
mbed_official	15:a81a8d6c1dfe	175	* individually as required.
mbed_official	15:a81a8d6c1dfe	176	*
mbed_official	15:a81a8d6c1dfe	177	* \anchor asfdoc_sam0_system_clock_module_chain_overview
mbed_official	15:a81a8d6c1dfe	178	* \dot
mbed_official	15:a81a8d6c1dfe	179	* digraph overview {
mbed_official	15:a81a8d6c1dfe	180	* rankdir=LR;
mbed_official	15:a81a8d6c1dfe	181	* node [label="Clock\nSource a" shape=square] system_clock_source;
mbed_official	15:a81a8d6c1dfe	182	* node [label="Generator 1" shape=square] clock_gen;
mbed_official	15:a81a8d6c1dfe	183	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	15:a81a8d6c1dfe	184	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	15:a81a8d6c1dfe	185	* node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	15:a81a8d6c1dfe	186	* node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	15:a81a8d6c1dfe	187	*
mbed_official	15:a81a8d6c1dfe	188	* system_clock_source -> clock_gen;
mbed_official	15:a81a8d6c1dfe	189	* clock_gen -> clock_chan0;
mbed_official	15:a81a8d6c1dfe	190	* clock_chan0 -> peripheral0;
mbed_official	15:a81a8d6c1dfe	191	* clock_gen -> clock_chan1;
mbed_official	15:a81a8d6c1dfe	192	* clock_chan1 -> peripheral1;
mbed_official	15:a81a8d6c1dfe	193	* }
mbed_official	15:a81a8d6c1dfe	194	* \enddot
mbed_official	15:a81a8d6c1dfe	195	*
mbed_official	15:a81a8d6c1dfe	196	* \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
mbed_official	15:a81a8d6c1dfe	197	* An example setup of a complete clock chain within the device is shown in
mbed_official	15:a81a8d6c1dfe	198	* \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
mbed_official	15:a81a8d6c1dfe	199	*
mbed_official	15:a81a8d6c1dfe	200	* \anchor asfdoc_sam0_system_clock_module_chain_example_fig
mbed_official	15:a81a8d6c1dfe	201	* \dot
mbed_official	15:a81a8d6c1dfe	202	* digraph overview {
mbed_official	15:a81a8d6c1dfe	203	* rankdir=LR;
mbed_official	15:a81a8d6c1dfe	204	* node [label="External\nOscillator" shape=square] system_clock_source0;
mbed_official	15:a81a8d6c1dfe	205	* node [label="Generator 0" shape=square] clock_gen0;
mbed_official	15:a81a8d6c1dfe	206	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	15:a81a8d6c1dfe	207	* node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	15:a81a8d6c1dfe	208	*
mbed_official	15:a81a8d6c1dfe	209	* system_clock_source0 -> clock_gen0;
mbed_official	15:a81a8d6c1dfe	210	* clock_gen0 -> clock_chan0;
mbed_official	15:a81a8d6c1dfe	211	* clock_chan0 -> peripheral0;
mbed_official	15:a81a8d6c1dfe	212	* node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
mbed_official	15:a81a8d6c1dfe	213	* node [label="Generator 1" shape=square] clock_gen1;
mbed_official	15:a81a8d6c1dfe	214	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	15:a81a8d6c1dfe	215	* node [label="Channel z" shape=square] clock_chan2;
mbed_official	15:a81a8d6c1dfe	216	* node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	15:a81a8d6c1dfe	217	* node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
mbed_official	15:a81a8d6c1dfe	218	*
mbed_official	15:a81a8d6c1dfe	219	* system_clock_source1 -> clock_gen1;
mbed_official	15:a81a8d6c1dfe	220	* clock_gen1 -> clock_chan1;
mbed_official	15:a81a8d6c1dfe	221	* clock_gen1 -> clock_chan2;
mbed_official	15:a81a8d6c1dfe	222	* clock_chan1 -> peripheral1;
mbed_official	15:a81a8d6c1dfe	223	* clock_chan2 -> peripheral2;
mbed_official	15:a81a8d6c1dfe	224	* }
mbed_official	15:a81a8d6c1dfe	225	* \enddot
mbed_official	15:a81a8d6c1dfe	226	*
mbed_official	15:a81a8d6c1dfe	227	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
mbed_official	15:a81a8d6c1dfe	228	* Each Generic Clock generator within the device can source its input clock
mbed_official	15:a81a8d6c1dfe	229	* from one of the provided Source Clocks, and prescale the output for one or
mbed_official	15:a81a8d6c1dfe	230	* more Generic Clock Channels in a one-to-many relationship. The generators
mbed_official	15:a81a8d6c1dfe	231	* thus allow for several clocks to be generated of different frequencies,
mbed_official	15:a81a8d6c1dfe	232	* power usages, and accuracies, which can be turned on and off individually to
mbed_official	15:a81a8d6c1dfe	233	* disable the clocks to multiple peripherals as a group.
mbed_official	15:a81a8d6c1dfe	234	*
mbed_official	15:a81a8d6c1dfe	235	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
mbed_official	15:a81a8d6c1dfe	236	* To connect a Generic Clock Generator to a peripheral within the
mbed_official	15:a81a8d6c1dfe	237	* device, a Generic Clock Channel is used. Each peripheral or
mbed_official	15:a81a8d6c1dfe	238	* peripheral group has an associated Generic Clock Channel, which serves as the
mbed_official	15:a81a8d6c1dfe	239	* clock input for the peripheral(s). To supply a clock to the peripheral
mbed_official	15:a81a8d6c1dfe	240	* module(s), the associated channel must be connected to a running Generic
mbed_official	15:a81a8d6c1dfe	241	* Clock Generator and the channel enabled.
mbed_official	15:a81a8d6c1dfe	242	*
mbed_official	15:a81a8d6c1dfe	243	* \section asfdoc_sam0_system_clock_special_considerations Special Considerations
mbed_official	15:a81a8d6c1dfe	244	*
mbed_official	15:a81a8d6c1dfe	245	* There are no special considerations for this module.
mbed_official	15:a81a8d6c1dfe	246	*
mbed_official	15:a81a8d6c1dfe	247	*
mbed_official	15:a81a8d6c1dfe	248	* \section asfdoc_sam0_system_clock_extra_info Extra Information
mbed_official	15:a81a8d6c1dfe	249	*
mbed_official	15:a81a8d6c1dfe	250	* For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
mbed_official	15:a81a8d6c1dfe	251	* - \ref asfdoc_sam0_system_clock_extra_acronyms
mbed_official	15:a81a8d6c1dfe	252	* - \ref asfdoc_sam0_system_clock_extra_dependencies
mbed_official	15:a81a8d6c1dfe	253	* - \ref asfdoc_sam0_system_clock_extra_errata
mbed_official	15:a81a8d6c1dfe	254	* - \ref asfdoc_sam0_system_clock_extra_history
mbed_official	15:a81a8d6c1dfe	255	*
mbed_official	15:a81a8d6c1dfe	256	*
mbed_official	15:a81a8d6c1dfe	257	* \section asfdoc_sam0_system_clock_examples Examples
mbed_official	15:a81a8d6c1dfe	258	*
mbed_official	15:a81a8d6c1dfe	259	* For a list of examples related to this driver, see
mbed_official	15:a81a8d6c1dfe	260	* \ref asfdoc_sam0_system_clock_exqsg.
mbed_official	15:a81a8d6c1dfe	261	*
mbed_official	15:a81a8d6c1dfe	262	*
mbed_official	15:a81a8d6c1dfe	263	* \section asfdoc_sam0_system_clock_api_overview API Overview
mbed_official	15:a81a8d6c1dfe	264	* @{
mbed_official	15:a81a8d6c1dfe	265	*/
mbed_official	15:a81a8d6c1dfe	266
mbed_official	15:a81a8d6c1dfe	267	#include <compiler.h>
mbed_official	15:a81a8d6c1dfe	268	#include <gclk.h>
mbed_official	15:a81a8d6c1dfe	269
mbed_official	15:a81a8d6c1dfe	270	/**
mbed_official	15:a81a8d6c1dfe	271	* \name Driver Feature Definition
mbed_official	15:a81a8d6c1dfe	272	* Define system clock features set according to different device family.
mbed_official	15:a81a8d6c1dfe	273	* @{
mbed_official	15:a81a8d6c1dfe	274	*/
mbed_official	15:a81a8d6c1dfe	275	#if (SAMD21) \|\| (SAMR21) \|\| (SAMD11) \|\| (SAMD10) \|\| (SAMDA1) \|\| defined(__DOXYGEN__)
mbed_official	15:a81a8d6c1dfe	276	/** Digital Phase Locked Loop (DPLL) feature support. */
mbed_official	15:a81a8d6c1dfe	277	# define FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	15:a81a8d6c1dfe	278	#endif
mbed_official	15:a81a8d6c1dfe	279	/@}/
mbed_official	15:a81a8d6c1dfe	280
mbed_official	15:a81a8d6c1dfe	281	/**
mbed_official	15:a81a8d6c1dfe	282	* \brief Available start-up times for the XOSC32K.
mbed_official	15:a81a8d6c1dfe	283	*
mbed_official	15:a81a8d6c1dfe	284	* Available external 32KHz oscillator start-up times, as a number of external
mbed_official	15:a81a8d6c1dfe	285	* clock cycles.
mbed_official	15:a81a8d6c1dfe	286	*/
mbed_official	15:a81a8d6c1dfe	287	enum system_xosc32k_startup {
mbed_official	15:a81a8d6c1dfe	288	/** Wait zero clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	289	SYSTEM_XOSC32K_STARTUP_0,
mbed_official	15:a81a8d6c1dfe	290	/** Wait 32 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	291	SYSTEM_XOSC32K_STARTUP_32,
mbed_official	15:a81a8d6c1dfe	292	/** Wait 2048 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	293	SYSTEM_XOSC32K_STARTUP_2048,
mbed_official	15:a81a8d6c1dfe	294	/** Wait 4096 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	295	SYSTEM_XOSC32K_STARTUP_4096,
mbed_official	15:a81a8d6c1dfe	296	/** Wait 16384 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	297	SYSTEM_XOSC32K_STARTUP_16384,
mbed_official	15:a81a8d6c1dfe	298	/** Wait 32768 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	299	SYSTEM_XOSC32K_STARTUP_32768,
mbed_official	15:a81a8d6c1dfe	300	/** Wait 65536 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	301	SYSTEM_XOSC32K_STARTUP_65536,
mbed_official	15:a81a8d6c1dfe	302	/** Wait 131072 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	303	SYSTEM_XOSC32K_STARTUP_131072,
mbed_official	15:a81a8d6c1dfe	304	};
mbed_official	15:a81a8d6c1dfe	305
mbed_official	15:a81a8d6c1dfe	306	/**
mbed_official	15:a81a8d6c1dfe	307	* \brief Available start-up times for the XOSC.
mbed_official	15:a81a8d6c1dfe	308	*
mbed_official	15:a81a8d6c1dfe	309	* Available external oscillator start-up times, as a number of external clock
mbed_official	15:a81a8d6c1dfe	310	* cycles.
mbed_official	15:a81a8d6c1dfe	311	*/
mbed_official	15:a81a8d6c1dfe	312	enum system_xosc_startup {
mbed_official	15:a81a8d6c1dfe	313	/** Wait one clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	314	SYSTEM_XOSC_STARTUP_1,
mbed_official	15:a81a8d6c1dfe	315	/** Wait two clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	316	SYSTEM_XOSC_STARTUP_2,
mbed_official	15:a81a8d6c1dfe	317	/** Wait four clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	318	SYSTEM_XOSC_STARTUP_4,
mbed_official	15:a81a8d6c1dfe	319	/** Wait eight clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	320	SYSTEM_XOSC_STARTUP_8,
mbed_official	15:a81a8d6c1dfe	321	/** Wait 16 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	322	SYSTEM_XOSC_STARTUP_16,
mbed_official	15:a81a8d6c1dfe	323	/** Wait 32 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	324	SYSTEM_XOSC_STARTUP_32,
mbed_official	15:a81a8d6c1dfe	325	/** Wait 64 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	326	SYSTEM_XOSC_STARTUP_64,
mbed_official	15:a81a8d6c1dfe	327	/** Wait 128 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	328	SYSTEM_XOSC_STARTUP_128,
mbed_official	15:a81a8d6c1dfe	329	/** Wait 256 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	330	SYSTEM_XOSC_STARTUP_256,
mbed_official	15:a81a8d6c1dfe	331	/** Wait 512 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	332	SYSTEM_XOSC_STARTUP_512,
mbed_official	15:a81a8d6c1dfe	333	/** Wait 1024 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	334	SYSTEM_XOSC_STARTUP_1024,
mbed_official	15:a81a8d6c1dfe	335	/** Wait 2048 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	336	SYSTEM_XOSC_STARTUP_2048,
mbed_official	15:a81a8d6c1dfe	337	/** Wait 4096 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	338	SYSTEM_XOSC_STARTUP_4096,
mbed_official	15:a81a8d6c1dfe	339	/** Wait 8192 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	340	SYSTEM_XOSC_STARTUP_8192,
mbed_official	15:a81a8d6c1dfe	341	/** Wait 16384 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	342	SYSTEM_XOSC_STARTUP_16384,
mbed_official	15:a81a8d6c1dfe	343	/** Wait 32768 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	344	SYSTEM_XOSC_STARTUP_32768,
mbed_official	15:a81a8d6c1dfe	345	};
mbed_official	15:a81a8d6c1dfe	346
mbed_official	15:a81a8d6c1dfe	347	/**
mbed_official	15:a81a8d6c1dfe	348	* \brief Available start-up times for the OSC32K.
mbed_official	15:a81a8d6c1dfe	349	*
mbed_official	15:a81a8d6c1dfe	350	* Available internal 32KHz oscillator start-up times, as a number of internal
mbed_official	15:a81a8d6c1dfe	351	* OSC32K clock cycles.
mbed_official	15:a81a8d6c1dfe	352	*/
mbed_official	15:a81a8d6c1dfe	353	enum system_osc32k_startup {
mbed_official	15:a81a8d6c1dfe	354	/** Wait three clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	355	SYSTEM_OSC32K_STARTUP_3,
mbed_official	15:a81a8d6c1dfe	356	/** Wait four clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	357	SYSTEM_OSC32K_STARTUP_4,
mbed_official	15:a81a8d6c1dfe	358	/** Wait six clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	359	SYSTEM_OSC32K_STARTUP_6,
mbed_official	15:a81a8d6c1dfe	360	/** Wait ten clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	361	SYSTEM_OSC32K_STARTUP_10,
mbed_official	15:a81a8d6c1dfe	362	/** Wait 18 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	363	SYSTEM_OSC32K_STARTUP_18,
mbed_official	15:a81a8d6c1dfe	364	/** Wait 34 clock cycles until the clock source is considered stable */
mbed_official	15:a81a8d6c1dfe	365	SYSTEM_OSC32K_STARTUP_34,
mbed_official	15:a81a8d6c1dfe	366	/** Wait 66 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	367	SYSTEM_OSC32K_STARTUP_66,
mbed_official	15:a81a8d6c1dfe	368	/** Wait 130 clock cycles until the clock source is considered stable. */
mbed_official	15:a81a8d6c1dfe	369	SYSTEM_OSC32K_STARTUP_130,
mbed_official	15:a81a8d6c1dfe	370	};
mbed_official	15:a81a8d6c1dfe	371
mbed_official	15:a81a8d6c1dfe	372	/**
mbed_official	15:a81a8d6c1dfe	373	* \brief Division prescalers for the internal 8MHz system clock.
mbed_official	15:a81a8d6c1dfe	374	*
mbed_official	15:a81a8d6c1dfe	375	* Available prescalers for the internal 8MHz (nominal) system clock.
mbed_official	15:a81a8d6c1dfe	376	*/
mbed_official	15:a81a8d6c1dfe	377	enum system_osc8m_div {
mbed_official	15:a81a8d6c1dfe	378	/** Do not divide the 8MHz RC oscillator output. */
mbed_official	15:a81a8d6c1dfe	379	SYSTEM_OSC8M_DIV_1,
mbed_official	15:a81a8d6c1dfe	380	/** Divide the 8MHz RC oscillator output by two. */
mbed_official	15:a81a8d6c1dfe	381	SYSTEM_OSC8M_DIV_2,
mbed_official	15:a81a8d6c1dfe	382	/** Divide the 8MHz RC oscillator output by four. */
mbed_official	15:a81a8d6c1dfe	383	SYSTEM_OSC8M_DIV_4,
mbed_official	15:a81a8d6c1dfe	384	/** Divide the 8MHz RC oscillator output by eight. */
mbed_official	15:a81a8d6c1dfe	385	SYSTEM_OSC8M_DIV_8,
mbed_official	15:a81a8d6c1dfe	386	};
mbed_official	15:a81a8d6c1dfe	387
mbed_official	15:a81a8d6c1dfe	388	/**
mbed_official	15:a81a8d6c1dfe	389	* \brief Frequency range for the internal 8MHz RC oscillator.
mbed_official	15:a81a8d6c1dfe	390	*
mbed_official	15:a81a8d6c1dfe	391	* Internal 8MHz RC oscillator frequency range setting
mbed_official	15:a81a8d6c1dfe	392	*/
mbed_official	15:a81a8d6c1dfe	393	enum system_osc8m_frequency_range {
mbed_official	15:a81a8d6c1dfe	394	/** Frequency range 4MHz to 6MHz. */
mbed_official	15:a81a8d6c1dfe	395	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
mbed_official	15:a81a8d6c1dfe	396	/** Frequency range 6MHz to 8MHz. */
mbed_official	15:a81a8d6c1dfe	397	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
mbed_official	15:a81a8d6c1dfe	398	/** Frequency range 8MHz to 11MHz. */
mbed_official	15:a81a8d6c1dfe	399	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
mbed_official	15:a81a8d6c1dfe	400	/** Frequency range 11MHz to 15MHz. */
mbed_official	15:a81a8d6c1dfe	401	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
mbed_official	15:a81a8d6c1dfe	402	};
mbed_official	15:a81a8d6c1dfe	403
mbed_official	15:a81a8d6c1dfe	404	/**
mbed_official	15:a81a8d6c1dfe	405	* \brief Main CPU and APB/AHB bus clock source prescaler values.
mbed_official	15:a81a8d6c1dfe	406	*
mbed_official	15:a81a8d6c1dfe	407	* Available division ratios for the CPU and APB/AHB bus clocks.
mbed_official	15:a81a8d6c1dfe	408	*/
mbed_official	15:a81a8d6c1dfe	409	enum system_main_clock_div {
mbed_official	15:a81a8d6c1dfe	410	/** Divide Main clock by one. */
mbed_official	15:a81a8d6c1dfe	411	SYSTEM_MAIN_CLOCK_DIV_1,
mbed_official	15:a81a8d6c1dfe	412	/** Divide Main clock by two. */
mbed_official	15:a81a8d6c1dfe	413	SYSTEM_MAIN_CLOCK_DIV_2,
mbed_official	15:a81a8d6c1dfe	414	/** Divide Main clock by four. */
mbed_official	15:a81a8d6c1dfe	415	SYSTEM_MAIN_CLOCK_DIV_4,
mbed_official	15:a81a8d6c1dfe	416	/** Divide Main clock by eight. */
mbed_official	15:a81a8d6c1dfe	417	SYSTEM_MAIN_CLOCK_DIV_8,
mbed_official	15:a81a8d6c1dfe	418	/** Divide Main clock by 16. */
mbed_official	15:a81a8d6c1dfe	419	SYSTEM_MAIN_CLOCK_DIV_16,
mbed_official	15:a81a8d6c1dfe	420	/** Divide Main clock by 32. */
mbed_official	15:a81a8d6c1dfe	421	SYSTEM_MAIN_CLOCK_DIV_32,
mbed_official	15:a81a8d6c1dfe	422	/** Divide Main clock by 64. */
mbed_official	15:a81a8d6c1dfe	423	SYSTEM_MAIN_CLOCK_DIV_64,
mbed_official	15:a81a8d6c1dfe	424	/** Divide Main clock by 128. */
mbed_official	15:a81a8d6c1dfe	425	SYSTEM_MAIN_CLOCK_DIV_128,
mbed_official	15:a81a8d6c1dfe	426	};
mbed_official	15:a81a8d6c1dfe	427
mbed_official	15:a81a8d6c1dfe	428	/**
mbed_official	15:a81a8d6c1dfe	429	* \brief External clock source types.
mbed_official	15:a81a8d6c1dfe	430	*
mbed_official	15:a81a8d6c1dfe	431	* Available external clock source types.
mbed_official	15:a81a8d6c1dfe	432	*/
mbed_official	15:a81a8d6c1dfe	433	enum system_clock_external {
mbed_official	15:a81a8d6c1dfe	434	/** The external clock source is a crystal oscillator. */
mbed_official	15:a81a8d6c1dfe	435	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
mbed_official	15:a81a8d6c1dfe	436	/** The connected clock source is an external logic level clock signal. */
mbed_official	15:a81a8d6c1dfe	437	SYSTEM_CLOCK_EXTERNAL_CLOCK,
mbed_official	15:a81a8d6c1dfe	438	};
mbed_official	15:a81a8d6c1dfe	439
mbed_official	15:a81a8d6c1dfe	440	/**
mbed_official	15:a81a8d6c1dfe	441	* \brief Operating modes of the DFLL clock source.
mbed_official	15:a81a8d6c1dfe	442	*
mbed_official	15:a81a8d6c1dfe	443	* Available operating modes of the DFLL clock source module.
mbed_official	15:a81a8d6c1dfe	444	*/
mbed_official	15:a81a8d6c1dfe	445	enum system_clock_dfll_loop_mode {
mbed_official	15:a81a8d6c1dfe	446	/** The DFLL is operating in open loop mode with no feedback. */
mbed_official	15:a81a8d6c1dfe	447	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
mbed_official	15:a81a8d6c1dfe	448	/** The DFLL is operating in closed loop mode with frequency feedback from
mbed_official	15:a81a8d6c1dfe	449	* a low frequency reference clock.
mbed_official	15:a81a8d6c1dfe	450	*/
mbed_official	15:a81a8d6c1dfe	451	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
mbed_official	15:a81a8d6c1dfe	452
mbed_official	15:a81a8d6c1dfe	453	#ifdef SYSCTRL_DFLLCTRL_USBCRM
mbed_official	15:a81a8d6c1dfe	454	/** The DFLL is operating in USB recovery mode with frequency feedback
mbed_official	15:a81a8d6c1dfe	455	* from USB SOF.
mbed_official	15:a81a8d6c1dfe	456	*/
mbed_official	15:a81a8d6c1dfe	457	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
mbed_official	15:a81a8d6c1dfe	458	#endif
mbed_official	15:a81a8d6c1dfe	459	};
mbed_official	15:a81a8d6c1dfe	460
mbed_official	15:a81a8d6c1dfe	461	/**
mbed_official	15:a81a8d6c1dfe	462	* \brief Locking behavior for the DFLL during device wake-up.
mbed_official	15:a81a8d6c1dfe	463	*
mbed_official	15:a81a8d6c1dfe	464	* DFLL lock behavior modes on device wake-up from sleep.
mbed_official	15:a81a8d6c1dfe	465	*/
mbed_official	15:a81a8d6c1dfe	466	enum system_clock_dfll_wakeup_lock {
mbed_official	15:a81a8d6c1dfe	467	/** Keep DFLL lock when the device wakes from sleep. */
mbed_official	15:a81a8d6c1dfe	468	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
mbed_official	15:a81a8d6c1dfe	469	/** Lose DFLL lock when the devices wakes from sleep. */
mbed_official	15:a81a8d6c1dfe	470	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
mbed_official	15:a81a8d6c1dfe	471	};
mbed_official	15:a81a8d6c1dfe	472
mbed_official	15:a81a8d6c1dfe	473	/**
mbed_official	15:a81a8d6c1dfe	474	* \brief Fine tracking behavior for the DFLL once a lock has been acquired.
mbed_official	15:a81a8d6c1dfe	475	*
mbed_official	15:a81a8d6c1dfe	476	* DFLL fine tracking behavior modes after a lock has been acquired.
mbed_official	15:a81a8d6c1dfe	477	*/
mbed_official	15:a81a8d6c1dfe	478	enum system_clock_dfll_stable_tracking {
mbed_official	15:a81a8d6c1dfe	479	/** Keep tracking after the DFLL has gotten a fine lock. */
mbed_official	15:a81a8d6c1dfe	480	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
mbed_official	15:a81a8d6c1dfe	481	/** Stop tracking after the DFLL has gotten a fine lock. */
mbed_official	15:a81a8d6c1dfe	482	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
mbed_official	15:a81a8d6c1dfe	483	};
mbed_official	15:a81a8d6c1dfe	484
mbed_official	15:a81a8d6c1dfe	485	/**
mbed_official	15:a81a8d6c1dfe	486	* \brief Chill-cycle behavior of the DFLL module.
mbed_official	15:a81a8d6c1dfe	487	*
mbed_official	15:a81a8d6c1dfe	488	* DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
mbed_official	15:a81a8d6c1dfe	489	* of time when the DFLL output frequency is not measured by the unit, to allow
mbed_official	15:a81a8d6c1dfe	490	* the output to stabilize after a change in the input clock source.
mbed_official	15:a81a8d6c1dfe	491	*/
mbed_official	15:a81a8d6c1dfe	492	enum system_clock_dfll_chill_cycle {
mbed_official	15:a81a8d6c1dfe	493	/** Enable a chill cycle, where the DFLL output frequency is not measured. */
mbed_official	15:a81a8d6c1dfe	494	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
mbed_official	15:a81a8d6c1dfe	495	/** Disable a chill cycle, where the DFLL output frequency is not measured. */
mbed_official	15:a81a8d6c1dfe	496	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
mbed_official	15:a81a8d6c1dfe	497	};
mbed_official	15:a81a8d6c1dfe	498
mbed_official	15:a81a8d6c1dfe	499	/**
mbed_official	15:a81a8d6c1dfe	500	* \brief QuickLock settings for the DFLL module.
mbed_official	15:a81a8d6c1dfe	501	*
mbed_official	15:a81a8d6c1dfe	502	* DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
mbed_official	15:a81a8d6c1dfe	503	* the DFLL output frequency at the expense of accuracy.
mbed_official	15:a81a8d6c1dfe	504	*/
mbed_official	15:a81a8d6c1dfe	505	enum system_clock_dfll_quick_lock {
mbed_official	15:a81a8d6c1dfe	506	/** Enable the QuickLock feature for looser lock requirements on the DFLL. */
mbed_official	15:a81a8d6c1dfe	507	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
mbed_official	15:a81a8d6c1dfe	508	/** Disable the QuickLock feature for strict lock requirements on the DFLL. */
mbed_official	15:a81a8d6c1dfe	509	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
mbed_official	15:a81a8d6c1dfe	510	};
mbed_official	15:a81a8d6c1dfe	511
mbed_official	15:a81a8d6c1dfe	512	/**
mbed_official	15:a81a8d6c1dfe	513	* \brief Available clock sources in the system.
mbed_official	15:a81a8d6c1dfe	514	*
mbed_official	15:a81a8d6c1dfe	515	* Clock sources available to the GCLK generators.
mbed_official	15:a81a8d6c1dfe	516	*/
mbed_official	15:a81a8d6c1dfe	517	enum system_clock_source {
mbed_official	15:a81a8d6c1dfe	518	/** Internal 8MHz RC oscillator. */
mbed_official	15:a81a8d6c1dfe	519	SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
mbed_official	15:a81a8d6c1dfe	520	/** Internal 32KHz RC oscillator. */
mbed_official	15:a81a8d6c1dfe	521	SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
mbed_official	15:a81a8d6c1dfe	522	/** External oscillator. */
mbed_official	15:a81a8d6c1dfe	523	SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
mbed_official	15:a81a8d6c1dfe	524	/** External 32KHz oscillator. */
mbed_official	15:a81a8d6c1dfe	525	SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
mbed_official	15:a81a8d6c1dfe	526	/** Digital Frequency Locked Loop (DFLL). */
mbed_official	15:a81a8d6c1dfe	527	SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
mbed_official	15:a81a8d6c1dfe	528	/** Internal Ultra Low Power 32KHz oscillator. */
mbed_official	15:a81a8d6c1dfe	529	SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
mbed_official	15:a81a8d6c1dfe	530	/** Generator input pad. */
mbed_official	15:a81a8d6c1dfe	531	SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
mbed_official	15:a81a8d6c1dfe	532	/** Generic clock generator one output. */
mbed_official	15:a81a8d6c1dfe	533	SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
mbed_official	15:a81a8d6c1dfe	534	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	15:a81a8d6c1dfe	535	/** Digital Phase Locked Loop (DPLL).
mbed_official	15:a81a8d6c1dfe	536	* Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
mbed_official	15:a81a8d6c1dfe	537	*/
mbed_official	15:a81a8d6c1dfe	538	SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
mbed_official	15:a81a8d6c1dfe	539	#endif
mbed_official	15:a81a8d6c1dfe	540	};
mbed_official	15:a81a8d6c1dfe	541
mbed_official	15:a81a8d6c1dfe	542	/**
mbed_official	15:a81a8d6c1dfe	543	* \brief List of APB peripheral buses.
mbed_official	15:a81a8d6c1dfe	544	*
mbed_official	15:a81a8d6c1dfe	545	* Available bus clock domains on the APB bus.
mbed_official	15:a81a8d6c1dfe	546	*/
mbed_official	15:a81a8d6c1dfe	547	enum system_clock_apb_bus {
mbed_official	15:a81a8d6c1dfe	548	/** Peripheral bus A on the APB bus. */
mbed_official	15:a81a8d6c1dfe	549	SYSTEM_CLOCK_APB_APBA,
mbed_official	15:a81a8d6c1dfe	550	/** Peripheral bus B on the APB bus. */
mbed_official	15:a81a8d6c1dfe	551	SYSTEM_CLOCK_APB_APBB,
mbed_official	15:a81a8d6c1dfe	552	/** Peripheral bus C on the APB bus. */
mbed_official	15:a81a8d6c1dfe	553	SYSTEM_CLOCK_APB_APBC,
mbed_official	15:a81a8d6c1dfe	554	};
mbed_official	15:a81a8d6c1dfe	555
mbed_official	15:a81a8d6c1dfe	556	/**
mbed_official	15:a81a8d6c1dfe	557	* \brief Configuration structure for XOSC.
mbed_official	15:a81a8d6c1dfe	558	*
mbed_official	15:a81a8d6c1dfe	559	* External oscillator clock configuration structure.
mbed_official	15:a81a8d6c1dfe	560	*/
mbed_official	15:a81a8d6c1dfe	561	struct system_clock_source_xosc_config {
mbed_official	15:a81a8d6c1dfe	562	/** External clock type. */
mbed_official	15:a81a8d6c1dfe	563	enum system_clock_external external_clock;
mbed_official	15:a81a8d6c1dfe	564	/** Crystal oscillator start-up time. */
mbed_official	15:a81a8d6c1dfe	565	enum system_xosc_startup startup_time;
mbed_official	15:a81a8d6c1dfe	566	/** Enable automatic amplitude gain control. */
mbed_official	15:a81a8d6c1dfe	567	bool auto_gain_control;
mbed_official	15:a81a8d6c1dfe	568	/** External clock/crystal frequency. */
mbed_official	15:a81a8d6c1dfe	569	uint32_t frequency;
mbed_official	15:a81a8d6c1dfe	570	/** Keep the XOSC enabled in standby sleep mode. */
mbed_official	15:a81a8d6c1dfe	571	bool run_in_standby;
mbed_official	15:a81a8d6c1dfe	572	/** Run On Demand. If this is set the XOSC won't run
mbed_official	15:a81a8d6c1dfe	573	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	574	bool on_demand;
mbed_official	15:a81a8d6c1dfe	575	};
mbed_official	15:a81a8d6c1dfe	576
mbed_official	15:a81a8d6c1dfe	577	/**
mbed_official	15:a81a8d6c1dfe	578	* \brief Configuration structure for XOSC32K.
mbed_official	15:a81a8d6c1dfe	579	*
mbed_official	15:a81a8d6c1dfe	580	* External 32KHz oscillator clock configuration structure.
mbed_official	15:a81a8d6c1dfe	581	*/
mbed_official	15:a81a8d6c1dfe	582	struct system_clock_source_xosc32k_config {
mbed_official	15:a81a8d6c1dfe	583	/** External clock type. */
mbed_official	15:a81a8d6c1dfe	584	enum system_clock_external external_clock;
mbed_official	15:a81a8d6c1dfe	585	/** Crystal oscillator start-up time. */
mbed_official	15:a81a8d6c1dfe	586	enum system_xosc32k_startup startup_time;
mbed_official	15:a81a8d6c1dfe	587	/** Enable automatic amplitude control. */
mbed_official	15:a81a8d6c1dfe	588	bool auto_gain_control;
mbed_official	15:a81a8d6c1dfe	589	/** Enable 1KHz output. */
mbed_official	15:a81a8d6c1dfe	590	bool enable_1khz_output;
mbed_official	15:a81a8d6c1dfe	591	/** Enable 32KHz output. */
mbed_official	15:a81a8d6c1dfe	592	bool enable_32khz_output;
mbed_official	15:a81a8d6c1dfe	593	/** External clock/crystal frequency. */
mbed_official	15:a81a8d6c1dfe	594	uint32_t frequency;
mbed_official	15:a81a8d6c1dfe	595	/** Keep the XOSC32K enabled in standby sleep mode. */
mbed_official	15:a81a8d6c1dfe	596	bool run_in_standby;
mbed_official	15:a81a8d6c1dfe	597	/** Run On Demand. If this is set the XOSC32K won't run
mbed_official	15:a81a8d6c1dfe	598	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	599	bool on_demand;
mbed_official	15:a81a8d6c1dfe	600	/** Lock configuration after it has been written,
mbed_official	15:a81a8d6c1dfe	601	* a device reset will release the lock. */
mbed_official	15:a81a8d6c1dfe	602	bool write_once;
mbed_official	15:a81a8d6c1dfe	603	};
mbed_official	15:a81a8d6c1dfe	604
mbed_official	15:a81a8d6c1dfe	605	/**
mbed_official	15:a81a8d6c1dfe	606	* \brief Configuration structure for OSC8M.
mbed_official	15:a81a8d6c1dfe	607	*
mbed_official	15:a81a8d6c1dfe	608	* Internal 8MHz (nominal) oscillator configuration structure.
mbed_official	15:a81a8d6c1dfe	609	*/
mbed_official	15:a81a8d6c1dfe	610	struct system_clock_source_osc8m_config {
mbed_official	15:a81a8d6c1dfe	611	/** Internal 8MHz RC oscillator prescaler. */
mbed_official	15:a81a8d6c1dfe	612	enum system_osc8m_div prescaler;
mbed_official	15:a81a8d6c1dfe	613	/** Keep the OSC8M enabled in standby sleep mode. */
mbed_official	15:a81a8d6c1dfe	614	bool run_in_standby;
mbed_official	15:a81a8d6c1dfe	615	/** Run On Demand. If this is set the OSC8M won't run
mbed_official	15:a81a8d6c1dfe	616	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	617	bool on_demand;
mbed_official	15:a81a8d6c1dfe	618	};
mbed_official	15:a81a8d6c1dfe	619
mbed_official	15:a81a8d6c1dfe	620	/**
mbed_official	15:a81a8d6c1dfe	621	* \brief Configuration structure for OSC32K.
mbed_official	15:a81a8d6c1dfe	622	*
mbed_official	15:a81a8d6c1dfe	623	* Internal 32KHz (nominal) oscillator configuration structure.
mbed_official	15:a81a8d6c1dfe	624	*/
mbed_official	15:a81a8d6c1dfe	625	struct system_clock_source_osc32k_config {
mbed_official	15:a81a8d6c1dfe	626	/** Startup time. */
mbed_official	15:a81a8d6c1dfe	627	enum system_osc32k_startup startup_time;
mbed_official	15:a81a8d6c1dfe	628	/** Enable 1KHz output. */
mbed_official	15:a81a8d6c1dfe	629	bool enable_1khz_output;
mbed_official	15:a81a8d6c1dfe	630	/** Enable 32KHz output. */
mbed_official	15:a81a8d6c1dfe	631	bool enable_32khz_output;
mbed_official	15:a81a8d6c1dfe	632	/** Keep the OSC32K enabled in standby sleep mode. */
mbed_official	15:a81a8d6c1dfe	633	bool run_in_standby;
mbed_official	15:a81a8d6c1dfe	634	/** Run On Demand. If this is set the OSC32K won't run
mbed_official	15:a81a8d6c1dfe	635	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	636	bool on_demand;
mbed_official	15:a81a8d6c1dfe	637	/** Lock configuration after it has been written,
mbed_official	15:a81a8d6c1dfe	638	* a device reset will release the lock. */
mbed_official	15:a81a8d6c1dfe	639	bool write_once;
mbed_official	15:a81a8d6c1dfe	640	};
mbed_official	15:a81a8d6c1dfe	641
mbed_official	15:a81a8d6c1dfe	642	/**
mbed_official	15:a81a8d6c1dfe	643	* \brief Configuration structure for DFLL.
mbed_official	15:a81a8d6c1dfe	644	*
mbed_official	15:a81a8d6c1dfe	645	* DFLL oscillator configuration structure.
mbed_official	15:a81a8d6c1dfe	646	*/
mbed_official	15:a81a8d6c1dfe	647	struct system_clock_source_dfll_config {
mbed_official	15:a81a8d6c1dfe	648	/** Loop mode. */
mbed_official	15:a81a8d6c1dfe	649	enum system_clock_dfll_loop_mode loop_mode;
mbed_official	15:a81a8d6c1dfe	650	/** Run On Demand. If this is set the DFLL won't run
mbed_official	15:a81a8d6c1dfe	651	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	652	bool on_demand;
mbed_official	15:a81a8d6c1dfe	653	/** Enable Quick Lock. */
mbed_official	15:a81a8d6c1dfe	654	enum system_clock_dfll_quick_lock quick_lock;
mbed_official	15:a81a8d6c1dfe	655	/** Enable Chill Cycle. */
mbed_official	15:a81a8d6c1dfe	656	enum system_clock_dfll_chill_cycle chill_cycle;
mbed_official	15:a81a8d6c1dfe	657	/** DFLL lock state on wakeup. */
mbed_official	15:a81a8d6c1dfe	658	enum system_clock_dfll_wakeup_lock wakeup_lock;
mbed_official	15:a81a8d6c1dfe	659	/** DFLL tracking after fine lock. */
mbed_official	15:a81a8d6c1dfe	660	enum system_clock_dfll_stable_tracking stable_tracking;
mbed_official	15:a81a8d6c1dfe	661	/** Coarse calibration value (Open loop mode). */
mbed_official	15:a81a8d6c1dfe	662	uint8_t coarse_value;
mbed_official	15:a81a8d6c1dfe	663	/** Fine calibration value (Open loop mode). */
mbed_official	15:a81a8d6c1dfe	664	uint16_t fine_value;
mbed_official	15:a81a8d6c1dfe	665	/** Coarse adjustment maximum step size (Closed loop mode). */
mbed_official	15:a81a8d6c1dfe	666	uint8_t coarse_max_step;
mbed_official	15:a81a8d6c1dfe	667	/** Fine adjustment maximum step size (Closed loop mode). */
mbed_official	15:a81a8d6c1dfe	668	uint16_t fine_max_step;
mbed_official	15:a81a8d6c1dfe	669	/** DFLL multiply factor (Closed loop mode. */
mbed_official	15:a81a8d6c1dfe	670	uint16_t multiply_factor;
mbed_official	15:a81a8d6c1dfe	671	};
mbed_official	15:a81a8d6c1dfe	672
mbed_official	15:a81a8d6c1dfe	673	/**
mbed_official	15:a81a8d6c1dfe	674	* \name External Oscillator Management
mbed_official	15:a81a8d6c1dfe	675	* @{
mbed_official	15:a81a8d6c1dfe	676	*/
mbed_official	15:a81a8d6c1dfe	677
mbed_official	15:a81a8d6c1dfe	678	/**
mbed_official	15:a81a8d6c1dfe	679	* \brief Retrieve the default configuration for XOSC.
mbed_official	15:a81a8d6c1dfe	680	*
mbed_official	15:a81a8d6c1dfe	681	* Fills a configuration structure with the default configuration for an
mbed_official	15:a81a8d6c1dfe	682	* external oscillator module:
mbed_official	15:a81a8d6c1dfe	683	* - External Crystal
mbed_official	15:a81a8d6c1dfe	684	* - Start-up time of 16384 external clock cycles
mbed_official	15:a81a8d6c1dfe	685	* - Automatic crystal gain control mode enabled
mbed_official	15:a81a8d6c1dfe	686	* - Frequency of 12MHz
mbed_official	15:a81a8d6c1dfe	687	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	688	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	689	*
mbed_official	15:a81a8d6c1dfe	690	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	691	*/
mbed_official	15:a81a8d6c1dfe	692	static inline void system_clock_source_xosc_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	693	struct system_clock_source_xosc_config *const config)
mbed_official	15:a81a8d6c1dfe	694	{
mbed_official	15:a81a8d6c1dfe	695	Assert(config);
mbed_official	15:a81a8d6c1dfe	696
mbed_official	15:a81a8d6c1dfe	697	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	15:a81a8d6c1dfe	698	config->startup_time = SYSTEM_XOSC_STARTUP_16384;
mbed_official	15:a81a8d6c1dfe	699	config->auto_gain_control = true;
mbed_official	15:a81a8d6c1dfe	700	config->frequency = 12000000UL;
mbed_official	15:a81a8d6c1dfe	701	config->run_in_standby = false;
mbed_official	15:a81a8d6c1dfe	702	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	703	}
mbed_official	15:a81a8d6c1dfe	704
mbed_official	15:a81a8d6c1dfe	705	void system_clock_source_xosc_set_config(
mbed_official	15:a81a8d6c1dfe	706	struct system_clock_source_xosc_config *const config);
mbed_official	15:a81a8d6c1dfe	707
mbed_official	15:a81a8d6c1dfe	708	/**
mbed_official	15:a81a8d6c1dfe	709	* @}
mbed_official	15:a81a8d6c1dfe	710	*/
mbed_official	15:a81a8d6c1dfe	711
mbed_official	15:a81a8d6c1dfe	712
mbed_official	15:a81a8d6c1dfe	713	/**
mbed_official	15:a81a8d6c1dfe	714	* \name External 32KHz Oscillator Management
mbed_official	15:a81a8d6c1dfe	715	* @{
mbed_official	15:a81a8d6c1dfe	716	*/
mbed_official	15:a81a8d6c1dfe	717
mbed_official	15:a81a8d6c1dfe	718	/**
mbed_official	15:a81a8d6c1dfe	719	* \brief Retrieve the default configuration for XOSC32K.
mbed_official	15:a81a8d6c1dfe	720	*
mbed_official	15:a81a8d6c1dfe	721	* Fills a configuration structure with the default configuration for an
mbed_official	15:a81a8d6c1dfe	722	* external 32KHz oscillator module:
mbed_official	15:a81a8d6c1dfe	723	* - External Crystal
mbed_official	15:a81a8d6c1dfe	724	* - Start-up time of 16384 external clock cycles
mbed_official	15:a81a8d6c1dfe	725	* - Automatic crystal gain control mode disabled
mbed_official	15:a81a8d6c1dfe	726	* - Frequency of 32.768KHz
mbed_official	15:a81a8d6c1dfe	727	* - 1KHz clock output disabled
mbed_official	15:a81a8d6c1dfe	728	* - 32KHz clock output enabled
mbed_official	15:a81a8d6c1dfe	729	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	730	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	731	* - Don't lock registers after configuration has been written
mbed_official	15:a81a8d6c1dfe	732	*
mbed_official	15:a81a8d6c1dfe	733	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	734	*/
mbed_official	15:a81a8d6c1dfe	735	static inline void system_clock_source_xosc32k_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	736	struct system_clock_source_xosc32k_config *const config)
mbed_official	15:a81a8d6c1dfe	737	{
mbed_official	15:a81a8d6c1dfe	738	Assert(config);
mbed_official	15:a81a8d6c1dfe	739
mbed_official	15:a81a8d6c1dfe	740	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	15:a81a8d6c1dfe	741	config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
mbed_official	15:a81a8d6c1dfe	742	config->auto_gain_control = false;
mbed_official	15:a81a8d6c1dfe	743	config->frequency = 32768UL;
mbed_official	15:a81a8d6c1dfe	744	config->enable_1khz_output = false;
mbed_official	15:a81a8d6c1dfe	745	config->enable_32khz_output = true;
mbed_official	15:a81a8d6c1dfe	746	config->run_in_standby = false;
mbed_official	15:a81a8d6c1dfe	747	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	748	config->write_once = false;
mbed_official	15:a81a8d6c1dfe	749	}
mbed_official	15:a81a8d6c1dfe	750
mbed_official	15:a81a8d6c1dfe	751	void system_clock_source_xosc32k_set_config(
mbed_official	15:a81a8d6c1dfe	752	struct system_clock_source_xosc32k_config *const config);
mbed_official	15:a81a8d6c1dfe	753	/**
mbed_official	15:a81a8d6c1dfe	754	* @}
mbed_official	15:a81a8d6c1dfe	755	*/
mbed_official	15:a81a8d6c1dfe	756
mbed_official	15:a81a8d6c1dfe	757
mbed_official	15:a81a8d6c1dfe	758	/**
mbed_official	15:a81a8d6c1dfe	759	* \name Internal 32KHz Oscillator Management
mbed_official	15:a81a8d6c1dfe	760	* @{
mbed_official	15:a81a8d6c1dfe	761	*/
mbed_official	15:a81a8d6c1dfe	762
mbed_official	15:a81a8d6c1dfe	763	/**
mbed_official	15:a81a8d6c1dfe	764	* \brief Retrieve the default configuration for OSC32K.
mbed_official	15:a81a8d6c1dfe	765	*
mbed_official	15:a81a8d6c1dfe	766	* Fills a configuration structure with the default configuration for an
mbed_official	15:a81a8d6c1dfe	767	* internal 32KHz oscillator module:
mbed_official	15:a81a8d6c1dfe	768	* - 1KHz clock output enabled
mbed_official	15:a81a8d6c1dfe	769	* - 32KHz clock output enabled
mbed_official	15:a81a8d6c1dfe	770	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	771	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	772	* - Set startup time to 130 cycles
mbed_official	15:a81a8d6c1dfe	773	* - Don't lock registers after configuration has been written
mbed_official	15:a81a8d6c1dfe	774	*
mbed_official	15:a81a8d6c1dfe	775	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	776	*/
mbed_official	15:a81a8d6c1dfe	777	static inline void system_clock_source_osc32k_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	778	struct system_clock_source_osc32k_config *const config)
mbed_official	15:a81a8d6c1dfe	779	{
mbed_official	15:a81a8d6c1dfe	780	Assert(config);
mbed_official	15:a81a8d6c1dfe	781
mbed_official	15:a81a8d6c1dfe	782	config->enable_1khz_output = true;
mbed_official	15:a81a8d6c1dfe	783	config->enable_32khz_output = true;
mbed_official	15:a81a8d6c1dfe	784	config->run_in_standby = false;
mbed_official	15:a81a8d6c1dfe	785	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	786	config->startup_time = SYSTEM_OSC32K_STARTUP_130;
mbed_official	15:a81a8d6c1dfe	787	config->write_once = false;
mbed_official	15:a81a8d6c1dfe	788	}
mbed_official	15:a81a8d6c1dfe	789
mbed_official	15:a81a8d6c1dfe	790	void system_clock_source_osc32k_set_config(
mbed_official	15:a81a8d6c1dfe	791	struct system_clock_source_osc32k_config *const config);
mbed_official	15:a81a8d6c1dfe	792
mbed_official	15:a81a8d6c1dfe	793	/**
mbed_official	15:a81a8d6c1dfe	794	* @}
mbed_official	15:a81a8d6c1dfe	795	*/
mbed_official	15:a81a8d6c1dfe	796
mbed_official	15:a81a8d6c1dfe	797
mbed_official	15:a81a8d6c1dfe	798	/**
mbed_official	15:a81a8d6c1dfe	799	* \name Internal 8MHz Oscillator Management
mbed_official	15:a81a8d6c1dfe	800	* @{
mbed_official	15:a81a8d6c1dfe	801	*/
mbed_official	15:a81a8d6c1dfe	802
mbed_official	15:a81a8d6c1dfe	803	/**
mbed_official	15:a81a8d6c1dfe	804	* \brief Retrieve the default configuration for OSC8M.
mbed_official	15:a81a8d6c1dfe	805	*
mbed_official	15:a81a8d6c1dfe	806	* Fills a configuration structure with the default configuration for an
mbed_official	15:a81a8d6c1dfe	807	* internal 8MHz (nominal) oscillator module:
mbed_official	15:a81a8d6c1dfe	808	* - Clock output frequency divided by a factor of eight
mbed_official	15:a81a8d6c1dfe	809	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	810	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	811	*
mbed_official	15:a81a8d6c1dfe	812	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	813	*/
mbed_official	15:a81a8d6c1dfe	814	static inline void system_clock_source_osc8m_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	815	struct system_clock_source_osc8m_config *const config)
mbed_official	15:a81a8d6c1dfe	816	{
mbed_official	15:a81a8d6c1dfe	817	Assert(config);
mbed_official	15:a81a8d6c1dfe	818
mbed_official	15:a81a8d6c1dfe	819	config->prescaler = SYSTEM_OSC8M_DIV_8;
mbed_official	15:a81a8d6c1dfe	820	config->run_in_standby = false;
mbed_official	15:a81a8d6c1dfe	821	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	822	}
mbed_official	15:a81a8d6c1dfe	823
mbed_official	15:a81a8d6c1dfe	824	void system_clock_source_osc8m_set_config(
mbed_official	15:a81a8d6c1dfe	825	struct system_clock_source_osc8m_config *const config);
mbed_official	15:a81a8d6c1dfe	826
mbed_official	15:a81a8d6c1dfe	827	/**
mbed_official	15:a81a8d6c1dfe	828	* @}
mbed_official	15:a81a8d6c1dfe	829	*/
mbed_official	15:a81a8d6c1dfe	830
mbed_official	15:a81a8d6c1dfe	831
mbed_official	15:a81a8d6c1dfe	832	/**
mbed_official	15:a81a8d6c1dfe	833	* \name Internal DFLL Management
mbed_official	15:a81a8d6c1dfe	834	* @{
mbed_official	15:a81a8d6c1dfe	835	*/
mbed_official	15:a81a8d6c1dfe	836
mbed_official	15:a81a8d6c1dfe	837	/**
mbed_official	15:a81a8d6c1dfe	838	* \brief Retrieve the default configuration for DFLL.
mbed_official	15:a81a8d6c1dfe	839	*
mbed_official	15:a81a8d6c1dfe	840	* Fills a configuration structure with the default configuration for a
mbed_official	15:a81a8d6c1dfe	841	* DFLL oscillator module:
mbed_official	15:a81a8d6c1dfe	842	* - Open loop mode
mbed_official	15:a81a8d6c1dfe	843	* - QuickLock mode enabled
mbed_official	15:a81a8d6c1dfe	844	* - Chill cycle enabled
mbed_official	15:a81a8d6c1dfe	845	* - Output frequency lock maintained during device wake-up
mbed_official	15:a81a8d6c1dfe	846	* - Continuous tracking of the output frequency
mbed_official	15:a81a8d6c1dfe	847	* - Default tracking values at the mid-points for both coarse and fine
mbed_official	15:a81a8d6c1dfe	848	* tracking parameters
mbed_official	15:a81a8d6c1dfe	849	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	850	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	851	*
mbed_official	15:a81a8d6c1dfe	852	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	853	*/
mbed_official	15:a81a8d6c1dfe	854	static inline void system_clock_source_dfll_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	855	struct system_clock_source_dfll_config *const config)
mbed_official	15:a81a8d6c1dfe	856	{
mbed_official	15:a81a8d6c1dfe	857	Assert(config);
mbed_official	15:a81a8d6c1dfe	858
mbed_official	15:a81a8d6c1dfe	859	config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
mbed_official	15:a81a8d6c1dfe	860	config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
mbed_official	15:a81a8d6c1dfe	861	config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
mbed_official	15:a81a8d6c1dfe	862	config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
mbed_official	15:a81a8d6c1dfe	863	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
mbed_official	15:a81a8d6c1dfe	864	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	865
mbed_official	15:a81a8d6c1dfe	866	/* Open loop mode calibration value */
mbed_official	15:a81a8d6c1dfe	867	config->coarse_value = 0x1f / 4; /* Midpoint */
mbed_official	15:a81a8d6c1dfe	868	config->fine_value = 0xff / 4; /* Midpoint */
mbed_official	15:a81a8d6c1dfe	869
mbed_official	15:a81a8d6c1dfe	870	/* Closed loop mode */
mbed_official	15:a81a8d6c1dfe	871	config->coarse_max_step = 1;
mbed_official	15:a81a8d6c1dfe	872	config->fine_max_step = 1;
mbed_official	15:a81a8d6c1dfe	873	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
mbed_official	15:a81a8d6c1dfe	874	}
mbed_official	15:a81a8d6c1dfe	875
mbed_official	15:a81a8d6c1dfe	876	void system_clock_source_dfll_set_config(
mbed_official	15:a81a8d6c1dfe	877	struct system_clock_source_dfll_config *const config);
mbed_official	15:a81a8d6c1dfe	878
mbed_official	15:a81a8d6c1dfe	879	/**
mbed_official	15:a81a8d6c1dfe	880	* @}
mbed_official	15:a81a8d6c1dfe	881	*/
mbed_official	15:a81a8d6c1dfe	882
mbed_official	15:a81a8d6c1dfe	883	/**
mbed_official	15:a81a8d6c1dfe	884	* \name Clock Source Management
mbed_official	15:a81a8d6c1dfe	885	* @{
mbed_official	15:a81a8d6c1dfe	886	*/
mbed_official	15:a81a8d6c1dfe	887	enum status_code system_clock_source_write_calibration(
mbed_official	15:a81a8d6c1dfe	888	const enum system_clock_source system_clock_source,
mbed_official	15:a81a8d6c1dfe	889	const uint16_t calibration_value,
mbed_official	15:a81a8d6c1dfe	890	const uint8_t freq_range);
mbed_official	15:a81a8d6c1dfe	891
mbed_official	15:a81a8d6c1dfe	892	enum status_code system_clock_source_enable(
mbed_official	15:a81a8d6c1dfe	893	const enum system_clock_source system_clock_source);
mbed_official	15:a81a8d6c1dfe	894
mbed_official	15:a81a8d6c1dfe	895	enum status_code system_clock_source_disable(
mbed_official	15:a81a8d6c1dfe	896	const enum system_clock_source clk_source);
mbed_official	15:a81a8d6c1dfe	897
mbed_official	15:a81a8d6c1dfe	898	bool system_clock_source_is_ready(
mbed_official	15:a81a8d6c1dfe	899	const enum system_clock_source clk_source);
mbed_official	15:a81a8d6c1dfe	900
mbed_official	15:a81a8d6c1dfe	901	uint32_t system_clock_source_get_hz(
mbed_official	15:a81a8d6c1dfe	902	const enum system_clock_source clk_source);
mbed_official	15:a81a8d6c1dfe	903
mbed_official	15:a81a8d6c1dfe	904	/**
mbed_official	15:a81a8d6c1dfe	905	* @}
mbed_official	15:a81a8d6c1dfe	906	*/
mbed_official	15:a81a8d6c1dfe	907
mbed_official	15:a81a8d6c1dfe	908	/**
mbed_official	15:a81a8d6c1dfe	909	* \name Main Clock Management
mbed_official	15:a81a8d6c1dfe	910	* @{
mbed_official	15:a81a8d6c1dfe	911	*/
mbed_official	15:a81a8d6c1dfe	912
mbed_official	15:a81a8d6c1dfe	913	/**
mbed_official	15:a81a8d6c1dfe	914	* \brief Set main CPU clock divider.
mbed_official	15:a81a8d6c1dfe	915	*
mbed_official	15:a81a8d6c1dfe	916	* Sets the clock divider used on the main clock to provide the CPU clock.
mbed_official	15:a81a8d6c1dfe	917	*
mbed_official	15:a81a8d6c1dfe	918	* \param[in] divider CPU clock divider to set
mbed_official	15:a81a8d6c1dfe	919	*/
mbed_official	15:a81a8d6c1dfe	920	static inline void system_cpu_clock_set_divider(
mbed_official	15:a81a8d6c1dfe	921	const enum system_main_clock_div divider)
mbed_official	15:a81a8d6c1dfe	922	{
mbed_official	15:a81a8d6c1dfe	923	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
mbed_official	15:a81a8d6c1dfe	924	PM->CPUSEL.reg = (uint32_t)divider;
mbed_official	15:a81a8d6c1dfe	925	}
mbed_official	15:a81a8d6c1dfe	926
mbed_official	15:a81a8d6c1dfe	927	/**
mbed_official	15:a81a8d6c1dfe	928	* \brief Retrieves the current frequency of the CPU core.
mbed_official	15:a81a8d6c1dfe	929	*
mbed_official	15:a81a8d6c1dfe	930	* Retrieves the operating frequency of the CPU core, obtained from the main
mbed_official	15:a81a8d6c1dfe	931	* generic clock and the set CPU bus divider.
mbed_official	15:a81a8d6c1dfe	932	*
mbed_official	15:a81a8d6c1dfe	933	* \return Current CPU frequency in Hz.
mbed_official	15:a81a8d6c1dfe	934	*/
mbed_official	15:a81a8d6c1dfe	935	static inline uint32_t system_cpu_clock_get_hz(void)
mbed_official	15:a81a8d6c1dfe	936	{
mbed_official	15:a81a8d6c1dfe	937	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
mbed_official	15:a81a8d6c1dfe	938	}
mbed_official	15:a81a8d6c1dfe	939
mbed_official	15:a81a8d6c1dfe	940	/**
mbed_official	15:a81a8d6c1dfe	941	* \brief Set APBx clock divider.
mbed_official	15:a81a8d6c1dfe	942	*
mbed_official	15:a81a8d6c1dfe	943	* Set the clock divider used on the main clock to provide the clock for the
mbed_official	15:a81a8d6c1dfe	944	* given APBx bus.
mbed_official	15:a81a8d6c1dfe	945	*
mbed_official	15:a81a8d6c1dfe	946	* \param[in] divider APBx bus divider to set
mbed_official	15:a81a8d6c1dfe	947	* \param[in] bus APBx bus to set divider
mbed_official	15:a81a8d6c1dfe	948	*
mbed_official	15:a81a8d6c1dfe	949	* \returns Status of the clock division change operation.
mbed_official	15:a81a8d6c1dfe	950	*
mbed_official	15:a81a8d6c1dfe	951	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
mbed_official	15:a81a8d6c1dfe	952	* \retval STATUS_OK The APBx clock was set successfully
mbed_official	15:a81a8d6c1dfe	953	*/
mbed_official	15:a81a8d6c1dfe	954	static inline enum status_code system_apb_clock_set_divider(
mbed_official	15:a81a8d6c1dfe	955	const enum system_clock_apb_bus bus,
mbed_official	15:a81a8d6c1dfe	956	const enum system_main_clock_div divider)
mbed_official	15:a81a8d6c1dfe	957	{
mbed_official	15:a81a8d6c1dfe	958	switch (bus) {
mbed_official	15:a81a8d6c1dfe	959	case SYSTEM_CLOCK_APB_APBA:
mbed_official	15:a81a8d6c1dfe	960	PM->APBASEL.reg = (uint32_t)divider;
mbed_official	15:a81a8d6c1dfe	961	break;
mbed_official	15:a81a8d6c1dfe	962	case SYSTEM_CLOCK_APB_APBB:
mbed_official	15:a81a8d6c1dfe	963	PM->APBBSEL.reg = (uint32_t)divider;
mbed_official	15:a81a8d6c1dfe	964	break;
mbed_official	15:a81a8d6c1dfe	965	case SYSTEM_CLOCK_APB_APBC:
mbed_official	15:a81a8d6c1dfe	966	PM->APBCSEL.reg = (uint32_t)divider;
mbed_official	15:a81a8d6c1dfe	967	break;
mbed_official	15:a81a8d6c1dfe	968	default:
mbed_official	15:a81a8d6c1dfe	969	Assert(false);
mbed_official	15:a81a8d6c1dfe	970	return STATUS_ERR_INVALID_ARG;
mbed_official	15:a81a8d6c1dfe	971	}
mbed_official	15:a81a8d6c1dfe	972
mbed_official	15:a81a8d6c1dfe	973	return STATUS_OK;
mbed_official	15:a81a8d6c1dfe	974	}
mbed_official	15:a81a8d6c1dfe	975
mbed_official	15:a81a8d6c1dfe	976	/**
mbed_official	15:a81a8d6c1dfe	977	* \brief Retrieves the current frequency of a ABPx.
mbed_official	15:a81a8d6c1dfe	978	*
mbed_official	15:a81a8d6c1dfe	979	* Retrieves the operating frequency of an APBx bus, obtained from the main
mbed_official	15:a81a8d6c1dfe	980	* generic clock and the set APBx bus divider.
mbed_official	15:a81a8d6c1dfe	981	*
mbed_official	15:a81a8d6c1dfe	982	* \return Current APBx bus frequency in Hz.
mbed_official	15:a81a8d6c1dfe	983	*/
mbed_official	15:a81a8d6c1dfe	984	static inline uint32_t system_apb_clock_get_hz(
mbed_official	15:a81a8d6c1dfe	985	const enum system_clock_apb_bus bus)
mbed_official	15:a81a8d6c1dfe	986	{
mbed_official	15:a81a8d6c1dfe	987	uint16_t bus_divider = 0;
mbed_official	15:a81a8d6c1dfe	988
mbed_official	15:a81a8d6c1dfe	989	switch (bus) {
mbed_official	15:a81a8d6c1dfe	990	case SYSTEM_CLOCK_APB_APBA:
mbed_official	15:a81a8d6c1dfe	991	bus_divider = PM->APBASEL.reg;
mbed_official	15:a81a8d6c1dfe	992	break;
mbed_official	15:a81a8d6c1dfe	993	case SYSTEM_CLOCK_APB_APBB:
mbed_official	15:a81a8d6c1dfe	994	bus_divider = PM->APBBSEL.reg;
mbed_official	15:a81a8d6c1dfe	995	break;
mbed_official	15:a81a8d6c1dfe	996	case SYSTEM_CLOCK_APB_APBC:
mbed_official	15:a81a8d6c1dfe	997	bus_divider = PM->APBCSEL.reg;
mbed_official	15:a81a8d6c1dfe	998	break;
mbed_official	15:a81a8d6c1dfe	999	default:
mbed_official	15:a81a8d6c1dfe	1000	Assert(false);
mbed_official	15:a81a8d6c1dfe	1001	return 0;
mbed_official	15:a81a8d6c1dfe	1002	}
mbed_official	15:a81a8d6c1dfe	1003
mbed_official	15:a81a8d6c1dfe	1004	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
mbed_official	15:a81a8d6c1dfe	1005	}
mbed_official	15:a81a8d6c1dfe	1006
mbed_official	15:a81a8d6c1dfe	1007
mbed_official	15:a81a8d6c1dfe	1008	/**
mbed_official	15:a81a8d6c1dfe	1009	* @}
mbed_official	15:a81a8d6c1dfe	1010	*/
mbed_official	15:a81a8d6c1dfe	1011
mbed_official	15:a81a8d6c1dfe	1012	/**
mbed_official	15:a81a8d6c1dfe	1013	* \name Bus Clock Masking
mbed_official	15:a81a8d6c1dfe	1014	* @{
mbed_official	15:a81a8d6c1dfe	1015	*/
mbed_official	15:a81a8d6c1dfe	1016
mbed_official	15:a81a8d6c1dfe	1017	/**
mbed_official	15:a81a8d6c1dfe	1018	* \brief Set bits in the clock mask for the AHB bus.
mbed_official	15:a81a8d6c1dfe	1019	*
mbed_official	15:a81a8d6c1dfe	1020	* This function will set bits in the clock mask for the AHB bus.
mbed_official	15:a81a8d6c1dfe	1021	* Any bits set to 1 will enable that clock, 0 bits in the mask
mbed_official	15:a81a8d6c1dfe	1022	* will be ignored.
mbed_official	15:a81a8d6c1dfe	1023	*
mbed_official	15:a81a8d6c1dfe	1024	* \param[in] ahb_mask AHB clock mask to enable
mbed_official	15:a81a8d6c1dfe	1025	*/
mbed_official	15:a81a8d6c1dfe	1026	static inline void system_ahb_clock_set_mask(
mbed_official	15:a81a8d6c1dfe	1027	const uint32_t ahb_mask)
mbed_official	15:a81a8d6c1dfe	1028	{
mbed_official	15:a81a8d6c1dfe	1029	PM->AHBMASK.reg \|= ahb_mask;
mbed_official	15:a81a8d6c1dfe	1030	}
mbed_official	15:a81a8d6c1dfe	1031
mbed_official	15:a81a8d6c1dfe	1032	/**
mbed_official	15:a81a8d6c1dfe	1033	* \brief Clear bits in the clock mask for the AHB bus.
mbed_official	15:a81a8d6c1dfe	1034	*
mbed_official	15:a81a8d6c1dfe	1035	* This function will clear bits in the clock mask for the AHB bus.
mbed_official	15:a81a8d6c1dfe	1036	* Any bits set to 1 will disable that clock, 0 bits in the mask
mbed_official	15:a81a8d6c1dfe	1037	* will be ignored.
mbed_official	15:a81a8d6c1dfe	1038	*
mbed_official	15:a81a8d6c1dfe	1039	* \param[in] ahb_mask AHB clock mask to disable
mbed_official	15:a81a8d6c1dfe	1040	*/
mbed_official	15:a81a8d6c1dfe	1041	static inline void system_ahb_clock_clear_mask(
mbed_official	15:a81a8d6c1dfe	1042	const uint32_t ahb_mask)
mbed_official	15:a81a8d6c1dfe	1043	{
mbed_official	15:a81a8d6c1dfe	1044	PM->AHBMASK.reg &= ~ahb_mask;
mbed_official	15:a81a8d6c1dfe	1045	}
mbed_official	15:a81a8d6c1dfe	1046
mbed_official	15:a81a8d6c1dfe	1047	/**
mbed_official	15:a81a8d6c1dfe	1048	* \brief Set bits in the clock mask for an APBx bus.
mbed_official	15:a81a8d6c1dfe	1049	*
mbed_official	15:a81a8d6c1dfe	1050	* This function will set bits in the clock mask for an APBx bus.
mbed_official	15:a81a8d6c1dfe	1051	* Any bits set to 1 will enable the corresponding module clock, zero bits in
mbed_official	15:a81a8d6c1dfe	1052	* the mask will be ignored.
mbed_official	15:a81a8d6c1dfe	1053	*
mbed_official	15:a81a8d6c1dfe	1054	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	15:a81a8d6c1dfe	1055	* the device header files
mbed_official	15:a81a8d6c1dfe	1056	* \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
mbed_official	15:a81a8d6c1dfe	1057	* constants from the device header files
mbed_official	15:a81a8d6c1dfe	1058	*
mbed_official	15:a81a8d6c1dfe	1059	* \returns Status indicating the result of the clock mask change operation.
mbed_official	15:a81a8d6c1dfe	1060	*
mbed_official	15:a81a8d6c1dfe	1061	* \retval STATUS_ERR_INVALID_ARG Invalid bus given
mbed_official	15:a81a8d6c1dfe	1062	* \retval STATUS_OK The clock mask was set successfully
mbed_official	15:a81a8d6c1dfe	1063	*/
mbed_official	15:a81a8d6c1dfe	1064	static inline enum status_code system_apb_clock_set_mask(
mbed_official	15:a81a8d6c1dfe	1065	const enum system_clock_apb_bus bus,
mbed_official	15:a81a8d6c1dfe	1066	const uint32_t mask)
mbed_official	15:a81a8d6c1dfe	1067	{
mbed_official	15:a81a8d6c1dfe	1068	switch (bus) {
mbed_official	15:a81a8d6c1dfe	1069	case SYSTEM_CLOCK_APB_APBA:
mbed_official	15:a81a8d6c1dfe	1070	PM->APBAMASK.reg \|= mask;
mbed_official	15:a81a8d6c1dfe	1071	break;
mbed_official	15:a81a8d6c1dfe	1072
mbed_official	15:a81a8d6c1dfe	1073	case SYSTEM_CLOCK_APB_APBB:
mbed_official	15:a81a8d6c1dfe	1074	PM->APBBMASK.reg \|= mask;
mbed_official	15:a81a8d6c1dfe	1075	break;
mbed_official	15:a81a8d6c1dfe	1076
mbed_official	15:a81a8d6c1dfe	1077	case SYSTEM_CLOCK_APB_APBC:
mbed_official	15:a81a8d6c1dfe	1078	PM->APBCMASK.reg \|= mask;
mbed_official	15:a81a8d6c1dfe	1079	break;
mbed_official	15:a81a8d6c1dfe	1080
mbed_official	15:a81a8d6c1dfe	1081	default:
mbed_official	15:a81a8d6c1dfe	1082	Assert(false);
mbed_official	15:a81a8d6c1dfe	1083	return STATUS_ERR_INVALID_ARG;
mbed_official	15:a81a8d6c1dfe	1084
mbed_official	15:a81a8d6c1dfe	1085	}
mbed_official	15:a81a8d6c1dfe	1086
mbed_official	15:a81a8d6c1dfe	1087	return STATUS_OK;
mbed_official	15:a81a8d6c1dfe	1088	}
mbed_official	15:a81a8d6c1dfe	1089
mbed_official	15:a81a8d6c1dfe	1090	/**
mbed_official	15:a81a8d6c1dfe	1091	* \brief Clear bits in the clock mask for an APBx bus.
mbed_official	15:a81a8d6c1dfe	1092	*
mbed_official	15:a81a8d6c1dfe	1093	* This function will clear bits in the clock mask for an APBx bus.
mbed_official	15:a81a8d6c1dfe	1094	* Any bits set to 1 will disable the corresponding module clock, zero bits in
mbed_official	15:a81a8d6c1dfe	1095	* the mask will be ignored.
mbed_official	15:a81a8d6c1dfe	1096	*
mbed_official	15:a81a8d6c1dfe	1097	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	15:a81a8d6c1dfe	1098	* the device header files
mbed_official	15:a81a8d6c1dfe	1099	* \param[in] bus Bus to clear clock mask bits
mbed_official	15:a81a8d6c1dfe	1100	*
mbed_official	15:a81a8d6c1dfe	1101	* \returns Status indicating the result of the clock mask change operation.
mbed_official	15:a81a8d6c1dfe	1102	*
mbed_official	15:a81a8d6c1dfe	1103	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
mbed_official	15:a81a8d6c1dfe	1104	* \retval STATUS_OK The clock mask was changed successfully
mbed_official	15:a81a8d6c1dfe	1105	*/
mbed_official	15:a81a8d6c1dfe	1106	static inline enum status_code system_apb_clock_clear_mask(
mbed_official	15:a81a8d6c1dfe	1107	const enum system_clock_apb_bus bus,
mbed_official	15:a81a8d6c1dfe	1108	const uint32_t mask)
mbed_official	15:a81a8d6c1dfe	1109	{
mbed_official	15:a81a8d6c1dfe	1110	switch (bus) {
mbed_official	15:a81a8d6c1dfe	1111	case SYSTEM_CLOCK_APB_APBA:
mbed_official	15:a81a8d6c1dfe	1112	PM->APBAMASK.reg &= ~mask;
mbed_official	15:a81a8d6c1dfe	1113	break;
mbed_official	15:a81a8d6c1dfe	1114
mbed_official	15:a81a8d6c1dfe	1115	case SYSTEM_CLOCK_APB_APBB:
mbed_official	15:a81a8d6c1dfe	1116	PM->APBBMASK.reg &= ~mask;
mbed_official	15:a81a8d6c1dfe	1117	break;
mbed_official	15:a81a8d6c1dfe	1118
mbed_official	15:a81a8d6c1dfe	1119	case SYSTEM_CLOCK_APB_APBC:
mbed_official	15:a81a8d6c1dfe	1120	PM->APBCMASK.reg &= ~mask;
mbed_official	15:a81a8d6c1dfe	1121	break;
mbed_official	15:a81a8d6c1dfe	1122
mbed_official	15:a81a8d6c1dfe	1123	default:
mbed_official	15:a81a8d6c1dfe	1124	Assert(false);
mbed_official	15:a81a8d6c1dfe	1125	return STATUS_ERR_INVALID_ARG;
mbed_official	15:a81a8d6c1dfe	1126	}
mbed_official	15:a81a8d6c1dfe	1127
mbed_official	15:a81a8d6c1dfe	1128	return STATUS_OK;
mbed_official	15:a81a8d6c1dfe	1129	}
mbed_official	15:a81a8d6c1dfe	1130
mbed_official	15:a81a8d6c1dfe	1131	/**
mbed_official	15:a81a8d6c1dfe	1132	* @}
mbed_official	15:a81a8d6c1dfe	1133	*/
mbed_official	15:a81a8d6c1dfe	1134
mbed_official	15:a81a8d6c1dfe	1135	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	15:a81a8d6c1dfe	1136	/**
mbed_official	15:a81a8d6c1dfe	1137	* \brief Reference clock source of the DPLL module.
mbed_official	15:a81a8d6c1dfe	1138	*/
mbed_official	15:a81a8d6c1dfe	1139	enum system_clock_source_dpll_reference_clock {
mbed_official	15:a81a8d6c1dfe	1140	/** Select XOSC32K as clock reference. */
mbed_official	15:a81a8d6c1dfe	1141	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
mbed_official	15:a81a8d6c1dfe	1142	/** Select XOSC as clock reference. */
mbed_official	15:a81a8d6c1dfe	1143	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
mbed_official	15:a81a8d6c1dfe	1144	/** Select GCLK as clock reference. */
mbed_official	15:a81a8d6c1dfe	1145	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
mbed_official	15:a81a8d6c1dfe	1146	};
mbed_official	15:a81a8d6c1dfe	1147
mbed_official	15:a81a8d6c1dfe	1148	/**
mbed_official	15:a81a8d6c1dfe	1149	* \brief Lock time-out value of the DPLL module.
mbed_official	15:a81a8d6c1dfe	1150	*/
mbed_official	15:a81a8d6c1dfe	1151	enum system_clock_source_dpll_lock_time {
mbed_official	15:a81a8d6c1dfe	1152	/** Set no time-out as default. */
mbed_official	15:a81a8d6c1dfe	1153	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
mbed_official	15:a81a8d6c1dfe	1154	/** Set time-out if no lock within 8ms. */
mbed_official	15:a81a8d6c1dfe	1155	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
mbed_official	15:a81a8d6c1dfe	1156	/** Set time-out if no lock within 9ms. */
mbed_official	15:a81a8d6c1dfe	1157	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
mbed_official	15:a81a8d6c1dfe	1158	/** Set time-out if no lock within 10ms. */
mbed_official	15:a81a8d6c1dfe	1159	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
mbed_official	15:a81a8d6c1dfe	1160	/** Set time-out if no lock within 11ms. */
mbed_official	15:a81a8d6c1dfe	1161	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
mbed_official	15:a81a8d6c1dfe	1162	};
mbed_official	15:a81a8d6c1dfe	1163
mbed_official	15:a81a8d6c1dfe	1164	/**
mbed_official	15:a81a8d6c1dfe	1165	* \brief Filter type of the DPLL module.
mbed_official	15:a81a8d6c1dfe	1166	*/
mbed_official	15:a81a8d6c1dfe	1167	enum system_clock_source_dpll_filter {
mbed_official	15:a81a8d6c1dfe	1168	/** Default filter mode. */
mbed_official	15:a81a8d6c1dfe	1169	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
mbed_official	15:a81a8d6c1dfe	1170	/** Low bandwidth filter. */
mbed_official	15:a81a8d6c1dfe	1171	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
mbed_official	15:a81a8d6c1dfe	1172	/** High bandwidth filter. */
mbed_official	15:a81a8d6c1dfe	1173	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
mbed_official	15:a81a8d6c1dfe	1174	/** High damping filter. */
mbed_official	15:a81a8d6c1dfe	1175	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
mbed_official	15:a81a8d6c1dfe	1176	};
mbed_official	15:a81a8d6c1dfe	1177
mbed_official	15:a81a8d6c1dfe	1178	/**
mbed_official	15:a81a8d6c1dfe	1179	* \brief Configuration structure for DPLL.
mbed_official	15:a81a8d6c1dfe	1180	*
mbed_official	15:a81a8d6c1dfe	1181	* DPLL oscillator configuration structure.
mbed_official	15:a81a8d6c1dfe	1182	*/
mbed_official	15:a81a8d6c1dfe	1183	struct system_clock_source_dpll_config {
mbed_official	15:a81a8d6c1dfe	1184	/** Run On Demand. If this is set the DPLL won't run
mbed_official	15:a81a8d6c1dfe	1185	* until requested by a peripheral. */
mbed_official	15:a81a8d6c1dfe	1186	bool on_demand;
mbed_official	15:a81a8d6c1dfe	1187	/** Keep the DPLL enabled in standby sleep mode. */
mbed_official	15:a81a8d6c1dfe	1188	bool run_in_standby;
mbed_official	15:a81a8d6c1dfe	1189	/** Bypass lock signal. */
mbed_official	15:a81a8d6c1dfe	1190	bool lock_bypass;
mbed_official	15:a81a8d6c1dfe	1191	/** Wake up fast. If this is set DPLL output clock is enabled after
mbed_official	15:a81a8d6c1dfe	1192	* the startup time. */
mbed_official	15:a81a8d6c1dfe	1193	bool wake_up_fast;
mbed_official	15:a81a8d6c1dfe	1194	/** Enable low power mode. */
mbed_official	15:a81a8d6c1dfe	1195	bool low_power_enable;
mbed_official	15:a81a8d6c1dfe	1196
mbed_official	15:a81a8d6c1dfe	1197	/** Output frequency of the clock. */
mbed_official	15:a81a8d6c1dfe	1198	uint32_t output_frequency;
mbed_official	15:a81a8d6c1dfe	1199	/** Reference frequency of the clock. */
mbed_official	15:a81a8d6c1dfe	1200	uint32_t reference_frequency;
mbed_official	15:a81a8d6c1dfe	1201	/** Devider of reference clock. */
mbed_official	15:a81a8d6c1dfe	1202	uint16_t reference_divider;
mbed_official	15:a81a8d6c1dfe	1203
mbed_official	15:a81a8d6c1dfe	1204	/** Filter type of the DPLL module. */
mbed_official	15:a81a8d6c1dfe	1205	enum system_clock_source_dpll_filter filter;
mbed_official	15:a81a8d6c1dfe	1206	/** Lock time-out value of the DPLL module. */
mbed_official	15:a81a8d6c1dfe	1207	enum system_clock_source_dpll_lock_time lock_time;
mbed_official	15:a81a8d6c1dfe	1208	/** Reference clock source of the DPLL module. */
mbed_official	15:a81a8d6c1dfe	1209	enum system_clock_source_dpll_reference_clock reference_clock;
mbed_official	15:a81a8d6c1dfe	1210	};
mbed_official	15:a81a8d6c1dfe	1211
mbed_official	15:a81a8d6c1dfe	1212	/**
mbed_official	15:a81a8d6c1dfe	1213	* \name Internal DPLL Management
mbed_official	15:a81a8d6c1dfe	1214	* @{
mbed_official	15:a81a8d6c1dfe	1215	*/
mbed_official	15:a81a8d6c1dfe	1216
mbed_official	15:a81a8d6c1dfe	1217	/**
mbed_official	15:a81a8d6c1dfe	1218	* \brief Retrieve the default configuration for DPLL.
mbed_official	15:a81a8d6c1dfe	1219	*
mbed_official	15:a81a8d6c1dfe	1220	* Fills a configuration structure with the default configuration for a
mbed_official	15:a81a8d6c1dfe	1221	* DPLL oscillator module:
mbed_official	15:a81a8d6c1dfe	1222	* - Run only when requested by peripheral (on demand)
mbed_official	15:a81a8d6c1dfe	1223	* - Don't run in STANDBY sleep mode
mbed_official	15:a81a8d6c1dfe	1224	* - Lock bypass disabled
mbed_official	15:a81a8d6c1dfe	1225	* - Fast wake up disabled
mbed_official	15:a81a8d6c1dfe	1226	* - Low power mode disabled
mbed_official	15:a81a8d6c1dfe	1227	* - Output frequency is 48MHz
mbed_official	15:a81a8d6c1dfe	1228	* - Reference clock frequency is 32768Hz
mbed_official	15:a81a8d6c1dfe	1229	* - Not divide reference clock
mbed_official	15:a81a8d6c1dfe	1230	* - Select REF0 as reference clock
mbed_official	15:a81a8d6c1dfe	1231	* - Set lock time to default mode
mbed_official	15:a81a8d6c1dfe	1232	* - Use default filter
mbed_official	15:a81a8d6c1dfe	1233	*
mbed_official	15:a81a8d6c1dfe	1234	* \param[out] config Configuration structure to fill with default values
mbed_official	15:a81a8d6c1dfe	1235	*/
mbed_official	15:a81a8d6c1dfe	1236	static inline void system_clock_source_dpll_get_config_defaults(
mbed_official	15:a81a8d6c1dfe	1237	struct system_clock_source_dpll_config *const config)
mbed_official	15:a81a8d6c1dfe	1238	{
mbed_official	15:a81a8d6c1dfe	1239	config->on_demand = true;
mbed_official	15:a81a8d6c1dfe	1240	config->run_in_standby = false;
mbed_official	15:a81a8d6c1dfe	1241	config->lock_bypass = false;
mbed_official	15:a81a8d6c1dfe	1242	config->wake_up_fast = false;
mbed_official	15:a81a8d6c1dfe	1243	config->low_power_enable = false;
mbed_official	15:a81a8d6c1dfe	1244
mbed_official	15:a81a8d6c1dfe	1245	config->output_frequency = 48000000;
mbed_official	15:a81a8d6c1dfe	1246	config->reference_frequency = 32768;
mbed_official	15:a81a8d6c1dfe	1247	config->reference_divider = 1;
mbed_official	15:a81a8d6c1dfe	1248	config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
mbed_official	15:a81a8d6c1dfe	1249
mbed_official	15:a81a8d6c1dfe	1250	config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
mbed_official	15:a81a8d6c1dfe	1251	config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
mbed_official	15:a81a8d6c1dfe	1252	};
mbed_official	15:a81a8d6c1dfe	1253
mbed_official	15:a81a8d6c1dfe	1254	void system_clock_source_dpll_set_config(
mbed_official	15:a81a8d6c1dfe	1255	struct system_clock_source_dpll_config *const config);
mbed_official	15:a81a8d6c1dfe	1256
mbed_official	15:a81a8d6c1dfe	1257	/* @} */
mbed_official	15:a81a8d6c1dfe	1258	#endif
mbed_official	15:a81a8d6c1dfe	1259
mbed_official	15:a81a8d6c1dfe	1260	/**
mbed_official	15:a81a8d6c1dfe	1261	* \name System Clock Initialization
mbed_official	15:a81a8d6c1dfe	1262	* @{
mbed_official	15:a81a8d6c1dfe	1263	*/
mbed_official	15:a81a8d6c1dfe	1264
mbed_official	15:a81a8d6c1dfe	1265	void system_clock_init(void);
mbed_official	15:a81a8d6c1dfe	1266
mbed_official	15:a81a8d6c1dfe	1267	/**
mbed_official	15:a81a8d6c1dfe	1268	* @}
mbed_official	15:a81a8d6c1dfe	1269	*/
mbed_official	15:a81a8d6c1dfe	1270
mbed_official	15:a81a8d6c1dfe	1271	/**
mbed_official	15:a81a8d6c1dfe	1272	* \name System Flash Wait States
mbed_official	15:a81a8d6c1dfe	1273	* @{
mbed_official	15:a81a8d6c1dfe	1274	*/
mbed_official	15:a81a8d6c1dfe	1275
mbed_official	15:a81a8d6c1dfe	1276	/**
mbed_official	15:a81a8d6c1dfe	1277	* \brief Set flash controller wait states.
mbed_official	15:a81a8d6c1dfe	1278	*
mbed_official	15:a81a8d6c1dfe	1279	* Will set the number of wait states that are used by the onboard
mbed_official	15:a81a8d6c1dfe	1280	* flash memory. The number of wait states depend on both device
mbed_official	15:a81a8d6c1dfe	1281	* supply voltage and CPU speed. The required number of wait states
mbed_official	15:a81a8d6c1dfe	1282	* can be found in the electrical characteristics of the device.
mbed_official	15:a81a8d6c1dfe	1283	*
mbed_official	15:a81a8d6c1dfe	1284	* \param[in] wait_states Number of wait states to use for internal flash
mbed_official	15:a81a8d6c1dfe	1285	*/
mbed_official	15:a81a8d6c1dfe	1286	static inline void system_flash_set_waitstates(uint8_t wait_states)
mbed_official	15:a81a8d6c1dfe	1287	{
mbed_official	15:a81a8d6c1dfe	1288	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
mbed_official	15:a81a8d6c1dfe	1289	((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
mbed_official	15:a81a8d6c1dfe	1290
mbed_official	15:a81a8d6c1dfe	1291	NVMCTRL->CTRLB.bit.RWS = wait_states;
mbed_official	15:a81a8d6c1dfe	1292	}
mbed_official	15:a81a8d6c1dfe	1293	/**
mbed_official	15:a81a8d6c1dfe	1294	* @}
mbed_official	15:a81a8d6c1dfe	1295	*/
mbed_official	15:a81a8d6c1dfe	1296
mbed_official	15:a81a8d6c1dfe	1297	/**
mbed_official	15:a81a8d6c1dfe	1298	* @}
mbed_official	15:a81a8d6c1dfe	1299	*/
mbed_official	15:a81a8d6c1dfe	1300
mbed_official	15:a81a8d6c1dfe	1301	/**
mbed_official	15:a81a8d6c1dfe	1302	* \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
mbed_official	15:a81a8d6c1dfe	1303	*
mbed_official	15:a81a8d6c1dfe	1304	* \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
mbed_official	15:a81a8d6c1dfe	1305	* Below is a table listing the acronyms used in this module, along with their
mbed_official	15:a81a8d6c1dfe	1306	* intended meanings.
mbed_official	15:a81a8d6c1dfe	1307	*
mbed_official	15:a81a8d6c1dfe	1308	* <table>
mbed_official	15:a81a8d6c1dfe	1309	* <tr>
mbed_official	15:a81a8d6c1dfe	1310	* <th>Acronym</th>
mbed_official	15:a81a8d6c1dfe	1311	* <th>Description</th>
mbed_official	15:a81a8d6c1dfe	1312	* </tr>
mbed_official	15:a81a8d6c1dfe	1313	* <tr>
mbed_official	15:a81a8d6c1dfe	1314	* <td>DFLL</td>
mbed_official	15:a81a8d6c1dfe	1315	* <td>Digital Frequency Locked Loop</td>
mbed_official	15:a81a8d6c1dfe	1316	* </tr>
mbed_official	15:a81a8d6c1dfe	1317	* <tr>
mbed_official	15:a81a8d6c1dfe	1318	* <td>MUX</td>
mbed_official	15:a81a8d6c1dfe	1319	* <td>Multiplexer</td>
mbed_official	15:a81a8d6c1dfe	1320	* </tr>
mbed_official	15:a81a8d6c1dfe	1321	* <tr>
mbed_official	15:a81a8d6c1dfe	1322	* <td>OSC32K</td>
mbed_official	15:a81a8d6c1dfe	1323	* <td>Internal 32KHz Oscillator</td>
mbed_official	15:a81a8d6c1dfe	1324	* </tr>
mbed_official	15:a81a8d6c1dfe	1325	* <tr>
mbed_official	15:a81a8d6c1dfe	1326	* <td>OSC8M</td>
mbed_official	15:a81a8d6c1dfe	1327	* <td>Internal 8MHz Oscillator</td>
mbed_official	15:a81a8d6c1dfe	1328	* </tr>
mbed_official	15:a81a8d6c1dfe	1329	* <tr>
mbed_official	15:a81a8d6c1dfe	1330	* <td>PLL</td>
mbed_official	15:a81a8d6c1dfe	1331	* <td>Phase Locked Loop</td>
mbed_official	15:a81a8d6c1dfe	1332	* </tr>
mbed_official	15:a81a8d6c1dfe	1333	* <tr>
mbed_official	15:a81a8d6c1dfe	1334	* <td>OSC</td>
mbed_official	15:a81a8d6c1dfe	1335	* <td>Oscillator</td>
mbed_official	15:a81a8d6c1dfe	1336	* </tr>
mbed_official	15:a81a8d6c1dfe	1337	* <tr>
mbed_official	15:a81a8d6c1dfe	1338	* <td>XOSC</td>
mbed_official	15:a81a8d6c1dfe	1339	* <td>External Oscillator</td>
mbed_official	15:a81a8d6c1dfe	1340	* </tr>
mbed_official	15:a81a8d6c1dfe	1341	* <tr>
mbed_official	15:a81a8d6c1dfe	1342	* <td>XOSC32K</td>
mbed_official	15:a81a8d6c1dfe	1343	* <td>External 32KHz Oscillator</td>
mbed_official	15:a81a8d6c1dfe	1344	* </tr>
mbed_official	15:a81a8d6c1dfe	1345	* <tr>
mbed_official	15:a81a8d6c1dfe	1346	* <td>AHB</td>
mbed_official	15:a81a8d6c1dfe	1347	* <td>Advanced High-performance Bus</td>
mbed_official	15:a81a8d6c1dfe	1348	* </tr>
mbed_official	15:a81a8d6c1dfe	1349	* <tr>
mbed_official	15:a81a8d6c1dfe	1350	* <td>APB</td>
mbed_official	15:a81a8d6c1dfe	1351	* <td>Advanced Peripheral Bus</td>
mbed_official	15:a81a8d6c1dfe	1352	* </tr>
mbed_official	15:a81a8d6c1dfe	1353	* <tr>
mbed_official	15:a81a8d6c1dfe	1354	* <td>DPLL</td>
mbed_official	15:a81a8d6c1dfe	1355	* <td>Digital Phase Locked Loop</td>
mbed_official	15:a81a8d6c1dfe	1356	* </tr>
mbed_official	15:a81a8d6c1dfe	1357	* </table>
mbed_official	15:a81a8d6c1dfe	1358	*
mbed_official	15:a81a8d6c1dfe	1359	*
mbed_official	15:a81a8d6c1dfe	1360	* \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
mbed_official	15:a81a8d6c1dfe	1361	* This driver has the following dependencies:
mbed_official	15:a81a8d6c1dfe	1362	*
mbed_official	15:a81a8d6c1dfe	1363	* - None
mbed_official	15:a81a8d6c1dfe	1364	*
mbed_official	15:a81a8d6c1dfe	1365	*
mbed_official	15:a81a8d6c1dfe	1366	* \section asfdoc_sam0_system_clock_extra_errata Errata
mbed_official	15:a81a8d6c1dfe	1367	*
mbed_official	15:a81a8d6c1dfe	1368	* - This driver implements experimental workaround for errata 9905
mbed_official	15:a81a8d6c1dfe	1369	*
mbed_official	15:a81a8d6c1dfe	1370	* "The DFLL clock must be requested before being configured otherwise a
mbed_official	15:a81a8d6c1dfe	1371	* write access to a DFLL register can freeze the device."
mbed_official	15:a81a8d6c1dfe	1372	* This driver will enable and configure the DFLL before the ONDEMAND bit is set.
mbed_official	15:a81a8d6c1dfe	1373	*
mbed_official	15:a81a8d6c1dfe	1374	*
mbed_official	15:a81a8d6c1dfe	1375	* \section asfdoc_sam0_system_clock_extra_history Module History
mbed_official	15:a81a8d6c1dfe	1376	* An overview of the module history is presented in the table below, with
mbed_official	15:a81a8d6c1dfe	1377	* details on the enhancements and fixes made to the module since its first
mbed_official	15:a81a8d6c1dfe	1378	* release. The current version of this corresponds to the newest version in
mbed_official	15:a81a8d6c1dfe	1379	* the table.
mbed_official	15:a81a8d6c1dfe	1380	*
mbed_official	15:a81a8d6c1dfe	1381	* <table>
mbed_official	15:a81a8d6c1dfe	1382	* <tr>
mbed_official	15:a81a8d6c1dfe	1383	* <th>Changelog</th>
mbed_official	15:a81a8d6c1dfe	1384	* </tr>
mbed_official	15:a81a8d6c1dfe	1385	* <tr>
mbed_official	15:a81a8d6c1dfe	1386	* <td>
mbed_official	15:a81a8d6c1dfe	1387	* \li Corrected OSC32K startup time definitions
mbed_official	15:a81a8d6c1dfe	1388	* \li Support locking of OSC32K and XOSC32K config register (default: false)
mbed_official	15:a81a8d6c1dfe	1389	* \li Added DPLL support, functions added:
mbed_official	15:a81a8d6c1dfe	1390	* \c system_clock_source_dpll_get_config_defaults() and
mbed_official	15:a81a8d6c1dfe	1391	* \c system_clock_source_dpll_set_config()
mbed_official	15:a81a8d6c1dfe	1392	* \li Moved gclk channel locking feature out of the config struct
mbed_official	15:a81a8d6c1dfe	1393	* functions added:
mbed_official	15:a81a8d6c1dfe	1394	* \c system_gclk_chan_lock(),
mbed_official	15:a81a8d6c1dfe	1395	* \c system_gclk_chan_is_locked()
mbed_official	15:a81a8d6c1dfe	1396	* \c system_gclk_chan_is_enabled() and
mbed_official	15:a81a8d6c1dfe	1397	* \c system_gclk_gen_is_enabled()
mbed_official	15:a81a8d6c1dfe	1398	* </td>
mbed_official	15:a81a8d6c1dfe	1399	* </tr>
mbed_official	15:a81a8d6c1dfe	1400	* <tr>
mbed_official	15:a81a8d6c1dfe	1401	* <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
mbed_official	15:a81a8d6c1dfe	1402	* and configured to a failed/not running clock generator</td>
mbed_official	15:a81a8d6c1dfe	1403	* </tr>
mbed_official	15:a81a8d6c1dfe	1404	* <tr>
mbed_official	15:a81a8d6c1dfe	1405	* <td>
mbed_official	15:a81a8d6c1dfe	1406	* \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
mbed_official	15:a81a8d6c1dfe	1407	* \li Fixed system_flash_set_waitstates() failing with an assertion
mbed_official	15:a81a8d6c1dfe	1408	* if an odd number of wait states provided
mbed_official	15:a81a8d6c1dfe	1409	* </td>
mbed_official	15:a81a8d6c1dfe	1410	* </tr>
mbed_official	15:a81a8d6c1dfe	1411	* <tr>
mbed_official	15:a81a8d6c1dfe	1412	* <td>
mbed_official	15:a81a8d6c1dfe	1413	* \li Updated dfll configuration function to implement workaround for
mbed_official	15:a81a8d6c1dfe	1414	* errata 9905 in the DFLL module
mbed_official	15:a81a8d6c1dfe	1415	* \li Updated \c system_clock_init() to reset interrupt flags before
mbed_official	15:a81a8d6c1dfe	1416	* they are used
mbed_official	15:a81a8d6c1dfe	1417	* \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
mbed_official	15:a81a8d6c1dfe	1418	* frequency number
mbed_official	15:a81a8d6c1dfe	1419	* </td>
mbed_official	15:a81a8d6c1dfe	1420	* </tr>
mbed_official	15:a81a8d6c1dfe	1421	* <tr>
mbed_official	15:a81a8d6c1dfe	1422	* <td>\li Fixed \c system_clock_source_is_ready not returning the correct
mbed_official	15:a81a8d6c1dfe	1423	* state for \c SYSTEM_CLOCK_SOURCE_OSC8M
mbed_official	15:a81a8d6c1dfe	1424	* \li Renamed the various \c system_clock_source_*_get_default_config()
mbed_official	15:a81a8d6c1dfe	1425	* functions to \c system_clock_source_*_get_config_defaults() to
mbed_official	15:a81a8d6c1dfe	1426	* match the remainder of ASF
mbed_official	15:a81a8d6c1dfe	1427	* \li Added OSC8M calibration constant loading from the device signature
mbed_official	15:a81a8d6c1dfe	1428	* row when the oscillator is initialized
mbed_official	15:a81a8d6c1dfe	1429	* \li Updated default configuration of the XOSC32 to disable Automatic
mbed_official	15:a81a8d6c1dfe	1430	* Gain Control due to silicon errata
mbed_official	15:a81a8d6c1dfe	1431	* </td>
mbed_official	15:a81a8d6c1dfe	1432	* </tr>
mbed_official	15:a81a8d6c1dfe	1433	* <tr>
mbed_official	15:a81a8d6c1dfe	1434	* <td>Initial Release</td>
mbed_official	15:a81a8d6c1dfe	1435	* </tr>
mbed_official	15:a81a8d6c1dfe	1436	* </table>
mbed_official	15:a81a8d6c1dfe	1437	*/
mbed_official	15:a81a8d6c1dfe	1438
mbed_official	15:a81a8d6c1dfe	1439	/**
mbed_official	15:a81a8d6c1dfe	1440	* \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
mbed_official	15:a81a8d6c1dfe	1441	*
mbed_official	15:a81a8d6c1dfe	1442	* This is a list of the available Quick Start guides (QSGs) and example
mbed_official	15:a81a8d6c1dfe	1443	* applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
mbed_official	15:a81a8d6c1dfe	1444	* examples with step-by-step instructions to configure and use this driver in
mbed_official	15:a81a8d6c1dfe	1445	* a selection of use cases. Note that QSGs can be compiled as a standalone
mbed_official	15:a81a8d6c1dfe	1446	* application or be added to the user application.
mbed_official	15:a81a8d6c1dfe	1447	*
mbed_official	15:a81a8d6c1dfe	1448	* - \subpage asfdoc_sam0_system_clock_basic_use_case
mbed_official	15:a81a8d6c1dfe	1449	* - \subpage asfdoc_sam0_system_gclk_basic_use_case
mbed_official	15:a81a8d6c1dfe	1450	*
mbed_official	15:a81a8d6c1dfe	1451	* \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
mbed_official	15:a81a8d6c1dfe	1452	*
mbed_official	15:a81a8d6c1dfe	1453	* <table>
mbed_official	15:a81a8d6c1dfe	1454	* <tr>
mbed_official	15:a81a8d6c1dfe	1455	* <th>Doc. Rev.</td>
mbed_official	15:a81a8d6c1dfe	1456	* <th>Date</td>
mbed_official	15:a81a8d6c1dfe	1457	* <th>Comments</td>
mbed_official	15:a81a8d6c1dfe	1458	* </tr>
mbed_official	15:a81a8d6c1dfe	1459	* <tr>
mbed_official	15:a81a8d6c1dfe	1460	* <td>E</td>
mbed_official	15:a81a8d6c1dfe	1461	* <td>04/2015</td>
mbed_official	15:a81a8d6c1dfe	1462	* <td>Added support for SAMDAx.</td>
mbed_official	15:a81a8d6c1dfe	1463	* </tr>
mbed_official	15:a81a8d6c1dfe	1464	* <tr>
mbed_official	15:a81a8d6c1dfe	1465	* <td>D</td>
mbed_official	15:a81a8d6c1dfe	1466	* <td>12/2014</td>
mbed_official	15:a81a8d6c1dfe	1467	* <td>Added support for SAMR21 and SAMD10/D11.</td>
mbed_official	15:a81a8d6c1dfe	1468	* </tr>
mbed_official	15:a81a8d6c1dfe	1469	* <tr>
mbed_official	15:a81a8d6c1dfe	1470	* <td>C</td>
mbed_official	15:a81a8d6c1dfe	1471	* <td>01/2014</td>
mbed_official	15:a81a8d6c1dfe	1472	* <td>Added support for SAMD21.</td>
mbed_official	15:a81a8d6c1dfe	1473	* </tr>
mbed_official	15:a81a8d6c1dfe	1474	* <tr>
mbed_official	15:a81a8d6c1dfe	1475	* <td>B</td>
mbed_official	15:a81a8d6c1dfe	1476	* <td>06/2013</td>
mbed_official	15:a81a8d6c1dfe	1477	* <td>Corrected documentation typos. Fixed missing steps in the Basic
mbed_official	15:a81a8d6c1dfe	1478	* Use Case Quick Start Guide.</td>
mbed_official	15:a81a8d6c1dfe	1479	* </tr>
mbed_official	15:a81a8d6c1dfe	1480	* <tr>
mbed_official	15:a81a8d6c1dfe	1481	* <td>A</td>
mbed_official	15:a81a8d6c1dfe	1482	* <td>06/2013</td>
mbed_official	15:a81a8d6c1dfe	1483	* <td>Initial release</td>
mbed_official	15:a81a8d6c1dfe	1484	* </tr>
mbed_official	15:a81a8d6c1dfe	1485	* </table>
mbed_official	15:a81a8d6c1dfe	1486	*/
mbed_official	15:a81a8d6c1dfe	1487
mbed_official	15:a81a8d6c1dfe	1488	#ifdef __cplusplus
mbed_official	15:a81a8d6c1dfe	1489	}
mbed_official	15:a81a8d6c1dfe	1490	#endif
mbed_official	15:a81a8d6c1dfe	1491
mbed_official	15:a81a8d6c1dfe	1492	#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */

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Type:	Library
Created:	07 Aug 2016
Imports:	4
Forks:	0
Commits:	145
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targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAMD21/clock_feature.h@18:da299f395b9e, 2015-11-09 (annotated)

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