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targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h@18:da299f395b9e, 2015-11-09 (annotated)

Committer:: mbed_official
Date:: Mon Nov 09 13:30:11 2015 +0000
Revision:: 18:da299f395b9e

Synchronized with git revision f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3

Full URL: https://github.com/mbedmicro/mbed/commit/f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3/

Added support for SAML21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	18:da299f395b9e	1	/**
mbed_official	18:da299f395b9e	2	* \file
mbed_official	18:da299f395b9e	3	*
mbed_official	18:da299f395b9e	4	* \brief SAM L21 Clock Driver
mbed_official	18:da299f395b9e	5	*
mbed_official	18:da299f395b9e	6	* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
mbed_official	18:da299f395b9e	7	*
mbed_official	18:da299f395b9e	8	* \asf_license_start
mbed_official	18:da299f395b9e	9	*
mbed_official	18:da299f395b9e	10	* \page License
mbed_official	18:da299f395b9e	11	*
mbed_official	18:da299f395b9e	12	* Redistribution and use in source and binary forms, with or without
mbed_official	18:da299f395b9e	13	* modification, are permitted provided that the following conditions are met:
mbed_official	18:da299f395b9e	14	*
mbed_official	18:da299f395b9e	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	18:da299f395b9e	16	* this list of conditions and the following disclaimer.
mbed_official	18:da299f395b9e	17	*
mbed_official	18:da299f395b9e	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	18:da299f395b9e	19	* this list of conditions and the following disclaimer in the documentation
mbed_official	18:da299f395b9e	20	* and/or other materials provided with the distribution.
mbed_official	18:da299f395b9e	21	*
mbed_official	18:da299f395b9e	22	* 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official	18:da299f395b9e	23	* from this software without specific prior written permission.
mbed_official	18:da299f395b9e	24	*
mbed_official	18:da299f395b9e	25	* 4. This software may only be redistributed and used in connection with an
mbed_official	18:da299f395b9e	26	* Atmel microcontroller product.
mbed_official	18:da299f395b9e	27	*
mbed_official	18:da299f395b9e	28	* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official	18:da299f395b9e	29	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official	18:da299f395b9e	30	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official	18:da299f395b9e	31	* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official	18:da299f395b9e	32	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	18:da299f395b9e	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official	18:da299f395b9e	34	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official	18:da299f395b9e	35	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official	18:da299f395b9e	36	* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official	18:da299f395b9e	37	* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official	18:da299f395b9e	38	* POSSIBILITY OF SUCH DAMAGE.
mbed_official	18:da299f395b9e	39	*
mbed_official	18:da299f395b9e	40	* \asf_license_stop
mbed_official	18:da299f395b9e	41	*
mbed_official	18:da299f395b9e	42	*/
mbed_official	18:da299f395b9e	43	/*
mbed_official	18:da299f395b9e	44	* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official	18:da299f395b9e	45	*/
mbed_official	18:da299f395b9e	46	#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	18:da299f395b9e	47	#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	18:da299f395b9e	48
mbed_official	18:da299f395b9e	49	#ifdef __cplusplus
mbed_official	18:da299f395b9e	50	extern "C" {
mbed_official	18:da299f395b9e	51	#endif
mbed_official	18:da299f395b9e	52
mbed_official	18:da299f395b9e	53	/**
mbed_official	18:da299f395b9e	54	* \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver
mbed_official	18:da299f395b9e	55	*
mbed_official	18:da299f395b9e	56	* This driver for Atmel® \| SMART ARM®-based microcontrollers provides an interface for the configuration
mbed_official	18:da299f395b9e	57	* and management of the device's clocking related functions. This includes
mbed_official	18:da299f395b9e	58	* the various clock sources, bus clocks, and generic clocks within the device,
mbed_official	18:da299f395b9e	59	* with functions to manage the enabling, disabling, source selection, and
mbed_official	18:da299f395b9e	60	* prescaling of clocks to various internal peripherals.
mbed_official	18:da299f395b9e	61	*
mbed_official	18:da299f395b9e	62	* The following peripherals are used by this module:
mbed_official	18:da299f395b9e	63	*
mbed_official	18:da299f395b9e	64	* - GCLK (Generic Clock Management)
mbed_official	18:da299f395b9e	65	* - PM (Power Management)
mbed_official	18:da299f395b9e	66	* - OSCCTRL (Oscillators Controller)
mbed_official	18:da299f395b9e	67	* - OSC32KCTRL (32K Oscillators Controller)
mbed_official	18:da299f395b9e	68	* - MCLK (Main Clock)
mbed_official	18:da299f395b9e	69	*
mbed_official	18:da299f395b9e	70	* The following devices can use this module:
mbed_official	18:da299f395b9e	71	* - Atmel \| SMART SAM L21
mbed_official	18:da299f395b9e	72	*
mbed_official	18:da299f395b9e	73	* The outline of this documentation is as follows:
mbed_official	18:da299f395b9e	74	* - \ref asfdoc_sam0_system_clock_prerequisites
mbed_official	18:da299f395b9e	75	* - \ref asfdoc_sam0_system_clock_module_overview
mbed_official	18:da299f395b9e	76	* - \ref asfdoc_sam0_system_clock_special_considerations
mbed_official	18:da299f395b9e	77	* - \ref asfdoc_sam0_system_clock_extra_info
mbed_official	18:da299f395b9e	78	* - \ref asfdoc_sam0_system_clock_examples
mbed_official	18:da299f395b9e	79	* - \ref asfdoc_sam0_system_clock_api_overview
mbed_official	18:da299f395b9e	80	*
mbed_official	18:da299f395b9e	81	*
mbed_official	18:da299f395b9e	82	* \section asfdoc_sam0_system_clock_prerequisites Prerequisites
mbed_official	18:da299f395b9e	83	*
mbed_official	18:da299f395b9e	84	* There are no prerequisites for this module.
mbed_official	18:da299f395b9e	85	*
mbed_official	18:da299f395b9e	86	*
mbed_official	18:da299f395b9e	87	* \section asfdoc_sam0_system_clock_module_overview Module Overview
mbed_official	18:da299f395b9e	88	* The SAM devices contain a sophisticated clocking system, which is designed
mbed_official	18:da299f395b9e	89	* to give the maximum flexibility to the user application. This system allows
mbed_official	18:da299f395b9e	90	* a system designer to tune the performance and power consumption of the device
mbed_official	18:da299f395b9e	91	* in a dynamic manner, to achieve the best trade-off between the two for a
mbed_official	18:da299f395b9e	92	* particular application.
mbed_official	18:da299f395b9e	93	*
mbed_official	18:da299f395b9e	94	* This driver provides a set of functions for the configuration and management
mbed_official	18:da299f395b9e	95	* of the various clock related functionalities within the device.
mbed_official	18:da299f395b9e	96	*
mbed_official	18:da299f395b9e	97	*
mbed_official	18:da299f395b9e	98	* \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
mbed_official	18:da299f395b9e	99	* The SAM devices have a number of master clock source modules, each of
mbed_official	18:da299f395b9e	100	* which being capable of producing a stabilized output frequency which can then
mbed_official	18:da299f395b9e	101	* be fed into the various peripherals and modules within the device.
mbed_official	18:da299f395b9e	102	*
mbed_official	18:da299f395b9e	103	* Possible clock source modules include internal R/C oscillators, internal
mbed_official	18:da299f395b9e	104	* DFLL modules, as well as external crystal oscillators and/or clock inputs.
mbed_official	18:da299f395b9e	105	*
mbed_official	18:da299f395b9e	106	* \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
mbed_official	18:da299f395b9e	107	* The CPU and AHB/APBx buses are clocked by the same physical clock source
mbed_official	18:da299f395b9e	108	* (referred in this module as the Main Clock).
mbed_official	18:da299f395b9e	109	* The CPU and bus clocks are divided into a number of clock domains. Each clock domain can
mbed_official	18:da299f395b9e	110	* run at different frequencies.
mbed_official	18:da299f395b9e	111	*
mbed_official	18:da299f395b9e	112	* There are three clock domains:
mbed_official	18:da299f395b9e	113	*
mbed_official	18:da299f395b9e	114	* - CPU Clock Domain
mbed_official	18:da299f395b9e	115	* - Low Power Clock Domain(LP Clock Domain)
mbed_official	18:da299f395b9e	116	* - Backup Clock Domain(BUP Clock Domain)
mbed_official	18:da299f395b9e	117	*
mbed_official	18:da299f395b9e	118	* Each clock domain (CPU, LP, BUP) can be changed on the fly. To ensure
mbed_official	18:da299f395b9e	119	* correct operation, frequencies must be selected so that BUPDIV ≥ LPDIV ≥ HSDIV.
mbed_official	18:da299f395b9e	120	* Also, frequencies must never exceed the specified maximum frequency for each clock domain.
mbed_official	18:da299f395b9e	121	* A module may be connected to several clock domains (for instance, AHB and APB).
mbed_official	18:da299f395b9e	122	*
mbed_official	18:da299f395b9e	123	* The general main clock tree for the CPU and associated buses is shown in
mbed_official	18:da299f395b9e	124	* \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
mbed_official	18:da299f395b9e	125	*
mbed_official	18:da299f395b9e	126	* \anchor asfdoc_sam0_system_clock_module_clock_tree
mbed_official	18:da299f395b9e	127	* \dot
mbed_official	18:da299f395b9e	128	* digraph overview {
mbed_official	18:da299f395b9e	129	* rankdir=LR;
mbed_official	18:da299f395b9e	130	* clk_src [label="Clock Sources", shape=none, height=0];
mbed_official	18:da299f395b9e	131	* node [label="CPU Bus" shape=ellipse] cpu_bus;
mbed_official	18:da299f395b9e	132	* node [label="AHB Bus" shape=ellipse] ahb_bus;
mbed_official	18:da299f395b9e	133	* node [label="APBx Bus" shape=ellipse] apb_bus;
mbed_official	18:da299f395b9e	134	* node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
mbed_official	18:da299f395b9e	135	* node [label="CPU Clock\nPrescaler" shape=square] cpu_prescaler;
mbed_official	18:da299f395b9e	136	* node [label="Low Power Clock\nPrescaler" shape=square] low_power_prescaler;
mbed_official	18:da299f395b9e	137	* node [label="Backup clock\nPrescaler" shape=square] backup_prescaler;
mbed_official	18:da299f395b9e	138	* node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
mbed_official	18:da299f395b9e	139	*
mbed_official	18:da299f395b9e	140	* clk_src -> main_clock_mux;
mbed_official	18:da299f395b9e	141	* main_clock_mux -> main_prescaler;
mbed_official	18:da299f395b9e	142	* main_prescaler -> cpu_prescaler;
mbed_official	18:da299f395b9e	143	* main_prescaler -> low_power_prescaler;
mbed_official	18:da299f395b9e	144	* main_prescaler -> backup_prescaler;
mbed_official	18:da299f395b9e	145	* cpu_prescaler -> cpu_bus;
mbed_official	18:da299f395b9e	146	* cpu_prescaler -> ahb_bus;
mbed_official	18:da299f395b9e	147	* cpu_prescaler -> apb_bus;
mbed_official	18:da299f395b9e	148	* low_power_prescaler -> ahb_bus;
mbed_official	18:da299f395b9e	149	* low_power_prescaler -> apb_bus;
mbed_official	18:da299f395b9e	150	* backup_prescaler -> apb_bus;
mbed_official	18:da299f395b9e	151	* }
mbed_official	18:da299f395b9e	152	* \enddot
mbed_official	18:da299f395b9e	153	*
mbed_official	18:da299f395b9e	154	* \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
mbed_official	18:da299f395b9e	155	* To save power, the input clock to one or more peripherals on the AHB and APBx
mbed_official	18:da299f395b9e	156	* buses can be masked away. When masked, no clock is passed into the module.
mbed_official	18:da299f395b9e	157	* Disabling of clocks of unused modules will prevent all access to the masked
mbed_official	18:da299f395b9e	158	* module, but will reduce the overall device power consumption.
mbed_official	18:da299f395b9e	159	*
mbed_official	18:da299f395b9e	160	* \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
mbed_official	18:da299f395b9e	161	* Within the SAM devices are a number of Generic Clocks; these are used to
mbed_official	18:da299f395b9e	162	* provide clocks to the various peripheral clock domains in the device in a
mbed_official	18:da299f395b9e	163	* standardized manner. One or more master source clocks can be selected as the
mbed_official	18:da299f395b9e	164	* input clock to a Generic Clock Generator, which can prescale down the input
mbed_official	18:da299f395b9e	165	* frequency to a slower rate for use in a peripheral.
mbed_official	18:da299f395b9e	166	*
mbed_official	18:da299f395b9e	167	* Additionally, a number of individually selectable Generic Clock Channels are
mbed_official	18:da299f395b9e	168	* provided, which multiplex and gate the various generator outputs for one or
mbed_official	18:da299f395b9e	169	* more peripherals within the device. This setup allows for a single common
mbed_official	18:da299f395b9e	170	* generator to feed one or more channels, which can then be enabled or disabled
mbed_official	18:da299f395b9e	171	* individually as required.
mbed_official	18:da299f395b9e	172	*
mbed_official	18:da299f395b9e	173	* \anchor asfdoc_sam0_system_clock_module_chain_overview
mbed_official	18:da299f395b9e	174	* \dot
mbed_official	18:da299f395b9e	175	* digraph overview {
mbed_official	18:da299f395b9e	176	* rankdir=LR;
mbed_official	18:da299f395b9e	177	* node [label="Clock\nSource a" shape=square] system_clock_source;
mbed_official	18:da299f395b9e	178	* node [label="Generator n" shape=square] clock_gen;
mbed_official	18:da299f395b9e	179	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	18:da299f395b9e	180	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	18:da299f395b9e	181	* node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	18:da299f395b9e	182	* node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	18:da299f395b9e	183	*
mbed_official	18:da299f395b9e	184	* system_clock_source -> clock_gen;
mbed_official	18:da299f395b9e	185	* clock_gen -> clock_chan0;
mbed_official	18:da299f395b9e	186	* clock_chan0 -> peripheral0;
mbed_official	18:da299f395b9e	187	* clock_gen -> clock_chan1;
mbed_official	18:da299f395b9e	188	* clock_chan1 -> peripheral1;
mbed_official	18:da299f395b9e	189	* }
mbed_official	18:da299f395b9e	190	* \enddot
mbed_official	18:da299f395b9e	191	*
mbed_official	18:da299f395b9e	192	* \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
mbed_official	18:da299f395b9e	193	* An example setup of a complete clock chain within the device is shown in
mbed_official	18:da299f395b9e	194	* \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
mbed_official	18:da299f395b9e	195	*
mbed_official	18:da299f395b9e	196	* \anchor asfdoc_sam0_system_clock_module_chain_example_fig
mbed_official	18:da299f395b9e	197	* \dot
mbed_official	18:da299f395b9e	198	* digraph overview {
mbed_official	18:da299f395b9e	199	* rankdir=LR;
mbed_official	18:da299f395b9e	200	* node [label="External\nOscillator" shape=square] system_clock_source0;
mbed_official	18:da299f395b9e	201	* node [label="Generator 0" shape=square] clock_gen0;
mbed_official	18:da299f395b9e	202	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	18:da299f395b9e	203	* node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	18:da299f395b9e	204	*
mbed_official	18:da299f395b9e	205	* system_clock_source0 -> clock_gen0;
mbed_official	18:da299f395b9e	206	* clock_gen0 -> clock_chan0;
mbed_official	18:da299f395b9e	207	* clock_chan0 -> peripheral0;
mbed_official	18:da299f395b9e	208	* node [label="16MHz R/C\nOscillator (OSC16M)" shape=square fillcolor=white] system_clock_source1;
mbed_official	18:da299f395b9e	209	* node [label="Generator 1" shape=square] clock_gen1;
mbed_official	18:da299f395b9e	210	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	18:da299f395b9e	211	* node [label="Channel z" shape=square] clock_chan2;
mbed_official	18:da299f395b9e	212	* node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	18:da299f395b9e	213	* node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
mbed_official	18:da299f395b9e	214	*
mbed_official	18:da299f395b9e	215	* system_clock_source1 -> clock_gen1;
mbed_official	18:da299f395b9e	216	* clock_gen1 -> clock_chan1;
mbed_official	18:da299f395b9e	217	* clock_gen1 -> clock_chan2;
mbed_official	18:da299f395b9e	218	* clock_chan1 -> peripheral1;
mbed_official	18:da299f395b9e	219	* clock_chan2 -> peripheral2;
mbed_official	18:da299f395b9e	220	* }
mbed_official	18:da299f395b9e	221	* \enddot
mbed_official	18:da299f395b9e	222	*
mbed_official	18:da299f395b9e	223	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
mbed_official	18:da299f395b9e	224	* Each Generic Clock generator within the device can source its input clock
mbed_official	18:da299f395b9e	225	* from one of the provided Source Clocks, and prescale the output for one or
mbed_official	18:da299f395b9e	226	* more Generic Clock Channels in a one-to-many relationship. The generators
mbed_official	18:da299f395b9e	227	* thus allow for several clocks to be generated of different frequencies,
mbed_official	18:da299f395b9e	228	* power usages, and accuracies, which can be turned on and off individually to
mbed_official	18:da299f395b9e	229	* disable the clocks to multiple peripherals as a group.
mbed_official	18:da299f395b9e	230	*
mbed_official	18:da299f395b9e	231	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
mbed_official	18:da299f395b9e	232	* To connect a Generic Clock Generator to a peripheral within the
mbed_official	18:da299f395b9e	233	* device, a Generic Clock Channel is used. Each peripheral or
mbed_official	18:da299f395b9e	234	* peripheral group has an associated Generic Clock Channel, which serves as the
mbed_official	18:da299f395b9e	235	* clock input for the peripheral(s). To supply a clock to the peripheral
mbed_official	18:da299f395b9e	236	* module(s), the associated channel must be connected to a running Generic
mbed_official	18:da299f395b9e	237	* Clock Generator and the channel enabled.
mbed_official	18:da299f395b9e	238	*
mbed_official	18:da299f395b9e	239	* \section asfdoc_sam0_system_clock_special_considerations Special Considerations
mbed_official	18:da299f395b9e	240	*
mbed_official	18:da299f395b9e	241	* There are no special considerations for this module.
mbed_official	18:da299f395b9e	242	*
mbed_official	18:da299f395b9e	243	*
mbed_official	18:da299f395b9e	244	* \section asfdoc_sam0_system_clock_extra_info Extra Information
mbed_official	18:da299f395b9e	245	*
mbed_official	18:da299f395b9e	246	* For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
mbed_official	18:da299f395b9e	247	* - \ref asfdoc_sam0_system_clock_extra_acronyms
mbed_official	18:da299f395b9e	248	* - \ref asfdoc_sam0_system_clock_extra_dependencies
mbed_official	18:da299f395b9e	249	* - \ref asfdoc_sam0_system_clock_extra_errata
mbed_official	18:da299f395b9e	250	* - \ref asfdoc_sam0_system_clock_extra_history
mbed_official	18:da299f395b9e	251	*
mbed_official	18:da299f395b9e	252	*
mbed_official	18:da299f395b9e	253	* \section asfdoc_sam0_system_clock_examples Examples
mbed_official	18:da299f395b9e	254	*
mbed_official	18:da299f395b9e	255	* For a list of examples related to this driver, see
mbed_official	18:da299f395b9e	256	* \ref asfdoc_sam0_system_clock_exqsg.
mbed_official	18:da299f395b9e	257	*
mbed_official	18:da299f395b9e	258	*
mbed_official	18:da299f395b9e	259	* \section asfdoc_sam0_system_clock_api_overview API Overview
mbed_official	18:da299f395b9e	260	* @{
mbed_official	18:da299f395b9e	261	*/
mbed_official	18:da299f395b9e	262
mbed_official	18:da299f395b9e	263	#include <compiler.h>
mbed_official	18:da299f395b9e	264	#include <gclk.h>
mbed_official	18:da299f395b9e	265
mbed_official	18:da299f395b9e	266
mbed_official	18:da299f395b9e	267
mbed_official	18:da299f395b9e	268	/**
mbed_official	18:da299f395b9e	269	* \brief Available start-up times for the XOSC32K.
mbed_official	18:da299f395b9e	270	*
mbed_official	18:da299f395b9e	271	* Available external 32KHz oscillator start-up times, as a number of external
mbed_official	18:da299f395b9e	272	* clock cycles.
mbed_official	18:da299f395b9e	273	*/
mbed_official	18:da299f395b9e	274	enum system_xosc32k_startup {
mbed_official	18:da299f395b9e	275	/** Wait 2048 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	276	SYSTEM_XOSC32K_STARTUP_2048,
mbed_official	18:da299f395b9e	277	/** Wait 4096 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	278	SYSTEM_XOSC32K_STARTUP_4096,
mbed_official	18:da299f395b9e	279	/** Wait 16384 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	280	SYSTEM_XOSC32K_STARTUP_16384,
mbed_official	18:da299f395b9e	281	/** Wait 32768 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	282	SYSTEM_XOSC32K_STARTUP_32768,
mbed_official	18:da299f395b9e	283	/** Wait 65536 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	284	SYSTEM_XOSC32K_STARTUP_65536,
mbed_official	18:da299f395b9e	285	/** Wait 131072 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	286	SYSTEM_XOSC32K_STARTUP_131072,
mbed_official	18:da299f395b9e	287	/** Wait 262144 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	288	SYSTEM_XOSC32K_STARTUP_262144,
mbed_official	18:da299f395b9e	289	};
mbed_official	18:da299f395b9e	290
mbed_official	18:da299f395b9e	291	/**
mbed_official	18:da299f395b9e	292	* \brief Available start-up times for the XOSC.
mbed_official	18:da299f395b9e	293	*
mbed_official	18:da299f395b9e	294	* Available external oscillator start-up times, as a number of external clock
mbed_official	18:da299f395b9e	295	* cycles.
mbed_official	18:da299f395b9e	296	*/
mbed_official	18:da299f395b9e	297	enum system_xosc_startup {
mbed_official	18:da299f395b9e	298	/** Wait one clock cycle until the clock source is considered stable */
mbed_official	18:da299f395b9e	299	SYSTEM_XOSC_STARTUP_1,
mbed_official	18:da299f395b9e	300	/** Wait two clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	301	SYSTEM_XOSC_STARTUP_2,
mbed_official	18:da299f395b9e	302	/** Wait four clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	303	SYSTEM_XOSC_STARTUP_4,
mbed_official	18:da299f395b9e	304	/** Wait eight clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	305	SYSTEM_XOSC_STARTUP_8,
mbed_official	18:da299f395b9e	306	/** Wait 16 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	307	SYSTEM_XOSC_STARTUP_16,
mbed_official	18:da299f395b9e	308	/** Wait 32 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	309	SYSTEM_XOSC_STARTUP_32,
mbed_official	18:da299f395b9e	310	/** Wait 64 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	311	SYSTEM_XOSC_STARTUP_64,
mbed_official	18:da299f395b9e	312	/** Wait 128 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	313	SYSTEM_XOSC_STARTUP_128,
mbed_official	18:da299f395b9e	314	/** Wait 256 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	315	SYSTEM_XOSC_STARTUP_256,
mbed_official	18:da299f395b9e	316	/** Wait 512 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	317	SYSTEM_XOSC_STARTUP_512,
mbed_official	18:da299f395b9e	318	/** Wait 1024 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	319	SYSTEM_XOSC_STARTUP_1024,
mbed_official	18:da299f395b9e	320	/** Wait 2048 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	321	SYSTEM_XOSC_STARTUP_2048,
mbed_official	18:da299f395b9e	322	/** Wait 4096 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	323	SYSTEM_XOSC_STARTUP_4096,
mbed_official	18:da299f395b9e	324	/** Wait 8192 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	325	SYSTEM_XOSC_STARTUP_8192,
mbed_official	18:da299f395b9e	326	/** Wait 16384 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	327	SYSTEM_XOSC_STARTUP_16384,
mbed_official	18:da299f395b9e	328	/** Wait 32768 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	329	SYSTEM_XOSC_STARTUP_32768,
mbed_official	18:da299f395b9e	330	};
mbed_official	18:da299f395b9e	331
mbed_official	18:da299f395b9e	332	/**
mbed_official	18:da299f395b9e	333	* \brief Available start-up times for the OSC32K.
mbed_official	18:da299f395b9e	334	*
mbed_official	18:da299f395b9e	335	* Available internal 32KHz oscillator start-up times, as a number of internal
mbed_official	18:da299f395b9e	336	* OSC32K clock cycles.
mbed_official	18:da299f395b9e	337	*/
mbed_official	18:da299f395b9e	338	enum system_osc32k_startup {
mbed_official	18:da299f395b9e	339	/** Wait three clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	340	SYSTEM_OSC32K_STARTUP_3,
mbed_official	18:da299f395b9e	341	/** Wait four clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	342	SYSTEM_OSC32K_STARTUP_4,
mbed_official	18:da299f395b9e	343	/** Wait six clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	344	SYSTEM_OSC32K_STARTUP_6,
mbed_official	18:da299f395b9e	345	/** Wait ten clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	346	SYSTEM_OSC32K_STARTUP_10,
mbed_official	18:da299f395b9e	347	/** Wait 18 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	348	SYSTEM_OSC32K_STARTUP_18,
mbed_official	18:da299f395b9e	349	/** Wait 34 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	350	SYSTEM_OSC32K_STARTUP_34,
mbed_official	18:da299f395b9e	351	/** Wait 66 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	352	SYSTEM_OSC32K_STARTUP_66,
mbed_official	18:da299f395b9e	353	/** Wait 130 clock cycles until the clock source is considered stable */
mbed_official	18:da299f395b9e	354	SYSTEM_OSC32K_STARTUP_130,
mbed_official	18:da299f395b9e	355	};
mbed_official	18:da299f395b9e	356
mbed_official	18:da299f395b9e	357	/**
mbed_official	18:da299f395b9e	358	* \brief Frequency selection for the internal 16MHz system clock.
mbed_official	18:da299f395b9e	359	*
mbed_official	18:da299f395b9e	360	* Available frequency selection for the internal 16MHz (nominal) system clock.
mbed_official	18:da299f395b9e	361	*/
mbed_official	18:da299f395b9e	362	enum system_osc16m_fsel {
mbed_official	18:da299f395b9e	363	/** Frequency Selection 4MHz */
mbed_official	18:da299f395b9e	364	SYSTEM_OSC16M_4M,
mbed_official	18:da299f395b9e	365	/** Frequency Selection 8MHz */
mbed_official	18:da299f395b9e	366	SYSTEM_OSC16M_8M,
mbed_official	18:da299f395b9e	367	/** Frequency Selection 12MHz */
mbed_official	18:da299f395b9e	368	SYSTEM_OSC16M_12M,
mbed_official	18:da299f395b9e	369	/** Frequency Selection 16MHz */
mbed_official	18:da299f395b9e	370	SYSTEM_OSC16M_16M,
mbed_official	18:da299f395b9e	371	};
mbed_official	18:da299f395b9e	372
mbed_official	18:da299f395b9e	373
mbed_official	18:da299f395b9e	374
mbed_official	18:da299f395b9e	375	/**
mbed_official	18:da299f395b9e	376	* \brief Main CPU, Lowpower and Backup clock division.
mbed_official	18:da299f395b9e	377	*
mbed_official	18:da299f395b9e	378	* Available division ratios for the CPU and Lowpower and Backup clocks.
mbed_official	18:da299f395b9e	379	*/
mbed_official	18:da299f395b9e	380	enum system_main_clock_div {
mbed_official	18:da299f395b9e	381	/** Divide Main clock by one */
mbed_official	18:da299f395b9e	382	SYSTEM_MAIN_CLOCK_DIV_1,
mbed_official	18:da299f395b9e	383	/** Divide Main clock by two */
mbed_official	18:da299f395b9e	384	SYSTEM_MAIN_CLOCK_DIV_2,
mbed_official	18:da299f395b9e	385	/** Divide Main clock by four */
mbed_official	18:da299f395b9e	386	SYSTEM_MAIN_CLOCK_DIV_4,
mbed_official	18:da299f395b9e	387	/** Divide Main clock by eight */
mbed_official	18:da299f395b9e	388	SYSTEM_MAIN_CLOCK_DIV_8,
mbed_official	18:da299f395b9e	389	/** Divide Main clock by 16 */
mbed_official	18:da299f395b9e	390	SYSTEM_MAIN_CLOCK_DIV_16,
mbed_official	18:da299f395b9e	391	/** Divide Main clock by 32 */
mbed_official	18:da299f395b9e	392	SYSTEM_MAIN_CLOCK_DIV_32,
mbed_official	18:da299f395b9e	393	/** Divide Main clock by 64 */
mbed_official	18:da299f395b9e	394	SYSTEM_MAIN_CLOCK_DIV_64,
mbed_official	18:da299f395b9e	395	/** Divide Main clock by 128 */
mbed_official	18:da299f395b9e	396	SYSTEM_MAIN_CLOCK_DIV_128,
mbed_official	18:da299f395b9e	397	};
mbed_official	18:da299f395b9e	398
mbed_official	18:da299f395b9e	399	/**
mbed_official	18:da299f395b9e	400	* \brief External clock source types.
mbed_official	18:da299f395b9e	401	*
mbed_official	18:da299f395b9e	402	* Available external clock source types.
mbed_official	18:da299f395b9e	403	*/
mbed_official	18:da299f395b9e	404	enum system_clock_external {
mbed_official	18:da299f395b9e	405	/** The external clock source is a crystal oscillator */
mbed_official	18:da299f395b9e	406	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
mbed_official	18:da299f395b9e	407	/** The connected clock source is an external logic level clock signal */
mbed_official	18:da299f395b9e	408	SYSTEM_CLOCK_EXTERNAL_CLOCK,
mbed_official	18:da299f395b9e	409	};
mbed_official	18:da299f395b9e	410
mbed_official	18:da299f395b9e	411	/**
mbed_official	18:da299f395b9e	412	* \brief Operating modes of the DFLL clock source.
mbed_official	18:da299f395b9e	413	*
mbed_official	18:da299f395b9e	414	* Available operating modes of the DFLL clock source module.
mbed_official	18:da299f395b9e	415	*/
mbed_official	18:da299f395b9e	416	enum system_clock_dfll_loop_mode {
mbed_official	18:da299f395b9e	417	/** The DFLL is operating in open loop mode with no feedback */
mbed_official	18:da299f395b9e	418	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
mbed_official	18:da299f395b9e	419	/** The DFLL is operating in closed loop mode with frequency feedback from
mbed_official	18:da299f395b9e	420	* a low frequency reference clock
mbed_official	18:da299f395b9e	421	*/
mbed_official	18:da299f395b9e	422	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = OSCCTRL_DFLLCTRL_MODE,
mbed_official	18:da299f395b9e	423
mbed_official	18:da299f395b9e	424	#ifdef OSCCTRL_DFLLCTRL_USBCRM
mbed_official	18:da299f395b9e	425	/** The DFLL is operating in USB recovery mode with frequency feedback
mbed_official	18:da299f395b9e	426	* from USB SOF
mbed_official	18:da299f395b9e	427	*/
mbed_official	18:da299f395b9e	428	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = OSCCTRL_DFLLCTRL_USBCRM,
mbed_official	18:da299f395b9e	429	#endif
mbed_official	18:da299f395b9e	430	};
mbed_official	18:da299f395b9e	431
mbed_official	18:da299f395b9e	432	/**
mbed_official	18:da299f395b9e	433	* \brief Locking behavior for the DFLL during device wake-up.
mbed_official	18:da299f395b9e	434	*
mbed_official	18:da299f395b9e	435	* DFLL lock behavior modes on device wake-up from sleep.
mbed_official	18:da299f395b9e	436	*/
mbed_official	18:da299f395b9e	437	enum system_clock_dfll_wakeup_lock {
mbed_official	18:da299f395b9e	438	/** Keep DFLL lock when the device wakes from sleep */
mbed_official	18:da299f395b9e	439	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
mbed_official	18:da299f395b9e	440	/** Lose DFLL lock when the devices wakes from sleep */
mbed_official	18:da299f395b9e	441	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = OSCCTRL_DFLLCTRL_LLAW,
mbed_official	18:da299f395b9e	442	};
mbed_official	18:da299f395b9e	443
mbed_official	18:da299f395b9e	444	/**
mbed_official	18:da299f395b9e	445	* \brief Fine tracking behavior for the DFLL once a lock has been acquired.
mbed_official	18:da299f395b9e	446	*
mbed_official	18:da299f395b9e	447	* DFLL fine tracking behavior modes after a lock has been acquired.
mbed_official	18:da299f395b9e	448	*/
mbed_official	18:da299f395b9e	449	enum system_clock_dfll_stable_tracking {
mbed_official	18:da299f395b9e	450	/** Keep tracking after the DFLL has gotten a fine lock */
mbed_official	18:da299f395b9e	451	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
mbed_official	18:da299f395b9e	452	/** Stop tracking after the DFLL has gotten a fine lock */
mbed_official	18:da299f395b9e	453	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = OSCCTRL_DFLLCTRL_STABLE,
mbed_official	18:da299f395b9e	454	};
mbed_official	18:da299f395b9e	455
mbed_official	18:da299f395b9e	456	/**
mbed_official	18:da299f395b9e	457	* \brief Chill cycle behavior of the DFLL module.
mbed_official	18:da299f395b9e	458	*
mbed_official	18:da299f395b9e	459	* DFLL chill cycle behavior modes of the DFLL module. A chill cycle is a period
mbed_official	18:da299f395b9e	460	* of time when the DFLL output frequency is not measured by the unit, to allow
mbed_official	18:da299f395b9e	461	* the output to stabilize after a change in the input clock source.
mbed_official	18:da299f395b9e	462	*/
mbed_official	18:da299f395b9e	463	enum system_clock_dfll_chill_cycle {
mbed_official	18:da299f395b9e	464	/** Enable a chill cycle, where the DFLL output frequency is not measured */
mbed_official	18:da299f395b9e	465	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
mbed_official	18:da299f395b9e	466	/** Disable a chill cycle, where the DFLL output frequency is not measured */
mbed_official	18:da299f395b9e	467	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = OSCCTRL_DFLLCTRL_CCDIS,
mbed_official	18:da299f395b9e	468	};
mbed_official	18:da299f395b9e	469
mbed_official	18:da299f395b9e	470	/**
mbed_official	18:da299f395b9e	471	* \brief QuickLock settings for the DFLL module.
mbed_official	18:da299f395b9e	472	*
mbed_official	18:da299f395b9e	473	* DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
mbed_official	18:da299f395b9e	474	* the DFLL output frequency at the expense of accuracy.
mbed_official	18:da299f395b9e	475	*/
mbed_official	18:da299f395b9e	476	enum system_clock_dfll_quick_lock {
mbed_official	18:da299f395b9e	477	/** Enable the QuickLock feature for looser lock requirements on the DFLL */
mbed_official	18:da299f395b9e	478	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
mbed_official	18:da299f395b9e	479	/** Disable the QuickLock feature for strict lock requirements on the DFLL */
mbed_official	18:da299f395b9e	480	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = OSCCTRL_DFLLCTRL_QLDIS,
mbed_official	18:da299f395b9e	481	};
mbed_official	18:da299f395b9e	482
mbed_official	18:da299f395b9e	483	/**
mbed_official	18:da299f395b9e	484	* \brief Available clock sources in the system.
mbed_official	18:da299f395b9e	485	*
mbed_official	18:da299f395b9e	486	* Clock sources available to the GCLK generators
mbed_official	18:da299f395b9e	487	*/
mbed_official	18:da299f395b9e	488	enum system_clock_source {
mbed_official	18:da299f395b9e	489	/** Internal 16MHz RC oscillator */
mbed_official	18:da299f395b9e	490	SYSTEM_CLOCK_SOURCE_OSC16M = GCLK_SOURCE_OSC16M,
mbed_official	18:da299f395b9e	491	/** Internal 32KHz RC oscillator */
mbed_official	18:da299f395b9e	492	SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
mbed_official	18:da299f395b9e	493	/** External oscillator */
mbed_official	18:da299f395b9e	494	SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
mbed_official	18:da299f395b9e	495	/** External 32KHz oscillator */
mbed_official	18:da299f395b9e	496	SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
mbed_official	18:da299f395b9e	497	/** Digital Frequency Locked Loop (DFLL) */
mbed_official	18:da299f395b9e	498	SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
mbed_official	18:da299f395b9e	499	/** Internal Ultra Low Power 32KHz oscillator */
mbed_official	18:da299f395b9e	500	SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
mbed_official	18:da299f395b9e	501	/** Generator input pad */
mbed_official	18:da299f395b9e	502	SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
mbed_official	18:da299f395b9e	503	/** Generic clock generator one output */
mbed_official	18:da299f395b9e	504	SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
mbed_official	18:da299f395b9e	505
mbed_official	18:da299f395b9e	506	/** Digital Phase Locked Loop (DPLL) */
mbed_official	18:da299f395b9e	507	SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
mbed_official	18:da299f395b9e	508	};
mbed_official	18:da299f395b9e	509
mbed_official	18:da299f395b9e	510	/**
mbed_official	18:da299f395b9e	511	* \brief List of APB peripheral buses.
mbed_official	18:da299f395b9e	512	*
mbed_official	18:da299f395b9e	513	* Available bus clock domains on the APB bus.
mbed_official	18:da299f395b9e	514	*/
mbed_official	18:da299f395b9e	515	enum system_clock_apb_bus {
mbed_official	18:da299f395b9e	516	/** Peripheral bus A on the APB bus */
mbed_official	18:da299f395b9e	517	SYSTEM_CLOCK_APB_APBA,
mbed_official	18:da299f395b9e	518	/** Peripheral bus B on the APB bus */
mbed_official	18:da299f395b9e	519	SYSTEM_CLOCK_APB_APBB,
mbed_official	18:da299f395b9e	520	/** Peripheral bus C on the APB bus */
mbed_official	18:da299f395b9e	521	SYSTEM_CLOCK_APB_APBC,
mbed_official	18:da299f395b9e	522	/** Peripheral bus D on the APB bus */
mbed_official	18:da299f395b9e	523	SYSTEM_CLOCK_APB_APBD,
mbed_official	18:da299f395b9e	524	/** Peripheral bus E on the APB bus */
mbed_official	18:da299f395b9e	525	SYSTEM_CLOCK_APB_APBE,
mbed_official	18:da299f395b9e	526	};
mbed_official	18:da299f395b9e	527
mbed_official	18:da299f395b9e	528	/**
mbed_official	18:da299f395b9e	529	* \brief Configuration structure for XOSC.
mbed_official	18:da299f395b9e	530	*
mbed_official	18:da299f395b9e	531	* External oscillator clock configuration structure.
mbed_official	18:da299f395b9e	532	*/
mbed_official	18:da299f395b9e	533	struct system_clock_source_xosc_config {
mbed_official	18:da299f395b9e	534	/** External clock type */
mbed_official	18:da299f395b9e	535	enum system_clock_external external_clock;
mbed_official	18:da299f395b9e	536	/** Crystal oscillator start-up time */
mbed_official	18:da299f395b9e	537	enum system_xosc_startup startup_time;
mbed_official	18:da299f395b9e	538	/** Enable automatic amplitude gain control */
mbed_official	18:da299f395b9e	539	bool auto_gain_control;
mbed_official	18:da299f395b9e	540	/** External clock/crystal frequency */
mbed_official	18:da299f395b9e	541	uint32_t frequency;
mbed_official	18:da299f395b9e	542	/** Keep the XOSC enabled in standby sleep mode */
mbed_official	18:da299f395b9e	543	bool run_in_standby;
mbed_official	18:da299f395b9e	544	/** Run On Demand. If this is set the XOSC won't run
mbed_official	18:da299f395b9e	545	* until requested by a peripheral */
mbed_official	18:da299f395b9e	546	bool on_demand;
mbed_official	18:da299f395b9e	547	};
mbed_official	18:da299f395b9e	548
mbed_official	18:da299f395b9e	549	/**
mbed_official	18:da299f395b9e	550	* \brief Configuration structure for XOSC32K.
mbed_official	18:da299f395b9e	551	*
mbed_official	18:da299f395b9e	552	* External 32KHz oscillator clock configuration structure.
mbed_official	18:da299f395b9e	553	*/
mbed_official	18:da299f395b9e	554	struct system_clock_source_xosc32k_config {
mbed_official	18:da299f395b9e	555	/** External clock type */
mbed_official	18:da299f395b9e	556	enum system_clock_external external_clock;
mbed_official	18:da299f395b9e	557	/** Crystal oscillator start-up time */
mbed_official	18:da299f395b9e	558	enum system_xosc32k_startup startup_time;
mbed_official	18:da299f395b9e	559	/** Enable 1KHz output */
mbed_official	18:da299f395b9e	560	bool enable_1khz_output;
mbed_official	18:da299f395b9e	561	/** Enable 32KHz output */
mbed_official	18:da299f395b9e	562	bool enable_32khz_output;
mbed_official	18:da299f395b9e	563	/** External clock/crystal frequency */
mbed_official	18:da299f395b9e	564	uint32_t frequency;
mbed_official	18:da299f395b9e	565	/** Keep the XOSC32K enabled in standby sleep mode */
mbed_official	18:da299f395b9e	566	bool run_in_standby;
mbed_official	18:da299f395b9e	567	/** Run On Demand. If this is set the XOSC32K won't run
mbed_official	18:da299f395b9e	568	* until requested by a peripheral */
mbed_official	18:da299f395b9e	569	bool on_demand;
mbed_official	18:da299f395b9e	570	/** Lock configuration after it has been written,
mbed_official	18:da299f395b9e	571	* a device reset will release the lock */
mbed_official	18:da299f395b9e	572	bool write_once;
mbed_official	18:da299f395b9e	573	};
mbed_official	18:da299f395b9e	574
mbed_official	18:da299f395b9e	575	/**
mbed_official	18:da299f395b9e	576	* \brief Configuration structure for OSC16M.
mbed_official	18:da299f395b9e	577	*
mbed_official	18:da299f395b9e	578	* Internal 16MHz (nominal) oscillator configuration structure.
mbed_official	18:da299f395b9e	579	*/
mbed_official	18:da299f395b9e	580	struct system_clock_source_osc16m_config {
mbed_official	18:da299f395b9e	581	/** Internal 16MHz RC oscillator prescaler */
mbed_official	18:da299f395b9e	582	enum system_osc16m_fsel fsel;
mbed_official	18:da299f395b9e	583	/** Keep the OSC16M enabled in standby sleep mode */
mbed_official	18:da299f395b9e	584	bool run_in_standby;
mbed_official	18:da299f395b9e	585	/** Run On Demand. If this is set the OSC16M won't run
mbed_official	18:da299f395b9e	586	* until requested by a peripheral */
mbed_official	18:da299f395b9e	587	bool on_demand;
mbed_official	18:da299f395b9e	588	};
mbed_official	18:da299f395b9e	589
mbed_official	18:da299f395b9e	590	/**
mbed_official	18:da299f395b9e	591	* \brief Configuration structure for OSCULP32K.
mbed_official	18:da299f395b9e	592	*
mbed_official	18:da299f395b9e	593	* Internal 32KHz Ultra Low Power oscillator configuration structure.
mbed_official	18:da299f395b9e	594	*/
mbed_official	18:da299f395b9e	595	struct system_clock_source_osculp32k_config {
mbed_official	18:da299f395b9e	596	/** Lock configuration after it has been written,
mbed_official	18:da299f395b9e	597	* a device reset will release the lock */
mbed_official	18:da299f395b9e	598	bool write_once;
mbed_official	18:da299f395b9e	599	};
mbed_official	18:da299f395b9e	600
mbed_official	18:da299f395b9e	601	/**
mbed_official	18:da299f395b9e	602	* \brief Configuration structure for OSCULP32K.
mbed_official	18:da299f395b9e	603	*
mbed_official	18:da299f395b9e	604	* Internal 32KHz oscillator configuration structure.
mbed_official	18:da299f395b9e	605	*/
mbed_official	18:da299f395b9e	606	struct system_clock_source_osc32k_config {
mbed_official	18:da299f395b9e	607	/** Start-up time */
mbed_official	18:da299f395b9e	608	enum system_osc32k_startup startup_time;
mbed_official	18:da299f395b9e	609	/** Enable 1KHz output */
mbed_official	18:da299f395b9e	610	bool enable_1khz_output;
mbed_official	18:da299f395b9e	611	/** Enable 32KHz output */
mbed_official	18:da299f395b9e	612	bool enable_32khz_output;
mbed_official	18:da299f395b9e	613	/** Keep the OSC32K enabled in standby sleep mode */
mbed_official	18:da299f395b9e	614	bool run_in_standby;
mbed_official	18:da299f395b9e	615	/** Run On Demand. If this is set the OSC32K won't run
mbed_official	18:da299f395b9e	616	* until requested by a peripheral */
mbed_official	18:da299f395b9e	617	bool on_demand;
mbed_official	18:da299f395b9e	618	/** Lock configuration after it has been written,
mbed_official	18:da299f395b9e	619	* a device reset will release the lock */
mbed_official	18:da299f395b9e	620	bool write_once;
mbed_official	18:da299f395b9e	621	};
mbed_official	18:da299f395b9e	622
mbed_official	18:da299f395b9e	623	/**
mbed_official	18:da299f395b9e	624	* \brief Configuration structure for DFLL.
mbed_official	18:da299f395b9e	625	*
mbed_official	18:da299f395b9e	626	* DFLL oscillator configuration structure.
mbed_official	18:da299f395b9e	627	*/
mbed_official	18:da299f395b9e	628	struct system_clock_source_dfll_config {
mbed_official	18:da299f395b9e	629	/** Loop mode */
mbed_official	18:da299f395b9e	630	enum system_clock_dfll_loop_mode loop_mode;
mbed_official	18:da299f395b9e	631	/** Run On Demand. If this is set the DFLL won't run
mbed_official	18:da299f395b9e	632	* until requested by a peripheral */
mbed_official	18:da299f395b9e	633	bool on_demand;
mbed_official	18:da299f395b9e	634	/** Run in stanby*/
mbed_official	18:da299f395b9e	635	bool run_in_stanby;
mbed_official	18:da299f395b9e	636	/** Enable quick lock */
mbed_official	18:da299f395b9e	637	enum system_clock_dfll_quick_lock quick_lock;
mbed_official	18:da299f395b9e	638	/** Enable chill cycle */
mbed_official	18:da299f395b9e	639	enum system_clock_dfll_chill_cycle chill_cycle;
mbed_official	18:da299f395b9e	640	/** DFLL lock state on wakeup */
mbed_official	18:da299f395b9e	641	enum system_clock_dfll_wakeup_lock wakeup_lock;
mbed_official	18:da299f395b9e	642	/** DFLL tracking after fine lock */
mbed_official	18:da299f395b9e	643	enum system_clock_dfll_stable_tracking stable_tracking;
mbed_official	18:da299f395b9e	644	/** Coarse calibration value (Open loop mode) */
mbed_official	18:da299f395b9e	645	uint8_t coarse_value;
mbed_official	18:da299f395b9e	646	/** Fine calibration value (Open loop mode) */
mbed_official	18:da299f395b9e	647	uint16_t fine_value;
mbed_official	18:da299f395b9e	648	/** Coarse adjustment maximum step size (Closed loop mode) */
mbed_official	18:da299f395b9e	649	uint8_t coarse_max_step;
mbed_official	18:da299f395b9e	650	/** Fine adjustment maximum step size (Closed loop mode) */
mbed_official	18:da299f395b9e	651	uint16_t fine_max_step;
mbed_official	18:da299f395b9e	652	/** DFLL multiply factor (Closed loop mode) */
mbed_official	18:da299f395b9e	653	uint16_t multiply_factor;
mbed_official	18:da299f395b9e	654	};
mbed_official	18:da299f395b9e	655
mbed_official	18:da299f395b9e	656	/**
mbed_official	18:da299f395b9e	657	* \name External Oscillator Management
mbed_official	18:da299f395b9e	658	* @{
mbed_official	18:da299f395b9e	659	*/
mbed_official	18:da299f395b9e	660
mbed_official	18:da299f395b9e	661	/**
mbed_official	18:da299f395b9e	662	* \brief Retrieve the default configuration for XOSC.
mbed_official	18:da299f395b9e	663	*
mbed_official	18:da299f395b9e	664	* Fills a configuration structure with the default configuration for an
mbed_official	18:da299f395b9e	665	* external oscillator module:
mbed_official	18:da299f395b9e	666	* - External Crystal
mbed_official	18:da299f395b9e	667	* - Start-up time of 16384 external clock cycles
mbed_official	18:da299f395b9e	668	* - Automatic crystal gain control mode enabled
mbed_official	18:da299f395b9e	669	* - Frequency of 12MHz
mbed_official	18:da299f395b9e	670	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	671	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	672	*
mbed_official	18:da299f395b9e	673	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	674	*/
mbed_official	18:da299f395b9e	675	static inline void system_clock_source_xosc_get_config_defaults(
mbed_official	18:da299f395b9e	676	struct system_clock_source_xosc_config *const config)
mbed_official	18:da299f395b9e	677	{
mbed_official	18:da299f395b9e	678	Assert(config);
mbed_official	18:da299f395b9e	679
mbed_official	18:da299f395b9e	680	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	18:da299f395b9e	681	config->startup_time = SYSTEM_XOSC_STARTUP_16384;
mbed_official	18:da299f395b9e	682	config->auto_gain_control = true;
mbed_official	18:da299f395b9e	683	config->frequency = 12000000UL;
mbed_official	18:da299f395b9e	684	config->run_in_standby = false;
mbed_official	18:da299f395b9e	685	config->on_demand = true;
mbed_official	18:da299f395b9e	686	}
mbed_official	18:da299f395b9e	687
mbed_official	18:da299f395b9e	688	void system_clock_source_xosc_set_config(
mbed_official	18:da299f395b9e	689	struct system_clock_source_xosc_config *const config);
mbed_official	18:da299f395b9e	690
mbed_official	18:da299f395b9e	691	/**
mbed_official	18:da299f395b9e	692	* @}
mbed_official	18:da299f395b9e	693	*/
mbed_official	18:da299f395b9e	694
mbed_official	18:da299f395b9e	695
mbed_official	18:da299f395b9e	696	/**
mbed_official	18:da299f395b9e	697	* \name External 32KHz Oscillator Management
mbed_official	18:da299f395b9e	698	* @{
mbed_official	18:da299f395b9e	699	*/
mbed_official	18:da299f395b9e	700
mbed_official	18:da299f395b9e	701	/**
mbed_official	18:da299f395b9e	702	* \brief Retrieve the default configuration for XOSC32K.
mbed_official	18:da299f395b9e	703	*
mbed_official	18:da299f395b9e	704	* Fills a configuration structure with the default configuration for an
mbed_official	18:da299f395b9e	705	* external 32KHz oscillator module:
mbed_official	18:da299f395b9e	706	* - External Crystal
mbed_official	18:da299f395b9e	707	* - Start-up time of 16384 external clock cycles
mbed_official	18:da299f395b9e	708	* - Automatic crystal gain control mode disabled
mbed_official	18:da299f395b9e	709	* - Frequency of 32.768KHz
mbed_official	18:da299f395b9e	710	* - 1KHz clock output disabled
mbed_official	18:da299f395b9e	711	* - 32KHz clock output enabled
mbed_official	18:da299f395b9e	712	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	713	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	714	* - Don't lock registers after configuration has been written
mbed_official	18:da299f395b9e	715	*
mbed_official	18:da299f395b9e	716	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	717	*/
mbed_official	18:da299f395b9e	718	static inline void system_clock_source_xosc32k_get_config_defaults(
mbed_official	18:da299f395b9e	719	struct system_clock_source_xosc32k_config *const config)
mbed_official	18:da299f395b9e	720	{
mbed_official	18:da299f395b9e	721	Assert(config);
mbed_official	18:da299f395b9e	722
mbed_official	18:da299f395b9e	723	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	18:da299f395b9e	724	config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
mbed_official	18:da299f395b9e	725	config->frequency = 32768UL;
mbed_official	18:da299f395b9e	726	config->enable_1khz_output = false;
mbed_official	18:da299f395b9e	727	config->enable_32khz_output = true;
mbed_official	18:da299f395b9e	728	config->run_in_standby = false;
mbed_official	18:da299f395b9e	729	config->on_demand = true;
mbed_official	18:da299f395b9e	730	config->write_once = false;
mbed_official	18:da299f395b9e	731	}
mbed_official	18:da299f395b9e	732
mbed_official	18:da299f395b9e	733	void system_clock_source_xosc32k_set_config(
mbed_official	18:da299f395b9e	734	struct system_clock_source_xosc32k_config *const config);
mbed_official	18:da299f395b9e	735	/**
mbed_official	18:da299f395b9e	736	* @}
mbed_official	18:da299f395b9e	737	*/
mbed_official	18:da299f395b9e	738
mbed_official	18:da299f395b9e	739
mbed_official	18:da299f395b9e	740	/**
mbed_official	18:da299f395b9e	741	* \name Internal 32KHz Oscillator Management
mbed_official	18:da299f395b9e	742	* @{
mbed_official	18:da299f395b9e	743	*/
mbed_official	18:da299f395b9e	744
mbed_official	18:da299f395b9e	745	/**
mbed_official	18:da299f395b9e	746	* \brief Retrieve the default configuration for OSC32K.
mbed_official	18:da299f395b9e	747	*
mbed_official	18:da299f395b9e	748	* Fills a configuration structure with the default configuration for an
mbed_official	18:da299f395b9e	749	* internal 32KHz oscillator module:
mbed_official	18:da299f395b9e	750	* - 1KHz clock output enabled
mbed_official	18:da299f395b9e	751	* - 32KHz clock output enabled
mbed_official	18:da299f395b9e	752	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	753	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	754	* - Set start-up time to 130 cycles
mbed_official	18:da299f395b9e	755	* - Don't lock registers after configuration has been written
mbed_official	18:da299f395b9e	756	*
mbed_official	18:da299f395b9e	757	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	758	*/
mbed_official	18:da299f395b9e	759	static inline void system_clock_source_osc32k_get_config_defaults(
mbed_official	18:da299f395b9e	760	struct system_clock_source_osc32k_config *const config)
mbed_official	18:da299f395b9e	761	{
mbed_official	18:da299f395b9e	762	Assert(config);
mbed_official	18:da299f395b9e	763
mbed_official	18:da299f395b9e	764	config->enable_1khz_output = true;
mbed_official	18:da299f395b9e	765	config->enable_32khz_output = true;
mbed_official	18:da299f395b9e	766	config->run_in_standby = false;
mbed_official	18:da299f395b9e	767	config->on_demand = true;
mbed_official	18:da299f395b9e	768	config->startup_time = SYSTEM_OSC32K_STARTUP_130;
mbed_official	18:da299f395b9e	769	config->write_once = false;
mbed_official	18:da299f395b9e	770	}
mbed_official	18:da299f395b9e	771
mbed_official	18:da299f395b9e	772	void system_clock_source_osc32k_set_config(
mbed_official	18:da299f395b9e	773	struct system_clock_source_osc32k_config *const config);
mbed_official	18:da299f395b9e	774
mbed_official	18:da299f395b9e	775	/**
mbed_official	18:da299f395b9e	776	* @}
mbed_official	18:da299f395b9e	777	*/
mbed_official	18:da299f395b9e	778
mbed_official	18:da299f395b9e	779	/**
mbed_official	18:da299f395b9e	780	* \name Internal Ultra Low Power 32KHz Oscillator Management
mbed_official	18:da299f395b9e	781	* @{
mbed_official	18:da299f395b9e	782	*/
mbed_official	18:da299f395b9e	783
mbed_official	18:da299f395b9e	784	/**
mbed_official	18:da299f395b9e	785	* \brief Retrieve the default configuration for OSCULP32K.
mbed_official	18:da299f395b9e	786	*
mbed_official	18:da299f395b9e	787	* Fills a configuration structure with the default configuration for an
mbed_official	18:da299f395b9e	788	* internal Ultra Low Power 32KHz oscillator module:
mbed_official	18:da299f395b9e	789	* - 1KHz clock output enabled
mbed_official	18:da299f395b9e	790	* - 32KHz clock output enabled
mbed_official	18:da299f395b9e	791	*
mbed_official	18:da299f395b9e	792	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	793	*/
mbed_official	18:da299f395b9e	794	static inline void system_clock_source_osculp32k_get_config_defaults(
mbed_official	18:da299f395b9e	795	struct system_clock_source_osculp32k_config *const config)
mbed_official	18:da299f395b9e	796	{
mbed_official	18:da299f395b9e	797	Assert(config);
mbed_official	18:da299f395b9e	798
mbed_official	18:da299f395b9e	799	config->write_once = false;
mbed_official	18:da299f395b9e	800	}
mbed_official	18:da299f395b9e	801
mbed_official	18:da299f395b9e	802	void system_clock_source_osculp32k_set_config(
mbed_official	18:da299f395b9e	803	struct system_clock_source_osculp32k_config *const config);
mbed_official	18:da299f395b9e	804
mbed_official	18:da299f395b9e	805	/**
mbed_official	18:da299f395b9e	806	* @}
mbed_official	18:da299f395b9e	807	*/
mbed_official	18:da299f395b9e	808
mbed_official	18:da299f395b9e	809
mbed_official	18:da299f395b9e	810	/**
mbed_official	18:da299f395b9e	811	* \name Internal 16MHz Oscillator Management
mbed_official	18:da299f395b9e	812	* @{
mbed_official	18:da299f395b9e	813	*/
mbed_official	18:da299f395b9e	814
mbed_official	18:da299f395b9e	815	/**
mbed_official	18:da299f395b9e	816	* \brief Retrieve the default configuration for OSC16M.
mbed_official	18:da299f395b9e	817	*
mbed_official	18:da299f395b9e	818	* Fills a configuration structure with the default configuration for an
mbed_official	18:da299f395b9e	819	* internal 16MHz (nominal) oscillator module:
mbed_official	18:da299f395b9e	820	* - Clock output frequency select 4MHz
mbed_official	18:da299f395b9e	821	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	822	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	823	*
mbed_official	18:da299f395b9e	824	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	825	*/
mbed_official	18:da299f395b9e	826	static inline void system_clock_source_osc16m_get_config_defaults(
mbed_official	18:da299f395b9e	827	struct system_clock_source_osc16m_config *const config)
mbed_official	18:da299f395b9e	828	{
mbed_official	18:da299f395b9e	829	Assert(config);
mbed_official	18:da299f395b9e	830
mbed_official	18:da299f395b9e	831	config->fsel = SYSTEM_OSC16M_4M;
mbed_official	18:da299f395b9e	832	config->run_in_standby = false;
mbed_official	18:da299f395b9e	833	config->on_demand = true;
mbed_official	18:da299f395b9e	834	}
mbed_official	18:da299f395b9e	835
mbed_official	18:da299f395b9e	836	void system_clock_source_osc16m_set_config(
mbed_official	18:da299f395b9e	837	struct system_clock_source_osc16m_config *const config);
mbed_official	18:da299f395b9e	838
mbed_official	18:da299f395b9e	839	/**
mbed_official	18:da299f395b9e	840	* @}
mbed_official	18:da299f395b9e	841	*/
mbed_official	18:da299f395b9e	842
mbed_official	18:da299f395b9e	843
mbed_official	18:da299f395b9e	844	/**
mbed_official	18:da299f395b9e	845	* \name Internal DFLL Management
mbed_official	18:da299f395b9e	846	* @{
mbed_official	18:da299f395b9e	847	*/
mbed_official	18:da299f395b9e	848
mbed_official	18:da299f395b9e	849	/**
mbed_official	18:da299f395b9e	850	* \brief Retrieve the default configuration for DFLL.
mbed_official	18:da299f395b9e	851	*
mbed_official	18:da299f395b9e	852	* Fills a configuration structure with the default configuration for a
mbed_official	18:da299f395b9e	853	* DFLL oscillator module:
mbed_official	18:da299f395b9e	854	* - Open loop mode
mbed_official	18:da299f395b9e	855	* - QuickLock mode enabled
mbed_official	18:da299f395b9e	856	* - Chill cycle enabled
mbed_official	18:da299f395b9e	857	* - Output frequency lock maintained during device wake-up
mbed_official	18:da299f395b9e	858	* - Continuous tracking of the output frequency
mbed_official	18:da299f395b9e	859	* - Default tracking values at the mid-points for both coarse and fine
mbed_official	18:da299f395b9e	860	* tracking parameters
mbed_official	18:da299f395b9e	861	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	862	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	863	*
mbed_official	18:da299f395b9e	864	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	865	*/
mbed_official	18:da299f395b9e	866	static inline void system_clock_source_dfll_get_config_defaults(
mbed_official	18:da299f395b9e	867	struct system_clock_source_dfll_config *const config)
mbed_official	18:da299f395b9e	868	{
mbed_official	18:da299f395b9e	869	Assert(config);
mbed_official	18:da299f395b9e	870
mbed_official	18:da299f395b9e	871	config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
mbed_official	18:da299f395b9e	872	config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
mbed_official	18:da299f395b9e	873	config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
mbed_official	18:da299f395b9e	874	config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
mbed_official	18:da299f395b9e	875	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
mbed_official	18:da299f395b9e	876	config->on_demand = true;
mbed_official	18:da299f395b9e	877	config->run_in_stanby = false;
mbed_official	18:da299f395b9e	878
mbed_official	18:da299f395b9e	879	/* Open loop mode calibration value */
mbed_official	18:da299f395b9e	880	config->coarse_value = 0x1f / 4; /* Midpoint */
mbed_official	18:da299f395b9e	881	config->fine_value = 0xff / 4; /* Midpoint */
mbed_official	18:da299f395b9e	882
mbed_official	18:da299f395b9e	883	/* Closed loop mode */
mbed_official	18:da299f395b9e	884	config->coarse_max_step = 1;
mbed_official	18:da299f395b9e	885	config->fine_max_step = 1;
mbed_official	18:da299f395b9e	886	config->multiply_factor = 12; /* Multiply 4MHz by 12 to get 48MHz */
mbed_official	18:da299f395b9e	887	}
mbed_official	18:da299f395b9e	888
mbed_official	18:da299f395b9e	889	void system_clock_source_dfll_set_config(
mbed_official	18:da299f395b9e	890	struct system_clock_source_dfll_config *const config);
mbed_official	18:da299f395b9e	891
mbed_official	18:da299f395b9e	892	/**
mbed_official	18:da299f395b9e	893	* @}
mbed_official	18:da299f395b9e	894	*/
mbed_official	18:da299f395b9e	895
mbed_official	18:da299f395b9e	896	/**
mbed_official	18:da299f395b9e	897	* \name Clock Source Management
mbed_official	18:da299f395b9e	898	* @{
mbed_official	18:da299f395b9e	899	*/
mbed_official	18:da299f395b9e	900	enum status_code system_clock_source_write_calibration(
mbed_official	18:da299f395b9e	901	const enum system_clock_source system_clock_source,
mbed_official	18:da299f395b9e	902	const uint16_t calibration_value,
mbed_official	18:da299f395b9e	903	const uint8_t freq_range);
mbed_official	18:da299f395b9e	904
mbed_official	18:da299f395b9e	905	enum status_code system_clock_source_enable(
mbed_official	18:da299f395b9e	906	const enum system_clock_source system_clock_source);
mbed_official	18:da299f395b9e	907
mbed_official	18:da299f395b9e	908	enum status_code system_clock_source_disable(
mbed_official	18:da299f395b9e	909	const enum system_clock_source clk_source);
mbed_official	18:da299f395b9e	910
mbed_official	18:da299f395b9e	911	bool system_clock_source_is_ready(
mbed_official	18:da299f395b9e	912	const enum system_clock_source clk_source);
mbed_official	18:da299f395b9e	913
mbed_official	18:da299f395b9e	914	uint32_t system_clock_source_get_hz(
mbed_official	18:da299f395b9e	915	const enum system_clock_source clk_source);
mbed_official	18:da299f395b9e	916
mbed_official	18:da299f395b9e	917	/**
mbed_official	18:da299f395b9e	918	* @}
mbed_official	18:da299f395b9e	919	*/
mbed_official	18:da299f395b9e	920
mbed_official	18:da299f395b9e	921	/**
mbed_official	18:da299f395b9e	922	* \name Main Clock Management
mbed_official	18:da299f395b9e	923	* @{
mbed_official	18:da299f395b9e	924	*/
mbed_official	18:da299f395b9e	925
mbed_official	18:da299f395b9e	926	/**
mbed_official	18:da299f395b9e	927	* \brief Enable or disable the main clock failure detection.
mbed_official	18:da299f395b9e	928	*
mbed_official	18:da299f395b9e	929	* This mechanism allows switching automatically the main clock to the safe
mbed_official	18:da299f395b9e	930	* RCSYS clock, when the main clock source is considered off.
mbed_official	18:da299f395b9e	931	*
mbed_official	18:da299f395b9e	932	* This may happen for instance when an external crystal is selected as the
mbed_official	18:da299f395b9e	933	* clock source of the main clock and the crystal dies. The mechanism is to
mbed_official	18:da299f395b9e	934	* detect, during a RCSYS period, at least one rising edge of the main clock.
mbed_official	18:da299f395b9e	935	* If no rising edge is seen the clock is considered failed.
mbed_official	18:da299f395b9e	936	* As soon as the detector is enabled, the clock failure detector
mbed_official	18:da299f395b9e	937	* (CFD) will monitor the divided main clock. When a clock failure is detected,
mbed_official	18:da299f395b9e	938	* the main clock automatically switches to the RCSYS clock and the CFD
mbed_official	18:da299f395b9e	939	* interrupt is generated if enabled.
mbed_official	18:da299f395b9e	940	*
mbed_official	18:da299f395b9e	941	* \note The failure detect must be disabled if the system clock is the same or
mbed_official	18:da299f395b9e	942	* slower than 32KHz as it will believe the system clock has failed with
mbed_official	18:da299f395b9e	943	* a too slow clock.
mbed_official	18:da299f395b9e	944	*
mbed_official	18:da299f395b9e	945	* \param[in] enable Boolean \c true to enable, \c false to disable detection
mbed_official	18:da299f395b9e	946	*/
mbed_official	18:da299f395b9e	947	static inline void system_main_clock_set_failure_detect(
mbed_official	18:da299f395b9e	948	const bool enable)
mbed_official	18:da299f395b9e	949	{
mbed_official	18:da299f395b9e	950	if (enable) {
mbed_official	18:da299f395b9e	951	MCLK->CTRLA.reg \|= MCLK_CTRLA_CFDEN;
mbed_official	18:da299f395b9e	952	} else {
mbed_official	18:da299f395b9e	953	MCLK->CTRLA.reg &= ~MCLK_CTRLA_CFDEN;
mbed_official	18:da299f395b9e	954	}
mbed_official	18:da299f395b9e	955	}
mbed_official	18:da299f395b9e	956
mbed_official	18:da299f395b9e	957	/**
mbed_official	18:da299f395b9e	958	* \brief Set main CPU clock divider.
mbed_official	18:da299f395b9e	959	*
mbed_official	18:da299f395b9e	960	* Sets the clock divider used on the main clock to provide the CPU clock.
mbed_official	18:da299f395b9e	961	*
mbed_official	18:da299f395b9e	962	* \param[in] divider CPU clock divider to set
mbed_official	18:da299f395b9e	963	*/
mbed_official	18:da299f395b9e	964	static inline void system_cpu_clock_set_divider(
mbed_official	18:da299f395b9e	965	const enum system_main_clock_div divider)
mbed_official	18:da299f395b9e	966	{
mbed_official	18:da299f395b9e	967	Assert(((uint32_t)divider & MCLK_CPUDIV_CPUDIV_Msk) == divider);
mbed_official	18:da299f395b9e	968	MCLK->CPUDIV.reg = (uint32_t)divider;
mbed_official	18:da299f395b9e	969
mbed_official	18:da299f395b9e	970	}
mbed_official	18:da299f395b9e	971
mbed_official	18:da299f395b9e	972	/**
mbed_official	18:da299f395b9e	973	* \brief Set Low-Power Clock divider.
mbed_official	18:da299f395b9e	974	*
mbed_official	18:da299f395b9e	975	* Sets the clock divider used on the main clock to provide the CPU clock.
mbed_official	18:da299f395b9e	976	*
mbed_official	18:da299f395b9e	977	* \param[in] divider CPU clock divider to set
mbed_official	18:da299f395b9e	978	*/
mbed_official	18:da299f395b9e	979	static inline void system_low_power_clock_set_divider(
mbed_official	18:da299f395b9e	980	const enum system_main_clock_div divider)
mbed_official	18:da299f395b9e	981	{
mbed_official	18:da299f395b9e	982	Assert(((uint32_t)divider & MCLK_LPDIV_LPDIV_Msk) == divider);
mbed_official	18:da299f395b9e	983	MCLK->LPDIV.reg = (uint32_t)divider;
mbed_official	18:da299f395b9e	984
mbed_official	18:da299f395b9e	985	}
mbed_official	18:da299f395b9e	986
mbed_official	18:da299f395b9e	987	/**
mbed_official	18:da299f395b9e	988	* \brief Set Backup Clock divider.
mbed_official	18:da299f395b9e	989	*
mbed_official	18:da299f395b9e	990	* Sets the clock divider used on the main clock to provide the CPU clock.
mbed_official	18:da299f395b9e	991	*
mbed_official	18:da299f395b9e	992	* \param[in] divider CPU clock divider to set
mbed_official	18:da299f395b9e	993	*/
mbed_official	18:da299f395b9e	994	static inline void system_backup_clock_set_divider(
mbed_official	18:da299f395b9e	995	const enum system_main_clock_div divider)
mbed_official	18:da299f395b9e	996	{
mbed_official	18:da299f395b9e	997	Assert(((uint32_t)divider & MCLK_BUPDIV_BUPDIV_Msk) == divider);
mbed_official	18:da299f395b9e	998	MCLK->BUPDIV.reg = (uint32_t)divider;
mbed_official	18:da299f395b9e	999
mbed_official	18:da299f395b9e	1000	}
mbed_official	18:da299f395b9e	1001
mbed_official	18:da299f395b9e	1002
mbed_official	18:da299f395b9e	1003	/**
mbed_official	18:da299f395b9e	1004	* \brief Retrieves the current frequency of the CPU core.
mbed_official	18:da299f395b9e	1005	*
mbed_official	18:da299f395b9e	1006	* Retrieves the operating frequency of the CPU core, obtained from the main
mbed_official	18:da299f395b9e	1007	* generic clock and the set CPU bus divider.
mbed_official	18:da299f395b9e	1008	*
mbed_official	18:da299f395b9e	1009	* \return Current CPU frequency in Hz.
mbed_official	18:da299f395b9e	1010	*/
mbed_official	18:da299f395b9e	1011	static inline uint32_t system_cpu_clock_get_hz(void)
mbed_official	18:da299f395b9e	1012	{
mbed_official	18:da299f395b9e	1013	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->CPUDIV.reg - 1));
mbed_official	18:da299f395b9e	1014
mbed_official	18:da299f395b9e	1015	}
mbed_official	18:da299f395b9e	1016
mbed_official	18:da299f395b9e	1017	/**
mbed_official	18:da299f395b9e	1018	* \brief Retrieves the current frequency of Low-Power clock.
mbed_official	18:da299f395b9e	1019	*
mbed_official	18:da299f395b9e	1020	* Retrieves the operating frequency of Low-Power, obtained from Low-Power
mbed_official	18:da299f395b9e	1021	* clock and the set Low-Power clock divider.
mbed_official	18:da299f395b9e	1022	*
mbed_official	18:da299f395b9e	1023	* \return Current CPU frequency in Hz.
mbed_official	18:da299f395b9e	1024	*/
mbed_official	18:da299f395b9e	1025	static inline uint32_t system_low_power_clock_get_hz(void)
mbed_official	18:da299f395b9e	1026	{
mbed_official	18:da299f395b9e	1027	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->LPDIV.reg - 1));
mbed_official	18:da299f395b9e	1028
mbed_official	18:da299f395b9e	1029	}
mbed_official	18:da299f395b9e	1030
mbed_official	18:da299f395b9e	1031	/**
mbed_official	18:da299f395b9e	1032	* \brief Retrieves the current frequency of backup clock.
mbed_official	18:da299f395b9e	1033	*
mbed_official	18:da299f395b9e	1034	* Retrieves the operating frequency of backup clock, obtained from backup
mbed_official	18:da299f395b9e	1035	* clock and the set backup clock divider.
mbed_official	18:da299f395b9e	1036	*
mbed_official	18:da299f395b9e	1037	* \return Current CPU frequency in Hz.
mbed_official	18:da299f395b9e	1038	*/
mbed_official	18:da299f395b9e	1039	static inline uint32_t system_backup_clock_get_hz(void)
mbed_official	18:da299f395b9e	1040	{
mbed_official	18:da299f395b9e	1041	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> (MCLK->BUPDIV.reg - 1));
mbed_official	18:da299f395b9e	1042
mbed_official	18:da299f395b9e	1043	}
mbed_official	18:da299f395b9e	1044
mbed_official	18:da299f395b9e	1045
mbed_official	18:da299f395b9e	1046	/**
mbed_official	18:da299f395b9e	1047	* @}
mbed_official	18:da299f395b9e	1048	*/
mbed_official	18:da299f395b9e	1049
mbed_official	18:da299f395b9e	1050	/**
mbed_official	18:da299f395b9e	1051	* \name Bus Clock Masking
mbed_official	18:da299f395b9e	1052	* @{
mbed_official	18:da299f395b9e	1053	*/
mbed_official	18:da299f395b9e	1054
mbed_official	18:da299f395b9e	1055	/**
mbed_official	18:da299f395b9e	1056	* \brief Set bits in the clock mask for the AHB bus.
mbed_official	18:da299f395b9e	1057	*
mbed_official	18:da299f395b9e	1058	* This function will set bits in the clock mask for the AHB bus.
mbed_official	18:da299f395b9e	1059	* Any bits set to 1 will enable that clock, 0 bits in the mask
mbed_official	18:da299f395b9e	1060	* will be ignored
mbed_official	18:da299f395b9e	1061	*
mbed_official	18:da299f395b9e	1062	* \param[in] ahb_mask AHB clock mask to enable
mbed_official	18:da299f395b9e	1063	*/
mbed_official	18:da299f395b9e	1064	static inline void system_ahb_clock_set_mask(
mbed_official	18:da299f395b9e	1065	const uint32_t ahb_mask)
mbed_official	18:da299f395b9e	1066	{
mbed_official	18:da299f395b9e	1067	MCLK->AHBMASK.reg \|= ahb_mask;
mbed_official	18:da299f395b9e	1068	}
mbed_official	18:da299f395b9e	1069
mbed_official	18:da299f395b9e	1070	/**
mbed_official	18:da299f395b9e	1071	* \brief Clear bits in the clock mask for the AHB bus.
mbed_official	18:da299f395b9e	1072	*
mbed_official	18:da299f395b9e	1073	* This function will clear bits in the clock mask for the AHB bus.
mbed_official	18:da299f395b9e	1074	* Any bits set to 1 will disable that clock, zero bits in the mask
mbed_official	18:da299f395b9e	1075	* will be ignored.
mbed_official	18:da299f395b9e	1076	*
mbed_official	18:da299f395b9e	1077	* \param[in] ahb_mask AHB clock mask to disable
mbed_official	18:da299f395b9e	1078	*/
mbed_official	18:da299f395b9e	1079	static inline void system_ahb_clock_clear_mask(
mbed_official	18:da299f395b9e	1080	const uint32_t ahb_mask)
mbed_official	18:da299f395b9e	1081	{
mbed_official	18:da299f395b9e	1082	MCLK->AHBMASK.reg &= ~ahb_mask;
mbed_official	18:da299f395b9e	1083	}
mbed_official	18:da299f395b9e	1084
mbed_official	18:da299f395b9e	1085	/**
mbed_official	18:da299f395b9e	1086	* \brief Set bits in the clock mask for an APBx bus.
mbed_official	18:da299f395b9e	1087	*
mbed_official	18:da299f395b9e	1088	* This function will set bits in the clock mask for an APBx bus.
mbed_official	18:da299f395b9e	1089	* Any bits set to 1 will enable the corresponding module clock, zero bits in
mbed_official	18:da299f395b9e	1090	* the mask will be ignored.
mbed_official	18:da299f395b9e	1091	*
mbed_official	18:da299f395b9e	1092	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	18:da299f395b9e	1093	* the device header files
mbed_official	18:da299f395b9e	1094	* \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
mbed_official	18:da299f395b9e	1095	* constants from the device header files
mbed_official	18:da299f395b9e	1096	*
mbed_official	18:da299f395b9e	1097	* \returns Status indicating the result of the clock mask change operation.
mbed_official	18:da299f395b9e	1098	*
mbed_official	18:da299f395b9e	1099	* \retval STATUS_ERR_INVALID_ARG Invalid bus given
mbed_official	18:da299f395b9e	1100	* \retval STATUS_OK The clock mask was set successfully
mbed_official	18:da299f395b9e	1101	*/
mbed_official	18:da299f395b9e	1102	static inline enum status_code system_apb_clock_set_mask(
mbed_official	18:da299f395b9e	1103	const enum system_clock_apb_bus bus,
mbed_official	18:da299f395b9e	1104	const uint32_t mask)
mbed_official	18:da299f395b9e	1105	{
mbed_official	18:da299f395b9e	1106	switch (bus) {
mbed_official	18:da299f395b9e	1107	case SYSTEM_CLOCK_APB_APBA:
mbed_official	18:da299f395b9e	1108	MCLK->APBAMASK.reg \|= mask;
mbed_official	18:da299f395b9e	1109	break;
mbed_official	18:da299f395b9e	1110
mbed_official	18:da299f395b9e	1111	case SYSTEM_CLOCK_APB_APBB:
mbed_official	18:da299f395b9e	1112	MCLK->APBBMASK.reg \|= mask;
mbed_official	18:da299f395b9e	1113	break;
mbed_official	18:da299f395b9e	1114
mbed_official	18:da299f395b9e	1115	case SYSTEM_CLOCK_APB_APBC:
mbed_official	18:da299f395b9e	1116	MCLK->APBCMASK.reg \|= mask;
mbed_official	18:da299f395b9e	1117	break;
mbed_official	18:da299f395b9e	1118	case SYSTEM_CLOCK_APB_APBD:
mbed_official	18:da299f395b9e	1119	MCLK->APBDMASK.reg \|= mask;
mbed_official	18:da299f395b9e	1120	break;
mbed_official	18:da299f395b9e	1121	case SYSTEM_CLOCK_APB_APBE:
mbed_official	18:da299f395b9e	1122	MCLK->APBEMASK.reg \|= mask;
mbed_official	18:da299f395b9e	1123	break;
mbed_official	18:da299f395b9e	1124	default:
mbed_official	18:da299f395b9e	1125	Assert(false);
mbed_official	18:da299f395b9e	1126	return STATUS_ERR_INVALID_ARG;
mbed_official	18:da299f395b9e	1127
mbed_official	18:da299f395b9e	1128	}
mbed_official	18:da299f395b9e	1129
mbed_official	18:da299f395b9e	1130	return STATUS_OK;
mbed_official	18:da299f395b9e	1131	}
mbed_official	18:da299f395b9e	1132
mbed_official	18:da299f395b9e	1133	/**
mbed_official	18:da299f395b9e	1134	* \brief Clear bits in the clock mask for an APBx bus.
mbed_official	18:da299f395b9e	1135	*
mbed_official	18:da299f395b9e	1136	* This function will clear bits in the clock mask for an APBx bus.
mbed_official	18:da299f395b9e	1137	* Any bits set to 1 will disable the corresponding module clock, zero bits in
mbed_official	18:da299f395b9e	1138	* the mask will be ignored.
mbed_official	18:da299f395b9e	1139	*
mbed_official	18:da299f395b9e	1140	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	18:da299f395b9e	1141	* the device header files
mbed_official	18:da299f395b9e	1142	* \param[in] bus Bus to clear clock mask bits
mbed_official	18:da299f395b9e	1143	*
mbed_official	18:da299f395b9e	1144	* \returns Status indicating the result of the clock mask change operation.
mbed_official	18:da299f395b9e	1145	*
mbed_official	18:da299f395b9e	1146	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given.
mbed_official	18:da299f395b9e	1147	* \retval STATUS_OK The clock mask was changed successfully.
mbed_official	18:da299f395b9e	1148	*/
mbed_official	18:da299f395b9e	1149	static inline enum status_code system_apb_clock_clear_mask(
mbed_official	18:da299f395b9e	1150	const enum system_clock_apb_bus bus,
mbed_official	18:da299f395b9e	1151	const uint32_t mask)
mbed_official	18:da299f395b9e	1152	{
mbed_official	18:da299f395b9e	1153	switch (bus) {
mbed_official	18:da299f395b9e	1154	case SYSTEM_CLOCK_APB_APBA:
mbed_official	18:da299f395b9e	1155	MCLK->APBAMASK.reg &= ~mask;
mbed_official	18:da299f395b9e	1156	break;
mbed_official	18:da299f395b9e	1157
mbed_official	18:da299f395b9e	1158	case SYSTEM_CLOCK_APB_APBB:
mbed_official	18:da299f395b9e	1159	MCLK->APBBMASK.reg &= ~mask;
mbed_official	18:da299f395b9e	1160	break;
mbed_official	18:da299f395b9e	1161
mbed_official	18:da299f395b9e	1162	case SYSTEM_CLOCK_APB_APBC:
mbed_official	18:da299f395b9e	1163	MCLK->APBCMASK.reg &= ~mask;
mbed_official	18:da299f395b9e	1164	break;
mbed_official	18:da299f395b9e	1165	case SYSTEM_CLOCK_APB_APBD:
mbed_official	18:da299f395b9e	1166	MCLK->APBDMASK.reg &= ~mask;
mbed_official	18:da299f395b9e	1167	break;
mbed_official	18:da299f395b9e	1168	case SYSTEM_CLOCK_APB_APBE:
mbed_official	18:da299f395b9e	1169	MCLK->APBEMASK.reg &= ~mask;
mbed_official	18:da299f395b9e	1170	break;
mbed_official	18:da299f395b9e	1171	default:
mbed_official	18:da299f395b9e	1172	Assert(false);
mbed_official	18:da299f395b9e	1173	return STATUS_ERR_INVALID_ARG;
mbed_official	18:da299f395b9e	1174	}
mbed_official	18:da299f395b9e	1175
mbed_official	18:da299f395b9e	1176	return STATUS_OK;
mbed_official	18:da299f395b9e	1177	}
mbed_official	18:da299f395b9e	1178
mbed_official	18:da299f395b9e	1179	/**
mbed_official	18:da299f395b9e	1180	* @}
mbed_official	18:da299f395b9e	1181	*/
mbed_official	18:da299f395b9e	1182
mbed_official	18:da299f395b9e	1183	/**
mbed_official	18:da299f395b9e	1184	* \brief Reference clock source of the DPLL module.
mbed_official	18:da299f395b9e	1185	*/
mbed_official	18:da299f395b9e	1186	enum system_clock_source_dpll_reference_clock {
mbed_official	18:da299f395b9e	1187	/** Select XOSC32K as clock reference */
mbed_official	18:da299f395b9e	1188	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
mbed_official	18:da299f395b9e	1189	/** Select XOSC as clock reference */
mbed_official	18:da299f395b9e	1190	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
mbed_official	18:da299f395b9e	1191	/** Select GCLK as clock reference */
mbed_official	18:da299f395b9e	1192	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
mbed_official	18:da299f395b9e	1193	};
mbed_official	18:da299f395b9e	1194
mbed_official	18:da299f395b9e	1195	/**
mbed_official	18:da299f395b9e	1196	* \brief Lock time-out value of the DPLL module.
mbed_official	18:da299f395b9e	1197	*/
mbed_official	18:da299f395b9e	1198	enum system_clock_source_dpll_lock_time {
mbed_official	18:da299f395b9e	1199	/** Set no time-out as default */
mbed_official	18:da299f395b9e	1200	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
mbed_official	18:da299f395b9e	1201	/** Set time-out if no lock within 8ms */
mbed_official	18:da299f395b9e	1202	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
mbed_official	18:da299f395b9e	1203	/** Set time-out if no lock within 9ms */
mbed_official	18:da299f395b9e	1204	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
mbed_official	18:da299f395b9e	1205	/** Set time-out if no lock within 10ms */
mbed_official	18:da299f395b9e	1206	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
mbed_official	18:da299f395b9e	1207	/** Set time-out if no lock within 11ms */
mbed_official	18:da299f395b9e	1208	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
mbed_official	18:da299f395b9e	1209	};
mbed_official	18:da299f395b9e	1210
mbed_official	18:da299f395b9e	1211	/**
mbed_official	18:da299f395b9e	1212	* \brief Filter type of the DPLL module.
mbed_official	18:da299f395b9e	1213	*/
mbed_official	18:da299f395b9e	1214	enum system_clock_source_dpll_filter {
mbed_official	18:da299f395b9e	1215	/** Default filter mode */
mbed_official	18:da299f395b9e	1216	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
mbed_official	18:da299f395b9e	1217	/** Low bandwidth filter */
mbed_official	18:da299f395b9e	1218	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
mbed_official	18:da299f395b9e	1219	/** High bandwidth filter */
mbed_official	18:da299f395b9e	1220	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
mbed_official	18:da299f395b9e	1221	/** High damping filter */
mbed_official	18:da299f395b9e	1222	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
mbed_official	18:da299f395b9e	1223	};
mbed_official	18:da299f395b9e	1224
mbed_official	18:da299f395b9e	1225	/**
mbed_official	18:da299f395b9e	1226	* \brief DPLL Output Clock Prescaler.
mbed_official	18:da299f395b9e	1227	*/
mbed_official	18:da299f395b9e	1228	enum system_clock_source_dpll_prescaler {
mbed_official	18:da299f395b9e	1229	/** DPLL output is divided by 1 */
mbed_official	18:da299f395b9e	1230	SYSTEM_CLOCK_SOURCE_DPLL_DIV_1,
mbed_official	18:da299f395b9e	1231	/** DPLL output is divided by 2 */
mbed_official	18:da299f395b9e	1232	SYSTEM_CLOCK_SOURCE_DPLL_DIV_2,
mbed_official	18:da299f395b9e	1233	/** DPLL output is divided by 4 */
mbed_official	18:da299f395b9e	1234	SYSTEM_CLOCK_SOURCE_DPLL_DIV_4,
mbed_official	18:da299f395b9e	1235	};
mbed_official	18:da299f395b9e	1236
mbed_official	18:da299f395b9e	1237	/**
mbed_official	18:da299f395b9e	1238	* \brief Configuration structure for DPLL.
mbed_official	18:da299f395b9e	1239	*
mbed_official	18:da299f395b9e	1240	* DPLL oscillator configuration structure.
mbed_official	18:da299f395b9e	1241	*/
mbed_official	18:da299f395b9e	1242	struct system_clock_source_dpll_config {
mbed_official	18:da299f395b9e	1243	/** Run On Demand. If this is set the DPLL won't run
mbed_official	18:da299f395b9e	1244	* until requested by a peripheral */
mbed_official	18:da299f395b9e	1245	bool on_demand;
mbed_official	18:da299f395b9e	1246	/** Keep the DPLL enabled in standby sleep mode */
mbed_official	18:da299f395b9e	1247	bool run_in_standby;
mbed_official	18:da299f395b9e	1248	/** Bypass lock signal */
mbed_official	18:da299f395b9e	1249	bool lock_bypass;
mbed_official	18:da299f395b9e	1250	/** Wake up fast. If this is set DPLL output clock is enabled after
mbed_official	18:da299f395b9e	1251	* the start-up time */
mbed_official	18:da299f395b9e	1252	bool wake_up_fast;
mbed_official	18:da299f395b9e	1253	/** Enable low power mode */
mbed_official	18:da299f395b9e	1254	bool low_power_enable;
mbed_official	18:da299f395b9e	1255
mbed_official	18:da299f395b9e	1256	/** Output frequency of the clock */
mbed_official	18:da299f395b9e	1257	uint32_t output_frequency;
mbed_official	18:da299f395b9e	1258	/** Reference frequency of the clock */
mbed_official	18:da299f395b9e	1259	uint32_t reference_frequency;
mbed_official	18:da299f395b9e	1260	/** Devider of reference clock */
mbed_official	18:da299f395b9e	1261	uint16_t reference_divider;
mbed_official	18:da299f395b9e	1262
mbed_official	18:da299f395b9e	1263	/** Filter type of the DPLL module */
mbed_official	18:da299f395b9e	1264	enum system_clock_source_dpll_filter filter;
mbed_official	18:da299f395b9e	1265	/** Lock time-out value of the DPLL module */
mbed_official	18:da299f395b9e	1266	enum system_clock_source_dpll_lock_time lock_time;
mbed_official	18:da299f395b9e	1267	/** Reference clock source of the DPLL module */
mbed_official	18:da299f395b9e	1268	enum system_clock_source_dpll_reference_clock reference_clock;
mbed_official	18:da299f395b9e	1269	/** DPLL prescaler */
mbed_official	18:da299f395b9e	1270	enum system_clock_source_dpll_prescaler prescaler;
mbed_official	18:da299f395b9e	1271	};
mbed_official	18:da299f395b9e	1272
mbed_official	18:da299f395b9e	1273	/**
mbed_official	18:da299f395b9e	1274	* \name Internal DPLL Management
mbed_official	18:da299f395b9e	1275	* @{
mbed_official	18:da299f395b9e	1276	*/
mbed_official	18:da299f395b9e	1277
mbed_official	18:da299f395b9e	1278	/**
mbed_official	18:da299f395b9e	1279	* \brief Retrieve the default configuration for DPLL.
mbed_official	18:da299f395b9e	1280	*
mbed_official	18:da299f395b9e	1281	* Fills a configuration structure with the default configuration for a
mbed_official	18:da299f395b9e	1282	* DPLL oscillator module:
mbed_official	18:da299f395b9e	1283	* - Run only when requested by peripheral (on demand)
mbed_official	18:da299f395b9e	1284	* - Don't run in STANDBY sleep mode
mbed_official	18:da299f395b9e	1285	* - Lock bypass disabled
mbed_official	18:da299f395b9e	1286	* - Fast wake up disabled
mbed_official	18:da299f395b9e	1287	* - Low power mode disabled
mbed_official	18:da299f395b9e	1288	* - Output frequency is 48MHz
mbed_official	18:da299f395b9e	1289	* - Reference clock frequency is 32768Hz
mbed_official	18:da299f395b9e	1290	* - Not divide reference clock
mbed_official	18:da299f395b9e	1291	* - Select REF0 as reference clock
mbed_official	18:da299f395b9e	1292	* - Set lock time to default mode
mbed_official	18:da299f395b9e	1293	* - Use default filter
mbed_official	18:da299f395b9e	1294	*
mbed_official	18:da299f395b9e	1295	* \param[out] config Configuration structure to fill with default values
mbed_official	18:da299f395b9e	1296	*/
mbed_official	18:da299f395b9e	1297	static inline void system_clock_source_dpll_get_config_defaults(
mbed_official	18:da299f395b9e	1298	struct system_clock_source_dpll_config *const config)
mbed_official	18:da299f395b9e	1299	{
mbed_official	18:da299f395b9e	1300	config->on_demand = true;
mbed_official	18:da299f395b9e	1301	config->run_in_standby = false;
mbed_official	18:da299f395b9e	1302	config->lock_bypass = false;
mbed_official	18:da299f395b9e	1303	config->wake_up_fast = false;
mbed_official	18:da299f395b9e	1304	config->low_power_enable = false;
mbed_official	18:da299f395b9e	1305
mbed_official	18:da299f395b9e	1306	config->output_frequency = 48000000;
mbed_official	18:da299f395b9e	1307	config->reference_frequency = 32768;
mbed_official	18:da299f395b9e	1308	config->reference_divider = 1;
mbed_official	18:da299f395b9e	1309	config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK;
mbed_official	18:da299f395b9e	1310	config->prescaler = SYSTEM_CLOCK_SOURCE_DPLL_DIV_1;
mbed_official	18:da299f395b9e	1311
mbed_official	18:da299f395b9e	1312	config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
mbed_official	18:da299f395b9e	1313	config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
mbed_official	18:da299f395b9e	1314	};
mbed_official	18:da299f395b9e	1315
mbed_official	18:da299f395b9e	1316	void system_clock_source_dpll_set_config(
mbed_official	18:da299f395b9e	1317	struct system_clock_source_dpll_config *const config);
mbed_official	18:da299f395b9e	1318
mbed_official	18:da299f395b9e	1319	/* @} */
mbed_official	18:da299f395b9e	1320
mbed_official	18:da299f395b9e	1321	/**
mbed_official	18:da299f395b9e	1322	* \name System Clock Initialization
mbed_official	18:da299f395b9e	1323	* @{
mbed_official	18:da299f395b9e	1324	*/
mbed_official	18:da299f395b9e	1325
mbed_official	18:da299f395b9e	1326	void system_clock_init(void);
mbed_official	18:da299f395b9e	1327
mbed_official	18:da299f395b9e	1328	/**
mbed_official	18:da299f395b9e	1329	* @}
mbed_official	18:da299f395b9e	1330	*/
mbed_official	18:da299f395b9e	1331
mbed_official	18:da299f395b9e	1332	/**
mbed_official	18:da299f395b9e	1333	* \name System Flash Wait States
mbed_official	18:da299f395b9e	1334	* @{
mbed_official	18:da299f395b9e	1335	*/
mbed_official	18:da299f395b9e	1336
mbed_official	18:da299f395b9e	1337	/**
mbed_official	18:da299f395b9e	1338	* \brief Set flash controller wait states.
mbed_official	18:da299f395b9e	1339	*
mbed_official	18:da299f395b9e	1340	* Will set the number of wait states that are used by the onboard
mbed_official	18:da299f395b9e	1341	* flash memory. The number of wait states depend on both device
mbed_official	18:da299f395b9e	1342	* supply voltage and CPU speed. The required number of wait states
mbed_official	18:da299f395b9e	1343	* can be found in the electrical characteristics of the device.
mbed_official	18:da299f395b9e	1344	*
mbed_official	18:da299f395b9e	1345	* \param[in] wait_states Number of wait states to use for internal flash
mbed_official	18:da299f395b9e	1346	*/
mbed_official	18:da299f395b9e	1347	static inline void system_flash_set_waitstates(uint8_t wait_states)
mbed_official	18:da299f395b9e	1348	{
mbed_official	18:da299f395b9e	1349	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
mbed_official	18:da299f395b9e	1350	((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
mbed_official	18:da299f395b9e	1351
mbed_official	18:da299f395b9e	1352	NVMCTRL->CTRLB.bit.RWS = wait_states;
mbed_official	18:da299f395b9e	1353	}
mbed_official	18:da299f395b9e	1354	/**
mbed_official	18:da299f395b9e	1355	* @}
mbed_official	18:da299f395b9e	1356	*/
mbed_official	18:da299f395b9e	1357
mbed_official	18:da299f395b9e	1358	/**
mbed_official	18:da299f395b9e	1359	* @}
mbed_official	18:da299f395b9e	1360	*/
mbed_official	18:da299f395b9e	1361
mbed_official	18:da299f395b9e	1362	/**
mbed_official	18:da299f395b9e	1363	* \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
mbed_official	18:da299f395b9e	1364	*
mbed_official	18:da299f395b9e	1365	* \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
mbed_official	18:da299f395b9e	1366	* Below is a table listing the acronyms used in this module, along with their
mbed_official	18:da299f395b9e	1367	* intended meanings.
mbed_official	18:da299f395b9e	1368	*
mbed_official	18:da299f395b9e	1369	* <table>
mbed_official	18:da299f395b9e	1370	* <tr>
mbed_official	18:da299f395b9e	1371	* <th>Acronym</th>
mbed_official	18:da299f395b9e	1372	* <th>Description</th>
mbed_official	18:da299f395b9e	1373	* </tr>
mbed_official	18:da299f395b9e	1374	* <tr>
mbed_official	18:da299f395b9e	1375	* <td>DFLL</td>
mbed_official	18:da299f395b9e	1376	* <td>Digital Frequency Locked Loop</td>
mbed_official	18:da299f395b9e	1377	* </tr>
mbed_official	18:da299f395b9e	1378	* <tr>
mbed_official	18:da299f395b9e	1379	* <td>MUX</td>
mbed_official	18:da299f395b9e	1380	* <td>Multiplexer</td>
mbed_official	18:da299f395b9e	1381	* </tr>
mbed_official	18:da299f395b9e	1382	* <tr>
mbed_official	18:da299f395b9e	1383	* <td>MCLK</td>
mbed_official	18:da299f395b9e	1384	* <td>Main Clock</td>
mbed_official	18:da299f395b9e	1385	* </tr>
mbed_official	18:da299f395b9e	1386	* <tr>
mbed_official	18:da299f395b9e	1387	* <td>OSC32K</td>
mbed_official	18:da299f395b9e	1388	* <td>Internal 32KHz Oscillator</td>
mbed_official	18:da299f395b9e	1389	* </tr>
mbed_official	18:da299f395b9e	1390	* <tr>
mbed_official	18:da299f395b9e	1391	* <td>OSC16M</td>
mbed_official	18:da299f395b9e	1392	* <td>Internal 16MHz Oscillator</td>
mbed_official	18:da299f395b9e	1393	* </tr>
mbed_official	18:da299f395b9e	1394	* <tr>
mbed_official	18:da299f395b9e	1395	* <td>PLL</td>
mbed_official	18:da299f395b9e	1396	* <td>Phase Locked Loop</td>
mbed_official	18:da299f395b9e	1397	* </tr>
mbed_official	18:da299f395b9e	1398	* <tr>
mbed_official	18:da299f395b9e	1399	* <td>OSC</td>
mbed_official	18:da299f395b9e	1400	* <td>Oscillator</td>
mbed_official	18:da299f395b9e	1401	* </tr>
mbed_official	18:da299f395b9e	1402	* <tr>
mbed_official	18:da299f395b9e	1403	* <td>XOSC</td>
mbed_official	18:da299f395b9e	1404	* <td>External Oscillator</td>
mbed_official	18:da299f395b9e	1405	* </tr>
mbed_official	18:da299f395b9e	1406	* <tr>
mbed_official	18:da299f395b9e	1407	* <td>XOSC32K</td>
mbed_official	18:da299f395b9e	1408	* <td>External 32KHz Oscillator</td>
mbed_official	18:da299f395b9e	1409	* </tr>
mbed_official	18:da299f395b9e	1410	* <tr>
mbed_official	18:da299f395b9e	1411	* <td>AHB</td>
mbed_official	18:da299f395b9e	1412	* <td>Advanced High-performance Bus</td>
mbed_official	18:da299f395b9e	1413	* </tr>
mbed_official	18:da299f395b9e	1414	* <tr>
mbed_official	18:da299f395b9e	1415	* <td>APB</td>
mbed_official	18:da299f395b9e	1416	* <td>Advanced Peripheral Bus</td>
mbed_official	18:da299f395b9e	1417	* </tr>
mbed_official	18:da299f395b9e	1418	* <tr>
mbed_official	18:da299f395b9e	1419	* <td>DPLL</td>
mbed_official	18:da299f395b9e	1420	* <td>Digital Phase Locked Loop</td>
mbed_official	18:da299f395b9e	1421	* </tr>
mbed_official	18:da299f395b9e	1422	* </table>
mbed_official	18:da299f395b9e	1423	*
mbed_official	18:da299f395b9e	1424	*
mbed_official	18:da299f395b9e	1425	* \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
mbed_official	18:da299f395b9e	1426	* This driver has the following dependencies:
mbed_official	18:da299f395b9e	1427	*
mbed_official	18:da299f395b9e	1428	* - None
mbed_official	18:da299f395b9e	1429	*
mbed_official	18:da299f395b9e	1430	*
mbed_official	18:da299f395b9e	1431	* \section asfdoc_sam0_system_clock_extra_errata Errata
mbed_official	18:da299f395b9e	1432	*
mbed_official	18:da299f395b9e	1433	* - This driver implements experimental workaround for errata 9905
mbed_official	18:da299f395b9e	1434	*
mbed_official	18:da299f395b9e	1435	* "The DFLL clock must be requested before being configured. Otherwise a
mbed_official	18:da299f395b9e	1436	* write access to a DFLL register can freeze the device."
mbed_official	18:da299f395b9e	1437	* This driver will enable and configure the DFLL before the ONDEMAND bit is set.
mbed_official	18:da299f395b9e	1438	*
mbed_official	18:da299f395b9e	1439	*
mbed_official	18:da299f395b9e	1440	* \section asfdoc_sam0_system_clock_extra_history Module History
mbed_official	18:da299f395b9e	1441	* An overview of the module history is presented in the table below, with
mbed_official	18:da299f395b9e	1442	* details on the enhancements and fixes made to the module since its first
mbed_official	18:da299f395b9e	1443	* release. The current version of this corresponds to the newest version in
mbed_official	18:da299f395b9e	1444	* the table.
mbed_official	18:da299f395b9e	1445	*
mbed_official	18:da299f395b9e	1446	* <table>
mbed_official	18:da299f395b9e	1447	* <tr>
mbed_official	18:da299f395b9e	1448	* <th>Changelog</th>
mbed_official	18:da299f395b9e	1449	* </tr>
mbed_official	18:da299f395b9e	1450	* <tr>
mbed_official	18:da299f395b9e	1451	* <td>Initial Release</td>
mbed_official	18:da299f395b9e	1452	* </tr>
mbed_official	18:da299f395b9e	1453	* </table>
mbed_official	18:da299f395b9e	1454	*/
mbed_official	18:da299f395b9e	1455
mbed_official	18:da299f395b9e	1456	/**
mbed_official	18:da299f395b9e	1457	* \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
mbed_official	18:da299f395b9e	1458	*
mbed_official	18:da299f395b9e	1459	* This is a list of the available Quick Start guides (QSGs) and example
mbed_official	18:da299f395b9e	1460	* applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
mbed_official	18:da299f395b9e	1461	* examples with step-by-step instructions to configure and use this driver in
mbed_official	18:da299f395b9e	1462	* a selection of use cases. Note that a QSG can be compiled as a standalone
mbed_official	18:da299f395b9e	1463	* application or be added to the user application.
mbed_official	18:da299f395b9e	1464	*
mbed_official	18:da299f395b9e	1465	* - \subpage asfdoc_sam0_system_clock_basic_use_case
mbed_official	18:da299f395b9e	1466	* - \subpage asfdoc_sam0_system_gclk_basic_use_case
mbed_official	18:da299f395b9e	1467	*
mbed_official	18:da299f395b9e	1468	* \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
mbed_official	18:da299f395b9e	1469	*
mbed_official	18:da299f395b9e	1470	* <table>
mbed_official	18:da299f395b9e	1471	* <tr>
mbed_official	18:da299f395b9e	1472	* <th>Doc. Rev.</td>
mbed_official	18:da299f395b9e	1473	* <th>Date</td>
mbed_official	18:da299f395b9e	1474	* <th>Comments</td>
mbed_official	18:da299f395b9e	1475	* </tr>
mbed_official	18:da299f395b9e	1476	* <tr>
mbed_official	18:da299f395b9e	1477	* <td>42452A</td>
mbed_official	18:da299f395b9e	1478	* <td>06/2015</td>
mbed_official	18:da299f395b9e	1479	* <td>Initial document release</td>
mbed_official	18:da299f395b9e	1480	* </tr>
mbed_official	18:da299f395b9e	1481	* </table>
mbed_official	18:da299f395b9e	1482	*/
mbed_official	18:da299f395b9e	1483
mbed_official	18:da299f395b9e	1484	#ifdef __cplusplus
mbed_official	18:da299f395b9e	1485	}
mbed_official	18:da299f395b9e	1486	#endif
mbed_official	18:da299f395b9e	1487
mbed_official	18:da299f395b9e	1488	#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */

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Type:	Library
Created:	07 Aug 2016
Imports:	4
Forks:	0
Commits:	145
Dependents:	0
Dependencies:	0
Followers:	1

targets/hal/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/clock/TARGET_SAML21/clock_feature.h@18:da299f395b9e, 2015-11-09 (annotated)

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