mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f30x.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 27-February-2014
bogdanm	0:9b334a45a8ff	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
bogdanm	0:9b334a45a8ff	8	* This file contains all the peripheral registers definitions, bits
bogdanm	0:9b334a45a8ff	9	* definitions and memory mapping for STM32F30x devices.
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* The file is the unique include file that the application programmer
bogdanm	0:9b334a45a8ff	12	* is using in the C source code, usually in main.c. This file contains:
bogdanm	0:9b334a45a8ff	13	* - Configuration section that allows to select:
bogdanm	0:9b334a45a8ff	14	* - The device used in the target application
bogdanm	0:9b334a45a8ff	15	* - To use or not the peripherals drivers in application code(i.e.
bogdanm	0:9b334a45a8ff	16	* code will be based on direct access to peripherals registers
bogdanm	0:9b334a45a8ff	17	* rather than drivers API), this option is controlled by
bogdanm	0:9b334a45a8ff	18	* "#define USE_STDPERIPH_DRIVER"
bogdanm	0:9b334a45a8ff	19	* - To change few application-specific parameters such as the HSE
bogdanm	0:9b334a45a8ff	20	* crystal frequency
bogdanm	0:9b334a45a8ff	21	* - Data structures and the address mapping for all peripherals
bogdanm	0:9b334a45a8ff	22	* - Peripheral registers declarations and bits definition
bogdanm	0:9b334a45a8ff	23	* - Macros to access peripheral registers hardware
bogdanm	0:9b334a45a8ff	24	*
bogdanm	0:9b334a45a8ff	25	******************************************************************************
bogdanm	0:9b334a45a8ff	26	* @attention
bogdanm	0:9b334a45a8ff	27	*
bogdanm	0:9b334a45a8ff	28	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	29	*
bogdanm	0:9b334a45a8ff	30	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	31	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	32	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	33	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	34	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	35	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	36	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	37	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	38	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	39	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	40	*
bogdanm	0:9b334a45a8ff	41	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	42	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	43	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	44	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	45	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	46	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	47	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	48	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	49	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	50	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	51	*
bogdanm	0:9b334a45a8ff	52	******************************************************************************
bogdanm	0:9b334a45a8ff	53	*/
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	/** @addtogroup CMSIS
bogdanm	0:9b334a45a8ff	56	* @{
bogdanm	0:9b334a45a8ff	57	*/
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/** @addtogroup stm32f30x
bogdanm	0:9b334a45a8ff	60	* @{
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	#ifndef __STM32F30x_H
bogdanm	0:9b334a45a8ff	64	#define __STM32F30x_H
bogdanm	0:9b334a45a8ff	65
bogdanm	0:9b334a45a8ff	66	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	67	extern "C" {
bogdanm	0:9b334a45a8ff	68	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	/** @addtogroup Library_configuration_section
bogdanm	0:9b334a45a8ff	71	* @{
bogdanm	0:9b334a45a8ff	72	*/
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	/* Uncomment the line below according to the target STM32 device used in your
bogdanm	0:9b334a45a8ff	75	application
bogdanm	0:9b334a45a8ff	76	*/
bogdanm	0:9b334a45a8ff	77
bogdanm	0:9b334a45a8ff	78	#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8)
bogdanm	0:9b334a45a8ff	79	#define STM32F303xC /!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices /
bogdanm	0:9b334a45a8ff	80	/* #define STM32F334x8 / /!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
bogdanm	0:9b334a45a8ff	81	/* #define STM32F302x8 / /!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8,
bogdanm	0:9b334a45a8ff	82	STM32F302R4, STM32F302R6 and STM32F302R8 Devices */
bogdanm	0:9b334a45a8ff	83	#endif
bogdanm	0:9b334a45a8ff	84
bogdanm	0:9b334a45a8ff	85	/* Tip: To avoid modifying this file each time you need to switch between these
bogdanm	0:9b334a45a8ff	86	devices, you can define the device in your toolchain compiler preprocessor.
bogdanm	0:9b334a45a8ff	87	*/
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/* Old STM32F30X definition, maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	90	#if defined(STM32F30X)
bogdanm	0:9b334a45a8ff	91	#define STM32F303xC
bogdanm	0:9b334a45a8ff	92	#endif /* STM32F30X */
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8)
bogdanm	0:9b334a45a8ff	95	#error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
bogdanm	0:9b334a45a8ff	96	#endif
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	#if !defined (USE_STDPERIPH_DRIVER)
bogdanm	0:9b334a45a8ff	99	/**
bogdanm	0:9b334a45a8ff	100	* @brief Comment the line below if you will not use the peripherals drivers.
bogdanm	0:9b334a45a8ff	101	In this case, these drivers will not be included and the application code will
bogdanm	0:9b334a45a8ff	102	be based on direct access to peripherals registers
bogdanm	0:9b334a45a8ff	103	*/
bogdanm	0:9b334a45a8ff	104	#define USE_STDPERIPH_DRIVER
bogdanm	0:9b334a45a8ff	105	#endif /* USE_STDPERIPH_DRIVER */
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	/**
bogdanm	0:9b334a45a8ff	108	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
bogdanm	0:9b334a45a8ff	109	used in your application
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	Tip: To avoid modifying this file each time you need to use different HSE, you
bogdanm	0:9b334a45a8ff	112	can define the HSE value in your toolchain compiler preprocessor.
bogdanm	0:9b334a45a8ff	113	*/
bogdanm	0:9b334a45a8ff	114	#if !defined (HSE_VALUE)
bogdanm	0:9b334a45a8ff	115	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External xtal in Hz /
bogdanm	0:9b334a45a8ff	116	#endif /* HSE_VALUE */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/**
bogdanm	0:9b334a45a8ff	119	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
bogdanm	0:9b334a45a8ff	120	Timeout value
bogdanm	0:9b334a45a8ff	121	*/
bogdanm	0:9b334a45a8ff	122	#if !defined (HSE_STARTUP_TIMEOUT)
bogdanm	0:9b334a45a8ff	123	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSE start up /
bogdanm	0:9b334a45a8ff	124	#endif /* HSE_STARTUP_TIMEOUT */
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	/**
bogdanm	0:9b334a45a8ff	127	* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
bogdanm	0:9b334a45a8ff	128	Timeout value
bogdanm	0:9b334a45a8ff	129	*/
bogdanm	0:9b334a45a8ff	130	#if !defined (HSI_STARTUP_TIMEOUT)
bogdanm	0:9b334a45a8ff	131	#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSI start up /
bogdanm	0:9b334a45a8ff	132	#endif /* HSI_STARTUP_TIMEOUT */
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	#if !defined (HSI_VALUE)
bogdanm	0:9b334a45a8ff	135	#define HSI_VALUE ((uint32_t)8000000)
bogdanm	0:9b334a45a8ff	136	#endif /* HSI_VALUE / /!< Value of the Internal High Speed oscillator in Hz.
bogdanm	0:9b334a45a8ff	137	The real value may vary depending on the variations
bogdanm	0:9b334a45a8ff	138	in voltage and temperature. */
bogdanm	0:9b334a45a8ff	139	#if !defined (LSI_VALUE)
bogdanm	0:9b334a45a8ff	140	#define LSI_VALUE ((uint32_t)40000)
bogdanm	0:9b334a45a8ff	141	#endif /* LSI_VALUE / /!< Value of the Internal Low Speed oscillator in Hz
bogdanm	0:9b334a45a8ff	142	The real value may vary depending on the variations
bogdanm	0:9b334a45a8ff	143	in voltage and temperature. */
bogdanm	0:9b334a45a8ff	144	#if !defined (LSE_VALUE)
bogdanm	0:9b334a45a8ff	145	#define LSE_VALUE ((uint32_t)32768) /!< Value of the External Low Speed oscillator in Hz /
bogdanm	0:9b334a45a8ff	146	#endif /* LSE_VALUE */
bogdanm	0:9b334a45a8ff	147
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	/**
bogdanm	0:9b334a45a8ff	150	* @brief STM32F30x Standard Peripherals Library version number V1.1.0
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152	#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
bogdanm	0:9b334a45a8ff	153	#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /!< [23:16] sub1 version /
bogdanm	0:9b334a45a8ff	154	#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
bogdanm	0:9b334a45a8ff	155	#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
bogdanm	0:9b334a45a8ff	156	#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
bogdanm	0:9b334a45a8ff	157	\|(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
bogdanm	0:9b334a45a8ff	158	\|(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
bogdanm	0:9b334a45a8ff	159	\|(__STM32F30X_STDPERIPH_VERSION_RC))
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	/**
bogdanm	0:9b334a45a8ff	162	* @}
bogdanm	0:9b334a45a8ff	163	*/
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	0:9b334a45a8ff	166	* @{
bogdanm	0:9b334a45a8ff	167	*/
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/**
bogdanm	0:9b334a45a8ff	170	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm	0:9b334a45a8ff	171	*/
bogdanm	0:9b334a45a8ff	172	#define __CM4_REV 0x0001 /!< Core revision r0p1 /
bogdanm	0:9b334a45a8ff	173	#define __MPU_PRESENT 1 /!< STM32F30X provide an MPU /
bogdanm	0:9b334a45a8ff	174	#define __NVIC_PRIO_BITS 4 /!< STM32F30X uses 4 Bits for the Priority Levels /
bogdanm	0:9b334a45a8ff	175	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	176	#define __FPU_PRESENT 1 /!< STM32F30X provide an FPU /
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	/**
bogdanm	0:9b334a45a8ff	180	* @brief STM32F30X Interrupt Number Definition, according to the selected device
bogdanm	0:9b334a45a8ff	181	* in @ref Library_configuration_section
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	typedef enum IRQn
bogdanm	0:9b334a45a8ff	184	{
bogdanm	0:9b334a45a8ff	185	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
bogdanm	0:9b334a45a8ff	186	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	0:9b334a45a8ff	187	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
bogdanm	0:9b334a45a8ff	188	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
bogdanm	0:9b334a45a8ff	189	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
bogdanm	0:9b334a45a8ff	190	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
bogdanm	0:9b334a45a8ff	191	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
bogdanm	0:9b334a45a8ff	192	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
bogdanm	0:9b334a45a8ff	193	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
bogdanm	0:9b334a45a8ff	194	/**** STM32 specific Interrupt Numbers ********************************************************************/
bogdanm	0:9b334a45a8ff	195	#ifdef STM32F303xC
bogdanm	0:9b334a45a8ff	196	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	197	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
bogdanm	0:9b334a45a8ff	198	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
bogdanm	0:9b334a45a8ff	199	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 /
bogdanm	0:9b334a45a8ff	200	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	201	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	202	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	0:9b334a45a8ff	203	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	0:9b334a45a8ff	204	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
bogdanm	0:9b334a45a8ff	205	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	0:9b334a45a8ff	206	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	0:9b334a45a8ff	207	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
bogdanm	0:9b334a45a8ff	208	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
bogdanm	0:9b334a45a8ff	209	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
bogdanm	0:9b334a45a8ff	210	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
bogdanm	0:9b334a45a8ff	211	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
bogdanm	0:9b334a45a8ff	212	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
bogdanm	0:9b334a45a8ff	213	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
bogdanm	0:9b334a45a8ff	214	ADC1_2_IRQn = 18, /!< ADC1 & ADC2 Interrupts /
bogdanm	0:9b334a45a8ff	215	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
bogdanm	0:9b334a45a8ff	216	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
bogdanm	0:9b334a45a8ff	217	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
bogdanm	0:9b334a45a8ff	218	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
bogdanm	0:9b334a45a8ff	219	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	0:9b334a45a8ff	220	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
bogdanm	0:9b334a45a8ff	221	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
bogdanm	0:9b334a45a8ff	222	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
bogdanm	0:9b334a45a8ff	223	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	224	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	225	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
bogdanm	0:9b334a45a8ff	226	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
bogdanm	0:9b334a45a8ff	227	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	0:9b334a45a8ff	228	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	0:9b334a45a8ff	229	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
bogdanm	0:9b334a45a8ff	230	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
bogdanm	0:9b334a45a8ff	231	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
bogdanm	0:9b334a45a8ff	232	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
bogdanm	0:9b334a45a8ff	233	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	0:9b334a45a8ff	234	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	0:9b334a45a8ff	235	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	0:9b334a45a8ff	236	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	0:9b334a45a8ff	237	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
bogdanm	0:9b334a45a8ff	238	USBWakeUp_IRQn = 42, /!< USB Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	239	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
bogdanm	0:9b334a45a8ff	240	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
bogdanm	0:9b334a45a8ff	241	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
bogdanm	0:9b334a45a8ff	242	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	243	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
bogdanm	0:9b334a45a8ff	244	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
bogdanm	0:9b334a45a8ff	245	UART4_IRQn = 52, /!< UART4 global Interrupt /
bogdanm	0:9b334a45a8ff	246	UART5_IRQn = 53, /!< UART5 global Interrupt /
bogdanm	0:9b334a45a8ff	247	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
bogdanm	0:9b334a45a8ff	248	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
bogdanm	0:9b334a45a8ff	249	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
bogdanm	0:9b334a45a8ff	250	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
bogdanm	0:9b334a45a8ff	251	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
bogdanm	0:9b334a45a8ff	252	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
bogdanm	0:9b334a45a8ff	253	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
bogdanm	0:9b334a45a8ff	254	ADC4_IRQn = 61, /!< ADC4 global Interrupt /
bogdanm	0:9b334a45a8ff	255	COMP1_2_3_IRQn = 64, /!< COMP1, COMP2 and COMP3 global Interrupt /
bogdanm	0:9b334a45a8ff	256	COMP4_5_6_IRQn = 65, /!< COMP5, COMP6 and COMP4 global Interrupt /
bogdanm	0:9b334a45a8ff	257	COMP7_IRQn = 66, /!< COMP7 global Interrupt /
bogdanm	0:9b334a45a8ff	258	USB_HP_IRQn = 74, /!< USB High Priority global Interrupt remap /
bogdanm	0:9b334a45a8ff	259	USB_LP_IRQn = 75, /!< USB Low Priority global Interrupt remap /
bogdanm	0:9b334a45a8ff	260	USBWakeUp_RMP_IRQn = 76, /!< USB Wakeup Interrupt remap /
bogdanm	0:9b334a45a8ff	261	FPU_IRQn = 81 /!< Floating point Interrupt /
bogdanm	0:9b334a45a8ff	262	#endif /* STM32F303xC */
bogdanm	0:9b334a45a8ff	263	#ifdef STM32F334x8
bogdanm	0:9b334a45a8ff	264	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	265	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
bogdanm	0:9b334a45a8ff	266	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
bogdanm	0:9b334a45a8ff	267	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 /
bogdanm	0:9b334a45a8ff	268	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	269	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	270	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	0:9b334a45a8ff	271	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	0:9b334a45a8ff	272	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
bogdanm	0:9b334a45a8ff	273	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	0:9b334a45a8ff	274	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	0:9b334a45a8ff	275	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
bogdanm	0:9b334a45a8ff	276	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
bogdanm	0:9b334a45a8ff	277	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
bogdanm	0:9b334a45a8ff	278	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
bogdanm	0:9b334a45a8ff	279	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
bogdanm	0:9b334a45a8ff	280	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
bogdanm	0:9b334a45a8ff	281	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
bogdanm	0:9b334a45a8ff	282	ADC1_2_IRQn = 18, /!< ADC1 & ADC2 Interrupts /
bogdanm	0:9b334a45a8ff	283	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupts /
bogdanm	0:9b334a45a8ff	284	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupts /
bogdanm	0:9b334a45a8ff	285	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
bogdanm	0:9b334a45a8ff	286	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
bogdanm	0:9b334a45a8ff	287	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	0:9b334a45a8ff	288	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
bogdanm	0:9b334a45a8ff	289	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
bogdanm	0:9b334a45a8ff	290	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
bogdanm	0:9b334a45a8ff	291	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	292	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	293	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
bogdanm	0:9b334a45a8ff	294	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	0:9b334a45a8ff	295	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	0:9b334a45a8ff	296	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
bogdanm	0:9b334a45a8ff	297	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	0:9b334a45a8ff	298	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	0:9b334a45a8ff	299	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	0:9b334a45a8ff	300	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	0:9b334a45a8ff	301	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
bogdanm	0:9b334a45a8ff	302	TIM6_DAC1_IRQn = 54, /!< TIM6 global and DAC1 underrun error interrupts /
bogdanm	0:9b334a45a8ff	303	TIM7_DAC2_IRQn = 55, /!< TIM7 global and DAC2 underrun error Interrupt /
bogdanm	0:9b334a45a8ff	304	COMP2_IRQn = 64, /!< COMP2 global Interrupt /
bogdanm	0:9b334a45a8ff	305	COMP4_6_IRQn = 65, /!< COMP6 and COMP4 global Interrupt /
bogdanm	0:9b334a45a8ff	306	HRTIM1_Master_IRQn = 67, /!< HRTIM Master Timer global Interrupts /
bogdanm	0:9b334a45a8ff	307	HRTIM1_TIMA_IRQn = 68, /!< HRTIM Timer A global Interrupt /
bogdanm	0:9b334a45a8ff	308	HRTIM1_TIMB_IRQn = 69, /!< HRTIM Timer B global Interrupt /
bogdanm	0:9b334a45a8ff	309	HRTIM1_TIMC_IRQn = 70, /!< HRTIM Timer C global Interrupt /
bogdanm	0:9b334a45a8ff	310	HRTIM1_TIMD_IRQn = 71, /!< HRTIM Timer D global Interrupt /
bogdanm	0:9b334a45a8ff	311	HRTIM1_TIME_IRQn = 72, /!< HRTIM Timer E global Interrupt /
bogdanm	0:9b334a45a8ff	312	HRTIM1_FLT_IRQn = 73, /!< HRTIM Fault global Interrupt /
bogdanm	0:9b334a45a8ff	313	FPU_IRQn = 81 /!< Floating point Interrupt /
bogdanm	0:9b334a45a8ff	314	#endif /* STM32F334x8 */
bogdanm	0:9b334a45a8ff	315	#ifdef STM32F302x8
bogdanm	0:9b334a45a8ff	316	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	0:9b334a45a8ff	317	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
bogdanm	0:9b334a45a8ff	318	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
bogdanm	0:9b334a45a8ff	319	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 20 /
bogdanm	0:9b334a45a8ff	320	FLASH_IRQn = 4, /!< FLASH global Interrupt /
bogdanm	0:9b334a45a8ff	321	RCC_IRQn = 5, /!< RCC global Interrupt /
bogdanm	0:9b334a45a8ff	322	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
bogdanm	0:9b334a45a8ff	323	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
bogdanm	0:9b334a45a8ff	324	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
bogdanm	0:9b334a45a8ff	325	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
bogdanm	0:9b334a45a8ff	326	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
bogdanm	0:9b334a45a8ff	327	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
bogdanm	0:9b334a45a8ff	328	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
bogdanm	0:9b334a45a8ff	329	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
bogdanm	0:9b334a45a8ff	330	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
bogdanm	0:9b334a45a8ff	331	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
bogdanm	0:9b334a45a8ff	332	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
bogdanm	0:9b334a45a8ff	333	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
bogdanm	0:9b334a45a8ff	334	ADC1_IRQn = 18, /!< ADC1 Interrupts /
bogdanm	0:9b334a45a8ff	335	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
bogdanm	0:9b334a45a8ff	336	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
bogdanm	0:9b334a45a8ff	337	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
bogdanm	0:9b334a45a8ff	338	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
bogdanm	0:9b334a45a8ff	339	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
bogdanm	0:9b334a45a8ff	340	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
bogdanm	0:9b334a45a8ff	341	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
bogdanm	0:9b334a45a8ff	342	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
bogdanm	0:9b334a45a8ff	343	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
bogdanm	0:9b334a45a8ff	344	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
bogdanm	0:9b334a45a8ff	345	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
bogdanm	0:9b334a45a8ff	346	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
bogdanm	0:9b334a45a8ff	347	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
bogdanm	0:9b334a45a8ff	348	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
bogdanm	0:9b334a45a8ff	349	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
bogdanm	0:9b334a45a8ff	350	USART1_IRQn = 37, /!< USART1 global Interrupt /
bogdanm	0:9b334a45a8ff	351	USART2_IRQn = 38, /!< USART2 global Interrupt /
bogdanm	0:9b334a45a8ff	352	USART3_IRQn = 39, /!< USART3 global Interrupt /
bogdanm	0:9b334a45a8ff	353	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
bogdanm	0:9b334a45a8ff	354	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
bogdanm	0:9b334a45a8ff	355	USBWakeUp_IRQn = 42, /!< USB Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	356	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
bogdanm	0:9b334a45a8ff	357	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
bogdanm	0:9b334a45a8ff	358	COMP2_IRQn = 64, /!< COMP2 global Interrupt /
bogdanm	0:9b334a45a8ff	359	COMP4_6_IRQn = 65, /!< COMP5, COMP6 and COMP4 global Interrupt /
bogdanm	0:9b334a45a8ff	360	COMP7_IRQn = 66, /!< COMP7 global Interrupt /
bogdanm	0:9b334a45a8ff	361	I2C3_EV_IRQn = 72, /!< I2C3 Event Interrupt /
bogdanm	0:9b334a45a8ff	362	I2C3_ER_IRQn = 73, /!< I2C3 Error Interrupt /
bogdanm	0:9b334a45a8ff	363	USB_HP_IRQn = 74, /!< USB High Priority global Interrupt remap /
bogdanm	0:9b334a45a8ff	364	USB_LP_IRQn = 75, /!< USB Low Priority global Interrupt remap /
bogdanm	0:9b334a45a8ff	365	USBWakeUp_RMP_IRQn = 76, /!< USB Wakeup Interrupt remap /
bogdanm	0:9b334a45a8ff	366	FPU_IRQn = 81 /!< Floating point Interrupt /
bogdanm	0:9b334a45a8ff	367	#endif /* STM32F302x8 */
bogdanm	0:9b334a45a8ff	368	} IRQn_Type;
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm	0:9b334a45a8ff	375	#include "system_stm32f30x.h" /* STM32F30x System Header */
bogdanm	0:9b334a45a8ff	376	#include <stdint.h>
bogdanm	0:9b334a45a8ff	377
bogdanm	0:9b334a45a8ff	378	/** @addtogroup Exported_types
bogdanm	0:9b334a45a8ff	379	* @{
bogdanm	0:9b334a45a8ff	380	*/
bogdanm	0:9b334a45a8ff	381	/!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) /
bogdanm	0:9b334a45a8ff	382	typedef int32_t s32;
bogdanm	0:9b334a45a8ff	383	typedef int16_t s16;
bogdanm	0:9b334a45a8ff	384	typedef int8_t s8;
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386	typedef const int32_t sc32; /!< Read Only /
bogdanm	0:9b334a45a8ff	387	typedef const int16_t sc16; /!< Read Only /
bogdanm	0:9b334a45a8ff	388	typedef const int8_t sc8; /!< Read Only /
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	typedef __IO int32_t vs32;
bogdanm	0:9b334a45a8ff	391	typedef __IO int16_t vs16;
bogdanm	0:9b334a45a8ff	392	typedef __IO int8_t vs8;
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	typedef __I int32_t vsc32; /!< Read Only /
bogdanm	0:9b334a45a8ff	395	typedef __I int16_t vsc16; /!< Read Only /
bogdanm	0:9b334a45a8ff	396	typedef __I int8_t vsc8; /!< Read Only /
bogdanm	0:9b334a45a8ff	397
bogdanm	0:9b334a45a8ff	398	typedef uint32_t u32;
bogdanm	0:9b334a45a8ff	399	typedef uint16_t u16;
bogdanm	0:9b334a45a8ff	400	typedef uint8_t u8;
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	typedef const uint32_t uc32; /!< Read Only /
bogdanm	0:9b334a45a8ff	403	typedef const uint16_t uc16; /!< Read Only /
bogdanm	0:9b334a45a8ff	404	typedef const uint8_t uc8; /!< Read Only /
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	typedef __IO uint32_t vu32;
bogdanm	0:9b334a45a8ff	407	typedef __IO uint16_t vu16;
bogdanm	0:9b334a45a8ff	408	typedef __IO uint8_t vu8;
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	typedef __I uint32_t vuc32; /!< Read Only /
bogdanm	0:9b334a45a8ff	411	typedef __I uint16_t vuc16; /!< Read Only /
bogdanm	0:9b334a45a8ff	412	typedef __I uint8_t vuc8; /!< Read Only /
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm	0:9b334a45a8ff	417	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
bogdanm	0:9b334a45a8ff	418
bogdanm	0:9b334a45a8ff	419	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/**
bogdanm	0:9b334a45a8ff	422	* @}
bogdanm	0:9b334a45a8ff	423	*/
bogdanm	0:9b334a45a8ff	424
bogdanm	0:9b334a45a8ff	425	/** @addtogroup Peripheral_registers_structures
bogdanm	0:9b334a45a8ff	426	* @{
bogdanm	0:9b334a45a8ff	427	*/
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/**
bogdanm	0:9b334a45a8ff	430	* @brief Analog to Digital Converter
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	typedef struct
bogdanm	0:9b334a45a8ff	434	{
bogdanm	0:9b334a45a8ff	435	__IO uint32_t ISR; /!< ADC Interrupt and Status Register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	436	__IO uint32_t IER; /!< ADC Interrupt Enable Register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	437	__IO uint32_t CR; /!< ADC control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	438	__IO uint32_t CFGR; /!< ADC Configuration register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	439	uint32_t RESERVED0; /!< Reserved, 0x010 /
bogdanm	0:9b334a45a8ff	440	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	441	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	442	uint32_t RESERVED1; /!< Reserved, 0x01C /
bogdanm	0:9b334a45a8ff	443	__IO uint32_t TR1; /!< ADC watchdog threshold register 1, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	444	__IO uint32_t TR2; /!< ADC watchdog threshold register 2, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	445	__IO uint32_t TR3; /!< ADC watchdog threshold register 3, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	446	uint32_t RESERVED2; /!< Reserved, 0x02C /
bogdanm	0:9b334a45a8ff	447	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	448	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	449	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	450	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	451	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	452	uint32_t RESERVED3; /!< Reserved, 0x044 /
bogdanm	0:9b334a45a8ff	453	uint32_t RESERVED4; /!< Reserved, 0x048 /
bogdanm	0:9b334a45a8ff	454	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	455	uint32_t RESERVED5[4]; /!< Reserved, 0x050 - 0x05C /
bogdanm	0:9b334a45a8ff	456	__IO uint32_t OFR1; /!< ADC offset register 1, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	457	__IO uint32_t OFR2; /!< ADC offset register 2, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	458	__IO uint32_t OFR3; /!< ADC offset register 3, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	459	__IO uint32_t OFR4; /!< ADC offset register 4, Address offset: 0x6C /
bogdanm	0:9b334a45a8ff	460	uint32_t RESERVED6[4]; /!< Reserved, 0x070 - 0x07C /
bogdanm	0:9b334a45a8ff	461	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	462	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	463	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	464	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	465	uint32_t RESERVED7[4]; /!< Reserved, 0x090 - 0x09C /
bogdanm	0:9b334a45a8ff	466	__IO uint32_t AWD2CR; /!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 /
bogdanm	0:9b334a45a8ff	467	__IO uint32_t AWD3CR; /!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 /
bogdanm	0:9b334a45a8ff	468	uint32_t RESERVED8; /!< Reserved, 0x0A8 /
bogdanm	0:9b334a45a8ff	469	uint32_t RESERVED9; /!< Reserved, 0x0AC /
bogdanm	0:9b334a45a8ff	470	__IO uint32_t DIFSEL; /!< ADC Differential Mode Selection Register, Address offset: 0xB0 /
bogdanm	0:9b334a45a8ff	471	__IO uint32_t CALFACT; /!< ADC Calibration Factors, Address offset: 0xB4 /
bogdanm	0:9b334a45a8ff	472
bogdanm	0:9b334a45a8ff	473	} ADC_TypeDef;
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	typedef struct
bogdanm	0:9b334a45a8ff	476	{
bogdanm	0:9b334a45a8ff	477	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 /
bogdanm	0:9b334a45a8ff	478	uint32_t RESERVED; /!< Reserved, ADC1/3 base address + 0x304 /
bogdanm	0:9b334a45a8ff	479	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1/3 base address + 0x308 /
bogdanm	0:9b334a45a8ff	480	__IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm	0:9b334a45a8ff	481	modes, Address offset: ADC1/3 base address + 0x30A */
bogdanm	0:9b334a45a8ff	482	} ADC_Common_TypeDef;
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484
bogdanm	0:9b334a45a8ff	485	/**
bogdanm	0:9b334a45a8ff	486	* @brief Controller Area Network TxMailBox
bogdanm	0:9b334a45a8ff	487	*/
bogdanm	0:9b334a45a8ff	488	typedef struct
bogdanm	0:9b334a45a8ff	489	{
bogdanm	0:9b334a45a8ff	490	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
bogdanm	0:9b334a45a8ff	491	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
bogdanm	0:9b334a45a8ff	492	__IO uint32_t TDLR; /!< CAN mailbox data low register /
bogdanm	0:9b334a45a8ff	493	__IO uint32_t TDHR; /!< CAN mailbox data high register /
bogdanm	0:9b334a45a8ff	494	} CAN_TxMailBox_TypeDef;
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/**
bogdanm	0:9b334a45a8ff	497	* @brief Controller Area Network FIFOMailBox
bogdanm	0:9b334a45a8ff	498	*/
bogdanm	0:9b334a45a8ff	499	typedef struct
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
bogdanm	0:9b334a45a8ff	502	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
bogdanm	0:9b334a45a8ff	503	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
bogdanm	0:9b334a45a8ff	504	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
bogdanm	0:9b334a45a8ff	505	} CAN_FIFOMailBox_TypeDef;
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @brief Controller Area Network FilterRegister
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510	typedef struct
bogdanm	0:9b334a45a8ff	511	{
bogdanm	0:9b334a45a8ff	512	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
bogdanm	0:9b334a45a8ff	513	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
bogdanm	0:9b334a45a8ff	514	} CAN_FilterRegister_TypeDef;
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/**
bogdanm	0:9b334a45a8ff	517	* @brief Controller Area Network
bogdanm	0:9b334a45a8ff	518	*/
bogdanm	0:9b334a45a8ff	519	typedef struct
bogdanm	0:9b334a45a8ff	520	{
bogdanm	0:9b334a45a8ff	521	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	522	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	523	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	524	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	525	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	526	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	527	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	528	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	529	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
bogdanm	0:9b334a45a8ff	530	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
bogdanm	0:9b334a45a8ff	531	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
bogdanm	0:9b334a45a8ff	532	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
bogdanm	0:9b334a45a8ff	533	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
bogdanm	0:9b334a45a8ff	534	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
bogdanm	0:9b334a45a8ff	535	uint32_t RESERVED2; /!< Reserved, 0x208 /
bogdanm	0:9b334a45a8ff	536	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
bogdanm	0:9b334a45a8ff	537	uint32_t RESERVED3; /!< Reserved, 0x210 /
bogdanm	0:9b334a45a8ff	538	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
bogdanm	0:9b334a45a8ff	539	uint32_t RESERVED4; /!< Reserved, 0x218 /
bogdanm	0:9b334a45a8ff	540	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
bogdanm	0:9b334a45a8ff	541	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
bogdanm	0:9b334a45a8ff	542	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
bogdanm	0:9b334a45a8ff	543	} CAN_TypeDef;
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	/**
bogdanm	0:9b334a45a8ff	547	* @brief Analog Comparators
bogdanm	0:9b334a45a8ff	548	*/
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	typedef struct
bogdanm	0:9b334a45a8ff	551	{
bogdanm	0:9b334a45a8ff	552	__IO uint32_t CSR; /!< Comparator control Status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	553	} COMP_TypeDef;
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/**
bogdanm	0:9b334a45a8ff	556	* @brief CRC calculation unit
bogdanm	0:9b334a45a8ff	557	*/
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	typedef struct
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	562	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	563	uint8_t RESERVED0; /!< Reserved, 0x05 /
bogdanm	0:9b334a45a8ff	564	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	565	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	566	uint32_t RESERVED2; /!< Reserved, 0x0C /
bogdanm	0:9b334a45a8ff	567	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	568	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	569	} CRC_TypeDef;
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	/**
bogdanm	0:9b334a45a8ff	572	* @brief Digital to Analog Converter
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	typedef struct
bogdanm	0:9b334a45a8ff	576	{
bogdanm	0:9b334a45a8ff	577	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	578	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	579	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	580	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	581	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	582	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	583	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	584	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	585	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	586	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	587	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	588	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	589	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	590	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	591	} DAC_TypeDef;
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	/**
bogdanm	0:9b334a45a8ff	594	* @brief Debug MCU
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	typedef struct
bogdanm	0:9b334a45a8ff	598	{
bogdanm	0:9b334a45a8ff	599	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	600	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	601	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	602	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	603	}DBGMCU_TypeDef;
bogdanm	0:9b334a45a8ff	604
bogdanm	0:9b334a45a8ff	605	/**
bogdanm	0:9b334a45a8ff	606	* @brief DMA Controller
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	typedef struct
bogdanm	0:9b334a45a8ff	610	{
bogdanm	0:9b334a45a8ff	611	__IO uint32_t CCR; /!< DMA channel x configuration register /
bogdanm	0:9b334a45a8ff	612	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
bogdanm	0:9b334a45a8ff	613	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
bogdanm	0:9b334a45a8ff	614	__IO uint32_t CMAR; /!< DMA channel x memory address register /
bogdanm	0:9b334a45a8ff	615	} DMA_Channel_TypeDef;
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	typedef struct
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	620	__IO uint32_t IFCR; /!< DMA interrupt clear flag register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	621	} DMA_TypeDef;
bogdanm	0:9b334a45a8ff	622
bogdanm	0:9b334a45a8ff	623	/**
bogdanm	0:9b334a45a8ff	624	* @brief External Interrupt/Event Controller
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626
bogdanm	0:9b334a45a8ff	627	typedef struct
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	630	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	631	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	632	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	633	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	634	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	635	uint32_t RESERVED1; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	636	uint32_t RESERVED2; /!< Reserved, 0x1C /
bogdanm	0:9b334a45a8ff	637	__IO uint32_t IMR2; /!< EXTI Interrupt mask register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	638	__IO uint32_t EMR2; /!< EXTI Event mask register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	639	__IO uint32_t RTSR2; /!< EXTI Rising trigger selection register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	640	__IO uint32_t FTSR2; /!< EXTI Falling trigger selection register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	641	__IO uint32_t SWIER2; /!< EXTI Software interrupt event register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	642	__IO uint32_t PR2; /!< EXTI Pending register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	643	}EXTI_TypeDef;
bogdanm	0:9b334a45a8ff	644
bogdanm	0:9b334a45a8ff	645	/**
bogdanm	0:9b334a45a8ff	646	* @brief FLASH Registers
bogdanm	0:9b334a45a8ff	647	*/
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	typedef struct
bogdanm	0:9b334a45a8ff	650	{
bogdanm	0:9b334a45a8ff	651	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	652	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	653	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	654	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	655	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	656	__IO uint32_t AR; /!< FLASH address register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	657	uint32_t RESERVED; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	658	__IO uint32_t OBR; /!< FLASH Option byte register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	659	__IO uint32_t WRPR; /!< FLASH Write register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	} FLASH_TypeDef;
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	/**
bogdanm	0:9b334a45a8ff	664	* @brief Option Bytes Registers
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666	typedef struct
bogdanm	0:9b334a45a8ff	667	{
bogdanm	0:9b334a45a8ff	668	__IO uint16_t RDP; /!<FLASH option byte Read protection, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	669	__IO uint16_t USER; /!<FLASH option byte user options, Address offset: 0x02 /
bogdanm	0:9b334a45a8ff	670	uint16_t RESERVED0; /!< Reserved, 0x04 /
bogdanm	0:9b334a45a8ff	671	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	672	__IO uint16_t WRP0; /!<FLASH option byte write protection 0, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	673	__IO uint16_t WRP1; /!<FLASH option byte write protection 1, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	674	__IO uint16_t WRP2; /!<FLASH option byte write protection 2, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	675	__IO uint16_t WRP3; /!<FLASH option byte write protection 3, Address offset: 0x12 /
bogdanm	0:9b334a45a8ff	676	} OB_TypeDef;
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/**
bogdanm	0:9b334a45a8ff	679	* @brief General Purpose I/O
bogdanm	0:9b334a45a8ff	680	*/
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	typedef struct
bogdanm	0:9b334a45a8ff	683	{
bogdanm	0:9b334a45a8ff	684	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	685	__IO uint16_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	686	uint16_t RESERVED0; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	687	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	688	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	689	__IO uint16_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	690	uint16_t RESERVED1; /!< Reserved, 0x12 /
bogdanm	0:9b334a45a8ff	691	__IO uint16_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	692	uint16_t RESERVED2; /!< Reserved, 0x16 /
bogdanm	0:9b334a45a8ff	693	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	694	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	695	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
bogdanm	0:9b334a45a8ff	696	__IO uint16_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	697	uint16_t RESERVED3; /!< Reserved, 0x2A /
bogdanm	0:9b334a45a8ff	698	}GPIO_TypeDef;
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/**
bogdanm	0:9b334a45a8ff	701	* @brief High resolution Timer (HRTIM)
bogdanm	0:9b334a45a8ff	702	*/
bogdanm	0:9b334a45a8ff	703	/* HRTIM master definition */
bogdanm	0:9b334a45a8ff	704	typedef struct
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	__IO uint32_t MCR; /!< HRTIM Master Timer control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	707	__IO uint32_t MISR; /!< HRTIM Master Timer interrupt status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	708	__IO uint32_t MICR; /!< HRTIM Master Timer interupt clear register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	709	__IO uint32_t MDIER; /!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	710	__IO uint32_t MCNTR; /!< HRTIM Master Timer counter register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	711	__IO uint32_t MPER; /!< HRTIM Master Timer period register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	712	__IO uint32_t MREP; /!< HRTIM Master Timer repetition register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	713	__IO uint32_t MCMP1R; /!< HRTIM Master Timer compare 1 register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	714	uint32_t RESERVED0; /!< Reserved, 0x20 /
bogdanm	0:9b334a45a8ff	715	__IO uint32_t MCMP2R; /!< HRTIM Master Timer compare 2 register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	716	__IO uint32_t MCMP3R; /!< HRTIM Master Timer compare 3 register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	717	__IO uint32_t MCMP4R; /!< HRTIM Master Timer compare 4 register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	718	}HRTIM_Master_TypeDef;
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* HRTIM slave definition */
bogdanm	0:9b334a45a8ff	721	typedef struct
bogdanm	0:9b334a45a8ff	722	{
bogdanm	0:9b334a45a8ff	723	__IO uint32_t TIMxCR; /!< HRTIM Timerx control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	724	__IO uint32_t TIMxISR; /!< HRTIM Timerx interrupt status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	725	__IO uint32_t TIMxICR; /!< HRTIM Timerx interrupt clear register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	726	__IO uint32_t TIMxDIER; /!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	727	__IO uint32_t CNTxR; /!< HRTIM Timerx counter register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	728	__IO uint32_t PERxR; /!< HRTIM Timerx period register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	729	__IO uint32_t REPxR; /!< HRTIM Timerx repetition register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	730	__IO uint32_t CMP1xR; /!< HRTIM Timerx compare 1 register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	731	__IO uint32_t CMP1CxR; /!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	732	__IO uint32_t CMP2xR; /!< HRTIM Timerx compare 2 register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	733	__IO uint32_t CMP3xR; /!< HRTIM Timerx compare 3 register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	734	__IO uint32_t CMP4xR; /!< HRTIM Timerx compare 4 register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	735	__IO uint32_t CPT1xR; /!< HRTIM Timerx capture 1 register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	736	__IO uint32_t CPT2xR; /!< HRTIM Timerx capture 2 register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	737	__IO uint32_t DTxR; /!< HRTIM Timerx dead time register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	738	__IO uint32_t SETx1R; /!< HRTIM Timerx output 1 set register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	739	__IO uint32_t RSTx1R; /!< HRTIM Timerx output 1 reset register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	740	__IO uint32_t SETx2R; /!< HRTIM Timerx output 2 set register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	741	__IO uint32_t RSTx2R; /!< HRTIM Timerx output 2 reset register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	742	__IO uint32_t EEFxR1; /!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	743	__IO uint32_t EEFxR2; /!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	744	__IO uint32_t RSTxR; /!< HRTIM Timerx Reset register, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	745	__IO uint32_t CHPxR; /!< HRTIM Timerx Chopper register, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	746	__IO uint32_t CPT1xCR; /!< HRTIM Timerx Capture 1 register, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	747	__IO uint32_t CPT2xCR; /!< HRTIM Timerx Capture 2 register, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	748	__IO uint32_t OUTxR; /!< HRTIM Timerx Output register, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	749	__IO uint32_t FLTxR; /!< HRTIM Timerx Fault register, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	750	uint32_t RESERVED0[5];/!< Reserved, /
bogdanm	0:9b334a45a8ff	751	}HRTIM_Timerx_TypeDef;
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/* HRTIM common register definition */
bogdanm	0:9b334a45a8ff	754	typedef struct
bogdanm	0:9b334a45a8ff	755	{
bogdanm	0:9b334a45a8ff	756	__IO uint32_t CR1; /!< HRTIM control register1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	757	__IO uint32_t CR2; /!< HRTIM control register2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	758	__IO uint32_t ISR; /!< HRTIM interrupt status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	759	__IO uint32_t ICR; /!< HRTIM interrupt clear register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	760	__IO uint32_t IER; /!< HRTIM interrupt enable register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	761	__IO uint32_t OENR; /!< HRTIM Output enable register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	762	__IO uint32_t DISR; /!< HRTIM Output disable register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	763	__IO uint32_t ODSR; /!< HRTIM Output disable status register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	764	__IO uint32_t BMCR; /!< HRTIM Burst mode control register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	765	__IO uint32_t BMTRGR; /!< HRTIM Busrt mode trigger register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	766	__IO uint32_t BMCMPR; /!< HRTIM Burst mode compare register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	767	__IO uint32_t BMPER; /!< HRTIM Burst mode period register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	768	__IO uint32_t EECR1; /!< HRTIM Timer external event control register1, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	769	__IO uint32_t EECR2; /!< HRTIM Timer external event control register2, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	770	__IO uint32_t EECR3; /!< HRTIM Timer external event control register3, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	771	__IO uint32_t ADC1R; /!< HRTIM ADC Trigger 1 register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	772	__IO uint32_t ADC2R; /!< HRTIM ADC Trigger 2 register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	773	__IO uint32_t ADC3R; /!< HRTIM ADC Trigger 3 register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	774	__IO uint32_t ADC4R; /!< HRTIM ADC Trigger 4 register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	775	__IO uint32_t DLLCR; /!< HRTIM DLL control register, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	776	__IO uint32_t FLTINxR1; /!< HRTIM Fault input register1, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	777	__IO uint32_t FLTINxR2; /!< HRTIM Fault input register2, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	778	__IO uint32_t BDMUPDR; /!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	779	__IO uint32_t BDTAUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	780	__IO uint32_t BDTBUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	781	__IO uint32_t BDTCUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	782	__IO uint32_t BDTDUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	783	__IO uint32_t BDTEUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C /
bogdanm	0:9b334a45a8ff	784	__IO uint32_t BDMADR; /!< HRTIM Burst DMA Master Data register, Address offset: 0x70 /
bogdanm	0:9b334a45a8ff	785	}HRTIM_Common_TypeDef;
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* HRTIM register definition */
bogdanm	0:9b334a45a8ff	788	typedef struct {
bogdanm	0:9b334a45a8ff	789	HRTIM_Master_TypeDef HRTIM_MASTER;
bogdanm	0:9b334a45a8ff	790	uint32_t RESERVED0[20];
bogdanm	0:9b334a45a8ff	791	HRTIM_Timerx_TypeDef HRTIM_TIMERx[5];
bogdanm	0:9b334a45a8ff	792	uint32_t RESERVED1[32];
bogdanm	0:9b334a45a8ff	793	HRTIM_Common_TypeDef HRTIM_COMMON;
bogdanm	0:9b334a45a8ff	794	}HRTIM_TypeDef;
bogdanm	0:9b334a45a8ff	795
bogdanm	0:9b334a45a8ff	796	/**
bogdanm	0:9b334a45a8ff	797	* @brief Operational Amplifier (OPAMP)
bogdanm	0:9b334a45a8ff	798	*/
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	typedef struct
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	__IO uint32_t CSR; /!< OPAMP control and status register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	803	} OPAMP_TypeDef;
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	/**
bogdanm	0:9b334a45a8ff	807	* @brief System configuration controller
bogdanm	0:9b334a45a8ff	808	*/
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	typedef struct
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	813	__IO uint32_t RCR; /!< SYSCFG CCM SRAM protection register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	814	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 /
bogdanm	0:9b334a45a8ff	815	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	816	__IO uint32_t RESERVED0; /!< Reserved, 0x1C /
bogdanm	0:9b334a45a8ff	817	__IO uint32_t RESERVED1; /!< Reserved, 0x20 /
bogdanm	0:9b334a45a8ff	818	__IO uint32_t RESERVED2; /!< Reserved, 0x24 /
bogdanm	0:9b334a45a8ff	819	__IO uint32_t RESERVED4; /!< Reserved, 0x28 /
bogdanm	0:9b334a45a8ff	820	__IO uint32_t RESERVED5; /!< Reserved, 0x2C /
bogdanm	0:9b334a45a8ff	821	__IO uint32_t RESERVED6; /!< Reserved, 0x30 /
bogdanm	0:9b334a45a8ff	822	__IO uint32_t RESERVED7; /!< Reserved, 0x34 /
bogdanm	0:9b334a45a8ff	823	__IO uint32_t RESERVED8; /!< Reserved, 0x38 /
bogdanm	0:9b334a45a8ff	824	__IO uint32_t RESERVED9; /!< Reserved, 0x3C /
bogdanm	0:9b334a45a8ff	825	__IO uint32_t RESERVED10; /!< Reserved, 0x40 /
bogdanm	0:9b334a45a8ff	826	__IO uint32_t RESERVED11; /!< Reserved, 0x44 /
bogdanm	0:9b334a45a8ff	827	__IO uint32_t RESERVED12; /!< Reserved, 0x48 /
bogdanm	0:9b334a45a8ff	828	__IO uint32_t RESERVED13; /!< Reserved, 0x4C /
bogdanm	0:9b334a45a8ff	829	__IO uint32_t CFGR3; /!< SYSCFG configuration register 3, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	830	} SYSCFG_TypeDef;
bogdanm	0:9b334a45a8ff	831
bogdanm	0:9b334a45a8ff	832	/**
bogdanm	0:9b334a45a8ff	833	* @brief Inter-integrated Circuit Interface
bogdanm	0:9b334a45a8ff	834	*/
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	typedef struct
bogdanm	0:9b334a45a8ff	837	{
bogdanm	0:9b334a45a8ff	838	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	839	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	840	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	841	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	842	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	843	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	844	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	845	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	846	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	847	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	848	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	849	}I2C_TypeDef;
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/**
bogdanm	0:9b334a45a8ff	852	* @brief Independent WATCHDOG
bogdanm	0:9b334a45a8ff	853	*/
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	typedef struct
bogdanm	0:9b334a45a8ff	856	{
bogdanm	0:9b334a45a8ff	857	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	858	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	859	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	860	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	861	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	862	} IWDG_TypeDef;
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/**
bogdanm	0:9b334a45a8ff	865	* @brief Power Control
bogdanm	0:9b334a45a8ff	866	*/
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	typedef struct
bogdanm	0:9b334a45a8ff	869	{
bogdanm	0:9b334a45a8ff	870	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	871	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	872	} PWR_TypeDef;
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	/**
bogdanm	0:9b334a45a8ff	875	* @brief Reset and Clock Control
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877	typedef struct
bogdanm	0:9b334a45a8ff	878	{
bogdanm	0:9b334a45a8ff	879	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	880	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	881	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	882	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	883	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	884	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	885	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	886	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	887	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	888	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	889	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	890	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	891	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	892	} RCC_TypeDef;
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/**
bogdanm	0:9b334a45a8ff	895	* @brief Real-Time Clock
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	typedef struct
bogdanm	0:9b334a45a8ff	899	{
bogdanm	0:9b334a45a8ff	900	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	901	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	902	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	903	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	904	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	905	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	906	uint32_t RESERVED0; /!< Reserved, 0x18 /
bogdanm	0:9b334a45a8ff	907	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	908	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	909	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	910	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	911	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	912	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	913	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	914	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	915	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	916	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	917	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	918	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	919	uint32_t RESERVED7; /!< Reserved, 0x4C /
bogdanm	0:9b334a45a8ff	920	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	921	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	922	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	923	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	924	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
bogdanm	0:9b334a45a8ff	925	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
bogdanm	0:9b334a45a8ff	926	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
bogdanm	0:9b334a45a8ff	927	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
bogdanm	0:9b334a45a8ff	928	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
bogdanm	0:9b334a45a8ff	929	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
bogdanm	0:9b334a45a8ff	930	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
bogdanm	0:9b334a45a8ff	931	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
bogdanm	0:9b334a45a8ff	932	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
bogdanm	0:9b334a45a8ff	933	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
bogdanm	0:9b334a45a8ff	934	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
bogdanm	0:9b334a45a8ff	935	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
bogdanm	0:9b334a45a8ff	936	} RTC_TypeDef;
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/**
bogdanm	0:9b334a45a8ff	940	* @brief Serial Peripheral Interface
bogdanm	0:9b334a45a8ff	941	*/
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	typedef struct
bogdanm	0:9b334a45a8ff	944	{
bogdanm	0:9b334a45a8ff	945	__IO uint16_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	946	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	0:9b334a45a8ff	947	__IO uint16_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	948	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	0:9b334a45a8ff	949	__IO uint16_t SR; /!< SPI Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	950	uint16_t RESERVED2; /!< Reserved, 0x0A /
bogdanm	0:9b334a45a8ff	951	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	952	uint16_t RESERVED3; /!< Reserved, 0x0E /
bogdanm	0:9b334a45a8ff	953	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	954	uint16_t RESERVED4; /!< Reserved, 0x12 /
bogdanm	0:9b334a45a8ff	955	__IO uint16_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	956	uint16_t RESERVED5; /!< Reserved, 0x16 /
bogdanm	0:9b334a45a8ff	957	__IO uint16_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	958	uint16_t RESERVED6; /!< Reserved, 0x1A /
bogdanm	0:9b334a45a8ff	959	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	960	uint16_t RESERVED7; /!< Reserved, 0x1E /
bogdanm	0:9b334a45a8ff	961	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	962	uint16_t RESERVED8; /!< Reserved, 0x22 /
bogdanm	0:9b334a45a8ff	963	} SPI_TypeDef;
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	/**
bogdanm	0:9b334a45a8ff	966	* @brief TIM
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968	typedef struct
bogdanm	0:9b334a45a8ff	969	{
bogdanm	0:9b334a45a8ff	970	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	971	uint16_t RESERVED0; /!< Reserved, 0x02 /
bogdanm	0:9b334a45a8ff	972	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	973	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	974	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	975	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	976	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	977	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	978	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	979	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	980	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	981	__IO uint16_t PSC; /!< TIM prescaler, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	982	uint16_t RESERVED9; /!< Reserved, 0x2A /
bogdanm	0:9b334a45a8ff	983	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	984	__IO uint16_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	985	uint16_t RESERVED10; /!< Reserved, 0x32 /
bogdanm	0:9b334a45a8ff	986	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	0:9b334a45a8ff	987	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	0:9b334a45a8ff	988	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	0:9b334a45a8ff	989	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	0:9b334a45a8ff	990	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	0:9b334a45a8ff	991	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	0:9b334a45a8ff	992	uint16_t RESERVED12; /!< Reserved, 0x4A /
bogdanm	0:9b334a45a8ff	993	__IO uint16_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
bogdanm	0:9b334a45a8ff	994	uint16_t RESERVED13; /!< Reserved, 0x4E /
bogdanm	0:9b334a45a8ff	995	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
bogdanm	0:9b334a45a8ff	996	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
bogdanm	0:9b334a45a8ff	997	__IO uint32_t CCR5; /!< TIM capture/compare register5, Address offset: 0x58 /
bogdanm	0:9b334a45a8ff	998	__IO uint32_t CCR6; /!< TIM capture/compare register 4, Address offset: 0x5C /
bogdanm	0:9b334a45a8ff	999	} TIM_TypeDef;
bogdanm	0:9b334a45a8ff	1000
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	/**
bogdanm	0:9b334a45a8ff	1003	* @brief Touch Sensing Controller (TSC)
bogdanm	0:9b334a45a8ff	1004	*/
bogdanm	0:9b334a45a8ff	1005	typedef struct
bogdanm	0:9b334a45a8ff	1006	{
bogdanm	0:9b334a45a8ff	1007	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	1008	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	1009	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	1010	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	1011	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	1012	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	1013	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	1014	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	1015	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	1016	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	1017	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	1018	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
bogdanm	0:9b334a45a8ff	1019	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
bogdanm	0:9b334a45a8ff	1020	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
bogdanm	0:9b334a45a8ff	1021	} TSC_TypeDef;
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/**
bogdanm	0:9b334a45a8ff	1024	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	0:9b334a45a8ff	1025	*/
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027	typedef struct
bogdanm	0:9b334a45a8ff	1028	{
bogdanm	0:9b334a45a8ff	1029	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	1030	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	1031	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	1032	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
bogdanm	0:9b334a45a8ff	1033	uint16_t RESERVED1; /!< Reserved, 0x0E /
bogdanm	0:9b334a45a8ff	1034	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
bogdanm	0:9b334a45a8ff	1035	uint16_t RESERVED2; /!< Reserved, 0x12 /
bogdanm	0:9b334a45a8ff	1036	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
bogdanm	0:9b334a45a8ff	1037	__IO uint16_t RQR; /!< USART Request register, Address offset: 0x18 /
bogdanm	0:9b334a45a8ff	1038	uint16_t RESERVED3; /!< Reserved, 0x1A /
bogdanm	0:9b334a45a8ff	1039	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
bogdanm	0:9b334a45a8ff	1040	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
bogdanm	0:9b334a45a8ff	1041	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
bogdanm	0:9b334a45a8ff	1042	uint16_t RESERVED4; /!< Reserved, 0x26 /
bogdanm	0:9b334a45a8ff	1043	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
bogdanm	0:9b334a45a8ff	1044	uint16_t RESERVED5; /!< Reserved, 0x2A /
bogdanm	0:9b334a45a8ff	1045	} USART_TypeDef;
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/**
bogdanm	0:9b334a45a8ff	1048	* @brief Window WATCHDOG
bogdanm	0:9b334a45a8ff	1049	*/
bogdanm	0:9b334a45a8ff	1050	typedef struct
bogdanm	0:9b334a45a8ff	1051	{
bogdanm	0:9b334a45a8ff	1052	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	0:9b334a45a8ff	1053	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	0:9b334a45a8ff	1054	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	0:9b334a45a8ff	1055	} WWDG_TypeDef;
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	/** @addtogroup Peripheral_memory_map
bogdanm	0:9b334a45a8ff	1059	* @{
bogdanm	0:9b334a45a8ff	1060	*/
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
bogdanm	0:9b334a45a8ff	1063	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
bogdanm	0:9b334a45a8ff	1064	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
bogdanm	0:9b334a45a8ff	1065
bogdanm	0:9b334a45a8ff	1066	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
bogdanm	0:9b334a45a8ff	1067	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/!< Peripheral memory map /
bogdanm	0:9b334a45a8ff	1071	#define APB1PERIPH_BASE PERIPH_BASE
bogdanm	0:9b334a45a8ff	1072	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm	0:9b334a45a8ff	1073	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm	0:9b334a45a8ff	1074	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm	0:9b334a45a8ff	1075	#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/!< APB1 peripherals /
bogdanm	0:9b334a45a8ff	1078	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	1079	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
bogdanm	0:9b334a45a8ff	1080	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
bogdanm	0:9b334a45a8ff	1081	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
bogdanm	0:9b334a45a8ff	1082	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
bogdanm	0:9b334a45a8ff	1083	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
bogdanm	0:9b334a45a8ff	1084	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
bogdanm	0:9b334a45a8ff	1085	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
bogdanm	0:9b334a45a8ff	1086	#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
bogdanm	0:9b334a45a8ff	1087	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
bogdanm	0:9b334a45a8ff	1088	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
bogdanm	0:9b334a45a8ff	1089	#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
bogdanm	0:9b334a45a8ff	1090	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
bogdanm	0:9b334a45a8ff	1091	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
bogdanm	0:9b334a45a8ff	1092	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
bogdanm	0:9b334a45a8ff	1093	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
bogdanm	0:9b334a45a8ff	1094	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
bogdanm	0:9b334a45a8ff	1095	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
bogdanm	0:9b334a45a8ff	1096	#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400)
bogdanm	0:9b334a45a8ff	1097	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
bogdanm	0:9b334a45a8ff	1098	#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
bogdanm	0:9b334a45a8ff	1099	#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
bogdanm	0:9b334a45a8ff	1100	#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
bogdanm	0:9b334a45a8ff	1101	#define DAC_BASE DAC1_BASE
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	/!< APB2 peripherals /
bogdanm	0:9b334a45a8ff	1104	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	1105	#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
bogdanm	0:9b334a45a8ff	1106	#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
bogdanm	0:9b334a45a8ff	1107	#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
bogdanm	0:9b334a45a8ff	1108	#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
bogdanm	0:9b334a45a8ff	1109	#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
bogdanm	0:9b334a45a8ff	1110	#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
bogdanm	0:9b334a45a8ff	1111	#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
bogdanm	0:9b334a45a8ff	1112	#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
bogdanm	0:9b334a45a8ff	1113	#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
bogdanm	0:9b334a45a8ff	1114	#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
bogdanm	0:9b334a45a8ff	1115	#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
bogdanm	0:9b334a45a8ff	1116	#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
bogdanm	0:9b334a45a8ff	1117	#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
bogdanm	0:9b334a45a8ff	1118	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
bogdanm	0:9b334a45a8ff	1119	#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
bogdanm	0:9b334a45a8ff	1120	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
bogdanm	0:9b334a45a8ff	1121	#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
bogdanm	0:9b334a45a8ff	1122	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
bogdanm	0:9b334a45a8ff	1123	#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
bogdanm	0:9b334a45a8ff	1124	#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
bogdanm	0:9b334a45a8ff	1125	#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
bogdanm	0:9b334a45a8ff	1126	#define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
bogdanm	0:9b334a45a8ff	1127	#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
bogdanm	0:9b334a45a8ff	1128	#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
bogdanm	0:9b334a45a8ff	1129	#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
bogdanm	0:9b334a45a8ff	1130	#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
bogdanm	0:9b334a45a8ff	1131	#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
bogdanm	0:9b334a45a8ff	1132	#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/!< AHB1 peripherals /
bogdanm	0:9b334a45a8ff	1135	#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
bogdanm	0:9b334a45a8ff	1136	#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
bogdanm	0:9b334a45a8ff	1137	#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
bogdanm	0:9b334a45a8ff	1138	#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
bogdanm	0:9b334a45a8ff	1139	#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
bogdanm	0:9b334a45a8ff	1140	#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
bogdanm	0:9b334a45a8ff	1141	#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
bogdanm	0:9b334a45a8ff	1142	#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
bogdanm	0:9b334a45a8ff	1143	#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
bogdanm	0:9b334a45a8ff	1144	#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
bogdanm	0:9b334a45a8ff	1145	#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
bogdanm	0:9b334a45a8ff	1146	#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
bogdanm	0:9b334a45a8ff	1147	#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
bogdanm	0:9b334a45a8ff	1148	#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
bogdanm	0:9b334a45a8ff	1149	#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
bogdanm	0:9b334a45a8ff	1150	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /!< Flash registers base address /
bogdanm	0:9b334a45a8ff	1151	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
bogdanm	0:9b334a45a8ff	1152	#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
bogdanm	0:9b334a45a8ff	1153	#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	/!< AHB2 peripherals /
bogdanm	0:9b334a45a8ff	1156	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1157	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1158	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
bogdanm	0:9b334a45a8ff	1159	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
bogdanm	0:9b334a45a8ff	1160	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
bogdanm	0:9b334a45a8ff	1161	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/!< AHB3 peripherals /
bogdanm	0:9b334a45a8ff	1164	#define ADC1_BASE (AHB3PERIPH_BASE + 0x0000)
bogdanm	0:9b334a45a8ff	1165	#define ADC2_BASE (AHB3PERIPH_BASE + 0x0100)
bogdanm	0:9b334a45a8ff	1166	#define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300)
bogdanm	0:9b334a45a8ff	1167	#define ADC3_BASE (AHB3PERIPH_BASE + 0x0400)
bogdanm	0:9b334a45a8ff	1168	#define ADC4_BASE (AHB3PERIPH_BASE + 0x0500)
bogdanm	0:9b334a45a8ff	1169	#define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700)
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
bogdanm	0:9b334a45a8ff	1172	/**
bogdanm	0:9b334a45a8ff	1173	* @}
bogdanm	0:9b334a45a8ff	1174	*/
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	/** @addtogroup Peripheral_declaration
bogdanm	0:9b334a45a8ff	1177	* @{
bogdanm	0:9b334a45a8ff	1178	*/
bogdanm	0:9b334a45a8ff	1179	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	0:9b334a45a8ff	1180	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	0:9b334a45a8ff	1181	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm	0:9b334a45a8ff	1182	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm	0:9b334a45a8ff	1183	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm	0:9b334a45a8ff	1184	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	0:9b334a45a8ff	1185	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	0:9b334a45a8ff	1186	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	0:9b334a45a8ff	1187	#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm	0:9b334a45a8ff	1188	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm	0:9b334a45a8ff	1189	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm	0:9b334a45a8ff	1190	#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm	0:9b334a45a8ff	1191	#define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm	0:9b334a45a8ff	1192	#define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm	0:9b334a45a8ff	1193	#define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm	0:9b334a45a8ff	1194	#define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm	0:9b334a45a8ff	1195	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	0:9b334a45a8ff	1196	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm	0:9b334a45a8ff	1197	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm	0:9b334a45a8ff	1198	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm	0:9b334a45a8ff	1199	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	0:9b334a45a8ff	1200	#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
bogdanm	0:9b334a45a8ff	1201	#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
bogdanm	0:9b334a45a8ff	1202	#define DAC DAC1
bogdanm	0:9b334a45a8ff	1203	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm	0:9b334a45a8ff	1204	#define COMP ((COMP_TypeDef *) COMP_BASE)
bogdanm	0:9b334a45a8ff	1205	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
bogdanm	0:9b334a45a8ff	1206	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
bogdanm	0:9b334a45a8ff	1207	#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
bogdanm	0:9b334a45a8ff	1208	#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
bogdanm	0:9b334a45a8ff	1209	#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
bogdanm	0:9b334a45a8ff	1210	#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
bogdanm	0:9b334a45a8ff	1211	#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
bogdanm	0:9b334a45a8ff	1212	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
bogdanm	0:9b334a45a8ff	1213	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
bogdanm	0:9b334a45a8ff	1214	#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
bogdanm	0:9b334a45a8ff	1215	#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
bogdanm	0:9b334a45a8ff	1216	#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
bogdanm	0:9b334a45a8ff	1217	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	0:9b334a45a8ff	1218	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	0:9b334a45a8ff	1219	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	0:9b334a45a8ff	1220	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm	0:9b334a45a8ff	1221	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	0:9b334a45a8ff	1222	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm	0:9b334a45a8ff	1223	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm	0:9b334a45a8ff	1224	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm	0:9b334a45a8ff	1225	#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
bogdanm	0:9b334a45a8ff	1226	#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
bogdanm	0:9b334a45a8ff	1227	#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
bogdanm	0:9b334a45a8ff	1228	#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
bogdanm	0:9b334a45a8ff	1229	#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
bogdanm	0:9b334a45a8ff	1230	#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
bogdanm	0:9b334a45a8ff	1231	#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
bogdanm	0:9b334a45a8ff	1232	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	0:9b334a45a8ff	1233	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	0:9b334a45a8ff	1234	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm	0:9b334a45a8ff	1235	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm	0:9b334a45a8ff	1236	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm	0:9b334a45a8ff	1237	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm	0:9b334a45a8ff	1238	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm	0:9b334a45a8ff	1239	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm	0:9b334a45a8ff	1240	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm	0:9b334a45a8ff	1241	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm	0:9b334a45a8ff	1242	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
bogdanm	0:9b334a45a8ff	1243	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
bogdanm	0:9b334a45a8ff	1244	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
bogdanm	0:9b334a45a8ff	1245	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
bogdanm	0:9b334a45a8ff	1246	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
bogdanm	0:9b334a45a8ff	1247	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	0:9b334a45a8ff	1248	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	0:9b334a45a8ff	1249	#define OB ((OB_TypeDef *) OB_BASE)
bogdanm	0:9b334a45a8ff	1250	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	0:9b334a45a8ff	1251	#define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm	0:9b334a45a8ff	1252	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	0:9b334a45a8ff	1253	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	0:9b334a45a8ff	1254	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	0:9b334a45a8ff	1255	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm	0:9b334a45a8ff	1256	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm	0:9b334a45a8ff	1257	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm	0:9b334a45a8ff	1258	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	0:9b334a45a8ff	1259	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm	0:9b334a45a8ff	1260	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm	0:9b334a45a8ff	1261	#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
bogdanm	0:9b334a45a8ff	1262	#define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE)
bogdanm	0:9b334a45a8ff	1263	#define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE)
bogdanm	0:9b334a45a8ff	1264	/**
bogdanm	0:9b334a45a8ff	1265	* @}
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/** @addtogroup Exported_constants
bogdanm	0:9b334a45a8ff	1269	* @{
bogdanm	0:9b334a45a8ff	1270	*/
bogdanm	0:9b334a45a8ff	1271
bogdanm	0:9b334a45a8ff	1272	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	0:9b334a45a8ff	1273	* @{
bogdanm	0:9b334a45a8ff	1274	*/
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1277	/* Peripheral Registers_Bits_Definition */
bogdanm	0:9b334a45a8ff	1278	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1279	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1280	/* */
bogdanm	0:9b334a45a8ff	1281	/* High Resolution Timer (HRTIM) */
bogdanm	0:9b334a45a8ff	1282	/* */
bogdanm	0:9b334a45a8ff	1283	/******************************************************************************/
bogdanm	0:9b334a45a8ff	1284	/****************** Master Timer control register *************************/
bogdanm	0:9b334a45a8ff	1285	#define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /!< Prescaler mask /
bogdanm	0:9b334a45a8ff	1286	#define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /!< Prescaler bit 0 /
bogdanm	0:9b334a45a8ff	1287	#define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /!< Prescaler bit 1 /
bogdanm	0:9b334a45a8ff	1288	#define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /!< Prescaler bit 2 /
bogdanm	0:9b334a45a8ff	1289
bogdanm	0:9b334a45a8ff	1290	#define HRTIM_MCR_CONT ((uint32_t)0x00000008) /!< Continuous mode /
bogdanm	0:9b334a45a8ff	1291	#define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /!< Rettrigreable mode /
bogdanm	0:9b334a45a8ff	1292	#define HRTIM_MCR_HALF ((uint32_t)0x00000020) /!< Half mode /
bogdanm	0:9b334a45a8ff	1293
bogdanm	0:9b334a45a8ff	1294	#define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /!< Synchronization input master /
bogdanm	0:9b334a45a8ff	1295	#define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /!< Synchronization input bit 0 /
bogdanm	0:9b334a45a8ff	1296	#define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /!< Synchronization input bit 1 /
bogdanm	0:9b334a45a8ff	1297	#define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /!< Synchronization reset master /
bogdanm	0:9b334a45a8ff	1298	#define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /!< Synchronization start master /
bogdanm	0:9b334a45a8ff	1299	#define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /!< Synchronization output master /
bogdanm	0:9b334a45a8ff	1300	#define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /!< Synchronization output bit 0 /
bogdanm	0:9b334a45a8ff	1301	#define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /!< Synchronization output bit 1 /
bogdanm	0:9b334a45a8ff	1302	#define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /!< Synchronization source /
bogdanm	0:9b334a45a8ff	1303	#define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /!< Synchronization source bit 0 /
bogdanm	0:9b334a45a8ff	1304	#define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /!< Synchronization source bit 1 /
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	#define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /!< Master counter enable /
bogdanm	0:9b334a45a8ff	1307	#define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /!< Timer A counter enable /
bogdanm	0:9b334a45a8ff	1308	#define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /!< Timer B counter enable /
bogdanm	0:9b334a45a8ff	1309	#define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /!< Timer C counter enable /
bogdanm	0:9b334a45a8ff	1310	#define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /!< Timer D counter enable /
bogdanm	0:9b334a45a8ff	1311	#define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /!< Timer E counter enable /
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	#define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /!< DAC synchronization mask /
bogdanm	0:9b334a45a8ff	1314	#define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /!< DAC synchronization bit 0 /
bogdanm	0:9b334a45a8ff	1315	#define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /!< DAC synchronization bit 1 /
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	#define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /!< Master preload enable /
bogdanm	0:9b334a45a8ff	1318	#define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /!< Master repetition update /
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	#define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /!< Burst DMA update /
bogdanm	0:9b334a45a8ff	1321	#define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /!< Burst DMA update bit 0/
bogdanm	0:9b334a45a8ff	1322	#define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /!< Burst DMA update bit 1 /
bogdanm	0:9b334a45a8ff	1323
bogdanm	0:9b334a45a8ff	1324	/****************** Master Timer Interrupt status register ****************/
bogdanm	0:9b334a45a8ff	1325	#define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /!< Master compare 1 interrupt flag /
bogdanm	0:9b334a45a8ff	1326	#define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /!< Master compare 2 interrupt flag /
bogdanm	0:9b334a45a8ff	1327	#define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /!< Master compare 3 interrupt flag /
bogdanm	0:9b334a45a8ff	1328	#define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /!< Master compare 4 interrupt flag /
bogdanm	0:9b334a45a8ff	1329	#define HRTIM_MISR_MREP ((uint32_t)0x00000010) /!< Master Repetition interrupt flag /
bogdanm	0:9b334a45a8ff	1330	#define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /!< Synchronization input interrupt flag /
bogdanm	0:9b334a45a8ff	1331	#define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /!< Master update interrupt flag /
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/****************** Master Timer Interrupt clear register *****************/
bogdanm	0:9b334a45a8ff	1334	#define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /!< Master compare 1 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1335	#define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /!< Master compare 2 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1336	#define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /!< Master compare 3 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1337	#define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /!< Master compare 4 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1338	#define HRTIM_MICR_MREP ((uint32_t)0x00000010) /!< Master Repetition interrupt flag clear /
bogdanm	0:9b334a45a8ff	1339	#define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /!< Synchronization input interrupt flag clear /
bogdanm	0:9b334a45a8ff	1340	#define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /!< Master update interrupt flag clear /
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/****************** Master Timer DMA/Interrupt enable register ************/
bogdanm	0:9b334a45a8ff	1343	#define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /!< Master compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	1344	#define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /!< Master compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	1345	#define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /!< Master compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	1346	#define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /!< Master compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	1347	#define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /!< Master Repetition interrupt enable /
bogdanm	0:9b334a45a8ff	1348	#define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /!< Synchronization input interrupt enable /
bogdanm	0:9b334a45a8ff	1349	#define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /!< Master update interrupt enable /
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	#define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /!< Master compare 1 DMA enable /
bogdanm	0:9b334a45a8ff	1352	#define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /!< Master compare 2 DMA enable /
bogdanm	0:9b334a45a8ff	1353	#define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /!< Master compare 3 DMA enable /
bogdanm	0:9b334a45a8ff	1354	#define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /!< Master compare 4 DMA enable /
bogdanm	0:9b334a45a8ff	1355	#define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /!< Master Repetition DMA enable /
bogdanm	0:9b334a45a8ff	1356	#define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /!< Synchronization input DMA enable /
bogdanm	0:9b334a45a8ff	1357	#define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /!< Master update DMA enable /
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/***************** Bit definition for HRTIM_MCNTR register **************/
bogdanm	0:9b334a45a8ff	1360	#define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	/***************** Bit definition for HRTIM_MPER register ***************/
bogdanm	0:9b334a45a8ff	1363	#define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /!< Period Value /
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365	/***************** Bit definition for HRTIM_MREP register ***************/
bogdanm	0:9b334a45a8ff	1366	#define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /!<Repetition Value /
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/***************** Bit definition for HRTIM_MCMP1R register ***************/
bogdanm	0:9b334a45a8ff	1369	#define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/***************** Bit definition for HRTIM_MCMP2R register ***************/
bogdanm	0:9b334a45a8ff	1372	#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
bogdanm	0:9b334a45a8ff	1373
bogdanm	0:9b334a45a8ff	1374	/***************** Bit definition for HRTIM_MCMP3R register ***************/
bogdanm	0:9b334a45a8ff	1375	#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/***************** Bit definition for HRTIM_MCMP4R register ***************/
bogdanm	0:9b334a45a8ff	1378	#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/****************** Slave control register ********************************/
bogdanm	0:9b334a45a8ff	1381	#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /!< Slave prescaler mask/
bogdanm	0:9b334a45a8ff	1382	#define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /!< prescaler bit 0 /
bogdanm	0:9b334a45a8ff	1383	#define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /!< prescaler bit 1 /
bogdanm	0:9b334a45a8ff	1384	#define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /!< prescaler bit 2 /
bogdanm	0:9b334a45a8ff	1385
bogdanm	0:9b334a45a8ff	1386	#define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /!< Slave continuous mode /
bogdanm	0:9b334a45a8ff	1387	#define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /!< Slave Retrigreable mode /
bogdanm	0:9b334a45a8ff	1388	#define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /!< Slave Half mode /
bogdanm	0:9b334a45a8ff	1389	#define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /!< Slave push-pull mode /
bogdanm	0:9b334a45a8ff	1390
bogdanm	0:9b334a45a8ff	1391	#define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /!< Slave synchronization resets /
bogdanm	0:9b334a45a8ff	1392	#define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /!< Slave synchronization starts /
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	#define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /!< Slave delayed comparator 2 mode mask /
bogdanm	0:9b334a45a8ff	1395	#define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /!< Slave delayed comparator 2 bit 0 /
bogdanm	0:9b334a45a8ff	1396	#define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /!< Slave delayed comparator 2 bit 1 /
bogdanm	0:9b334a45a8ff	1397	#define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /!< Slave delayed comparator 4 mode mask /
bogdanm	0:9b334a45a8ff	1398	#define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /!< Slave delayed comparator 4 bit 0 /
bogdanm	0:9b334a45a8ff	1399	#define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /!< Slave delayed comparator 4 bit 1 /
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	#define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /!< Slave repetition update /
bogdanm	0:9b334a45a8ff	1402	#define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /!< Slave reset update /
bogdanm	0:9b334a45a8ff	1403	#define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /!< Slave Timer A update reserved for TIM A /
bogdanm	0:9b334a45a8ff	1404	#define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /!< Slave Timer B update reserved for TIM B /
bogdanm	0:9b334a45a8ff	1405	#define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /!< Slave Timer C update reserved for TIM C /
bogdanm	0:9b334a45a8ff	1406	#define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /!< Slave Timer D update reserved for TIM D /
bogdanm	0:9b334a45a8ff	1407	#define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /!< Slave Timer E update reserved for TIM E /
bogdanm	0:9b334a45a8ff	1408	#define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /!< Master Update /
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	#define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /!< DAC synchronization mask /
bogdanm	0:9b334a45a8ff	1411	#define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /!< DAC synchronization bit 0 /
bogdanm	0:9b334a45a8ff	1412	#define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /!< DAC synchronization bit 1 /
bogdanm	0:9b334a45a8ff	1413	#define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /!< Slave preload enable /
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	#define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /!< Slave update gating mask /
bogdanm	0:9b334a45a8ff	1416	#define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /!< Update gating bit 0 /
bogdanm	0:9b334a45a8ff	1417	#define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /!< Update gating bit 1 /
bogdanm	0:9b334a45a8ff	1418	#define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /!< Update gating bit 2 /
bogdanm	0:9b334a45a8ff	1419	#define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /!< Update gating bit 3 /
bogdanm	0:9b334a45a8ff	1420
bogdanm	0:9b334a45a8ff	1421	/****************** Slave Interrupt status register ************************/
bogdanm	0:9b334a45a8ff	1422	#define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /!< Slave compare 1 interrupt flag /
bogdanm	0:9b334a45a8ff	1423	#define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /!< Slave compare 2 interrupt flag /
bogdanm	0:9b334a45a8ff	1424	#define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /!< Slave compare 3 interrupt flag /
bogdanm	0:9b334a45a8ff	1425	#define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /!< Slave compare 4 interrupt flag /
bogdanm	0:9b334a45a8ff	1426	#define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /!< Slave repetition interrupt flag /
bogdanm	0:9b334a45a8ff	1427	#define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /!< Slave update interrupt flag /
bogdanm	0:9b334a45a8ff	1428	#define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /!< Slave capture 1 interrupt flag /
bogdanm	0:9b334a45a8ff	1429	#define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /!< Slave capture 2 interrupt flag /
bogdanm	0:9b334a45a8ff	1430	#define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /!< Slave output 1 set interrupt flag /
bogdanm	0:9b334a45a8ff	1431	#define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /!< Slave output 1 reset interrupt flag /
bogdanm	0:9b334a45a8ff	1432	#define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /!< Slave output 2 set interrupt flag /
bogdanm	0:9b334a45a8ff	1433	#define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /!< Slave output 2 reset interrupt flag /
bogdanm	0:9b334a45a8ff	1434	#define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /!< Slave reset interrupt flag /
bogdanm	0:9b334a45a8ff	1435	#define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /!< Slave output 1 delay protection interrupt flag /
bogdanm	0:9b334a45a8ff	1436	#define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /!< Slave current push-pull flag /
bogdanm	0:9b334a45a8ff	1437	#define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /!< Slave idle push-pull flag /
bogdanm	0:9b334a45a8ff	1438	#define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /!< Slave output 1 state flag /
bogdanm	0:9b334a45a8ff	1439	#define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /!< Slave output 2 state flag /
bogdanm	0:9b334a45a8ff	1440	#define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /!< Slave output 1 copy flag /
bogdanm	0:9b334a45a8ff	1441	#define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /!< Slave output 2 copy flag /
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	/****************** Slave Interrupt clear register ************************/
bogdanm	0:9b334a45a8ff	1444	#define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /!< Slave compare 1 clear flag /
bogdanm	0:9b334a45a8ff	1445	#define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /!< Slave compare 2 clear flag /
bogdanm	0:9b334a45a8ff	1446	#define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /!< Slave compare 3 clear flag /
bogdanm	0:9b334a45a8ff	1447	#define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /!< Slave compare 4 clear flag /
bogdanm	0:9b334a45a8ff	1448	#define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /!< Slave repetition clear flag /
bogdanm	0:9b334a45a8ff	1449	#define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /!< Slave update clear flag /
bogdanm	0:9b334a45a8ff	1450	#define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /!< Slave capture 1 clear flag /
bogdanm	0:9b334a45a8ff	1451	#define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /!< Slave capture 2 clear flag /
bogdanm	0:9b334a45a8ff	1452	#define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /!< Slave output 1 set clear flag /
bogdanm	0:9b334a45a8ff	1453	#define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /!< Slave output 1 reset clear flag /
bogdanm	0:9b334a45a8ff	1454	#define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /!< Slave output 2 set clear flag /
bogdanm	0:9b334a45a8ff	1455	#define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /!< Slave output 2 reset clear flag /
bogdanm	0:9b334a45a8ff	1456	#define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /!< Slave reset clear flag /
bogdanm	0:9b334a45a8ff	1457	#define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /!< Slave output 1 delay protection clear flag /
bogdanm	0:9b334a45a8ff	1458	#define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /!< Slave output 2 delay protection clear flag /
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/****************** Slave DMA/Interrupt enable register *******************/
bogdanm	0:9b334a45a8ff	1461	#define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /!< Slave compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	1462	#define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /!< Slave compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	1463	#define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /!< Slave compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	1464	#define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /!< Slave compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	1465	#define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /!< Slave repetition interrupt enable /
bogdanm	0:9b334a45a8ff	1466	#define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /!< Slave update interrupt enable /
bogdanm	0:9b334a45a8ff	1467	#define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /!< Slave capture 1 interrupt enable /
bogdanm	0:9b334a45a8ff	1468	#define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /!< Slave capture 2 interrupt enable /
bogdanm	0:9b334a45a8ff	1469	#define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /!< Slave output 1 set interrupt enable /
bogdanm	0:9b334a45a8ff	1470	#define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /!< Slave output 1 reset interrupt enable /
bogdanm	0:9b334a45a8ff	1471	#define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /!< Slave output 2 set interrupt enable /
bogdanm	0:9b334a45a8ff	1472	#define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /!< Slave output 2 reset interrupt enable /
bogdanm	0:9b334a45a8ff	1473	#define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /!< Slave reset interrupt enable /
bogdanm	0:9b334a45a8ff	1474	#define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /!< Slave delay protection interrupt enable /
bogdanm	0:9b334a45a8ff	1475
bogdanm	0:9b334a45a8ff	1476	#define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /!< Slave compare 1 request enable /
bogdanm	0:9b334a45a8ff	1477	#define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /!< Slave compare 2 request enable /
bogdanm	0:9b334a45a8ff	1478	#define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /!< Slave compare 3 request enable /
bogdanm	0:9b334a45a8ff	1479	#define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /!< Slave compare 4 request enable /
bogdanm	0:9b334a45a8ff	1480	#define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /!< Slave repetition request enable /
bogdanm	0:9b334a45a8ff	1481	#define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /!< Slave update request enable /
bogdanm	0:9b334a45a8ff	1482	#define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /!< Slave capture 1 request enable /
bogdanm	0:9b334a45a8ff	1483	#define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /!< Slave capture 2 request enable /
bogdanm	0:9b334a45a8ff	1484	#define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /!< Slave output 1 set request enable /
bogdanm	0:9b334a45a8ff	1485	#define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /!< Slave output 1 reset request enable /
bogdanm	0:9b334a45a8ff	1486	#define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /!< Slave output 2 set request enable /
bogdanm	0:9b334a45a8ff	1487	#define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /!< Slave output 2 reset request enable /
bogdanm	0:9b334a45a8ff	1488	#define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /!< Slave reset request enable /
bogdanm	0:9b334a45a8ff	1489	#define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /!< Slave delay protection request enable /
bogdanm	0:9b334a45a8ff	1490
bogdanm	0:9b334a45a8ff	1491	/**************** Bit definition for HRTIM_CNTR register **************/
bogdanm	0:9b334a45a8ff	1492	#define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /!< Counter Value /
bogdanm	0:9b334a45a8ff	1493
bogdanm	0:9b334a45a8ff	1494	/***************** Bit definition for HRTIM_PER register ***************/
bogdanm	0:9b334a45a8ff	1495	#define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /!< Period Value /
bogdanm	0:9b334a45a8ff	1496
bogdanm	0:9b334a45a8ff	1497	/***************** Bit definition for HRTIM_REP register ***************/
bogdanm	0:9b334a45a8ff	1498	#define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /!< Repetition Value /
bogdanm	0:9b334a45a8ff	1499
bogdanm	0:9b334a45a8ff	1500	/***************** Bit definition for HRTIM_CMP1R register ***************/
bogdanm	0:9b334a45a8ff	1501	#define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
bogdanm	0:9b334a45a8ff	1502
bogdanm	0:9b334a45a8ff	1503	/***************** Bit definition for HRTIM_CMP1CR register ***************/
bogdanm	0:9b334a45a8ff	1504	#define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /!< Compare Value /
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	/***************** Bit definition for HRTIM_CMP2R register ***************/
bogdanm	0:9b334a45a8ff	1507	#define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	/***************** Bit definition for HRTIM_CMP3R register ***************/
bogdanm	0:9b334a45a8ff	1510	#define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	/***************** Bit definition for HRTIM_CMP4R register ***************/
bogdanm	0:9b334a45a8ff	1513	#define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
bogdanm	0:9b334a45a8ff	1514
bogdanm	0:9b334a45a8ff	1515	/***************** Bit definition for HRTIM_CPT1R register **************/
bogdanm	0:9b334a45a8ff	1516	#define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /!< Capture Value /
bogdanm	0:9b334a45a8ff	1517
bogdanm	0:9b334a45a8ff	1518	/***************** Bit definition for HRTIM_CPT2R register **************/
bogdanm	0:9b334a45a8ff	1519	#define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /!< Capture Value /
bogdanm	0:9b334a45a8ff	1520
bogdanm	0:9b334a45a8ff	1521	/****************** Bit definition for Slave Deadtime register ************/
bogdanm	0:9b334a45a8ff	1522	#define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /!< Dead time rising value /
bogdanm	0:9b334a45a8ff	1523	#define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /!< Dead time rising bit 0 /
bogdanm	0:9b334a45a8ff	1524	#define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /!< Dead time rising bit 1 /
bogdanm	0:9b334a45a8ff	1525	#define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /!< Dead time rising bit 2 /
bogdanm	0:9b334a45a8ff	1526	#define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /!< Dead time rising bit 3 /
bogdanm	0:9b334a45a8ff	1527	#define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /!< Dead time rising bit 4 /
bogdanm	0:9b334a45a8ff	1528	#define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /!< Dead time rising bit 5 /
bogdanm	0:9b334a45a8ff	1529	#define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /!< Dead time rising bit 6 /
bogdanm	0:9b334a45a8ff	1530	#define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /!< Dead time rising bit 7 /
bogdanm	0:9b334a45a8ff	1531	#define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /!< Dead time rising bit 8 /
bogdanm	0:9b334a45a8ff	1532	#define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /!< Sign dead time rising value /
bogdanm	0:9b334a45a8ff	1533	#define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /!< Dead time prescaler /
bogdanm	0:9b334a45a8ff	1534	#define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /!< Dead time prescaler bit 0 /
bogdanm	0:9b334a45a8ff	1535	#define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /!< Dead time prescaler bit 1 /
bogdanm	0:9b334a45a8ff	1536	#define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /!< Dead time prescaler bit 2 /
bogdanm	0:9b334a45a8ff	1537	#define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /!< Dead time rising sign lock /
bogdanm	0:9b334a45a8ff	1538	#define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /!< Dead time rising lock /
bogdanm	0:9b334a45a8ff	1539	#define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /!< Dead time falling value /
bogdanm	0:9b334a45a8ff	1540	#define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /!< Dead time falling bit 0 /
bogdanm	0:9b334a45a8ff	1541	#define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /!< Dead time falling bit 1 /
bogdanm	0:9b334a45a8ff	1542	#define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /!< Dead time falling bit 2 /
bogdanm	0:9b334a45a8ff	1543	#define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /!< Dead time falling bit 3 /
bogdanm	0:9b334a45a8ff	1544	#define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /!< Dead time falling bit 4 /
bogdanm	0:9b334a45a8ff	1545	#define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /!< Dead time falling bit 5 /
bogdanm	0:9b334a45a8ff	1546	#define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /!< Dead time falling bit 6 /
bogdanm	0:9b334a45a8ff	1547	#define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /!< Dead time falling bit 7 /
bogdanm	0:9b334a45a8ff	1548	#define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /!< Dead time falling bit 8 /
bogdanm	0:9b334a45a8ff	1549	#define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /!< Sign dead time falling value /
bogdanm	0:9b334a45a8ff	1550	#define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /!< Dead time falling sign lock /
bogdanm	0:9b334a45a8ff	1551	#define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /!< Dead time falling lock /
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/** Bit definition for Slave Output 1 set register ************************/
bogdanm	0:9b334a45a8ff	1554	#define HRTIM_SET1R_SST ((uint32_t)0x00000001) /!< software set trigger /
bogdanm	0:9b334a45a8ff	1555	#define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
bogdanm	0:9b334a45a8ff	1556	#define HRTIM_SET1R_PER ((uint32_t)0x00000004) /!< Timer A period /
bogdanm	0:9b334a45a8ff	1557	#define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1558	#define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1559	#define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
bogdanm	0:9b334a45a8ff	1560	#define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
bogdanm	0:9b334a45a8ff	1561
bogdanm	0:9b334a45a8ff	1562	#define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /!< Master period /
bogdanm	0:9b334a45a8ff	1563	#define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	1564	#define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	1565	#define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	1566	#define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	#define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
bogdanm	0:9b334a45a8ff	1569	#define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
bogdanm	0:9b334a45a8ff	1570	#define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
bogdanm	0:9b334a45a8ff	1571	#define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
bogdanm	0:9b334a45a8ff	1572	#define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
bogdanm	0:9b334a45a8ff	1573	#define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
bogdanm	0:9b334a45a8ff	1574	#define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
bogdanm	0:9b334a45a8ff	1575	#define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
bogdanm	0:9b334a45a8ff	1576	#define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
bogdanm	0:9b334a45a8ff	1577
bogdanm	0:9b334a45a8ff	1578	#define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
bogdanm	0:9b334a45a8ff	1579	#define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
bogdanm	0:9b334a45a8ff	1580	#define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
bogdanm	0:9b334a45a8ff	1581	#define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
bogdanm	0:9b334a45a8ff	1582	#define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
bogdanm	0:9b334a45a8ff	1583	#define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
bogdanm	0:9b334a45a8ff	1584	#define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
bogdanm	0:9b334a45a8ff	1585	#define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
bogdanm	0:9b334a45a8ff	1586	#define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
bogdanm	0:9b334a45a8ff	1587	#define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	#define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	/** Bit definition for Slave Output 1 reset register **********************/
bogdanm	0:9b334a45a8ff	1592	#define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /!< software reset trigger /
bogdanm	0:9b334a45a8ff	1593	#define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
bogdanm	0:9b334a45a8ff	1594	#define HRTIM_RST1R_PER ((uint32_t)0x00000004) /!< Timer A period /
bogdanm	0:9b334a45a8ff	1595	#define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1596	#define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1597	#define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
bogdanm	0:9b334a45a8ff	1598	#define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	#define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /!< Master period /
bogdanm	0:9b334a45a8ff	1601	#define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	1602	#define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	1603	#define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	1604	#define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	1605
bogdanm	0:9b334a45a8ff	1606	#define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
bogdanm	0:9b334a45a8ff	1607	#define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
bogdanm	0:9b334a45a8ff	1608	#define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
bogdanm	0:9b334a45a8ff	1609	#define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
bogdanm	0:9b334a45a8ff	1610	#define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
bogdanm	0:9b334a45a8ff	1611	#define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
bogdanm	0:9b334a45a8ff	1612	#define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
bogdanm	0:9b334a45a8ff	1613	#define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
bogdanm	0:9b334a45a8ff	1614	#define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	#define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
bogdanm	0:9b334a45a8ff	1617	#define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
bogdanm	0:9b334a45a8ff	1618	#define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
bogdanm	0:9b334a45a8ff	1619	#define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
bogdanm	0:9b334a45a8ff	1620	#define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
bogdanm	0:9b334a45a8ff	1621	#define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
bogdanm	0:9b334a45a8ff	1622	#define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
bogdanm	0:9b334a45a8ff	1623	#define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
bogdanm	0:9b334a45a8ff	1624	#define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
bogdanm	0:9b334a45a8ff	1625	#define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
bogdanm	0:9b334a45a8ff	1626
bogdanm	0:9b334a45a8ff	1627	#define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
bogdanm	0:9b334a45a8ff	1628
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/** Bit definition for Slave Output 2 set register ************************/
bogdanm	0:9b334a45a8ff	1631	#define HRTIM_SET2R_SST ((uint32_t)0x00000001) /!< software set trigger /
bogdanm	0:9b334a45a8ff	1632	#define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
bogdanm	0:9b334a45a8ff	1633	#define HRTIM_SET2R_PER ((uint32_t)0x00000004) /!< Timer A period /
bogdanm	0:9b334a45a8ff	1634	#define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1635	#define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1636	#define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
bogdanm	0:9b334a45a8ff	1637	#define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	#define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /!< Master period /
bogdanm	0:9b334a45a8ff	1640	#define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	1641	#define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	1642	#define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	1643	#define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	#define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
bogdanm	0:9b334a45a8ff	1646	#define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
bogdanm	0:9b334a45a8ff	1647	#define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
bogdanm	0:9b334a45a8ff	1648	#define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
bogdanm	0:9b334a45a8ff	1649	#define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
bogdanm	0:9b334a45a8ff	1650	#define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
bogdanm	0:9b334a45a8ff	1651	#define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
bogdanm	0:9b334a45a8ff	1652	#define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
bogdanm	0:9b334a45a8ff	1653	#define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	#define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
bogdanm	0:9b334a45a8ff	1656	#define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
bogdanm	0:9b334a45a8ff	1657	#define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
bogdanm	0:9b334a45a8ff	1658	#define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
bogdanm	0:9b334a45a8ff	1659	#define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
bogdanm	0:9b334a45a8ff	1660	#define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
bogdanm	0:9b334a45a8ff	1661	#define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
bogdanm	0:9b334a45a8ff	1662	#define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
bogdanm	0:9b334a45a8ff	1663	#define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
bogdanm	0:9b334a45a8ff	1664	#define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
bogdanm	0:9b334a45a8ff	1665
bogdanm	0:9b334a45a8ff	1666	#define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	/** Bit definition for Slave Output 2 reset register **********************/
bogdanm	0:9b334a45a8ff	1669	#define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /!< software reset trigger /
bogdanm	0:9b334a45a8ff	1670	#define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
bogdanm	0:9b334a45a8ff	1671	#define HRTIM_RST2R_PER ((uint32_t)0x00000004) /!< Timer A period /
bogdanm	0:9b334a45a8ff	1672	#define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1673	#define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1674	#define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
bogdanm	0:9b334a45a8ff	1675	#define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
bogdanm	0:9b334a45a8ff	1676
bogdanm	0:9b334a45a8ff	1677	#define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /!< Master period /
bogdanm	0:9b334a45a8ff	1678	#define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	1679	#define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	1680	#define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	1681	#define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	#define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
bogdanm	0:9b334a45a8ff	1684	#define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
bogdanm	0:9b334a45a8ff	1685	#define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
bogdanm	0:9b334a45a8ff	1686	#define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
bogdanm	0:9b334a45a8ff	1687	#define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
bogdanm	0:9b334a45a8ff	1688	#define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
bogdanm	0:9b334a45a8ff	1689	#define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
bogdanm	0:9b334a45a8ff	1690	#define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
bogdanm	0:9b334a45a8ff	1691	#define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
bogdanm	0:9b334a45a8ff	1692
bogdanm	0:9b334a45a8ff	1693	#define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
bogdanm	0:9b334a45a8ff	1694	#define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
bogdanm	0:9b334a45a8ff	1695	#define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
bogdanm	0:9b334a45a8ff	1696	#define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
bogdanm	0:9b334a45a8ff	1697	#define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
bogdanm	0:9b334a45a8ff	1698	#define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
bogdanm	0:9b334a45a8ff	1699	#define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
bogdanm	0:9b334a45a8ff	1700	#define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
bogdanm	0:9b334a45a8ff	1701	#define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
bogdanm	0:9b334a45a8ff	1702	#define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
bogdanm	0:9b334a45a8ff	1703
bogdanm	0:9b334a45a8ff	1704	#define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	/** Bit definition for Slave external event filtering register 1 *********/
bogdanm	0:9b334a45a8ff	1707	#define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /!< External Event 1 latch /
bogdanm	0:9b334a45a8ff	1708	#define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /!< External Event 1 filter mask /
bogdanm	0:9b334a45a8ff	1709	#define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /!< External Event 1 bit 0 /
bogdanm	0:9b334a45a8ff	1710	#define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /!< External Event 1 bit 1/
bogdanm	0:9b334a45a8ff	1711	#define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /!< External Event 1 bit 2 /
bogdanm	0:9b334a45a8ff	1712	#define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /!< External Event 1 bit 3 /
bogdanm	0:9b334a45a8ff	1713
bogdanm	0:9b334a45a8ff	1714	#define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /!< External Event 2 latch /
bogdanm	0:9b334a45a8ff	1715	#define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /!< External Event 2 filter mask /
bogdanm	0:9b334a45a8ff	1716	#define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /!< External Event 2 bit 0 /
bogdanm	0:9b334a45a8ff	1717	#define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /!< External Event 2 bit 1/
bogdanm	0:9b334a45a8ff	1718	#define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /!< External Event 2 bit 2 /
bogdanm	0:9b334a45a8ff	1719	#define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /!< External Event 2 bit 3 /
bogdanm	0:9b334a45a8ff	1720
bogdanm	0:9b334a45a8ff	1721	#define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /!< External Event 3 latch /
bogdanm	0:9b334a45a8ff	1722	#define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /!< External Event 3 filter mask /
bogdanm	0:9b334a45a8ff	1723	#define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /!< External Event 3 bit 0 /
bogdanm	0:9b334a45a8ff	1724	#define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /!< External Event 3 bit 1/
bogdanm	0:9b334a45a8ff	1725	#define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /!< External Event 3 bit 2 /
bogdanm	0:9b334a45a8ff	1726	#define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /!< External Event 3 bit 3 /
bogdanm	0:9b334a45a8ff	1727
bogdanm	0:9b334a45a8ff	1728	#define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /!< External Event 4 latch /
bogdanm	0:9b334a45a8ff	1729	#define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /!< External Event 4 filter mask /
bogdanm	0:9b334a45a8ff	1730	#define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /!< External Event 4 bit 0 /
bogdanm	0:9b334a45a8ff	1731	#define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /!< External Event 4 bit 1/
bogdanm	0:9b334a45a8ff	1732	#define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /!< External Event 4 bit 2 /
bogdanm	0:9b334a45a8ff	1733	#define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /!< External Event 4 bit 3 /
bogdanm	0:9b334a45a8ff	1734
bogdanm	0:9b334a45a8ff	1735	#define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /!< External Event 5 latch /
bogdanm	0:9b334a45a8ff	1736	#define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /!< External Event 5 filter mask /
bogdanm	0:9b334a45a8ff	1737	#define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /!< External Event 5 bit 0 /
bogdanm	0:9b334a45a8ff	1738	#define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /!< External Event 5 bit 1/
bogdanm	0:9b334a45a8ff	1739	#define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /!< External Event 5 bit 2 /
bogdanm	0:9b334a45a8ff	1740	#define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /!< External Event 5 bit 3 /
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	/** Bit definition for Slave external event filtering register 2 *********/
bogdanm	0:9b334a45a8ff	1743	#define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /!< External Event 6 latch /
bogdanm	0:9b334a45a8ff	1744	#define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /!< External Event 6 filter mask /
bogdanm	0:9b334a45a8ff	1745	#define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /!< External Event 6 bit 0 /
bogdanm	0:9b334a45a8ff	1746	#define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /!< External Event 6 bit 1/
bogdanm	0:9b334a45a8ff	1747	#define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /!< External Event 6 bit 2 /
bogdanm	0:9b334a45a8ff	1748	#define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /!< External Event 6 bit 3 /
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	#define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /!< External Event 7 latch /
bogdanm	0:9b334a45a8ff	1751	#define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /!< External Event 7 filter mask /
bogdanm	0:9b334a45a8ff	1752	#define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /!< External Event 7 bit 0 /
bogdanm	0:9b334a45a8ff	1753	#define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /!< External Event 7 bit 1/
bogdanm	0:9b334a45a8ff	1754	#define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /!< External Event 7 bit 2 /
bogdanm	0:9b334a45a8ff	1755	#define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /!< External Event 7 bit 3 /
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	#define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /!< External Event 8 latch /
bogdanm	0:9b334a45a8ff	1758	#define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /!< External Event 8 filter mask /
bogdanm	0:9b334a45a8ff	1759	#define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /!< External Event 8 bit 0 /
bogdanm	0:9b334a45a8ff	1760	#define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /!< External Event 8 bit 1/
bogdanm	0:9b334a45a8ff	1761	#define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /!< External Event 8 bit 2 /
bogdanm	0:9b334a45a8ff	1762	#define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /!< External Event 8 bit 3 /
bogdanm	0:9b334a45a8ff	1763
bogdanm	0:9b334a45a8ff	1764	#define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /!< External Event 9 latch /
bogdanm	0:9b334a45a8ff	1765	#define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /!< External Event 9 filter mask /
bogdanm	0:9b334a45a8ff	1766	#define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /!< External Event 9 bit 0 /
bogdanm	0:9b334a45a8ff	1767	#define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /!< External Event 9 bit 1/
bogdanm	0:9b334a45a8ff	1768	#define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /!< External Event 9 bit 2 /
bogdanm	0:9b334a45a8ff	1769	#define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /!< External Event 9 bit 3 /
bogdanm	0:9b334a45a8ff	1770
bogdanm	0:9b334a45a8ff	1771	#define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /!< External Event 10 latch /
bogdanm	0:9b334a45a8ff	1772	#define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /!< External Event 10 filter mask /
bogdanm	0:9b334a45a8ff	1773	#define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /!< External Event 10 bit 0 /
bogdanm	0:9b334a45a8ff	1774	#define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /!< External Event 10 bit 1/
bogdanm	0:9b334a45a8ff	1775	#define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /!< External Event 10 bit 2 /
bogdanm	0:9b334a45a8ff	1776	#define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /!< External Event 10 bit 3 /
bogdanm	0:9b334a45a8ff	1777
bogdanm	0:9b334a45a8ff	1778	/** Bit definition for Slave Timer reset register *************************/
bogdanm	0:9b334a45a8ff	1779	#define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /!< Timer update /
bogdanm	0:9b334a45a8ff	1780	#define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /!< Timer compare2 /
bogdanm	0:9b334a45a8ff	1781	#define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /!< Timer compare4 /
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	#define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /!< Master period /
bogdanm	0:9b334a45a8ff	1784	#define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /!< Master compare1 /
bogdanm	0:9b334a45a8ff	1785	#define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /!< Master compare2 /
bogdanm	0:9b334a45a8ff	1786	#define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /!< Master compare3 /
bogdanm	0:9b334a45a8ff	1787	#define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /!< Master compare4 /
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	#define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /!< External event 1 /
bogdanm	0:9b334a45a8ff	1790	#define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /!< External event 2 /
bogdanm	0:9b334a45a8ff	1791	#define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /!< External event 3 /
bogdanm	0:9b334a45a8ff	1792	#define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /!< External event 4 /
bogdanm	0:9b334a45a8ff	1793	#define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /!< External event 5 /
bogdanm	0:9b334a45a8ff	1794	#define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /!< External event 6 /
bogdanm	0:9b334a45a8ff	1795	#define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /!< External event 7 /
bogdanm	0:9b334a45a8ff	1796	#define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /!< External event 8 /
bogdanm	0:9b334a45a8ff	1797	#define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /!< External event 9 /
bogdanm	0:9b334a45a8ff	1798	#define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /!< External event 10 /
bogdanm	0:9b334a45a8ff	1799
bogdanm	0:9b334a45a8ff	1800	#define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /!< Timer B compare 1 /
bogdanm	0:9b334a45a8ff	1801	#define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /!< Timer B compare 2 /
bogdanm	0:9b334a45a8ff	1802	#define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /!< Timer B compare 4 /
bogdanm	0:9b334a45a8ff	1803
bogdanm	0:9b334a45a8ff	1804	#define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
bogdanm	0:9b334a45a8ff	1805	#define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
bogdanm	0:9b334a45a8ff	1806	#define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /!< Timer C compare 4 /
bogdanm	0:9b334a45a8ff	1807
bogdanm	0:9b334a45a8ff	1808	#define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /!< Timer D compare 1 /
bogdanm	0:9b334a45a8ff	1809	#define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /!< Timer D compare 2 /
bogdanm	0:9b334a45a8ff	1810	#define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /!< Timer D compare 4 /
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	#define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /!< Timer E compare 1 /
bogdanm	0:9b334a45a8ff	1813	#define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /!< Timer E compare 2 /
bogdanm	0:9b334a45a8ff	1814	#define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /!< Timer E compare 4 /
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/** Bit definition for Slave Timer Chopper register ***********************/
bogdanm	0:9b334a45a8ff	1817	#define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /!< Timer carrier frequency value /
bogdanm	0:9b334a45a8ff	1818	#define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /!< Timer carrier frequency value bit 0 /
bogdanm	0:9b334a45a8ff	1819	#define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /!< Timer carrier frequency value bit 1 /
bogdanm	0:9b334a45a8ff	1820	#define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /!< Timer carrier frequency value bit 2 /
bogdanm	0:9b334a45a8ff	1821	#define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /!< Timer carrier frequency value bit 3 /
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	#define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /!< Timer chopper duty cycle value /
bogdanm	0:9b334a45a8ff	1824	#define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /!< Timer chopper duty cycle value bit 0 /
bogdanm	0:9b334a45a8ff	1825	#define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /!< Timer chopper duty cycle value bit 1 /
bogdanm	0:9b334a45a8ff	1826	#define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /!< Timer chopper duty cycle value bit 2 /
bogdanm	0:9b334a45a8ff	1827
bogdanm	0:9b334a45a8ff	1828	#define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /!< Timer start pulse width value /
bogdanm	0:9b334a45a8ff	1829	#define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /!< Timer start pulse width value bit 0 /
bogdanm	0:9b334a45a8ff	1830	#define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /!< Timer start pulse width value bit 1 /
bogdanm	0:9b334a45a8ff	1831	#define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /!< Timer start pulse width value bit 2 /
bogdanm	0:9b334a45a8ff	1832	#define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /!< Timer start pulse width value bit 3 /
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	/** Bit definition for Slave Timer Capture 1 control register *************/
bogdanm	0:9b334a45a8ff	1835	#define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /!< Software capture /
bogdanm	0:9b334a45a8ff	1836	#define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /!< Update capture /
bogdanm	0:9b334a45a8ff	1837	#define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /!< External event 1 capture /
bogdanm	0:9b334a45a8ff	1838	#define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /!< External event 2 capture /
bogdanm	0:9b334a45a8ff	1839	#define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /!< External event 3 capture /
bogdanm	0:9b334a45a8ff	1840	#define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /!< External event 4 capture /
bogdanm	0:9b334a45a8ff	1841	#define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /!< External event 5 capture /
bogdanm	0:9b334a45a8ff	1842	#define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /!< External event 6 capture /
bogdanm	0:9b334a45a8ff	1843	#define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /!< External event 7 capture /
bogdanm	0:9b334a45a8ff	1844	#define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /!< External event 8 capture /
bogdanm	0:9b334a45a8ff	1845	#define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /!< External event 9 capture /
bogdanm	0:9b334a45a8ff	1846	#define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /!< External event 10 capture /
bogdanm	0:9b334a45a8ff	1847
bogdanm	0:9b334a45a8ff	1848	#define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /!< Timer A output 1 set /
bogdanm	0:9b334a45a8ff	1849	#define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /!< Timer A output 1 reset /
bogdanm	0:9b334a45a8ff	1850	#define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1851	#define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1852
bogdanm	0:9b334a45a8ff	1853	#define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /!< Timer B output 1 set /
bogdanm	0:9b334a45a8ff	1854	#define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /!< Timer B output 1 reset /
bogdanm	0:9b334a45a8ff	1855	#define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /!< Timer B compare 1 /
bogdanm	0:9b334a45a8ff	1856	#define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /!< Timer B compare 2 /
bogdanm	0:9b334a45a8ff	1857
bogdanm	0:9b334a45a8ff	1858	#define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /!< Timer C output 1 set /
bogdanm	0:9b334a45a8ff	1859	#define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /!< Timer C output 1 reset /
bogdanm	0:9b334a45a8ff	1860	#define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
bogdanm	0:9b334a45a8ff	1861	#define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
bogdanm	0:9b334a45a8ff	1862
bogdanm	0:9b334a45a8ff	1863	#define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /!< Timer D output 1 set /
bogdanm	0:9b334a45a8ff	1864	#define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /!< Timer D output 1 reset /
bogdanm	0:9b334a45a8ff	1865	#define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /!< Timer D compare 1 /
bogdanm	0:9b334a45a8ff	1866	#define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /!< Timer D compare 2 /
bogdanm	0:9b334a45a8ff	1867
bogdanm	0:9b334a45a8ff	1868	#define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /!< Timer E output 1 set /
bogdanm	0:9b334a45a8ff	1869	#define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /!< Timer E output 1 reset /
bogdanm	0:9b334a45a8ff	1870	#define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /!< Timer E compare 1 /
bogdanm	0:9b334a45a8ff	1871	#define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /!< Timer E compare 2 /
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	/** Bit definition for Slave Timer Capture 2 control register *************/
bogdanm	0:9b334a45a8ff	1874	#define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /!< Software capture /
bogdanm	0:9b334a45a8ff	1875	#define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /!< Update capture /
bogdanm	0:9b334a45a8ff	1876	#define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /!< External event 1 capture /
bogdanm	0:9b334a45a8ff	1877	#define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /!< External event 2 capture /
bogdanm	0:9b334a45a8ff	1878	#define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /!< External event 3 capture /
bogdanm	0:9b334a45a8ff	1879	#define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /!< External event 4 capture /
bogdanm	0:9b334a45a8ff	1880	#define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /!< External event 5 capture /
bogdanm	0:9b334a45a8ff	1881	#define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /!< External event 6 capture /
bogdanm	0:9b334a45a8ff	1882	#define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /!< External event 7 capture /
bogdanm	0:9b334a45a8ff	1883	#define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /!< External event 8 capture /
bogdanm	0:9b334a45a8ff	1884	#define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /!< External event 9 capture /
bogdanm	0:9b334a45a8ff	1885	#define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /!< External event 10 capture /
bogdanm	0:9b334a45a8ff	1886
bogdanm	0:9b334a45a8ff	1887	#define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /!< Timer A output 1 set /
bogdanm	0:9b334a45a8ff	1888	#define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /!< Timer A output 1 reset /
bogdanm	0:9b334a45a8ff	1889	#define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	1890	#define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	1891
bogdanm	0:9b334a45a8ff	1892	#define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /!< Timer B output 1 set /
bogdanm	0:9b334a45a8ff	1893	#define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /!< Timer B output 1 reset /
bogdanm	0:9b334a45a8ff	1894	#define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /!< Timer B compare 1 /
bogdanm	0:9b334a45a8ff	1895	#define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /!< Timer B compare 2 /
bogdanm	0:9b334a45a8ff	1896
bogdanm	0:9b334a45a8ff	1897	#define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /!< Timer C output 1 set /
bogdanm	0:9b334a45a8ff	1898	#define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /!< Timer C output 1 reset /
bogdanm	0:9b334a45a8ff	1899	#define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
bogdanm	0:9b334a45a8ff	1900	#define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
bogdanm	0:9b334a45a8ff	1901
bogdanm	0:9b334a45a8ff	1902	#define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /!< Timer D output 1 set /
bogdanm	0:9b334a45a8ff	1903	#define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /!< Timer D output 1 reset /
bogdanm	0:9b334a45a8ff	1904	#define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /!< Timer D compare 1 /
bogdanm	0:9b334a45a8ff	1905	#define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /!< Timer D compare 2 /
bogdanm	0:9b334a45a8ff	1906
bogdanm	0:9b334a45a8ff	1907	#define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /!< Timer E output 1 set /
bogdanm	0:9b334a45a8ff	1908	#define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /!< Timer E output 1 reset /
bogdanm	0:9b334a45a8ff	1909	#define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /!< Timer E compare 1 /
bogdanm	0:9b334a45a8ff	1910	#define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /!< Timer E compare 2 /
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	/** Bit definition for Slave Timer Output register ************************/
bogdanm	0:9b334a45a8ff	1913	#define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /!< Slave output 1 polarity /
bogdanm	0:9b334a45a8ff	1914	#define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /!< Slave output 1 idle mode /
bogdanm	0:9b334a45a8ff	1915	#define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /!< Slave output 1 idle state /
bogdanm	0:9b334a45a8ff	1916	#define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /!< Slave output 1 fault state /
bogdanm	0:9b334a45a8ff	1917	#define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /!< Slave output 1 fault state bit 0 /
bogdanm	0:9b334a45a8ff	1918	#define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /!< Slave output 1 fault state bit 1 /
bogdanm	0:9b334a45a8ff	1919	#define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /!< Slave output 1 chopper enable /
bogdanm	0:9b334a45a8ff	1920	#define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /!< Slave output 1 dead time idle /
bogdanm	0:9b334a45a8ff	1921
bogdanm	0:9b334a45a8ff	1922	#define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /!< Slave output deadtime enable /
bogdanm	0:9b334a45a8ff	1923	#define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /!< Slave output delay protection enable /
bogdanm	0:9b334a45a8ff	1924	#define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /!< Slave output delay protection /
bogdanm	0:9b334a45a8ff	1925	#define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /!< Slave output delay protection bit 0 /
bogdanm	0:9b334a45a8ff	1926	#define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /!< Slave output delay protection bit 1 /
bogdanm	0:9b334a45a8ff	1927	#define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /!< Slave output delay protection bit 2 /
bogdanm	0:9b334a45a8ff	1928
bogdanm	0:9b334a45a8ff	1929	#define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /!< Slave output 2 polarity /
bogdanm	0:9b334a45a8ff	1930	#define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /!< Slave output 2 idle mode /
bogdanm	0:9b334a45a8ff	1931	#define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /!< Slave output 2 idle state /
bogdanm	0:9b334a45a8ff	1932	#define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /!< Slave output 2 fault state /
bogdanm	0:9b334a45a8ff	1933	#define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /!< Slave output 2 fault state bit 0 /
bogdanm	0:9b334a45a8ff	1934	#define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /!< Slave output 2 fault state bit 1 /
bogdanm	0:9b334a45a8ff	1935	#define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /!< Slave output 2 chopper enable /
bogdanm	0:9b334a45a8ff	1936	#define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /!< Slave output 2 dead time idle /
bogdanm	0:9b334a45a8ff	1937
bogdanm	0:9b334a45a8ff	1938	/** Bit definition for Slave Timer Fault register *************************/
bogdanm	0:9b334a45a8ff	1939	#define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /!< Fault 1 enable /
bogdanm	0:9b334a45a8ff	1940	#define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /!< Fault 2 enable /
bogdanm	0:9b334a45a8ff	1941	#define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /!< Fault 3 enable /
bogdanm	0:9b334a45a8ff	1942	#define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /!< Fault 4 enable /
bogdanm	0:9b334a45a8ff	1943	#define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /!< Fault 5 enable /
bogdanm	0:9b334a45a8ff	1944	#define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /!< Fault sources lock /
bogdanm	0:9b334a45a8ff	1945
bogdanm	0:9b334a45a8ff	1946	/** Bit definition for Common HRTIM Timer control register 1 **************/
bogdanm	0:9b334a45a8ff	1947	#define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /!< Master update disable/
bogdanm	0:9b334a45a8ff	1948	#define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /!< Timer A update disable/
bogdanm	0:9b334a45a8ff	1949	#define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /!< Timer B update disable/
bogdanm	0:9b334a45a8ff	1950	#define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /!< Timer C update disable/
bogdanm	0:9b334a45a8ff	1951	#define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /!< Timer D update disable/
bogdanm	0:9b334a45a8ff	1952	#define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /!< Timer E update disable/
bogdanm	0:9b334a45a8ff	1953	#define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /!< ADC Trigger 1 update source /
bogdanm	0:9b334a45a8ff	1954	#define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /!< ADC Trigger 1 update source bit 0 /
bogdanm	0:9b334a45a8ff	1955	#define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /!< ADC Trigger 1 update source bit 1 /
bogdanm	0:9b334a45a8ff	1956	#define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /!< ADC Trigger 1 update source bit 2 /
bogdanm	0:9b334a45a8ff	1957	#define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /!< ADC Trigger 2 update source /
bogdanm	0:9b334a45a8ff	1958	#define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /!< ADC Trigger 2 update source bit 0 /
bogdanm	0:9b334a45a8ff	1959	#define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /!< ADC Trigger 2 update source bit 1 /
bogdanm	0:9b334a45a8ff	1960	#define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /!< ADC Trigger 2 update source bit 2 /
bogdanm	0:9b334a45a8ff	1961	#define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /!< ADC Trigger 3 update source /
bogdanm	0:9b334a45a8ff	1962	#define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /!< ADC Trigger 3 update source bit 0 /
bogdanm	0:9b334a45a8ff	1963	#define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /!< ADC Trigger 3 update source bit 1 /
bogdanm	0:9b334a45a8ff	1964	#define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /!< ADC Trigger 3 update source bit 2 /
bogdanm	0:9b334a45a8ff	1965	#define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /!< ADC Trigger 4 update source /
bogdanm	0:9b334a45a8ff	1966	#define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /!< ADC Trigger 4 update source bit 0 /
bogdanm	0:9b334a45a8ff	1967	#define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /!< ADC Trigger 4 update source bit 1 /
bogdanm	0:9b334a45a8ff	1968	#define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /!< ADC Trigger 4 update source bit 2 /
bogdanm	0:9b334a45a8ff	1969
bogdanm	0:9b334a45a8ff	1970	/** Bit definition for Common HRTIM Timer control register 2 **************/
bogdanm	0:9b334a45a8ff	1971	#define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /!< Master software update /
bogdanm	0:9b334a45a8ff	1972	#define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /!< Timer A software update /
bogdanm	0:9b334a45a8ff	1973	#define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /!< Timer B software update /
bogdanm	0:9b334a45a8ff	1974	#define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /!< Timer C software update /
bogdanm	0:9b334a45a8ff	1975	#define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /!< Timer D software update /
bogdanm	0:9b334a45a8ff	1976	#define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /!< Timer E software update /
bogdanm	0:9b334a45a8ff	1977	#define HRTIM_CR2_MRST ((uint32_t)0x00000100) /!< Master count software reset /
bogdanm	0:9b334a45a8ff	1978	#define HRTIM_CR2_TARST ((uint32_t)0x00000200) /!< Timer A count software reset /
bogdanm	0:9b334a45a8ff	1979	#define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /!< Timer B count software reset /
bogdanm	0:9b334a45a8ff	1980	#define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /!< Timer C count software reset /
bogdanm	0:9b334a45a8ff	1981	#define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /!< Timer D count software reset /
bogdanm	0:9b334a45a8ff	1982	#define HRTIM_CR2_TERST ((uint32_t)0x00002000) /!< Timer E count software reset /
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	/** Bit definition for Common HRTIM Timer interrupt status register *******/
bogdanm	0:9b334a45a8ff	1985	#define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /!< Fault 1 interrupt flag /
bogdanm	0:9b334a45a8ff	1986	#define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /!< Fault 2 interrupt flag /
bogdanm	0:9b334a45a8ff	1987	#define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /!< Fault 3 interrupt flag /
bogdanm	0:9b334a45a8ff	1988	#define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /!< Fault 4 interrupt flag /
bogdanm	0:9b334a45a8ff	1989	#define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /!< Fault 5 interrupt flag /
bogdanm	0:9b334a45a8ff	1990	#define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /!< System Fault interrupt flag /
bogdanm	0:9b334a45a8ff	1991	#define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /!< DLL ready interrupt flag /
bogdanm	0:9b334a45a8ff	1992	#define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /!< Burst mode period interrupt flag /
bogdanm	0:9b334a45a8ff	1993
bogdanm	0:9b334a45a8ff	1994	/** Bit definition for Common HRTIM Timer interrupt clear register ********/
bogdanm	0:9b334a45a8ff	1995	#define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /!< Fault 1 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1996	#define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /!< Fault 2 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1997	#define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /!< Fault 3 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1998	#define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /!< Fault 4 interrupt flag clear /
bogdanm	0:9b334a45a8ff	1999	#define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /!< Fault 5 interrupt flag clear /
bogdanm	0:9b334a45a8ff	2000	#define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /!< System Fault interrupt flag clear /
bogdanm	0:9b334a45a8ff	2001	#define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /!< DLL ready interrupt flag clear /
bogdanm	0:9b334a45a8ff	2002	#define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /!< Burst mode period interrupt flag clear /
bogdanm	0:9b334a45a8ff	2003
bogdanm	0:9b334a45a8ff	2004	/** Bit definition for Common HRTIM Timer interrupt enable register *******/
bogdanm	0:9b334a45a8ff	2005	#define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /!< Fault 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2006	#define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /!< Fault 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2007	#define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /!< Fault 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2008	#define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /!< Fault 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2009	#define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /!< Fault 5 interrupt enable /
bogdanm	0:9b334a45a8ff	2010	#define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /!< System Fault interrupt enable /
bogdanm	0:9b334a45a8ff	2011	#define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /!< DLL ready interrupt enable /
bogdanm	0:9b334a45a8ff	2012	#define HRTIM_IER_BMPER ((uint32_t)0x00020000) /!< Burst mode period interrupt enable /
bogdanm	0:9b334a45a8ff	2013
bogdanm	0:9b334a45a8ff	2014	/** Bit definition for Common HRTIM Timer output enable register **********/
bogdanm	0:9b334a45a8ff	2015	#define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /!< Timer A Output 1 enable /
bogdanm	0:9b334a45a8ff	2016	#define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /!< Timer A Output 2 enable /
bogdanm	0:9b334a45a8ff	2017	#define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /!< Timer B Output 1 enable /
bogdanm	0:9b334a45a8ff	2018	#define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /!< Timer B Output 2 enable /
bogdanm	0:9b334a45a8ff	2019	#define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /!< Timer C Output 1 enable /
bogdanm	0:9b334a45a8ff	2020	#define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /!< Timer C Output 2 enable /
bogdanm	0:9b334a45a8ff	2021	#define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /!< Timer D Output 1 enable /
bogdanm	0:9b334a45a8ff	2022	#define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /!< Timer D Output 2 enable /
bogdanm	0:9b334a45a8ff	2023	#define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /!< Timer E Output 1 enable /
bogdanm	0:9b334a45a8ff	2024	#define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /!< Timer E Output 2 enable /
bogdanm	0:9b334a45a8ff	2025
bogdanm	0:9b334a45a8ff	2026	/** Bit definition for Common HRTIM Timer output disable register *********/
bogdanm	0:9b334a45a8ff	2027	#define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /!< Timer A Output 1 disable /
bogdanm	0:9b334a45a8ff	2028	#define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /!< Timer A Output 2 disable /
bogdanm	0:9b334a45a8ff	2029	#define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /!< Timer B Output 1 disable /
bogdanm	0:9b334a45a8ff	2030	#define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /!< Timer B Output 2 disable /
bogdanm	0:9b334a45a8ff	2031	#define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /!< Timer C Output 1 disable /
bogdanm	0:9b334a45a8ff	2032	#define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /!< Timer C Output 2 disable /
bogdanm	0:9b334a45a8ff	2033	#define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /!< Timer D Output 1 disable /
bogdanm	0:9b334a45a8ff	2034	#define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /!< Timer D Output 2 disable /
bogdanm	0:9b334a45a8ff	2035	#define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /!< Timer E Output 1 disable /
bogdanm	0:9b334a45a8ff	2036	#define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /!< Timer E Output 2 disable /
bogdanm	0:9b334a45a8ff	2037
bogdanm	0:9b334a45a8ff	2038	/** Bit definition for Common HRTIM Timer output disable status register ***/
bogdanm	0:9b334a45a8ff	2039	#define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /!< Timer A Output 1 disable status /
bogdanm	0:9b334a45a8ff	2040	#define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /!< Timer A Output 2 disable status /
bogdanm	0:9b334a45a8ff	2041	#define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /!< Timer B Output 1 disable status /
bogdanm	0:9b334a45a8ff	2042	#define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /!< Timer B Output 2 disable status /
bogdanm	0:9b334a45a8ff	2043	#define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /!< Timer C Output 1 disable status /
bogdanm	0:9b334a45a8ff	2044	#define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /!< Timer C Output 2 disable status /
bogdanm	0:9b334a45a8ff	2045	#define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /!< Timer D Output 1 disable status /
bogdanm	0:9b334a45a8ff	2046	#define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /!< Timer D Output 2 disable status /
bogdanm	0:9b334a45a8ff	2047	#define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /!< Timer E Output 1 disable status /
bogdanm	0:9b334a45a8ff	2048	#define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /!< Timer E Output 2 disable status /
bogdanm	0:9b334a45a8ff	2049
bogdanm	0:9b334a45a8ff	2050	/** Bit definition for Common HRTIM Timer Burst mode control register ******/
bogdanm	0:9b334a45a8ff	2051	#define HRTIM_BMCR_BME ((uint32_t)0x00000001) /!< Burst mode enable /
bogdanm	0:9b334a45a8ff	2052	#define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /!< Burst mode operating mode /
bogdanm	0:9b334a45a8ff	2053	#define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /!< Burst mode clock source /
bogdanm	0:9b334a45a8ff	2054	#define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /!< Burst mode clock source bit 0 /
bogdanm	0:9b334a45a8ff	2055	#define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /!< Burst mode clock source bit 1 /
bogdanm	0:9b334a45a8ff	2056	#define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /!< Burst mode clock source bit 2 /
bogdanm	0:9b334a45a8ff	2057	#define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /!< Burst mode clock source bit 3 /
bogdanm	0:9b334a45a8ff	2058	#define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /!< Burst mode prescaler /
bogdanm	0:9b334a45a8ff	2059	#define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /!< Burst mode prescaler bit 0 /
bogdanm	0:9b334a45a8ff	2060	#define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /!< Burst mode prescaler bit 1 /
bogdanm	0:9b334a45a8ff	2061	#define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /!< Burst mode prescaler bit 2 /
bogdanm	0:9b334a45a8ff	2062	#define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /!< Burst mode prescaler bit 3 /
bogdanm	0:9b334a45a8ff	2063	#define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /!< Burst mode Preload bit /
bogdanm	0:9b334a45a8ff	2064	#define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /!< Master Timer Burst mode /
bogdanm	0:9b334a45a8ff	2065	#define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /!< Timer A Burst mode /
bogdanm	0:9b334a45a8ff	2066	#define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /!< Timer B Burst mode /
bogdanm	0:9b334a45a8ff	2067	#define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /!< Timer C Burst mode /
bogdanm	0:9b334a45a8ff	2068	#define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /!< Timer D Burst mode /
bogdanm	0:9b334a45a8ff	2069	#define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /!< Timer E Burst mode /
bogdanm	0:9b334a45a8ff	2070	#define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /!< Burst mode status /
bogdanm	0:9b334a45a8ff	2071
bogdanm	0:9b334a45a8ff	2072	/** Bit definition for Common HRTIM Timer Burst mode Trigger register *****/
bogdanm	0:9b334a45a8ff	2073	#define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /!< Software start /
bogdanm	0:9b334a45a8ff	2074	#define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /!< Master reset /
bogdanm	0:9b334a45a8ff	2075	#define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /!< Master repetition /
bogdanm	0:9b334a45a8ff	2076	#define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	2077	#define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	2078	#define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	2079	#define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	2080	#define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /!< Timer A reset /
bogdanm	0:9b334a45a8ff	2081	#define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /!< Timer A repetition /
bogdanm	0:9b334a45a8ff	2082	#define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	2083	#define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2084	#define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /!< Timer B reset /
bogdanm	0:9b334a45a8ff	2085	#define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /!< Timer B repetition /
bogdanm	0:9b334a45a8ff	2086	#define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /!< Timer B compare 1 /
bogdanm	0:9b334a45a8ff	2087	#define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /!< Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2088	#define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /!< Timer C reset /
bogdanm	0:9b334a45a8ff	2089	#define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /!< Timer C repetition /
bogdanm	0:9b334a45a8ff	2090	#define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /!< Timer C compare 1 /
bogdanm	0:9b334a45a8ff	2091	#define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /!< Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2092	#define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /!< Timer D reset /
bogdanm	0:9b334a45a8ff	2093	#define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /!< Timer D repetition /
bogdanm	0:9b334a45a8ff	2094	#define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /!< Timer D compare 1 /
bogdanm	0:9b334a45a8ff	2095	#define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /!< Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2096	#define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /!< Timer E reset /
bogdanm	0:9b334a45a8ff	2097	#define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /!< Timer E repetition /
bogdanm	0:9b334a45a8ff	2098	#define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /!< Timer E compare 1 /
bogdanm	0:9b334a45a8ff	2099	#define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /!< Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2100	#define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /!< Timer A period following External Event7 /
bogdanm	0:9b334a45a8ff	2101	#define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /!< Timer D period following External Event8 /
bogdanm	0:9b334a45a8ff	2102	#define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /!< External Event 7 /
bogdanm	0:9b334a45a8ff	2103	#define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /!< External Event 8 /
bogdanm	0:9b334a45a8ff	2104	#define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /!< on-chip Event /
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	/***************** Bit definition for HRTIM_BMCMPR register *************/
bogdanm	0:9b334a45a8ff	2107	#define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /!<!<Burst Compare Value /
bogdanm	0:9b334a45a8ff	2108
bogdanm	0:9b334a45a8ff	2109	/***************** Bit definition for HRTIM_BMPER register **************/
bogdanm	0:9b334a45a8ff	2110	#define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /!<!<Burst period Value /
bogdanm	0:9b334a45a8ff	2111
bogdanm	0:9b334a45a8ff	2112	/***************** Bit definition for HRTIM_EECR1 register **************/
bogdanm	0:9b334a45a8ff	2113	#define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /!< External event 1 source /
bogdanm	0:9b334a45a8ff	2114	#define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /!< External event 1 source bit 0 /
bogdanm	0:9b334a45a8ff	2115	#define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /!< External event 1 source bit 1 /
bogdanm	0:9b334a45a8ff	2116	#define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /!< External event 1 Polarity /
bogdanm	0:9b334a45a8ff	2117	#define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /!< External event 1 sensitivity /
bogdanm	0:9b334a45a8ff	2118	#define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /!< External event 1 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2119	#define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /!< External event 1 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2120	#define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /!< External event 1 Fast mode /
bogdanm	0:9b334a45a8ff	2121
bogdanm	0:9b334a45a8ff	2122	#define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /!< External event 2 source /
bogdanm	0:9b334a45a8ff	2123	#define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /!< External event 2 source bit 0 /
bogdanm	0:9b334a45a8ff	2124	#define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /!< External event 2 source bit 1 /
bogdanm	0:9b334a45a8ff	2125	#define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /!< External event 2 Polarity /
bogdanm	0:9b334a45a8ff	2126	#define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /!< External event 2 sensitivity /
bogdanm	0:9b334a45a8ff	2127	#define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /!< External event 2 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2128	#define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /!< External event 2 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2129	#define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /!< External event 2 Fast mode /
bogdanm	0:9b334a45a8ff	2130
bogdanm	0:9b334a45a8ff	2131	#define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /!< External event 3 source /
bogdanm	0:9b334a45a8ff	2132	#define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /!< External event 3 source bit 0 /
bogdanm	0:9b334a45a8ff	2133	#define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /!< External event 3 source bit 1 /
bogdanm	0:9b334a45a8ff	2134	#define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /!< External event 3 Polarity /
bogdanm	0:9b334a45a8ff	2135	#define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /!< External event 3 sensitivity /
bogdanm	0:9b334a45a8ff	2136	#define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /!< External event 3 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2137	#define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /!< External event 3 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2138	#define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /!< External event 3 Fast mode /
bogdanm	0:9b334a45a8ff	2139
bogdanm	0:9b334a45a8ff	2140	#define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /!< External event 4 source /
bogdanm	0:9b334a45a8ff	2141	#define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /!< External event 4 source bit 0 /
bogdanm	0:9b334a45a8ff	2142	#define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /!< External event 4 source bit 1 /
bogdanm	0:9b334a45a8ff	2143	#define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /!< External event 4 Polarity /
bogdanm	0:9b334a45a8ff	2144	#define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /!< External event 4 sensitivity /
bogdanm	0:9b334a45a8ff	2145	#define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /!< External event 4 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2146	#define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /!< External event 4 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2147	#define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /!< External event 4 Fast mode /
bogdanm	0:9b334a45a8ff	2148
bogdanm	0:9b334a45a8ff	2149	#define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /!< External event 5 source /
bogdanm	0:9b334a45a8ff	2150	#define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /!< External event 5 source bit 0 /
bogdanm	0:9b334a45a8ff	2151	#define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /!< External event 5 source bit 1 /
bogdanm	0:9b334a45a8ff	2152	#define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /!< External event 5 Polarity /
bogdanm	0:9b334a45a8ff	2153	#define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /!< External event 5 sensitivity /
bogdanm	0:9b334a45a8ff	2154	#define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /!< External event 5 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2155	#define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /!< External event 5 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2156	#define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /!< External event 5 Fast mode /
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	/***************** Bit definition for HRTIM_EECR2 register **************/
bogdanm	0:9b334a45a8ff	2159	#define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /!< External event 6 source /
bogdanm	0:9b334a45a8ff	2160	#define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /!< External event 6 source bit 0 /
bogdanm	0:9b334a45a8ff	2161	#define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /!< External event 6 source bit 1 /
bogdanm	0:9b334a45a8ff	2162	#define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /!< External event 6 Polarity /
bogdanm	0:9b334a45a8ff	2163	#define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /!< External event 6 sensitivity /
bogdanm	0:9b334a45a8ff	2164	#define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /!< External event 6 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2165	#define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /!< External event 6 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2166
bogdanm	0:9b334a45a8ff	2167	#define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /!< External event 7 source /
bogdanm	0:9b334a45a8ff	2168	#define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /!< External event 7 source bit 0 /
bogdanm	0:9b334a45a8ff	2169	#define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /!< External event 7 source bit 1 /
bogdanm	0:9b334a45a8ff	2170	#define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /!< External event 7 Polarity /
bogdanm	0:9b334a45a8ff	2171	#define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /!< External event 7 sensitivity /
bogdanm	0:9b334a45a8ff	2172	#define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /!< External event 7 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2173	#define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /!< External event 7 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	#define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /!< External event 8 source /
bogdanm	0:9b334a45a8ff	2176	#define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /!< External event 8 source bit 0 /
bogdanm	0:9b334a45a8ff	2177	#define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /!< External event 8 source bit 1 /
bogdanm	0:9b334a45a8ff	2178	#define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /!< External event 8 Polarity /
bogdanm	0:9b334a45a8ff	2179	#define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /!< External event 8 sensitivity /
bogdanm	0:9b334a45a8ff	2180	#define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /!< External event 8 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2181	#define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /!< External event 8 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2182
bogdanm	0:9b334a45a8ff	2183	#define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /!< External event 9 source /
bogdanm	0:9b334a45a8ff	2184	#define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /!< External event 9 source bit 0 /
bogdanm	0:9b334a45a8ff	2185	#define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /!< External event 9 source bit 1 /
bogdanm	0:9b334a45a8ff	2186	#define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /!< External event 9 Polarity /
bogdanm	0:9b334a45a8ff	2187	#define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /!< External event 9 sensitivity /
bogdanm	0:9b334a45a8ff	2188	#define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /!< External event 9 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2189	#define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /!< External event 9 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2190
bogdanm	0:9b334a45a8ff	2191	#define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /!< External event 10 source /
bogdanm	0:9b334a45a8ff	2192	#define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /!< External event 10 source bit 0 /
bogdanm	0:9b334a45a8ff	2193	#define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /!< External event 10 source bit 1 /
bogdanm	0:9b334a45a8ff	2194	#define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /!< External event 10 Polarity /
bogdanm	0:9b334a45a8ff	2195	#define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /!< External event 10 sensitivity /
bogdanm	0:9b334a45a8ff	2196	#define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /!< External event 10 sensitivity bit 0 /
bogdanm	0:9b334a45a8ff	2197	#define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /!< External event 10 sensitivity bit 1 /
bogdanm	0:9b334a45a8ff	2198
bogdanm	0:9b334a45a8ff	2199	/***************** Bit definition for HRTIM_EECR3 register **************/
bogdanm	0:9b334a45a8ff	2200	#define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /!< External event 6 filter /
bogdanm	0:9b334a45a8ff	2201	#define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /!< External event 6 filter bit 0 /
bogdanm	0:9b334a45a8ff	2202	#define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /!< External event 6 filter bit 1 /
bogdanm	0:9b334a45a8ff	2203	#define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /!< External event 6 filter bit 2 /
bogdanm	0:9b334a45a8ff	2204	#define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /!< External event 6 filter bit 3 /
bogdanm	0:9b334a45a8ff	2205	#define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /!< External event 7 filter /
bogdanm	0:9b334a45a8ff	2206	#define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /!< External event 7 filter bit 0 /
bogdanm	0:9b334a45a8ff	2207	#define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /!< External event 7 filter bit 1 /
bogdanm	0:9b334a45a8ff	2208	#define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /!< External event 7 filter bit 2 /
bogdanm	0:9b334a45a8ff	2209	#define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /!< External event 7 filter bit 3 /
bogdanm	0:9b334a45a8ff	2210	#define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /!< External event 8 filter /
bogdanm	0:9b334a45a8ff	2211	#define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /!< External event 8 filter bit 0 /
bogdanm	0:9b334a45a8ff	2212	#define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /!< External event 8 filter bit 1 /
bogdanm	0:9b334a45a8ff	2213	#define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /!< External event 8 filter bit 2 /
bogdanm	0:9b334a45a8ff	2214	#define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /!< External event 8 filter bit 3 /
bogdanm	0:9b334a45a8ff	2215	#define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /!< External event 9 filter /
bogdanm	0:9b334a45a8ff	2216	#define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /!< External event 9 filter bit 0 /
bogdanm	0:9b334a45a8ff	2217	#define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /!< External event 9 filter bit 1 /
bogdanm	0:9b334a45a8ff	2218	#define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /!< External event 9 filter bit 2 /
bogdanm	0:9b334a45a8ff	2219	#define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /!< External event 9 filter bit 3 /
bogdanm	0:9b334a45a8ff	2220	#define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /!< External event 10 filter /
bogdanm	0:9b334a45a8ff	2221	#define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /!< External event 10 filter bit 0 /
bogdanm	0:9b334a45a8ff	2222	#define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /!< External event 10 filter bit 1 /
bogdanm	0:9b334a45a8ff	2223	#define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /!< External event 10 filter bit 2 /
bogdanm	0:9b334a45a8ff	2224	#define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /!< External event 10 filter bit 3 /
bogdanm	0:9b334a45a8ff	2225	#define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /!< External event sampling clock division /
bogdanm	0:9b334a45a8ff	2226	#define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /!< External event sampling clock division bit 0 /
bogdanm	0:9b334a45a8ff	2227	#define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /!< External event sampling clock division bit 1 /
bogdanm	0:9b334a45a8ff	2228
bogdanm	0:9b334a45a8ff	2229	/***************** Bit definition for HRTIM_ADC1R register **************/
bogdanm	0:9b334a45a8ff	2230	#define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /!< ADC Trigger 1 on master compare 1 /
bogdanm	0:9b334a45a8ff	2231	#define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /!< ADC Trigger 1 on master compare 2 /
bogdanm	0:9b334a45a8ff	2232	#define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /!< ADC Trigger 1 on master compare 3 /
bogdanm	0:9b334a45a8ff	2233	#define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /!< ADC Trigger 1 on master compare 4 /
bogdanm	0:9b334a45a8ff	2234	#define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /!< ADC Trigger 1 on master period /
bogdanm	0:9b334a45a8ff	2235	#define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /!< ADC Trigger 1 on external event 1 /
bogdanm	0:9b334a45a8ff	2236	#define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /!< ADC Trigger 1 on external event 2 /
bogdanm	0:9b334a45a8ff	2237	#define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /!< ADC Trigger 1 on external event 3 /
bogdanm	0:9b334a45a8ff	2238	#define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /!< ADC Trigger 1 on external event 4 /
bogdanm	0:9b334a45a8ff	2239	#define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /!< ADC Trigger 1 on external event 5 /
bogdanm	0:9b334a45a8ff	2240	#define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 1 on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2241	#define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 1 on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2242	#define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 1 on Timer A compare 4 /
bogdanm	0:9b334a45a8ff	2243	#define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /!< ADC Trigger 1 on Timer A period /
bogdanm	0:9b334a45a8ff	2244	#define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /!< ADC Trigger 1 on Timer A reset /
bogdanm	0:9b334a45a8ff	2245	#define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /!< ADC Trigger 1 on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2246	#define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /!< ADC Trigger 1 on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2247	#define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /!< ADC Trigger 1 on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2248	#define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /!< ADC Trigger 1 on Timer B period /
bogdanm	0:9b334a45a8ff	2249	#define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /!< ADC Trigger 1 on Timer B reset /
bogdanm	0:9b334a45a8ff	2250	#define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /!< ADC Trigger 1 on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2251	#define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /!< ADC Trigger 1 on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2252	#define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /!< ADC Trigger 1 on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2253	#define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /!< ADC Trigger 1 on Timer C period /
bogdanm	0:9b334a45a8ff	2254	#define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /!< ADC Trigger 1 on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2255	#define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /!< ADC Trigger 1 on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2256	#define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /!< ADC Trigger 1 on Timer D compare 4 /
bogdanm	0:9b334a45a8ff	2257	#define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /!< ADC Trigger 1 on Timer D period /
bogdanm	0:9b334a45a8ff	2258	#define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 1 on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2259	#define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 1 on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2260	#define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 1 on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2261	#define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /!< ADC Trigger 1 on Timer E period /
bogdanm	0:9b334a45a8ff	2262
bogdanm	0:9b334a45a8ff	2263	/***************** Bit definition for HRTIM_ADC2R register **************/
bogdanm	0:9b334a45a8ff	2264	#define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /!< ADC Trigger 2 on master compare 1 /
bogdanm	0:9b334a45a8ff	2265	#define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /!< ADC Trigger 2 on master compare 2 /
bogdanm	0:9b334a45a8ff	2266	#define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /!< ADC Trigger 2 on master compare 3 /
bogdanm	0:9b334a45a8ff	2267	#define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /!< ADC Trigger 2 on master compare 4 /
bogdanm	0:9b334a45a8ff	2268	#define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /!< ADC Trigger 2 on master period /
bogdanm	0:9b334a45a8ff	2269	#define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /!< ADC Trigger 2 on external event 6 /
bogdanm	0:9b334a45a8ff	2270	#define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /!< ADC Trigger 2 on external event 7 /
bogdanm	0:9b334a45a8ff	2271	#define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /!< ADC Trigger 2 on external event 8 /
bogdanm	0:9b334a45a8ff	2272	#define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /!< ADC Trigger 2 on external event 9 /
bogdanm	0:9b334a45a8ff	2273	#define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /!< ADC Trigger 2 on external event 10 /
bogdanm	0:9b334a45a8ff	2274	#define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 2 on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2275	#define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 2 on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2276	#define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 2 on Timer A compare 4/
bogdanm	0:9b334a45a8ff	2277	#define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /!< ADC Trigger 2 on Timer A period /
bogdanm	0:9b334a45a8ff	2278	#define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /!< ADC Trigger 2 on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2279	#define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /!< ADC Trigger 2 on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2280	#define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /!< ADC Trigger 2 on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2281	#define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /!< ADC Trigger 2 on Timer B period /
bogdanm	0:9b334a45a8ff	2282	#define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /!< ADC Trigger 2 on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2283	#define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /!< ADC Trigger 2 on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2284	#define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /!< ADC Trigger 2 on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2285	#define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /!< ADC Trigger 2 on Timer C period /
bogdanm	0:9b334a45a8ff	2286	#define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /!< ADC Trigger 2 on Timer C reset /
bogdanm	0:9b334a45a8ff	2287	#define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /!< ADC Trigger 2 on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2288	#define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /!< ADC Trigger 2 on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2289	#define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /!< ADC Trigger 2 on Timer D compare 4/
bogdanm	0:9b334a45a8ff	2290	#define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /!< ADC Trigger 2 on Timer D period /
bogdanm	0:9b334a45a8ff	2291	#define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /!< ADC Trigger 2 on Timer D reset /
bogdanm	0:9b334a45a8ff	2292	#define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 2 on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2293	#define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 2 on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2294	#define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 2 on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2295	#define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /!< ADC Trigger 2 on Timer E reset /
bogdanm	0:9b334a45a8ff	2296
bogdanm	0:9b334a45a8ff	2297	/***************** Bit definition for HRTIM_ADC3R register **************/
bogdanm	0:9b334a45a8ff	2298	#define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /!< ADC Trigger 3 on master compare 1 /
bogdanm	0:9b334a45a8ff	2299	#define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /!< ADC Trigger 3 on master compare 2 /
bogdanm	0:9b334a45a8ff	2300	#define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /!< ADC Trigger 3 on master compare 3 /
bogdanm	0:9b334a45a8ff	2301	#define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /!< ADC Trigger 3 on master compare 4 /
bogdanm	0:9b334a45a8ff	2302	#define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /!< ADC Trigger 3 on master period /
bogdanm	0:9b334a45a8ff	2303	#define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /!< ADC Trigger 3 on external event 1 /
bogdanm	0:9b334a45a8ff	2304	#define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /!< ADC Trigger 3 on external event 2 /
bogdanm	0:9b334a45a8ff	2305	#define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /!< ADC Trigger 3 on external event 3 /
bogdanm	0:9b334a45a8ff	2306	#define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /!< ADC Trigger 3 on external event 4 /
bogdanm	0:9b334a45a8ff	2307	#define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /!< ADC Trigger 3 on external event 5 /
bogdanm	0:9b334a45a8ff	2308	#define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 3 on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2309	#define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 3 on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2310	#define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 3 on Timer A compare 4 /
bogdanm	0:9b334a45a8ff	2311	#define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /!< ADC Trigger 3 on Timer A period /
bogdanm	0:9b334a45a8ff	2312	#define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /!< ADC Trigger 3 on Timer A reset /
bogdanm	0:9b334a45a8ff	2313	#define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /!< ADC Trigger 3 on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2314	#define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /!< ADC Trigger 3 on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2315	#define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /!< ADC Trigger 3 on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2316	#define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /!< ADC Trigger 3 on Timer B period /
bogdanm	0:9b334a45a8ff	2317	#define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /!< ADC Trigger 3 on Timer B reset /
bogdanm	0:9b334a45a8ff	2318	#define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /!< ADC Trigger 3 on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2319	#define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /!< ADC Trigger 3 on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2320	#define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /!< ADC Trigger 3 on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2321	#define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /!< ADC Trigger 3 on Timer C period /
bogdanm	0:9b334a45a8ff	2322	#define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /!< ADC Trigger 3 on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2323	#define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /!< ADC Trigger 3 on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2324	#define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /!< ADC Trigger 3 on Timer D compare 4 /
bogdanm	0:9b334a45a8ff	2325	#define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /!< ADC Trigger 3 on Timer D period /
bogdanm	0:9b334a45a8ff	2326	#define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 3 on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2327	#define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 3 on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2328	#define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 3 on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2329	#define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /!< ADC Trigger 3 on Timer E period /
bogdanm	0:9b334a45a8ff	2330
bogdanm	0:9b334a45a8ff	2331	/***************** Bit definition for HRTIM_ADC4R register **************/
bogdanm	0:9b334a45a8ff	2332	#define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /!< ADC Trigger 4 on master compare 1 /
bogdanm	0:9b334a45a8ff	2333	#define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /!< ADC Trigger 4 on master compare 2 /
bogdanm	0:9b334a45a8ff	2334	#define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /!< ADC Trigger 4 on master compare 3 /
bogdanm	0:9b334a45a8ff	2335	#define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /!< ADC Trigger 4 on master compare 4 /
bogdanm	0:9b334a45a8ff	2336	#define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /!< ADC Trigger 4 on master period /
bogdanm	0:9b334a45a8ff	2337	#define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /!< ADC Trigger 4 on external event 6 /
bogdanm	0:9b334a45a8ff	2338	#define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /!< ADC Trigger 4 on external event 7 /
bogdanm	0:9b334a45a8ff	2339	#define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /!< ADC Trigger 4 on external event 8 /
bogdanm	0:9b334a45a8ff	2340	#define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /!< ADC Trigger 4 on external event 9 /
bogdanm	0:9b334a45a8ff	2341	#define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /!< ADC Trigger 4 on external event 10 /
bogdanm	0:9b334a45a8ff	2342	#define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 4 on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2343	#define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 4 on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2344	#define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 4 on Timer A compare 4/
bogdanm	0:9b334a45a8ff	2345	#define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /!< ADC Trigger 4 on Timer A period /
bogdanm	0:9b334a45a8ff	2346	#define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /!< ADC Trigger 4 on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2347	#define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /!< ADC Trigger 4 on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2348	#define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /!< ADC Trigger 4 on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2349	#define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /!< ADC Trigger 4 on Timer B period /
bogdanm	0:9b334a45a8ff	2350	#define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /!< ADC Trigger 4 on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2351	#define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /!< ADC Trigger 4 on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2352	#define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /!< ADC Trigger 4 on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2353	#define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /!< ADC Trigger 4 on Timer C period /
bogdanm	0:9b334a45a8ff	2354	#define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /!< ADC Trigger 4 on Timer C reset /
bogdanm	0:9b334a45a8ff	2355	#define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /!< ADC Trigger 4 on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2356	#define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /!< ADC Trigger 4 on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2357	#define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /!< ADC Trigger 4 on Timer D compare 4/
bogdanm	0:9b334a45a8ff	2358	#define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /!< ADC Trigger 4 on Timer D period /
bogdanm	0:9b334a45a8ff	2359	#define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /!< ADC Trigger 4 on Timer D reset /
bogdanm	0:9b334a45a8ff	2360	#define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 4 on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2361	#define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 4 on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2362	#define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 4 on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2363	#define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /!< ADC Trigger 4 on Timer E reset /
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/***************** Bit definition for HRTIM_DLLCR register **************/
bogdanm	0:9b334a45a8ff	2366	#define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /!< DLL calibration start /
bogdanm	0:9b334a45a8ff	2367	#define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /!< DLL calibration enable /
bogdanm	0:9b334a45a8ff	2368	#define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /!< DLL calibration rate /
bogdanm	0:9b334a45a8ff	2369	#define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /!< DLL calibration rate bit 0 /
bogdanm	0:9b334a45a8ff	2370	#define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /!< DLL calibration rate bit 1 /
bogdanm	0:9b334a45a8ff	2371
bogdanm	0:9b334a45a8ff	2372	/***************** Bit definition for HRTIM_FLTINR1 register *************/
bogdanm	0:9b334a45a8ff	2373	#define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /!< Fault 1 enable /
bogdanm	0:9b334a45a8ff	2374	#define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /!< Fault 1 polarity /
bogdanm	0:9b334a45a8ff	2375	#define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /!< Fault 1 source /
bogdanm	0:9b334a45a8ff	2376	#define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /!< Fault 1 filter /
bogdanm	0:9b334a45a8ff	2377	#define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /!< Fault 1 filter bit 0 /
bogdanm	0:9b334a45a8ff	2378	#define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /!< Fault 1 filter bit 1 /
bogdanm	0:9b334a45a8ff	2379	#define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /!< Fault 1 filter bit 2 /
bogdanm	0:9b334a45a8ff	2380	#define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /!< Fault 1 filter bit 3 /
bogdanm	0:9b334a45a8ff	2381	#define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /!< Fault 1 lock /
bogdanm	0:9b334a45a8ff	2382
bogdanm	0:9b334a45a8ff	2383	#define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /!< Fault 2 enable /
bogdanm	0:9b334a45a8ff	2384	#define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /!< Fault 2 polarity /
bogdanm	0:9b334a45a8ff	2385	#define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /!< Fault 2 source /
bogdanm	0:9b334a45a8ff	2386	#define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /!< Fault 2 filter /
bogdanm	0:9b334a45a8ff	2387	#define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /!< Fault 2 filter bit 0 /
bogdanm	0:9b334a45a8ff	2388	#define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /!< Fault 2 filter bit 1 /
bogdanm	0:9b334a45a8ff	2389	#define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /!< Fault 2 filter bit 2 /
bogdanm	0:9b334a45a8ff	2390	#define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /!< Fault 2 filter bit 3 /
bogdanm	0:9b334a45a8ff	2391	#define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /!< Fault 2 lock /
bogdanm	0:9b334a45a8ff	2392
bogdanm	0:9b334a45a8ff	2393	#define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /!< Fault 3 enable /
bogdanm	0:9b334a45a8ff	2394	#define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /!< Fault 3 polarity /
bogdanm	0:9b334a45a8ff	2395	#define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /!< Fault 3 source /
bogdanm	0:9b334a45a8ff	2396	#define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /!< Fault 3 filter /
bogdanm	0:9b334a45a8ff	2397	#define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /!< Fault 3 filter bit 0 /
bogdanm	0:9b334a45a8ff	2398	#define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /!< Fault 3 filter bit 1 /
bogdanm	0:9b334a45a8ff	2399	#define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /!< Fault 3 filter bit 2 /
bogdanm	0:9b334a45a8ff	2400	#define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /!< Fault 3 filter bit 3 /
bogdanm	0:9b334a45a8ff	2401	#define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /!< Fault 3 lock /
bogdanm	0:9b334a45a8ff	2402
bogdanm	0:9b334a45a8ff	2403	#define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /!< Fault 4 enable /
bogdanm	0:9b334a45a8ff	2404	#define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /!< Fault 4 polarity /
bogdanm	0:9b334a45a8ff	2405	#define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /!< Fault 4 source /
bogdanm	0:9b334a45a8ff	2406	#define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /!< Fault 4 filter /
bogdanm	0:9b334a45a8ff	2407	#define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /!< Fault 4 filter bit 0 /
bogdanm	0:9b334a45a8ff	2408	#define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /!< Fault 4 filter bit 1 /
bogdanm	0:9b334a45a8ff	2409	#define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /!< Fault 4 filter bit 2 /
bogdanm	0:9b334a45a8ff	2410	#define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /!< Fault 4 filter bit 3 /
bogdanm	0:9b334a45a8ff	2411	#define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /!< Fault 4 lock /
bogdanm	0:9b334a45a8ff	2412
bogdanm	0:9b334a45a8ff	2413	/***************** Bit definition for HRTIM_FLTINR2 register *************/
bogdanm	0:9b334a45a8ff	2414	#define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /!< Fault 5 enable /
bogdanm	0:9b334a45a8ff	2415	#define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /!< Fault 5 polarity /
bogdanm	0:9b334a45a8ff	2416	#define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /!< Fault 5 source /
bogdanm	0:9b334a45a8ff	2417	#define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /!< Fault 5 filter /
bogdanm	0:9b334a45a8ff	2418	#define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /!< Fault 5 filter bit 0 /
bogdanm	0:9b334a45a8ff	2419	#define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /!< Fault 5 filter bit 1 /
bogdanm	0:9b334a45a8ff	2420	#define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /!< Fault 5 filter bit 2 /
bogdanm	0:9b334a45a8ff	2421	#define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /!< Fault 5 filter bit 3 /
bogdanm	0:9b334a45a8ff	2422	#define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /!< Fault 5 lock /
bogdanm	0:9b334a45a8ff	2423	#define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /!< Fault sampling clock division /
bogdanm	0:9b334a45a8ff	2424	#define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /!< Fault sampling clock division bit 0 /
bogdanm	0:9b334a45a8ff	2425	#define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /!< Fault sampling clock division bit 1 /
bogdanm	0:9b334a45a8ff	2426
bogdanm	0:9b334a45a8ff	2427	/***************** Bit definition for HRTIM_BDMUPR register *************/
bogdanm	0:9b334a45a8ff	2428	#define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /!< MCR register update enable /
bogdanm	0:9b334a45a8ff	2429	#define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /!< MICR register update enable /
bogdanm	0:9b334a45a8ff	2430	#define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /!< MDIER register update enable /
bogdanm	0:9b334a45a8ff	2431	#define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /!< MCNT register update enable /
bogdanm	0:9b334a45a8ff	2432	#define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /!< MPER register update enable /
bogdanm	0:9b334a45a8ff	2433	#define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /!< MREP register update enable /
bogdanm	0:9b334a45a8ff	2434	#define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /!< MCMP1 register update enable /
bogdanm	0:9b334a45a8ff	2435	#define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /!< MCMP2 register update enable /
bogdanm	0:9b334a45a8ff	2436	#define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /!< MCMP3 register update enable /
bogdanm	0:9b334a45a8ff	2437	#define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /!< MPCMP4 register update enable /
bogdanm	0:9b334a45a8ff	2438
bogdanm	0:9b334a45a8ff	2439	/***************** Bit definition for HRTIM_BDTUPR register *************/
bogdanm	0:9b334a45a8ff	2440	#define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /!< TIMCR register update enable /
bogdanm	0:9b334a45a8ff	2441	#define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /!< TIMICR register update enable /
bogdanm	0:9b334a45a8ff	2442	#define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /!< TIMDIER register update enable /
bogdanm	0:9b334a45a8ff	2443	#define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /!< TIMCNT register update enable /
bogdanm	0:9b334a45a8ff	2444	#define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /!< TIMPER register update enable /
bogdanm	0:9b334a45a8ff	2445	#define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /!< TIMREP register update enable /
bogdanm	0:9b334a45a8ff	2446	#define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /!< TIMCMP1 register update enable /
bogdanm	0:9b334a45a8ff	2447	#define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /!< TIMCMP2 register update enable /
bogdanm	0:9b334a45a8ff	2448	#define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /!< TIMCMP3 register update enable /
bogdanm	0:9b334a45a8ff	2449	#define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /!< TIMCMP4 register update enable /
bogdanm	0:9b334a45a8ff	2450	#define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /!< TIMDTR register update enable /
bogdanm	0:9b334a45a8ff	2451	#define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /!< TIMSET1R register update enable /
bogdanm	0:9b334a45a8ff	2452	#define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /!< TIMRST1R register update enable /
bogdanm	0:9b334a45a8ff	2453	#define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /!< TIMSET2R register update enable /
bogdanm	0:9b334a45a8ff	2454	#define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /!< TIMRST2R register update enable /
bogdanm	0:9b334a45a8ff	2455	#define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /!< TIMEEFR1 register update enable /
bogdanm	0:9b334a45a8ff	2456	#define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /!< TIMEEFR2 register update enable /
bogdanm	0:9b334a45a8ff	2457	#define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /!< TIMRSTR register update enable /
bogdanm	0:9b334a45a8ff	2458	#define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /!< TIMCHPR register update enable /
bogdanm	0:9b334a45a8ff	2459	#define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /!< TIMOUTR register update enable /
bogdanm	0:9b334a45a8ff	2460	#define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /!< TIMFLTR register update enable /
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	/***************** Bit definition for HRTIM_BDMADR register *************/
bogdanm	0:9b334a45a8ff	2463	#define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /!< Burst DMA Data register /
bogdanm	0:9b334a45a8ff	2464
bogdanm	0:9b334a45a8ff	2465	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2466	/* */
bogdanm	0:9b334a45a8ff	2467	/* Analog to Digital Converter SAR (ADC) */
bogdanm	0:9b334a45a8ff	2468	/* */
bogdanm	0:9b334a45a8ff	2469	/******************************************************************************/
bogdanm	0:9b334a45a8ff	2470	/****************** Bit definition for ADC_ISR register ******************/
bogdanm	0:9b334a45a8ff	2471	#define ADC_ISR_ADRD ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) flag /
bogdanm	0:9b334a45a8ff	2472	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling flag /
bogdanm	0:9b334a45a8ff	2473	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion flag /
bogdanm	0:9b334a45a8ff	2474	#define ADC_ISR_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	2475	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< ADC overrun flag /
bogdanm	0:9b334a45a8ff	2476	#define ADC_ISR_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion flag /
bogdanm	0:9b334a45a8ff	2477	#define ADC_ISR_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions flag /
bogdanm	0:9b334a45a8ff	2478	#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 flag /
bogdanm	0:9b334a45a8ff	2479	#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 flag /
bogdanm	0:9b334a45a8ff	2480	#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 flag /
bogdanm	0:9b334a45a8ff	2481	#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow flag /
bogdanm	0:9b334a45a8ff	2482
bogdanm	0:9b334a45a8ff	2483	/****************** Bit definition for ADC_IER register ******************/
bogdanm	0:9b334a45a8ff	2484	#define ADC_IER_RDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) interrupt source /
bogdanm	0:9b334a45a8ff	2485	#define ADC_IER_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling interrupt source /
bogdanm	0:9b334a45a8ff	2486	#define ADC_IER_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion interrupt source /
bogdanm	0:9b334a45a8ff	2487	#define ADC_IER_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions interrupt source /
bogdanm	0:9b334a45a8ff	2488	#define ADC_IER_OVR ((uint32_t)0x00000010) /!< ADC overrun interrupt source /
bogdanm	0:9b334a45a8ff	2489	#define ADC_IER_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion interrupt source /
bogdanm	0:9b334a45a8ff	2490	#define ADC_IER_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions interrupt source /
bogdanm	0:9b334a45a8ff	2491	#define ADC_IER_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 interrupt source /
bogdanm	0:9b334a45a8ff	2492	#define ADC_IER_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 interrupt source /
bogdanm	0:9b334a45a8ff	2493	#define ADC_IER_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 interrupt source /
bogdanm	0:9b334a45a8ff	2494	#define ADC_IER_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow interrupt source /
bogdanm	0:9b334a45a8ff	2495
bogdanm	0:9b334a45a8ff	2496	/****************** Bit definition for ADC_CR register ******************/
bogdanm	0:9b334a45a8ff	2497	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC Enable control /
bogdanm	0:9b334a45a8ff	2498	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC Disable command /
bogdanm	0:9b334a45a8ff	2499	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC Start of Regular conversion /
bogdanm	0:9b334a45a8ff	2500	#define ADC_CR_JADSTART ((uint32_t)0x00000008) /!< ADC Start of injected conversion /
bogdanm	0:9b334a45a8ff	2501	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC Stop of Regular conversion /
bogdanm	0:9b334a45a8ff	2502	#define ADC_CR_JADSTP ((uint32_t)0x00000020) /!< ADC Stop of injected conversion /
bogdanm	0:9b334a45a8ff	2503	#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /!< ADC Voltage regulator Enable /
bogdanm	0:9b334a45a8ff	2504	#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /!< ADC ADVREGEN bit 0 /
bogdanm	0:9b334a45a8ff	2505	#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /!< ADC ADVREGEN bit 1 /
bogdanm	0:9b334a45a8ff	2506	#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /!< ADC Differential Mode for calibration /
bogdanm	0:9b334a45a8ff	2507	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC Calibration /
bogdanm	0:9b334a45a8ff	2508
bogdanm	0:9b334a45a8ff	2509	/****************** Bit definition for ADC_CFGR register ******************/
bogdanm	0:9b334a45a8ff	2510	#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /!< ADC DMA Enable /
bogdanm	0:9b334a45a8ff	2511	#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /!< ADC DMA configuration /
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	#define ADC_CFGR_RES ((uint32_t)0x00000018) /!< ADC Data resolution /
bogdanm	0:9b334a45a8ff	2514	#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /!< ADC RES bit 0 /
bogdanm	0:9b334a45a8ff	2515	#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /!< ADC RES bit 1 /
bogdanm	0:9b334a45a8ff	2516
bogdanm	0:9b334a45a8ff	2517	#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /!< ADC Data Alignment /
bogdanm	0:9b334a45a8ff	2518
bogdanm	0:9b334a45a8ff	2519	#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /!< ADC External trigger selection for regular group /
bogdanm	0:9b334a45a8ff	2520	#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /!< ADC EXTSEL bit 0 /
bogdanm	0:9b334a45a8ff	2521	#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /!< ADC EXTSEL bit 1 /
bogdanm	0:9b334a45a8ff	2522	#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /!< ADC EXTSEL bit 2 /
bogdanm	0:9b334a45a8ff	2523	#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /!< ADC EXTSEL bit 3 /
bogdanm	0:9b334a45a8ff	2524
bogdanm	0:9b334a45a8ff	2525	#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /!< ADC External trigger enable and polarity selection for regular channels /
bogdanm	0:9b334a45a8ff	2526	#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /!< ADC EXTEN bit 0 /
bogdanm	0:9b334a45a8ff	2527	#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /!< ADC EXTEN bit 1 /
bogdanm	0:9b334a45a8ff	2528
bogdanm	0:9b334a45a8ff	2529	#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /!< ADC overrun mode /
bogdanm	0:9b334a45a8ff	2530	#define ADC_CFGR_CONT ((uint32_t)0x00002000) /!< ADC Single/continuous conversion mode for regular conversion /
bogdanm	0:9b334a45a8ff	2531	#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /!< ADC Delayed conversion mode /
bogdanm	0:9b334a45a8ff	2532	#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /!< ADC Discontinuous mode for regular channels /
bogdanm	0:9b334a45a8ff	2533
bogdanm	0:9b334a45a8ff	2534	#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /!< ADC Discontinuous mode channel count /
bogdanm	0:9b334a45a8ff	2535	#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /!< ADC DISCNUM bit 0 /
bogdanm	0:9b334a45a8ff	2536	#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /!< ADC DISCNUM bit 1 /
bogdanm	0:9b334a45a8ff	2537	#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /!< ADC DISCNUM bit 2 /
bogdanm	0:9b334a45a8ff	2538
bogdanm	0:9b334a45a8ff	2539	#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /!< ADC Discontinuous mode on injected channels /
bogdanm	0:9b334a45a8ff	2540	#define ADC_CFGR_JQM ((uint32_t)0x00200000) /!< ADC JSQR Queue mode /
bogdanm	0:9b334a45a8ff	2541	#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /!< Enable the watchdog 1 on a single channel or on all channels /
bogdanm	0:9b334a45a8ff	2542	#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /!< ADC Analog watchdog 1 enable on regular Channels /
bogdanm	0:9b334a45a8ff	2543	#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /!< ADC Analog watchdog 1 enable on injected Channels /
bogdanm	0:9b334a45a8ff	2544	#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /!< ADC Automatic injected group conversion /
bogdanm	0:9b334a45a8ff	2545
bogdanm	0:9b334a45a8ff	2546	#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /!< ADC Analog watchdog 1 Channel selection /
bogdanm	0:9b334a45a8ff	2547	#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /!< ADC AWD1CH bit 0 /
bogdanm	0:9b334a45a8ff	2548	#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /!< ADC AWD1CH bit 1 /
bogdanm	0:9b334a45a8ff	2549	#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /!< ADC AWD1CH bit 2 /
bogdanm	0:9b334a45a8ff	2550	#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /!< ADC AWD1CH bit 3 /
bogdanm	0:9b334a45a8ff	2551	#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /!< ADC AWD1CH bit 4 /
bogdanm	0:9b334a45a8ff	2552
bogdanm	0:9b334a45a8ff	2553	/****************** Bit definition for ADC_SMPR1 register ******************/
bogdanm	0:9b334a45a8ff	2554	#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /!< ADC Channel 0 Sampling time selection /
bogdanm	0:9b334a45a8ff	2555	#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /!< ADC SMP0 bit 0 /
bogdanm	0:9b334a45a8ff	2556	#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /!< ADC SMP0 bit 1 /
bogdanm	0:9b334a45a8ff	2557	#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /!< ADC SMP0 bit 2 /
bogdanm	0:9b334a45a8ff	2558
bogdanm	0:9b334a45a8ff	2559	#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /!< ADC Channel 1 Sampling time selection /
bogdanm	0:9b334a45a8ff	2560	#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /!< ADC SMP1 bit 0 /
bogdanm	0:9b334a45a8ff	2561	#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /!< ADC SMP1 bit 1 /
bogdanm	0:9b334a45a8ff	2562	#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /!< ADC SMP1 bit 2 /
bogdanm	0:9b334a45a8ff	2563
bogdanm	0:9b334a45a8ff	2564	#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /!< ADC Channel 2 Sampling time selection /
bogdanm	0:9b334a45a8ff	2565	#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /!< ADC SMP2 bit 0 /
bogdanm	0:9b334a45a8ff	2566	#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /!< ADC SMP2 bit 1 /
bogdanm	0:9b334a45a8ff	2567	#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /!< ADC SMP2 bit 2 /
bogdanm	0:9b334a45a8ff	2568
bogdanm	0:9b334a45a8ff	2569	#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /!< ADC Channel 3 Sampling time selection /
bogdanm	0:9b334a45a8ff	2570	#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /!< ADC SMP3 bit 0 /
bogdanm	0:9b334a45a8ff	2571	#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /!< ADC SMP3 bit 1 /
bogdanm	0:9b334a45a8ff	2572	#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /!< ADC SMP3 bit 2 /
bogdanm	0:9b334a45a8ff	2573
bogdanm	0:9b334a45a8ff	2574	#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /!< ADC Channel 4 Sampling time selection /
bogdanm	0:9b334a45a8ff	2575	#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /!< ADC SMP4 bit 0 /
bogdanm	0:9b334a45a8ff	2576	#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /!< ADC SMP4 bit 1 /
bogdanm	0:9b334a45a8ff	2577	#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /!< ADC SMP4 bit 2 /
bogdanm	0:9b334a45a8ff	2578
bogdanm	0:9b334a45a8ff	2579	#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /!< ADC Channel 5 Sampling time selection /
bogdanm	0:9b334a45a8ff	2580	#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /!< ADC SMP5 bit 0 /
bogdanm	0:9b334a45a8ff	2581	#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /!< ADC SMP5 bit 1 /
bogdanm	0:9b334a45a8ff	2582	#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /!< ADC SMP5 bit 2 /
bogdanm	0:9b334a45a8ff	2583
bogdanm	0:9b334a45a8ff	2584	#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /!< ADC Channel 6 Sampling time selection /
bogdanm	0:9b334a45a8ff	2585	#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /!< ADC SMP6 bit 0 /
bogdanm	0:9b334a45a8ff	2586	#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /!< ADC SMP6 bit 1 /
bogdanm	0:9b334a45a8ff	2587	#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /!< ADC SMP6 bit 2 /
bogdanm	0:9b334a45a8ff	2588
bogdanm	0:9b334a45a8ff	2589	#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /!< ADC Channel 7 Sampling time selection /
bogdanm	0:9b334a45a8ff	2590	#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /!< ADC SMP7 bit 0 /
bogdanm	0:9b334a45a8ff	2591	#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /!< ADC SMP7 bit 1 /
bogdanm	0:9b334a45a8ff	2592	#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /!< ADC SMP7 bit 2 /
bogdanm	0:9b334a45a8ff	2593
bogdanm	0:9b334a45a8ff	2594	#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /!< ADC Channel 8 Sampling time selection /
bogdanm	0:9b334a45a8ff	2595	#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /!< ADC SMP8 bit 0 /
bogdanm	0:9b334a45a8ff	2596	#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /!< ADC SMP8 bit 1 /
bogdanm	0:9b334a45a8ff	2597	#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /!< ADC SMP8 bit 2 /
bogdanm	0:9b334a45a8ff	2598
bogdanm	0:9b334a45a8ff	2599	#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /!< ADC Channel 9 Sampling time selection /
bogdanm	0:9b334a45a8ff	2600	#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /!< ADC SMP9 bit 0 /
bogdanm	0:9b334a45a8ff	2601	#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /!< ADC SMP9 bit 1 /
bogdanm	0:9b334a45a8ff	2602	#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /!< ADC SMP9 bit 2 /
bogdanm	0:9b334a45a8ff	2603
bogdanm	0:9b334a45a8ff	2604	/****************** Bit definition for ADC_SMPR2 register ******************/
bogdanm	0:9b334a45a8ff	2605	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< ADC Channel 10 Sampling time selection /
bogdanm	0:9b334a45a8ff	2606	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< ADC SMP10 bit 0 /
bogdanm	0:9b334a45a8ff	2607	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< ADC SMP10 bit 1 /
bogdanm	0:9b334a45a8ff	2608	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< ADC SMP10 bit 2 /
bogdanm	0:9b334a45a8ff	2609
bogdanm	0:9b334a45a8ff	2610	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< ADC Channel 11 Sampling time selection /
bogdanm	0:9b334a45a8ff	2611	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< ADC SMP11 bit 0 /
bogdanm	0:9b334a45a8ff	2612	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< ADC SMP11 bit 1 /
bogdanm	0:9b334a45a8ff	2613	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< ADC SMP11 bit 2 /
bogdanm	0:9b334a45a8ff	2614
bogdanm	0:9b334a45a8ff	2615	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< ADC Channel 12 Sampling time selection /
bogdanm	0:9b334a45a8ff	2616	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< ADC SMP12 bit 0 /
bogdanm	0:9b334a45a8ff	2617	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< ADC SMP12 bit 1 /
bogdanm	0:9b334a45a8ff	2618	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< ADC SMP12 bit 2 /
bogdanm	0:9b334a45a8ff	2619
bogdanm	0:9b334a45a8ff	2620	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< ADC Channel 13 Sampling time selection /
bogdanm	0:9b334a45a8ff	2621	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< ADC SMP13 bit 0 /
bogdanm	0:9b334a45a8ff	2622	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< ADC SMP13 bit 1 /
bogdanm	0:9b334a45a8ff	2623	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< ADC SMP13 bit 2 /
bogdanm	0:9b334a45a8ff	2624
bogdanm	0:9b334a45a8ff	2625	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< ADC Channel 14 Sampling time selection /
bogdanm	0:9b334a45a8ff	2626	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< ADC SMP14 bit 0 /
bogdanm	0:9b334a45a8ff	2627	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< ADC SMP14 bit 1 /
bogdanm	0:9b334a45a8ff	2628	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< ADC SMP14 bit 2 /
bogdanm	0:9b334a45a8ff	2629
bogdanm	0:9b334a45a8ff	2630	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< ADC Channel 15 Sampling time selection /
bogdanm	0:9b334a45a8ff	2631	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< ADC SMP15 bit 0 /
bogdanm	0:9b334a45a8ff	2632	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< ADC SMP15 bit 1 /
bogdanm	0:9b334a45a8ff	2633	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< ADC SMP15 bit 2 /
bogdanm	0:9b334a45a8ff	2634
bogdanm	0:9b334a45a8ff	2635	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< ADC Channel 16 Sampling time selection /
bogdanm	0:9b334a45a8ff	2636	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< ADC SMP16 bit 0 /
bogdanm	0:9b334a45a8ff	2637	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< ADC SMP16 bit 1 /
bogdanm	0:9b334a45a8ff	2638	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< ADC SMP16 bit 2 /
bogdanm	0:9b334a45a8ff	2639
bogdanm	0:9b334a45a8ff	2640	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< ADC Channel 17 Sampling time selection /
bogdanm	0:9b334a45a8ff	2641	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< ADC SMP17 bit 0 /
bogdanm	0:9b334a45a8ff	2642	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< ADC SMP17 bit 1 /
bogdanm	0:9b334a45a8ff	2643	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< ADC SMP17 bit 2 /
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< ADC Channel 18 Sampling time selection /
bogdanm	0:9b334a45a8ff	2646	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< ADC SMP18 bit 0 /
bogdanm	0:9b334a45a8ff	2647	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< ADC SMP18 bit 1 /
bogdanm	0:9b334a45a8ff	2648	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< ADC SMP18 bit 2 /
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/****************** Bit definition for ADC_TR1 register ******************/
bogdanm	0:9b334a45a8ff	2651	#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /!< ADC Analog watchdog 1 lower threshold /
bogdanm	0:9b334a45a8ff	2652	#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /!< ADC LT1 bit 0 /
bogdanm	0:9b334a45a8ff	2653	#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /!< ADC LT1 bit 1 /
bogdanm	0:9b334a45a8ff	2654	#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /!< ADC LT1 bit 2 /
bogdanm	0:9b334a45a8ff	2655	#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /!< ADC LT1 bit 3 /
bogdanm	0:9b334a45a8ff	2656	#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /!< ADC LT1 bit 4 /
bogdanm	0:9b334a45a8ff	2657	#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /!< ADC LT1 bit 5 /
bogdanm	0:9b334a45a8ff	2658	#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /!< ADC LT1 bit 6 /
bogdanm	0:9b334a45a8ff	2659	#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /!< ADC LT1 bit 7 /
bogdanm	0:9b334a45a8ff	2660	#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /!< ADC LT1 bit 8 /
bogdanm	0:9b334a45a8ff	2661	#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /!< ADC LT1 bit 9 /
bogdanm	0:9b334a45a8ff	2662	#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /!< ADC LT1 bit 10 /
bogdanm	0:9b334a45a8ff	2663	#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /!< ADC LT1 bit 11 /
bogdanm	0:9b334a45a8ff	2664
bogdanm	0:9b334a45a8ff	2665	#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /!< ADC Analog watchdog 1 higher threshold /
bogdanm	0:9b334a45a8ff	2666	#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /!< ADC HT1 bit 0 /
bogdanm	0:9b334a45a8ff	2667	#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /!< ADC HT1 bit 1 /
bogdanm	0:9b334a45a8ff	2668	#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /!< ADC HT1 bit 2 /
bogdanm	0:9b334a45a8ff	2669	#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /!< ADC HT1 bit 3 /
bogdanm	0:9b334a45a8ff	2670	#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /!< ADC HT1 bit 4 /
bogdanm	0:9b334a45a8ff	2671	#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /!< ADC HT1 bit 5 /
bogdanm	0:9b334a45a8ff	2672	#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /!< ADC HT1 bit 6 /
bogdanm	0:9b334a45a8ff	2673	#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /!< ADC HT1 bit 7 /
bogdanm	0:9b334a45a8ff	2674	#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /!< ADC HT1 bit 8 /
bogdanm	0:9b334a45a8ff	2675	#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /!< ADC HT1 bit 9 /
bogdanm	0:9b334a45a8ff	2676	#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /!< ADC HT1 bit 10 /
bogdanm	0:9b334a45a8ff	2677	#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /!< ADC HT1 bit 11 /
bogdanm	0:9b334a45a8ff	2678
bogdanm	0:9b334a45a8ff	2679	/****************** Bit definition for ADC_TR2 register ******************/
bogdanm	0:9b334a45a8ff	2680	#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 2 lower threshold /
bogdanm	0:9b334a45a8ff	2681	#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /!< ADC LT2 bit 0 /
bogdanm	0:9b334a45a8ff	2682	#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /!< ADC LT2 bit 1 /
bogdanm	0:9b334a45a8ff	2683	#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /!< ADC LT2 bit 2 /
bogdanm	0:9b334a45a8ff	2684	#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /!< ADC LT2 bit 3 /
bogdanm	0:9b334a45a8ff	2685	#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /!< ADC LT2 bit 4 /
bogdanm	0:9b334a45a8ff	2686	#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /!< ADC LT2 bit 5 /
bogdanm	0:9b334a45a8ff	2687	#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /!< ADC LT2 bit 6 /
bogdanm	0:9b334a45a8ff	2688	#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /!< ADC LT2 bit 7 /
bogdanm	0:9b334a45a8ff	2689
bogdanm	0:9b334a45a8ff	2690	#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 2 higher threshold /
bogdanm	0:9b334a45a8ff	2691	#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /!< ADC HT2 bit 0 /
bogdanm	0:9b334a45a8ff	2692	#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /!< ADC HT2 bit 1 /
bogdanm	0:9b334a45a8ff	2693	#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /!< ADC HT2 bit 2 /
bogdanm	0:9b334a45a8ff	2694	#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /!< ADC HT2 bit 3 /
bogdanm	0:9b334a45a8ff	2695	#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /!< ADC HT2 bit 4 /
bogdanm	0:9b334a45a8ff	2696	#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /!< ADC HT2 bit 5 /
bogdanm	0:9b334a45a8ff	2697	#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /!< ADC HT2 bit 6 /
bogdanm	0:9b334a45a8ff	2698	#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /!< ADC HT2 bit 7 /
bogdanm	0:9b334a45a8ff	2699
bogdanm	0:9b334a45a8ff	2700	/****************** Bit definition for ADC_TR3 register ******************/
bogdanm	0:9b334a45a8ff	2701	#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 3 lower threshold /
bogdanm	0:9b334a45a8ff	2702	#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /!< ADC LT3 bit 0 /
bogdanm	0:9b334a45a8ff	2703	#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /!< ADC LT3 bit 1 /
bogdanm	0:9b334a45a8ff	2704	#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /!< ADC LT3 bit 2 /
bogdanm	0:9b334a45a8ff	2705	#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /!< ADC LT3 bit 3 /
bogdanm	0:9b334a45a8ff	2706	#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /!< ADC LT3 bit 4 /
bogdanm	0:9b334a45a8ff	2707	#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /!< ADC LT3 bit 5 /
bogdanm	0:9b334a45a8ff	2708	#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /!< ADC LT3 bit 6 /
bogdanm	0:9b334a45a8ff	2709	#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /!< ADC LT3 bit 7 /
bogdanm	0:9b334a45a8ff	2710
bogdanm	0:9b334a45a8ff	2711	#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 3 higher threshold /
bogdanm	0:9b334a45a8ff	2712	#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /!< ADC HT3 bit 0 /
bogdanm	0:9b334a45a8ff	2713	#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /!< ADC HT3 bit 1 /
bogdanm	0:9b334a45a8ff	2714	#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /!< ADC HT3 bit 2 /
bogdanm	0:9b334a45a8ff	2715	#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /!< ADC HT3 bit 3 /
bogdanm	0:9b334a45a8ff	2716	#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /!< ADC HT3 bit 4 /
bogdanm	0:9b334a45a8ff	2717	#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /!< ADC HT3 bit 5 /
bogdanm	0:9b334a45a8ff	2718	#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /!< ADC HT3 bit 6 /
bogdanm	0:9b334a45a8ff	2719	#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /!< ADC HT3 bit 7 /
bogdanm	0:9b334a45a8ff	2720
bogdanm	0:9b334a45a8ff	2721	/****************** Bit definition for ADC_SQR1 register ******************/
bogdanm	0:9b334a45a8ff	2722	#define ADC_SQR1_L ((uint32_t)0x0000000F) /!< ADC regular channel sequence length /
bogdanm	0:9b334a45a8ff	2723	#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /!< ADC L bit 0 /
bogdanm	0:9b334a45a8ff	2724	#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /!< ADC L bit 1 /
bogdanm	0:9b334a45a8ff	2725	#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /!< ADC L bit 2 /
bogdanm	0:9b334a45a8ff	2726	#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /!< ADC L bit 3 /
bogdanm	0:9b334a45a8ff	2727
bogdanm	0:9b334a45a8ff	2728	#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /!< ADC 1st conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2729	#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /!< ADC SQ1 bit 0 /
bogdanm	0:9b334a45a8ff	2730	#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /!< ADC SQ1 bit 1 /
bogdanm	0:9b334a45a8ff	2731	#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /!< ADC SQ1 bit 2 /
bogdanm	0:9b334a45a8ff	2732	#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /!< ADC SQ1 bit 3 /
bogdanm	0:9b334a45a8ff	2733	#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /!< ADC SQ1 bit 4 /
bogdanm	0:9b334a45a8ff	2734
bogdanm	0:9b334a45a8ff	2735	#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /!< ADC 2nd conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2736	#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /!< ADC SQ2 bit 0 /
bogdanm	0:9b334a45a8ff	2737	#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /!< ADC SQ2 bit 1 /
bogdanm	0:9b334a45a8ff	2738	#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /!< ADC SQ2 bit 2 /
bogdanm	0:9b334a45a8ff	2739	#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /!< ADC SQ2 bit 3 /
bogdanm	0:9b334a45a8ff	2740	#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /!< ADC SQ2 bit 4 /
bogdanm	0:9b334a45a8ff	2741
bogdanm	0:9b334a45a8ff	2742	#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /!< ADC 3rd conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2743	#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /!< ADC SQ3 bit 0 /
bogdanm	0:9b334a45a8ff	2744	#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /!< ADC SQ3 bit 1 /
bogdanm	0:9b334a45a8ff	2745	#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /!< ADC SQ3 bit 2 /
bogdanm	0:9b334a45a8ff	2746	#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /!< ADC SQ3 bit 3 /
bogdanm	0:9b334a45a8ff	2747	#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /!< ADC SQ3 bit 4 /
bogdanm	0:9b334a45a8ff	2748
bogdanm	0:9b334a45a8ff	2749	#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /!< ADC 4th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2750	#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /!< ADC SQ4 bit 0 /
bogdanm	0:9b334a45a8ff	2751	#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /!< ADC SQ4 bit 1 /
bogdanm	0:9b334a45a8ff	2752	#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /!< ADC SQ4 bit 2 /
bogdanm	0:9b334a45a8ff	2753	#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /!< ADC SQ4 bit 3 /
bogdanm	0:9b334a45a8ff	2754	#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /!< ADC SQ4 bit 4 /
bogdanm	0:9b334a45a8ff	2755
bogdanm	0:9b334a45a8ff	2756	/****************** Bit definition for ADC_SQR2 register ******************/
bogdanm	0:9b334a45a8ff	2757	#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /!< ADC 5th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2758	#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /!< ADC SQ5 bit 0 /
bogdanm	0:9b334a45a8ff	2759	#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /!< ADC SQ5 bit 1 /
bogdanm	0:9b334a45a8ff	2760	#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /!< ADC SQ5 bit 2 /
bogdanm	0:9b334a45a8ff	2761	#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /!< ADC SQ5 bit 3 /
bogdanm	0:9b334a45a8ff	2762	#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /!< ADC SQ5 bit 4 /
bogdanm	0:9b334a45a8ff	2763
bogdanm	0:9b334a45a8ff	2764	#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /!< ADC 6th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2765	#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /!< ADC SQ6 bit 0 /
bogdanm	0:9b334a45a8ff	2766	#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /!< ADC SQ6 bit 1 /
bogdanm	0:9b334a45a8ff	2767	#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /!< ADC SQ6 bit 2 /
bogdanm	0:9b334a45a8ff	2768	#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /!< ADC SQ6 bit 3 /
bogdanm	0:9b334a45a8ff	2769	#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /!< ADC SQ6 bit 4 /
bogdanm	0:9b334a45a8ff	2770
bogdanm	0:9b334a45a8ff	2771	#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /!< ADC 7th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2772	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /!< ADC SQ7 bit 0 /
bogdanm	0:9b334a45a8ff	2773	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /!< ADC SQ7 bit 1 /
bogdanm	0:9b334a45a8ff	2774	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /!< ADC SQ7 bit 2 /
bogdanm	0:9b334a45a8ff	2775	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /!< ADC SQ7 bit 3 /
bogdanm	0:9b334a45a8ff	2776	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /!< ADC SQ7 bit 4 /
bogdanm	0:9b334a45a8ff	2777
bogdanm	0:9b334a45a8ff	2778	#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /!< ADC 8th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2779	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /!< ADC SQ8 bit 0 /
bogdanm	0:9b334a45a8ff	2780	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /!< ADC SQ8 bit 1 /
bogdanm	0:9b334a45a8ff	2781	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /!< ADC SQ8 bit 2 /
bogdanm	0:9b334a45a8ff	2782	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /!< ADC SQ8 bit 3 /
bogdanm	0:9b334a45a8ff	2783	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /!< ADC SQ8 bit 4 /
bogdanm	0:9b334a45a8ff	2784
bogdanm	0:9b334a45a8ff	2785	#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /!< ADC 9th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2786	#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /!< ADC SQ9 bit 0 /
bogdanm	0:9b334a45a8ff	2787	#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /!< ADC SQ9 bit 1 /
bogdanm	0:9b334a45a8ff	2788	#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /!< ADC SQ9 bit 2 /
bogdanm	0:9b334a45a8ff	2789	#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /!< ADC SQ9 bit 3 /
bogdanm	0:9b334a45a8ff	2790	#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /!< ADC SQ9 bit 4 /
bogdanm	0:9b334a45a8ff	2791
bogdanm	0:9b334a45a8ff	2792	/****************** Bit definition for ADC_SQR3 register ******************/
bogdanm	0:9b334a45a8ff	2793	#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /!< ADC 10th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2794	#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /!< ADC SQ10 bit 0 /
bogdanm	0:9b334a45a8ff	2795	#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /!< ADC SQ10 bit 1 /
bogdanm	0:9b334a45a8ff	2796	#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /!< ADC SQ10 bit 2 /
bogdanm	0:9b334a45a8ff	2797	#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /!< ADC SQ10 bit 3 /
bogdanm	0:9b334a45a8ff	2798	#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /!< ADC SQ10 bit 4 /
bogdanm	0:9b334a45a8ff	2799
bogdanm	0:9b334a45a8ff	2800	#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /!< ADC 11th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2801	#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /!< ADC SQ11 bit 0 /
bogdanm	0:9b334a45a8ff	2802	#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /!< ADC SQ11 bit 1 /
bogdanm	0:9b334a45a8ff	2803	#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /!< ADC SQ11 bit 2 /
bogdanm	0:9b334a45a8ff	2804	#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /!< ADC SQ11 bit 3 /
bogdanm	0:9b334a45a8ff	2805	#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /!< ADC SQ11 bit 4 /
bogdanm	0:9b334a45a8ff	2806
bogdanm	0:9b334a45a8ff	2807	#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /!< ADC 12th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2808	#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /!< ADC SQ12 bit 0 /
bogdanm	0:9b334a45a8ff	2809	#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /!< ADC SQ12 bit 1 /
bogdanm	0:9b334a45a8ff	2810	#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /!< ADC SQ12 bit 2 /
bogdanm	0:9b334a45a8ff	2811	#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /!< ADC SQ12 bit 3 /
bogdanm	0:9b334a45a8ff	2812	#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /!< ADC SQ12 bit 4 /
bogdanm	0:9b334a45a8ff	2813
bogdanm	0:9b334a45a8ff	2814	#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /!< ADC 13th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2815	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /!< ADC SQ13 bit 0 /
bogdanm	0:9b334a45a8ff	2816	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /!< ADC SQ13 bit 1 /
bogdanm	0:9b334a45a8ff	2817	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /!< ADC SQ13 bit 2 /
bogdanm	0:9b334a45a8ff	2818	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /!< ADC SQ13 bit 3 /
bogdanm	0:9b334a45a8ff	2819	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /!< ADC SQ13 bit 4 /
bogdanm	0:9b334a45a8ff	2820
bogdanm	0:9b334a45a8ff	2821	#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /!< ADC 14th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2822	#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /!< ADC SQ14 bit 0 /
bogdanm	0:9b334a45a8ff	2823	#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /!< ADC SQ14 bit 1 /
bogdanm	0:9b334a45a8ff	2824	#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /!< ADC SQ14 bit 2 /
bogdanm	0:9b334a45a8ff	2825	#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /!< ADC SQ14 bit 3 /
bogdanm	0:9b334a45a8ff	2826	#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /!< ADC SQ14 bit 4 /
bogdanm	0:9b334a45a8ff	2827
bogdanm	0:9b334a45a8ff	2828	/****************** Bit definition for ADC_SQR4 register ******************/
bogdanm	0:9b334a45a8ff	2829	#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /!< ADC 15th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2830	#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /!< ADC SQ15 bit 0 /
bogdanm	0:9b334a45a8ff	2831	#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /!< ADC SQ15 bit 1 /
bogdanm	0:9b334a45a8ff	2832	#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /!< ADC SQ15 bit 2 /
bogdanm	0:9b334a45a8ff	2833	#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /!< ADC SQ15 bit 3 /
bogdanm	0:9b334a45a8ff	2834	#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /!< ADC SQ105 bit 4 /
bogdanm	0:9b334a45a8ff	2835
bogdanm	0:9b334a45a8ff	2836	#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /!< ADC 16th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2837	#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /!< ADC SQ16 bit 0 /
bogdanm	0:9b334a45a8ff	2838	#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /!< ADC SQ16 bit 1 /
bogdanm	0:9b334a45a8ff	2839	#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /!< ADC SQ16 bit 2 /
bogdanm	0:9b334a45a8ff	2840	#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /!< ADC SQ16 bit 3 /
bogdanm	0:9b334a45a8ff	2841	#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /!< ADC SQ16 bit 4 /
bogdanm	0:9b334a45a8ff	2842
bogdanm	0:9b334a45a8ff	2843	/* these defines are maintained for legacy purpose */
bogdanm	0:9b334a45a8ff	2844	#define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /!< ADC 15th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2845	#define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /!< ADC SQ15 bit 0 /
bogdanm	0:9b334a45a8ff	2846	#define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /!< ADC SQ15 bit 1 /
bogdanm	0:9b334a45a8ff	2847	#define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /!< ADC SQ15 bit 2 /
bogdanm	0:9b334a45a8ff	2848	#define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /!< ADC SQ15 bit 3 /
bogdanm	0:9b334a45a8ff	2849	#define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /!< ADC SQ105 bit 4 /
bogdanm	0:9b334a45a8ff	2850
bogdanm	0:9b334a45a8ff	2851	#define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /!< ADC 16th conversion in regular sequence /
bogdanm	0:9b334a45a8ff	2852	#define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /!< ADC SQ16 bit 0 /
bogdanm	0:9b334a45a8ff	2853	#define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /!< ADC SQ16 bit 1 /
bogdanm	0:9b334a45a8ff	2854	#define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /!< ADC SQ16 bit 2 /
bogdanm	0:9b334a45a8ff	2855	#define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /!< ADC SQ16 bit 3 /
bogdanm	0:9b334a45a8ff	2856	#define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /!< ADC SQ16 bit 4 /
bogdanm	0:9b334a45a8ff	2857	/****************** Bit definition for ADC_DR register ******************/
bogdanm	0:9b334a45a8ff	2858	#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /!< ADC regular Data converted /
bogdanm	0:9b334a45a8ff	2859	#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /!< ADC RDATA bit 0 /
bogdanm	0:9b334a45a8ff	2860	#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /!< ADC RDATA bit 1 /
bogdanm	0:9b334a45a8ff	2861	#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /!< ADC RDATA bit 2 /
bogdanm	0:9b334a45a8ff	2862	#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /!< ADC RDATA bit 3 /
bogdanm	0:9b334a45a8ff	2863	#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /!< ADC RDATA bit 4 /
bogdanm	0:9b334a45a8ff	2864	#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /!< ADC RDATA bit 5 /
bogdanm	0:9b334a45a8ff	2865	#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /!< ADC RDATA bit 6 /
bogdanm	0:9b334a45a8ff	2866	#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /!< ADC RDATA bit 7 /
bogdanm	0:9b334a45a8ff	2867	#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /!< ADC RDATA bit 8 /
bogdanm	0:9b334a45a8ff	2868	#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /!< ADC RDATA bit 9 /
bogdanm	0:9b334a45a8ff	2869	#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /!< ADC RDATA bit 10 /
bogdanm	0:9b334a45a8ff	2870	#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /!< ADC RDATA bit 11 /
bogdanm	0:9b334a45a8ff	2871	#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /!< ADC RDATA bit 12 /
bogdanm	0:9b334a45a8ff	2872	#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /!< ADC RDATA bit 13 /
bogdanm	0:9b334a45a8ff	2873	#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /!< ADC RDATA bit 14 /
bogdanm	0:9b334a45a8ff	2874	#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /!< ADC RDATA bit 15 /
bogdanm	0:9b334a45a8ff	2875
bogdanm	0:9b334a45a8ff	2876	/****************** Bit definition for ADC_JSQR register ******************/
bogdanm	0:9b334a45a8ff	2877	#define ADC_JSQR_JL ((uint32_t)0x00000003) /!< ADC injected channel sequence length /
bogdanm	0:9b334a45a8ff	2878	#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /!< ADC JL bit 0 /
bogdanm	0:9b334a45a8ff	2879	#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /!< ADC JL bit 1 /
bogdanm	0:9b334a45a8ff	2880
bogdanm	0:9b334a45a8ff	2881	#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /!< ADC external trigger selection for injected group /
bogdanm	0:9b334a45a8ff	2882	#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /!< ADC JEXTSEL bit 0 /
bogdanm	0:9b334a45a8ff	2883	#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /!< ADC JEXTSEL bit 1 /
bogdanm	0:9b334a45a8ff	2884	#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /!< ADC JEXTSEL bit 2 /
bogdanm	0:9b334a45a8ff	2885	#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /!< ADC JEXTSEL bit 3 /
bogdanm	0:9b334a45a8ff	2886
bogdanm	0:9b334a45a8ff	2887	#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /!< ADC external trigger enable and polarity selection for injected channels /
bogdanm	0:9b334a45a8ff	2888	#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /!< ADC JEXTEN bit 0 /
bogdanm	0:9b334a45a8ff	2889	#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /!< ADC JEXTEN bit 1 /
bogdanm	0:9b334a45a8ff	2890
bogdanm	0:9b334a45a8ff	2891	#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /!< ADC 1st conversion in injected sequence /
bogdanm	0:9b334a45a8ff	2892	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /!< ADC JSQ1 bit 0 /
bogdanm	0:9b334a45a8ff	2893	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /!< ADC JSQ1 bit 1 /
bogdanm	0:9b334a45a8ff	2894	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /!< ADC JSQ1 bit 2 /
bogdanm	0:9b334a45a8ff	2895	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /!< ADC JSQ1 bit 3 /
bogdanm	0:9b334a45a8ff	2896	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /!< ADC JSQ1 bit 4 /
bogdanm	0:9b334a45a8ff	2897
bogdanm	0:9b334a45a8ff	2898	#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /!< ADC 2nd conversion in injected sequence /
bogdanm	0:9b334a45a8ff	2899	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /!< ADC JSQ2 bit 0 /
bogdanm	0:9b334a45a8ff	2900	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /!< ADC JSQ2 bit 1 /
bogdanm	0:9b334a45a8ff	2901	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /!< ADC JSQ2 bit 2 /
bogdanm	0:9b334a45a8ff	2902	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /!< ADC JSQ2 bit 3 /
bogdanm	0:9b334a45a8ff	2903	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /!< ADC JSQ2 bit 4 /
bogdanm	0:9b334a45a8ff	2904
bogdanm	0:9b334a45a8ff	2905	#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /!< ADC 3rd conversion in injected sequence /
bogdanm	0:9b334a45a8ff	2906	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /!< ADC JSQ3 bit 0 /
bogdanm	0:9b334a45a8ff	2907	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /!< ADC JSQ3 bit 1 /
bogdanm	0:9b334a45a8ff	2908	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /!< ADC JSQ3 bit 2 /
bogdanm	0:9b334a45a8ff	2909	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /!< ADC JSQ3 bit 3 /
bogdanm	0:9b334a45a8ff	2910	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /!< ADC JSQ3 bit 4 /
bogdanm	0:9b334a45a8ff	2911
bogdanm	0:9b334a45a8ff	2912	#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /!< ADC 4th conversion in injected sequence /
bogdanm	0:9b334a45a8ff	2913	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /!< ADC JSQ4 bit 0 /
bogdanm	0:9b334a45a8ff	2914	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /!< ADC JSQ4 bit 1 /
bogdanm	0:9b334a45a8ff	2915	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /!< ADC JSQ4 bit 2 /
bogdanm	0:9b334a45a8ff	2916	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /!< ADC JSQ4 bit 3 /
bogdanm	0:9b334a45a8ff	2917	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /!< ADC JSQ4 bit 4 /
bogdanm	0:9b334a45a8ff	2918
bogdanm	0:9b334a45a8ff	2919	/****************** Bit definition for ADC_OFR1 register ******************/
bogdanm	0:9b334a45a8ff	2920	#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] /
bogdanm	0:9b334a45a8ff	2921	#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /!< ADC OFFSET1 bit 0 /
bogdanm	0:9b334a45a8ff	2922	#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /!< ADC OFFSET1 bit 1 /
bogdanm	0:9b334a45a8ff	2923	#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /!< ADC OFFSET1 bit 2 /
bogdanm	0:9b334a45a8ff	2924	#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /!< ADC OFFSET1 bit 3 /
bogdanm	0:9b334a45a8ff	2925	#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /!< ADC OFFSET1 bit 4 /
bogdanm	0:9b334a45a8ff	2926	#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /!< ADC OFFSET1 bit 5 /
bogdanm	0:9b334a45a8ff	2927	#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /!< ADC OFFSET1 bit 6 /
bogdanm	0:9b334a45a8ff	2928	#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /!< ADC OFFSET1 bit 7 /
bogdanm	0:9b334a45a8ff	2929	#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /!< ADC OFFSET1 bit 8 /
bogdanm	0:9b334a45a8ff	2930	#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /!< ADC OFFSET1 bit 9 /
bogdanm	0:9b334a45a8ff	2931	#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /!< ADC OFFSET1 bit 10 /
bogdanm	0:9b334a45a8ff	2932	#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /!< ADC OFFSET1 bit 11 /
bogdanm	0:9b334a45a8ff	2933
bogdanm	0:9b334a45a8ff	2934	#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 1 /
bogdanm	0:9b334a45a8ff	2935	#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET1_CH bit 0 /
bogdanm	0:9b334a45a8ff	2936	#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET1_CH bit 1 /
bogdanm	0:9b334a45a8ff	2937	#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET1_CH bit 2 /
bogdanm	0:9b334a45a8ff	2938	#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET1_CH bit 3 /
bogdanm	0:9b334a45a8ff	2939	#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET1_CH bit 4 /
bogdanm	0:9b334a45a8ff	2940
bogdanm	0:9b334a45a8ff	2941	#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /!< ADC offset 1 enable /
bogdanm	0:9b334a45a8ff	2942
bogdanm	0:9b334a45a8ff	2943	/****************** Bit definition for ADC_OFR2 register ******************/
bogdanm	0:9b334a45a8ff	2944	#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] /
bogdanm	0:9b334a45a8ff	2945	#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /!< ADC OFFSET2 bit 0 /
bogdanm	0:9b334a45a8ff	2946	#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /!< ADC OFFSET2 bit 1 /
bogdanm	0:9b334a45a8ff	2947	#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /!< ADC OFFSET2 bit 2 /
bogdanm	0:9b334a45a8ff	2948	#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /!< ADC OFFSET2 bit 3 /
bogdanm	0:9b334a45a8ff	2949	#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /!< ADC OFFSET2 bit 4 /
bogdanm	0:9b334a45a8ff	2950	#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /!< ADC OFFSET2 bit 5 /
bogdanm	0:9b334a45a8ff	2951	#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /!< ADC OFFSET2 bit 6 /
bogdanm	0:9b334a45a8ff	2952	#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /!< ADC OFFSET2 bit 7 /
bogdanm	0:9b334a45a8ff	2953	#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /!< ADC OFFSET2 bit 8 /
bogdanm	0:9b334a45a8ff	2954	#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /!< ADC OFFSET2 bit 9 /
bogdanm	0:9b334a45a8ff	2955	#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /!< ADC OFFSET2 bit 10 /
bogdanm	0:9b334a45a8ff	2956	#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /!< ADC OFFSET2 bit 11 /
bogdanm	0:9b334a45a8ff	2957
bogdanm	0:9b334a45a8ff	2958	#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 2 /
bogdanm	0:9b334a45a8ff	2959	#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET2_CH bit 0 /
bogdanm	0:9b334a45a8ff	2960	#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET2_CH bit 1 /
bogdanm	0:9b334a45a8ff	2961	#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET2_CH bit 2 /
bogdanm	0:9b334a45a8ff	2962	#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET2_CH bit 3 /
bogdanm	0:9b334a45a8ff	2963	#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET2_CH bit 4 /
bogdanm	0:9b334a45a8ff	2964
bogdanm	0:9b334a45a8ff	2965	#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /!< ADC offset 2 enable /
bogdanm	0:9b334a45a8ff	2966
bogdanm	0:9b334a45a8ff	2967	/****************** Bit definition for ADC_OFR3 register ******************/
bogdanm	0:9b334a45a8ff	2968	#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] /
bogdanm	0:9b334a45a8ff	2969	#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /!< ADC OFFSET3 bit 0 /
bogdanm	0:9b334a45a8ff	2970	#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /!< ADC OFFSET3 bit 1 /
bogdanm	0:9b334a45a8ff	2971	#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /!< ADC OFFSET3 bit 2 /
bogdanm	0:9b334a45a8ff	2972	#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /!< ADC OFFSET3 bit 3 /
bogdanm	0:9b334a45a8ff	2973	#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /!< ADC OFFSET3 bit 4 /
bogdanm	0:9b334a45a8ff	2974	#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /!< ADC OFFSET3 bit 5 /
bogdanm	0:9b334a45a8ff	2975	#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /!< ADC OFFSET3 bit 6 /
bogdanm	0:9b334a45a8ff	2976	#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /!< ADC OFFSET3 bit 7 /
bogdanm	0:9b334a45a8ff	2977	#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /!< ADC OFFSET3 bit 8 /
bogdanm	0:9b334a45a8ff	2978	#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /!< ADC OFFSET3 bit 9 /
bogdanm	0:9b334a45a8ff	2979	#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /!< ADC OFFSET3 bit 10 /
bogdanm	0:9b334a45a8ff	2980	#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /!< ADC OFFSET3 bit 11 /
bogdanm	0:9b334a45a8ff	2981
bogdanm	0:9b334a45a8ff	2982	#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 3 /
bogdanm	0:9b334a45a8ff	2983	#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET3_CH bit 0 /
bogdanm	0:9b334a45a8ff	2984	#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET3_CH bit 1 /
bogdanm	0:9b334a45a8ff	2985	#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET3_CH bit 2 /
bogdanm	0:9b334a45a8ff	2986	#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET3_CH bit 3 /
bogdanm	0:9b334a45a8ff	2987	#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET3_CH bit 4 /
bogdanm	0:9b334a45a8ff	2988
bogdanm	0:9b334a45a8ff	2989	#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /!< ADC offset 3 enable /
bogdanm	0:9b334a45a8ff	2990
bogdanm	0:9b334a45a8ff	2991	/****************** Bit definition for ADC_OFR4 register ******************/
bogdanm	0:9b334a45a8ff	2992	#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] /
bogdanm	0:9b334a45a8ff	2993	#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /!< ADC OFFSET4 bit 0 /
bogdanm	0:9b334a45a8ff	2994	#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /!< ADC OFFSET4 bit 1 /
bogdanm	0:9b334a45a8ff	2995	#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /!< ADC OFFSET4 bit 2 /
bogdanm	0:9b334a45a8ff	2996	#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /!< ADC OFFSET4 bit 3 /
bogdanm	0:9b334a45a8ff	2997	#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /!< ADC OFFSET4 bit 4 /
bogdanm	0:9b334a45a8ff	2998	#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /!< ADC OFFSET4 bit 5 /
bogdanm	0:9b334a45a8ff	2999	#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /!< ADC OFFSET4 bit 6 /
bogdanm	0:9b334a45a8ff	3000	#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /!< ADC OFFSET4 bit 7 /
bogdanm	0:9b334a45a8ff	3001	#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /!< ADC OFFSET4 bit 8 /
bogdanm	0:9b334a45a8ff	3002	#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /!< ADC OFFSET4 bit 9 /
bogdanm	0:9b334a45a8ff	3003	#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /!< ADC OFFSET4 bit 10 /
bogdanm	0:9b334a45a8ff	3004	#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /!< ADC OFFSET4 bit 11 /
bogdanm	0:9b334a45a8ff	3005
bogdanm	0:9b334a45a8ff	3006	#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 4 /
bogdanm	0:9b334a45a8ff	3007	#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET4_CH bit 0 /
bogdanm	0:9b334a45a8ff	3008	#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET4_CH bit 1 /
bogdanm	0:9b334a45a8ff	3009	#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET4_CH bit 2 /
bogdanm	0:9b334a45a8ff	3010	#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET4_CH bit 3 /
bogdanm	0:9b334a45a8ff	3011	#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET4_CH bit 4 /
bogdanm	0:9b334a45a8ff	3012
bogdanm	0:9b334a45a8ff	3013	#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /!< ADC offset 4 enable /
bogdanm	0:9b334a45a8ff	3014
bogdanm	0:9b334a45a8ff	3015	/****************** Bit definition for ADC_JDR1 register ******************/
bogdanm	0:9b334a45a8ff	3016	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	3017	#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	3018	#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	3019	#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	3020	#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	3021	#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	3022	#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	3023	#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	3024	#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	3025	#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	3026	#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	3027	#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	3028	#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	3029	#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	3030	#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	3031	#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	3032	#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	3033
bogdanm	0:9b334a45a8ff	3034	/****************** Bit definition for ADC_JDR2 register ******************/
bogdanm	0:9b334a45a8ff	3035	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	3036	#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	3037	#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	3038	#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	3039	#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	3040	#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	3041	#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	3042	#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	3043	#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	3044	#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	3045	#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	3046	#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	3047	#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	3048	#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	3049	#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	3050	#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	3051	#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	3052
bogdanm	0:9b334a45a8ff	3053	/****************** Bit definition for ADC_JDR3 register ******************/
bogdanm	0:9b334a45a8ff	3054	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	3055	#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	3056	#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	3057	#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	3058	#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	3059	#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	3060	#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	3061	#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	3062	#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	3063	#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	3064	#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	3065	#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	3066	#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	3067	#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	3068	#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	3069	#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	3070	#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	3071
bogdanm	0:9b334a45a8ff	3072	/****************** Bit definition for ADC_JDR4 register ******************/
bogdanm	0:9b334a45a8ff	3073	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
bogdanm	0:9b334a45a8ff	3074	#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
bogdanm	0:9b334a45a8ff	3075	#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
bogdanm	0:9b334a45a8ff	3076	#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
bogdanm	0:9b334a45a8ff	3077	#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
bogdanm	0:9b334a45a8ff	3078	#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
bogdanm	0:9b334a45a8ff	3079	#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
bogdanm	0:9b334a45a8ff	3080	#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
bogdanm	0:9b334a45a8ff	3081	#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
bogdanm	0:9b334a45a8ff	3082	#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
bogdanm	0:9b334a45a8ff	3083	#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
bogdanm	0:9b334a45a8ff	3084	#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
bogdanm	0:9b334a45a8ff	3085	#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
bogdanm	0:9b334a45a8ff	3086	#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
bogdanm	0:9b334a45a8ff	3087	#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
bogdanm	0:9b334a45a8ff	3088	#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
bogdanm	0:9b334a45a8ff	3089	#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
bogdanm	0:9b334a45a8ff	3090
bogdanm	0:9b334a45a8ff	3091	/****************** Bit definition for ADC_AWD2CR register ******************/
bogdanm	0:9b334a45a8ff	3092	#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /!< ADC Analog watchdog 2 channel selection /
bogdanm	0:9b334a45a8ff	3093	#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /!< ADC AWD2CH bit 0 /
bogdanm	0:9b334a45a8ff	3094	#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /!< ADC AWD2CH bit 1 /
bogdanm	0:9b334a45a8ff	3095	#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /!< ADC AWD2CH bit 2 /
bogdanm	0:9b334a45a8ff	3096	#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /!< ADC AWD2CH bit 3 /
bogdanm	0:9b334a45a8ff	3097	#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /!< ADC AWD2CH bit 4 /
bogdanm	0:9b334a45a8ff	3098	#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /!< ADC AWD2CH bit 5 /
bogdanm	0:9b334a45a8ff	3099	#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /!< ADC AWD2CH bit 6 /
bogdanm	0:9b334a45a8ff	3100	#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /!< ADC AWD2CH bit 7 /
bogdanm	0:9b334a45a8ff	3101	#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /!< ADC AWD2CH bit 8 /
bogdanm	0:9b334a45a8ff	3102	#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /!< ADC AWD2CH bit 9 /
bogdanm	0:9b334a45a8ff	3103	#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /!< ADC AWD2CH bit 10 /
bogdanm	0:9b334a45a8ff	3104	#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /!< ADC AWD2CH bit 11 /
bogdanm	0:9b334a45a8ff	3105	#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /!< ADC AWD2CH bit 12 /
bogdanm	0:9b334a45a8ff	3106	#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /!< ADC AWD2CH bit 13 /
bogdanm	0:9b334a45a8ff	3107	#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /!< ADC AWD2CH bit 14 /
bogdanm	0:9b334a45a8ff	3108	#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /!< ADC AWD2CH bit 15 /
bogdanm	0:9b334a45a8ff	3109	#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /!< ADC AWD2CH bit 16 /
bogdanm	0:9b334a45a8ff	3110	#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /!< ADC AWD2CH bit 17 /
bogdanm	0:9b334a45a8ff	3111
bogdanm	0:9b334a45a8ff	3112	/****************** Bit definition for ADC_AWD3CR register ******************/
bogdanm	0:9b334a45a8ff	3113	#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /!< ADC Analog watchdog 2 channel selection /
bogdanm	0:9b334a45a8ff	3114	#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /!< ADC AWD3CH bit 0 /
bogdanm	0:9b334a45a8ff	3115	#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /!< ADC AWD3CH bit 1 /
bogdanm	0:9b334a45a8ff	3116	#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /!< ADC AWD3CH bit 2 /
bogdanm	0:9b334a45a8ff	3117	#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /!< ADC AWD3CH bit 3 /
bogdanm	0:9b334a45a8ff	3118	#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /!< ADC AWD3CH bit 4 /
bogdanm	0:9b334a45a8ff	3119	#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /!< ADC AWD3CH bit 5 /
bogdanm	0:9b334a45a8ff	3120	#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /!< ADC AWD3CH bit 6 /
bogdanm	0:9b334a45a8ff	3121	#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /!< ADC AWD3CH bit 7 /
bogdanm	0:9b334a45a8ff	3122	#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /!< ADC AWD3CH bit 8 /
bogdanm	0:9b334a45a8ff	3123	#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /!< ADC AWD3CH bit 9 /
bogdanm	0:9b334a45a8ff	3124	#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /!< ADC AWD3CH bit 10 /
bogdanm	0:9b334a45a8ff	3125	#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /!< ADC AWD3CH bit 11 /
bogdanm	0:9b334a45a8ff	3126	#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /!< ADC AWD3CH bit 12 /
bogdanm	0:9b334a45a8ff	3127	#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /!< ADC AWD3CH bit 13 /
bogdanm	0:9b334a45a8ff	3128	#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /!< ADC AWD3CH bit 14 /
bogdanm	0:9b334a45a8ff	3129	#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /!< ADC AWD3CH bit 15 /
bogdanm	0:9b334a45a8ff	3130	#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /!< ADC AWD3CH bit 16 /
bogdanm	0:9b334a45a8ff	3131	#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /!< ADC AWD3CH bit 17 /
bogdanm	0:9b334a45a8ff	3132
bogdanm	0:9b334a45a8ff	3133	/****************** Bit definition for ADC_DIFSEL register ******************/
bogdanm	0:9b334a45a8ff	3134	#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /!< ADC differential modes for channels 1 to 18 /
bogdanm	0:9b334a45a8ff	3135	#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /!< ADC DIFSEL bit 0 /
bogdanm	0:9b334a45a8ff	3136	#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /!< ADC DIFSEL bit 1 /
bogdanm	0:9b334a45a8ff	3137	#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /!< ADC DIFSEL bit 2 /
bogdanm	0:9b334a45a8ff	3138	#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /!< ADC DIFSEL bit 3 /
bogdanm	0:9b334a45a8ff	3139	#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /!< ADC DIFSEL bit 4 /
bogdanm	0:9b334a45a8ff	3140	#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /!< ADC DIFSEL bit 5 /
bogdanm	0:9b334a45a8ff	3141	#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /!< ADC DIFSEL bit 6 /
bogdanm	0:9b334a45a8ff	3142	#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /!< ADC DIFSEL bit 7 /
bogdanm	0:9b334a45a8ff	3143	#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /!< ADC DIFSEL bit 8 /
bogdanm	0:9b334a45a8ff	3144	#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /!< ADC DIFSEL bit 9 /
bogdanm	0:9b334a45a8ff	3145	#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /!< ADC DIFSEL bit 10 /
bogdanm	0:9b334a45a8ff	3146	#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /!< ADC DIFSEL bit 11 /
bogdanm	0:9b334a45a8ff	3147	#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /!< ADC DIFSEL bit 12 /
bogdanm	0:9b334a45a8ff	3148	#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /!< ADC DIFSEL bit 13 /
bogdanm	0:9b334a45a8ff	3149	#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /!< ADC DIFSEL bit 14 /
bogdanm	0:9b334a45a8ff	3150	#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /!< ADC DIFSEL bit 15 /
bogdanm	0:9b334a45a8ff	3151	#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /!< ADC DIFSEL bit 16 /
bogdanm	0:9b334a45a8ff	3152	#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /!< ADC DIFSEL bit 17 /
bogdanm	0:9b334a45a8ff	3153
bogdanm	0:9b334a45a8ff	3154	/****************** Bit definition for ADC_CALFACT register ******************/
bogdanm	0:9b334a45a8ff	3155	#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /!< ADC calibration factors in single-ended mode /
bogdanm	0:9b334a45a8ff	3156	#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /!< ADC CALFACT_S bit 0 /
bogdanm	0:9b334a45a8ff	3157	#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /!< ADC CALFACT_S bit 1 /
bogdanm	0:9b334a45a8ff	3158	#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /!< ADC CALFACT_S bit 2 /
bogdanm	0:9b334a45a8ff	3159	#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /!< ADC CALFACT_S bit 3 /
bogdanm	0:9b334a45a8ff	3160	#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /!< ADC CALFACT_S bit 4 /
bogdanm	0:9b334a45a8ff	3161	#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /!< ADC CALFACT_S bit 5 /
bogdanm	0:9b334a45a8ff	3162	#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /!< ADC CALFACT_S bit 6 /
bogdanm	0:9b334a45a8ff	3163	#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /!< ADC calibration factors in differential mode /
bogdanm	0:9b334a45a8ff	3164	#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /!< ADC CALFACT_D bit 0 /
bogdanm	0:9b334a45a8ff	3165	#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /!< ADC CALFACT_D bit 1 /
bogdanm	0:9b334a45a8ff	3166	#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /!< ADC CALFACT_D bit 2 /
bogdanm	0:9b334a45a8ff	3167	#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /!< ADC CALFACT_D bit 3 /
bogdanm	0:9b334a45a8ff	3168	#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /!< ADC CALFACT_D bit 4 /
bogdanm	0:9b334a45a8ff	3169	#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /!< ADC CALFACT_D bit 5 /
bogdanm	0:9b334a45a8ff	3170	#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /!< ADC CALFACT_D bit 6 /
bogdanm	0:9b334a45a8ff	3171
bogdanm	0:9b334a45a8ff	3172	/*********************** ADC Common registers ***************************/
bogdanm	0:9b334a45a8ff	3173	/****************** Bit definition for ADC12_CSR register ******************/
bogdanm	0:9b334a45a8ff	3174	#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
bogdanm	0:9b334a45a8ff	3175	#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
bogdanm	0:9b334a45a8ff	3176	#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
bogdanm	0:9b334a45a8ff	3177	#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	3178	#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
bogdanm	0:9b334a45a8ff	3179	#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
bogdanm	0:9b334a45a8ff	3180	#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	3181	#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3182	#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3183	#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3184	#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
bogdanm	0:9b334a45a8ff	3185	#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
bogdanm	0:9b334a45a8ff	3186	#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3187	#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	3188	#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3189	#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3190	#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	3191	#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3192	#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3193	#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3194	#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3195	#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3196
bogdanm	0:9b334a45a8ff	3197	/****************** Bit definition for ADC34_CSR register ******************/
bogdanm	0:9b334a45a8ff	3198	#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
bogdanm	0:9b334a45a8ff	3199	#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
bogdanm	0:9b334a45a8ff	3200	#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
bogdanm	0:9b334a45a8ff	3201	#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	3202	#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
bogdanm	0:9b334a45a8ff	3203	#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
bogdanm	0:9b334a45a8ff	3204	#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
bogdanm	0:9b334a45a8ff	3205	#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3206	#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3207	#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
bogdanm	0:9b334a45a8ff	3208	#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
bogdanm	0:9b334a45a8ff	3209	#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
bogdanm	0:9b334a45a8ff	3210	#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3211	#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	3212	#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3213	#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3214	#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
bogdanm	0:9b334a45a8ff	3215	#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3216	#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3217	#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3218	#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3219	#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
bogdanm	0:9b334a45a8ff	3220
bogdanm	0:9b334a45a8ff	3221	/****************** Bit definition for ADC_CCR register ******************/
bogdanm	0:9b334a45a8ff	3222	#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /!< Multi ADC mode selection /
bogdanm	0:9b334a45a8ff	3223	#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /!< MULTI bit 0 /
bogdanm	0:9b334a45a8ff	3224	#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /!< MULTI bit 1 /
bogdanm	0:9b334a45a8ff	3225	#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /!< MULTI bit 2 /
bogdanm	0:9b334a45a8ff	3226	#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /!< MULTI bit 3 /
bogdanm	0:9b334a45a8ff	3227	#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /!< MULTI bit 4 /
bogdanm	0:9b334a45a8ff	3228	#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
bogdanm	0:9b334a45a8ff	3229	#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
bogdanm	0:9b334a45a8ff	3230	#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
bogdanm	0:9b334a45a8ff	3231	#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
bogdanm	0:9b334a45a8ff	3232	#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
bogdanm	0:9b334a45a8ff	3233	#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
bogdanm	0:9b334a45a8ff	3234	#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
bogdanm	0:9b334a45a8ff	3235	#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
bogdanm	0:9b334a45a8ff	3236	#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
bogdanm	0:9b334a45a8ff	3237	#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
bogdanm	0:9b334a45a8ff	3238	#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
bogdanm	0:9b334a45a8ff	3239	#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
bogdanm	0:9b334a45a8ff	3240	#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
bogdanm	0:9b334a45a8ff	3241	#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /!< Temperature sensor enable /
bogdanm	0:9b334a45a8ff	3242	#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /!< VBAT enable /
bogdanm	0:9b334a45a8ff	3243
bogdanm	0:9b334a45a8ff	3244	/****************** Bit definition for ADC_CCR register ******************/
bogdanm	0:9b334a45a8ff	3245	#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /!< Multi ADC mode selection /
bogdanm	0:9b334a45a8ff	3246	#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /!< MULTI bit 0 /
bogdanm	0:9b334a45a8ff	3247	#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /!< MULTI bit 1 /
bogdanm	0:9b334a45a8ff	3248	#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /!< MULTI bit 2 /
bogdanm	0:9b334a45a8ff	3249	#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /!< MULTI bit 3 /
bogdanm	0:9b334a45a8ff	3250	#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /!< MULTI bit 4 /
bogdanm	0:9b334a45a8ff	3251
bogdanm	0:9b334a45a8ff	3252	#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
bogdanm	0:9b334a45a8ff	3253	#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
bogdanm	0:9b334a45a8ff	3254	#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
bogdanm	0:9b334a45a8ff	3255	#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
bogdanm	0:9b334a45a8ff	3256	#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
bogdanm	0:9b334a45a8ff	3257
bogdanm	0:9b334a45a8ff	3258	#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
bogdanm	0:9b334a45a8ff	3259	#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
bogdanm	0:9b334a45a8ff	3260	#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
bogdanm	0:9b334a45a8ff	3261	#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
bogdanm	0:9b334a45a8ff	3262
bogdanm	0:9b334a45a8ff	3263	#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
bogdanm	0:9b334a45a8ff	3264	#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
bogdanm	0:9b334a45a8ff	3265	#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
bogdanm	0:9b334a45a8ff	3266
bogdanm	0:9b334a45a8ff	3267	#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
bogdanm	0:9b334a45a8ff	3268
bogdanm	0:9b334a45a8ff	3269	/****************** Bit definition for ADC_CDR register ******************/
bogdanm	0:9b334a45a8ff	3270	#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	3271	#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
bogdanm	0:9b334a45a8ff	3272	#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
bogdanm	0:9b334a45a8ff	3273	#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
bogdanm	0:9b334a45a8ff	3274	#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
bogdanm	0:9b334a45a8ff	3275	#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
bogdanm	0:9b334a45a8ff	3276	#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
bogdanm	0:9b334a45a8ff	3277	#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
bogdanm	0:9b334a45a8ff	3278	#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
bogdanm	0:9b334a45a8ff	3279	#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
bogdanm	0:9b334a45a8ff	3280	#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
bogdanm	0:9b334a45a8ff	3281	#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
bogdanm	0:9b334a45a8ff	3282	#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
bogdanm	0:9b334a45a8ff	3283	#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
bogdanm	0:9b334a45a8ff	3284	#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
bogdanm	0:9b334a45a8ff	3285	#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
bogdanm	0:9b334a45a8ff	3286	#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
bogdanm	0:9b334a45a8ff	3287
bogdanm	0:9b334a45a8ff	3288	#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	3289	#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
bogdanm	0:9b334a45a8ff	3290	#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
bogdanm	0:9b334a45a8ff	3291	#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
bogdanm	0:9b334a45a8ff	3292	#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
bogdanm	0:9b334a45a8ff	3293	#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
bogdanm	0:9b334a45a8ff	3294	#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
bogdanm	0:9b334a45a8ff	3295	#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
bogdanm	0:9b334a45a8ff	3296	#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
bogdanm	0:9b334a45a8ff	3297	#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
bogdanm	0:9b334a45a8ff	3298	#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
bogdanm	0:9b334a45a8ff	3299	#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
bogdanm	0:9b334a45a8ff	3300	#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
bogdanm	0:9b334a45a8ff	3301	#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
bogdanm	0:9b334a45a8ff	3302	#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
bogdanm	0:9b334a45a8ff	3303	#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
bogdanm	0:9b334a45a8ff	3304	#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
bogdanm	0:9b334a45a8ff	3305
bogdanm	0:9b334a45a8ff	3306	/****************** Bit definition for ADC_CDR register ******************/
bogdanm	0:9b334a45a8ff	3307	#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	3308	#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
bogdanm	0:9b334a45a8ff	3309	#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
bogdanm	0:9b334a45a8ff	3310	#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
bogdanm	0:9b334a45a8ff	3311	#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
bogdanm	0:9b334a45a8ff	3312	#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
bogdanm	0:9b334a45a8ff	3313	#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
bogdanm	0:9b334a45a8ff	3314	#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
bogdanm	0:9b334a45a8ff	3315	#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
bogdanm	0:9b334a45a8ff	3316	#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
bogdanm	0:9b334a45a8ff	3317	#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
bogdanm	0:9b334a45a8ff	3318	#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
bogdanm	0:9b334a45a8ff	3319	#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
bogdanm	0:9b334a45a8ff	3320	#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
bogdanm	0:9b334a45a8ff	3321	#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
bogdanm	0:9b334a45a8ff	3322	#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
bogdanm	0:9b334a45a8ff	3323	#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
bogdanm	0:9b334a45a8ff	3324
bogdanm	0:9b334a45a8ff	3325	#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
bogdanm	0:9b334a45a8ff	3326	#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
bogdanm	0:9b334a45a8ff	3327	#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
bogdanm	0:9b334a45a8ff	3328	#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
bogdanm	0:9b334a45a8ff	3329	#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
bogdanm	0:9b334a45a8ff	3330	#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
bogdanm	0:9b334a45a8ff	3331	#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
bogdanm	0:9b334a45a8ff	3332	#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
bogdanm	0:9b334a45a8ff	3333	#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
bogdanm	0:9b334a45a8ff	3334	#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
bogdanm	0:9b334a45a8ff	3335	#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
bogdanm	0:9b334a45a8ff	3336	#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
bogdanm	0:9b334a45a8ff	3337	#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
bogdanm	0:9b334a45a8ff	3338	#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
bogdanm	0:9b334a45a8ff	3339	#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
bogdanm	0:9b334a45a8ff	3340	#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
bogdanm	0:9b334a45a8ff	3341	#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
bogdanm	0:9b334a45a8ff	3342
bogdanm	0:9b334a45a8ff	3343	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3344	/* */
bogdanm	0:9b334a45a8ff	3345	/* Analog Comparators (COMP) */
bogdanm	0:9b334a45a8ff	3346	/* */
bogdanm	0:9b334a45a8ff	3347	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3348	/******************** Bit definition for COMP1_CSR register *************/
bogdanm	0:9b334a45a8ff	3349	#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
bogdanm	0:9b334a45a8ff	3350	#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< COMP1 SW1 switch control /
bogdanm	0:9b334a45a8ff	3351	#define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
bogdanm	0:9b334a45a8ff	3352	#define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3353	#define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3354	#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
bogdanm	0:9b334a45a8ff	3355	#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3356	#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3357	#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3358	#define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /!< COMP1 non inverting input select /
bogdanm	0:9b334a45a8ff	3359	#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /!< COMP1 output select /
bogdanm	0:9b334a45a8ff	3360	#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /!< COMP1 output select bit 0 /
bogdanm	0:9b334a45a8ff	3361	#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /!< COMP1 output select bit 1 /
bogdanm	0:9b334a45a8ff	3362	#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /!< COMP1 output select bit 2 /
bogdanm	0:9b334a45a8ff	3363	#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /!< COMP1 output select bit 3 /
bogdanm	0:9b334a45a8ff	3364	#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /!< COMP1 output polarity /
bogdanm	0:9b334a45a8ff	3365	#define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /!< COMP1 hysteresis /
bogdanm	0:9b334a45a8ff	3366	#define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /!< COMP1 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3367	#define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /!< COMP1 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3368	#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /!< COMP1 blanking /
bogdanm	0:9b334a45a8ff	3369	#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /!< COMP1 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3370	#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /!< COMP1 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3371	#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /!< COMP1 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3372	#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /!< COMP1 output level /
bogdanm	0:9b334a45a8ff	3373	#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /!< COMP1 lock /
bogdanm	0:9b334a45a8ff	3374
bogdanm	0:9b334a45a8ff	3375	/******************** Bit definition for COMP2_CSR register *************/
bogdanm	0:9b334a45a8ff	3376	#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /!< COMP2 enable /
bogdanm	0:9b334a45a8ff	3377	#define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /!< COMP2 power mode /
bogdanm	0:9b334a45a8ff	3378	#define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /!< COMP2 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3379	#define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /!< COMP2 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3380	#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /!< COMP2 inverting input select /
bogdanm	0:9b334a45a8ff	3381	#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /!< COMP2 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3382	#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /!< COMP2 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3383	#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /!< COMP2 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3384	#define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /!< COMP2 non inverting input select /
bogdanm	0:9b334a45a8ff	3385	#define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /!< COMP2 window mode enable /
bogdanm	0:9b334a45a8ff	3386	#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /!< COMP2 output select /
bogdanm	0:9b334a45a8ff	3387	#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /!< COMP2 output select bit 0 /
bogdanm	0:9b334a45a8ff	3388	#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /!< COMP2 output select bit 1 /
bogdanm	0:9b334a45a8ff	3389	#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /!< COMP2 output select bit 2 /
bogdanm	0:9b334a45a8ff	3390	#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /!< COMP2 output select bit 3 /
bogdanm	0:9b334a45a8ff	3391	#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /!< COMP2 output polarity /
bogdanm	0:9b334a45a8ff	3392	#define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /!< COMP2 hysteresis /
bogdanm	0:9b334a45a8ff	3393	#define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /!< COMP2 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3394	#define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /!< COMP2 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3395	#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /!< COMP2 blanking /
bogdanm	0:9b334a45a8ff	3396	#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /!< COMP2 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3397	#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /!< COMP2 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3398	#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /!< COMP2 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3399	#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
bogdanm	0:9b334a45a8ff	3400	#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
bogdanm	0:9b334a45a8ff	3401
bogdanm	0:9b334a45a8ff	3402	/******************** Bit definition for COMP3_CSR register *************/
bogdanm	0:9b334a45a8ff	3403	#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /!< COMP3 enable /
bogdanm	0:9b334a45a8ff	3404	#define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /!< COMP3 power mode /
bogdanm	0:9b334a45a8ff	3405	#define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /!< COMP3 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3406	#define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /!< COMP3 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3407	#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /!< COMP3 inverting input select /
bogdanm	0:9b334a45a8ff	3408	#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /!< COMP3 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3409	#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /!< COMP3 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3410	#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /!< COMP3 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3411	#define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /!< COMP3 non inverting input select /
bogdanm	0:9b334a45a8ff	3412	#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /!< COMP3 output select /
bogdanm	0:9b334a45a8ff	3413	#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /!< COMP3 output select bit 0 /
bogdanm	0:9b334a45a8ff	3414	#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /!< COMP3 output select bit 1 /
bogdanm	0:9b334a45a8ff	3415	#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /!< COMP3 output select bit 2 /
bogdanm	0:9b334a45a8ff	3416	#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /!< COMP3 output select bit 3 /
bogdanm	0:9b334a45a8ff	3417	#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /!< COMP3 output polarity /
bogdanm	0:9b334a45a8ff	3418	#define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /!< COMP3 hysteresis /
bogdanm	0:9b334a45a8ff	3419	#define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /!< COMP3 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3420	#define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /!< COMP3 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3421	#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /!< COMP3 blanking /
bogdanm	0:9b334a45a8ff	3422	#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /!< COMP3 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3423	#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /!< COMP3 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3424	#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /!< COMP3 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3425	#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /!< COMP3 output level /
bogdanm	0:9b334a45a8ff	3426	#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /!< COMP3 lock /
bogdanm	0:9b334a45a8ff	3427
bogdanm	0:9b334a45a8ff	3428	/******************** Bit definition for COMP4_CSR register *************/
bogdanm	0:9b334a45a8ff	3429	#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /!< COMP4 enable /
bogdanm	0:9b334a45a8ff	3430	#define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /!< COMP4 power mode /
bogdanm	0:9b334a45a8ff	3431	#define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /!< COMP4 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3432	#define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /!< COMP4 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3433	#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /!< COMP4 inverting input select /
bogdanm	0:9b334a45a8ff	3434	#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /!< COMP4 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3435	#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /!< COMP4 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3436	#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /!< COMP4 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3437	#define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /!< COMP4 non inverting input select /
bogdanm	0:9b334a45a8ff	3438	#define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /!< COMP4 window mode enable /
bogdanm	0:9b334a45a8ff	3439	#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /!< COMP4 output select /
bogdanm	0:9b334a45a8ff	3440	#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /!< COMP4 output select bit 0 /
bogdanm	0:9b334a45a8ff	3441	#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /!< COMP4 output select bit 1 /
bogdanm	0:9b334a45a8ff	3442	#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /!< COMP4 output select bit 2 /
bogdanm	0:9b334a45a8ff	3443	#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /!< COMP4 output select bit 3 /
bogdanm	0:9b334a45a8ff	3444	#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /!< COMP4 output polarity /
bogdanm	0:9b334a45a8ff	3445	#define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /!< COMP4 hysteresis /
bogdanm	0:9b334a45a8ff	3446	#define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /!< COMP4 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3447	#define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /!< COMP4 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3448	#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /!< COMP4 blanking /
bogdanm	0:9b334a45a8ff	3449	#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /!< COMP4 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3450	#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /!< COMP4 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3451	#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /!< COMP4 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3452	#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /!< COMP4 output level /
bogdanm	0:9b334a45a8ff	3453	#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /!< COMP4 lock /
bogdanm	0:9b334a45a8ff	3454
bogdanm	0:9b334a45a8ff	3455	/******************** Bit definition for COMP5_CSR register *************/
bogdanm	0:9b334a45a8ff	3456	#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /!< COMP5 enable /
bogdanm	0:9b334a45a8ff	3457	#define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /!< COMP5 power mode /
bogdanm	0:9b334a45a8ff	3458	#define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /!< COMP5 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3459	#define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /!< COMP5 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3460	#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /!< COMP5 inverting input select /
bogdanm	0:9b334a45a8ff	3461	#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /!< COMP5 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3462	#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /!< COMP5 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3463	#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /!< COMP5 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3464	#define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /!< COMP5 non inverting input select /
bogdanm	0:9b334a45a8ff	3465	#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /!< COMP5 output select /
bogdanm	0:9b334a45a8ff	3466	#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /!< COMP5 output select bit 0 /
bogdanm	0:9b334a45a8ff	3467	#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /!< COMP5 output select bit 1 /
bogdanm	0:9b334a45a8ff	3468	#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /!< COMP5 output select bit 2 /
bogdanm	0:9b334a45a8ff	3469	#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /!< COMP5 output select bit 3 /
bogdanm	0:9b334a45a8ff	3470	#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /!< COMP5 output polarity /
bogdanm	0:9b334a45a8ff	3471	#define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /!< COMP5 hysteresis /
bogdanm	0:9b334a45a8ff	3472	#define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /!< COMP5 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3473	#define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /!< COMP5 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3474	#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /!< COMP5 blanking /
bogdanm	0:9b334a45a8ff	3475	#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /!< COMP5 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3476	#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /!< COMP5 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3477	#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /!< COMP5 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3478	#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /!< COMP5 output level /
bogdanm	0:9b334a45a8ff	3479	#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /!< COMP5 lock /
bogdanm	0:9b334a45a8ff	3480
bogdanm	0:9b334a45a8ff	3481	/******************** Bit definition for COMP6_CSR register *************/
bogdanm	0:9b334a45a8ff	3482	#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /!< COMP6 enable /
bogdanm	0:9b334a45a8ff	3483	#define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /!< COMP6 power mode /
bogdanm	0:9b334a45a8ff	3484	#define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /!< COMP6 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3485	#define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /!< COMP6 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3486	#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /!< COMP6 inverting input select /
bogdanm	0:9b334a45a8ff	3487	#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /!< COMP6 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3488	#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /!< COMP6 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3489	#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /!< COMP6 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3490	#define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /!< COMP6 non inverting input select /
bogdanm	0:9b334a45a8ff	3491	#define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /!< COMP6 window mode enable /
bogdanm	0:9b334a45a8ff	3492	#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /!< COMP6 output select /
bogdanm	0:9b334a45a8ff	3493	#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /!< COMP6 output select bit 0 /
bogdanm	0:9b334a45a8ff	3494	#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /!< COMP6 output select bit 1 /
bogdanm	0:9b334a45a8ff	3495	#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /!< COMP6 output select bit 2 /
bogdanm	0:9b334a45a8ff	3496	#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /!< COMP6 output select bit 3 /
bogdanm	0:9b334a45a8ff	3497	#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /!< COMP6 output polarity /
bogdanm	0:9b334a45a8ff	3498	#define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /!< COMP6 hysteresis /
bogdanm	0:9b334a45a8ff	3499	#define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /!< COMP6 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3500	#define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /!< COMP6 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3501	#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /!< COMP6 blanking /
bogdanm	0:9b334a45a8ff	3502	#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /!< COMP6 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3503	#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /!< COMP6 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3504	#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /!< COMP6 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3505	#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /!< COMP6 output level /
bogdanm	0:9b334a45a8ff	3506	#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /!< COMP6 lock /
bogdanm	0:9b334a45a8ff	3507
bogdanm	0:9b334a45a8ff	3508	/******************** Bit definition for COMP7_CSR register *************/
bogdanm	0:9b334a45a8ff	3509	#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /!< COMP7 enable /
bogdanm	0:9b334a45a8ff	3510	#define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /!< COMP7 power mode /
bogdanm	0:9b334a45a8ff	3511	#define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /!< COMP7 power mode bit 0 /
bogdanm	0:9b334a45a8ff	3512	#define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /!< COMP7 power mode bit 1 /
bogdanm	0:9b334a45a8ff	3513	#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /!< COMP7 inverting input select /
bogdanm	0:9b334a45a8ff	3514	#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /!< COMP7 inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3515	#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /!< COMP7 inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3516	#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /!< COMP7 inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3517	#define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /!< COMP7 non inverting input select /
bogdanm	0:9b334a45a8ff	3518	#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /!< COMP7 output select /
bogdanm	0:9b334a45a8ff	3519	#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /!< COMP7 output select bit 0 /
bogdanm	0:9b334a45a8ff	3520	#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /!< COMP7 output select bit 1 /
bogdanm	0:9b334a45a8ff	3521	#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /!< COMP7 output select bit 2 /
bogdanm	0:9b334a45a8ff	3522	#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /!< COMP7 output select bit 3 /
bogdanm	0:9b334a45a8ff	3523	#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /!< COMP7 output polarity /
bogdanm	0:9b334a45a8ff	3524	#define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /!< COMP7 hysteresis /
bogdanm	0:9b334a45a8ff	3525	#define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /!< COMP7 hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3526	#define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /!< COMP7 hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3527	#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /!< COMP7 blanking /
bogdanm	0:9b334a45a8ff	3528	#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /!< COMP7 blanking bit 0 /
bogdanm	0:9b334a45a8ff	3529	#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /!< COMP7 blanking bit 1 /
bogdanm	0:9b334a45a8ff	3530	#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /!< COMP7 blanking bit 2 /
bogdanm	0:9b334a45a8ff	3531	#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /!< COMP7 output level /
bogdanm	0:9b334a45a8ff	3532	#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /!< COMP7 lock /
bogdanm	0:9b334a45a8ff	3533
bogdanm	0:9b334a45a8ff	3534	/******************** Bit definition for COMP_CSR register **************/
bogdanm	0:9b334a45a8ff	3535	#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /!< COMPx enable /
bogdanm	0:9b334a45a8ff	3536	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< COMP1 SW1 switch control /
bogdanm	0:9b334a45a8ff	3537	#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /!< COMPx power mode /
bogdanm	0:9b334a45a8ff	3538	#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /!< COMPx power mode bit 0 /
bogdanm	0:9b334a45a8ff	3539	#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /!< COMPx power mode bit 1 /
bogdanm	0:9b334a45a8ff	3540	#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /!< COMPx inverting input select /
bogdanm	0:9b334a45a8ff	3541	#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /!< COMPx inverting input select bit 0 /
bogdanm	0:9b334a45a8ff	3542	#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /!< COMPx inverting input select bit 1 /
bogdanm	0:9b334a45a8ff	3543	#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /!< COMPx inverting input select bit 2 /
bogdanm	0:9b334a45a8ff	3544	#define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /!< COMPx non inverting input select /
bogdanm	0:9b334a45a8ff	3545	#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /!< COMPx window mode enable /
bogdanm	0:9b334a45a8ff	3546	#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /!< COMPx output select /
bogdanm	0:9b334a45a8ff	3547	#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /!< COMPx output select bit 0 /
bogdanm	0:9b334a45a8ff	3548	#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /!< COMPx output select bit 1 /
bogdanm	0:9b334a45a8ff	3549	#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /!< COMPx output select bit 2 /
bogdanm	0:9b334a45a8ff	3550	#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /!< COMPx output select bit 3 /
bogdanm	0:9b334a45a8ff	3551	#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /!< COMPx output polarity /
bogdanm	0:9b334a45a8ff	3552	#define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /!< COMPx hysteresis /
bogdanm	0:9b334a45a8ff	3553	#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /!< COMPx hysteresis bit 0 /
bogdanm	0:9b334a45a8ff	3554	#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /!< COMPx hysteresis bit 1 /
bogdanm	0:9b334a45a8ff	3555	#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /!< COMPx blanking /
bogdanm	0:9b334a45a8ff	3556	#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /!< COMPx blanking bit 0 /
bogdanm	0:9b334a45a8ff	3557	#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /!< COMPx blanking bit 1 /
bogdanm	0:9b334a45a8ff	3558	#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /!< COMPx blanking bit 2 /
bogdanm	0:9b334a45a8ff	3559	#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /!< COMPx inverting input select bit 3 /
bogdanm	0:9b334a45a8ff	3560	#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /!< COMPx output level /
bogdanm	0:9b334a45a8ff	3561	#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /!< COMPx lock /
bogdanm	0:9b334a45a8ff	3562
bogdanm	0:9b334a45a8ff	3563	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3564	/* */
bogdanm	0:9b334a45a8ff	3565	/* Operational Amplifier (OPAMP) */
bogdanm	0:9b334a45a8ff	3566	/* */
bogdanm	0:9b334a45a8ff	3567	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3568	/******************* Bit definition for OPAMP1_CSR register *************/
bogdanm	0:9b334a45a8ff	3569	#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /!< OPAMP1 enable /
bogdanm	0:9b334a45a8ff	3570	#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
bogdanm	0:9b334a45a8ff	3571	#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
bogdanm	0:9b334a45a8ff	3572	#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3573	#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3574	#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	3575	#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3576	#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3577	#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
bogdanm	0:9b334a45a8ff	3578	#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3579	#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3580	#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3581	#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3582	#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	3583	#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	3584	#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3585	#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3586	#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
bogdanm	0:9b334a45a8ff	3587	#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3588	#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3589	#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3590	#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3591	#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	3592	#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
bogdanm	0:9b334a45a8ff	3593	#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
bogdanm	0:9b334a45a8ff	3594	#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
bogdanm	0:9b334a45a8ff	3595	#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
bogdanm	0:9b334a45a8ff	3596	#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
bogdanm	0:9b334a45a8ff	3597
bogdanm	0:9b334a45a8ff	3598	/******************* Bit definition for OPAMP2_CSR register *************/
bogdanm	0:9b334a45a8ff	3599	#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /!< OPAMP2 enable /
bogdanm	0:9b334a45a8ff	3600	#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
bogdanm	0:9b334a45a8ff	3601	#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
bogdanm	0:9b334a45a8ff	3602	#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3603	#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3604	#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	3605	#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3606	#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3607	#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
bogdanm	0:9b334a45a8ff	3608	#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3609	#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3610	#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3611	#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3612	#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	3613	#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	3614	#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3615	#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3616	#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
bogdanm	0:9b334a45a8ff	3617	#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3618	#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3619	#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3620	#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3621	#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	3622	#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
bogdanm	0:9b334a45a8ff	3623	#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
bogdanm	0:9b334a45a8ff	3624	#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
bogdanm	0:9b334a45a8ff	3625	#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
bogdanm	0:9b334a45a8ff	3626	#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
bogdanm	0:9b334a45a8ff	3627
bogdanm	0:9b334a45a8ff	3628	/******************* Bit definition for OPAMP3_CSR register *************/
bogdanm	0:9b334a45a8ff	3629	#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /!< OPAMP3 enable /
bogdanm	0:9b334a45a8ff	3630	#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
bogdanm	0:9b334a45a8ff	3631	#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
bogdanm	0:9b334a45a8ff	3632	#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3633	#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3634	#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	3635	#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3636	#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3637	#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
bogdanm	0:9b334a45a8ff	3638	#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3639	#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3640	#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3641	#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3642	#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	3643	#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	3644	#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3645	#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3646	#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
bogdanm	0:9b334a45a8ff	3647	#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3648	#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3649	#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3650	#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3651	#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	3652	#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
bogdanm	0:9b334a45a8ff	3653	#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
bogdanm	0:9b334a45a8ff	3654	#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
bogdanm	0:9b334a45a8ff	3655	#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
bogdanm	0:9b334a45a8ff	3656	#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
bogdanm	0:9b334a45a8ff	3657
bogdanm	0:9b334a45a8ff	3658	/******************* Bit definition for OPAMP4_CSR register *************/
bogdanm	0:9b334a45a8ff	3659	#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /!< OPAMP4 enable /
bogdanm	0:9b334a45a8ff	3660	#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
bogdanm	0:9b334a45a8ff	3661	#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
bogdanm	0:9b334a45a8ff	3662	#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3663	#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3664	#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	3665	#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3666	#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3667	#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
bogdanm	0:9b334a45a8ff	3668	#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3669	#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3670	#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3671	#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3672	#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	3673	#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	3674	#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3675	#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3676	#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
bogdanm	0:9b334a45a8ff	3677	#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3678	#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3679	#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3680	#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3681	#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	3682	#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
bogdanm	0:9b334a45a8ff	3683	#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
bogdanm	0:9b334a45a8ff	3684	#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
bogdanm	0:9b334a45a8ff	3685	#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
bogdanm	0:9b334a45a8ff	3686	#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
bogdanm	0:9b334a45a8ff	3687
bogdanm	0:9b334a45a8ff	3688	/******************* Bit definition for OPAMPx_CSR register *************/
bogdanm	0:9b334a45a8ff	3689	#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /!< OPAMP enable /
bogdanm	0:9b334a45a8ff	3690	#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
bogdanm	0:9b334a45a8ff	3691	#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
bogdanm	0:9b334a45a8ff	3692	#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3693	#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3694	#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
bogdanm	0:9b334a45a8ff	3695	#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3696	#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3697	#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
bogdanm	0:9b334a45a8ff	3698	#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3699	#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
bogdanm	0:9b334a45a8ff	3700	#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3701	#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3702	#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
bogdanm	0:9b334a45a8ff	3703	#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
bogdanm	0:9b334a45a8ff	3704	#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3705	#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3706	#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
bogdanm	0:9b334a45a8ff	3707	#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	3708	#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	3709	#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	3710	#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	3711	#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
bogdanm	0:9b334a45a8ff	3712	#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
bogdanm	0:9b334a45a8ff	3713	#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
bogdanm	0:9b334a45a8ff	3714	#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
bogdanm	0:9b334a45a8ff	3715	#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
bogdanm	0:9b334a45a8ff	3716	#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
bogdanm	0:9b334a45a8ff	3717
bogdanm	0:9b334a45a8ff	3718
bogdanm	0:9b334a45a8ff	3719	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3720	/* */
bogdanm	0:9b334a45a8ff	3721	/* Controller Area Network (CAN ) */
bogdanm	0:9b334a45a8ff	3722	/* */
bogdanm	0:9b334a45a8ff	3723	/******************************************************************************/
bogdanm	0:9b334a45a8ff	3724	/!<CAN control and status registers /
bogdanm	0:9b334a45a8ff	3725	/***************** Bit definition for CAN_MCR register ******************/
bogdanm	0:9b334a45a8ff	3726	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
bogdanm	0:9b334a45a8ff	3727	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
bogdanm	0:9b334a45a8ff	3728	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
bogdanm	0:9b334a45a8ff	3729	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
bogdanm	0:9b334a45a8ff	3730	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
bogdanm	0:9b334a45a8ff	3731	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
bogdanm	0:9b334a45a8ff	3732	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
bogdanm	0:9b334a45a8ff	3733	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
bogdanm	0:9b334a45a8ff	3734	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
bogdanm	0:9b334a45a8ff	3735
bogdanm	0:9b334a45a8ff	3736	/***************** Bit definition for CAN_MSR register ******************/
bogdanm	0:9b334a45a8ff	3737	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
bogdanm	0:9b334a45a8ff	3738	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
bogdanm	0:9b334a45a8ff	3739	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
bogdanm	0:9b334a45a8ff	3740	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	3741	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
bogdanm	0:9b334a45a8ff	3742	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
bogdanm	0:9b334a45a8ff	3743	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
bogdanm	0:9b334a45a8ff	3744	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
bogdanm	0:9b334a45a8ff	3745	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
bogdanm	0:9b334a45a8ff	3746
bogdanm	0:9b334a45a8ff	3747	/***************** Bit definition for CAN_TSR register ******************/
bogdanm	0:9b334a45a8ff	3748	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
bogdanm	0:9b334a45a8ff	3749	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
bogdanm	0:9b334a45a8ff	3750	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
bogdanm	0:9b334a45a8ff	3751	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
bogdanm	0:9b334a45a8ff	3752	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
bogdanm	0:9b334a45a8ff	3753	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
bogdanm	0:9b334a45a8ff	3754	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
bogdanm	0:9b334a45a8ff	3755	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
bogdanm	0:9b334a45a8ff	3756	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
bogdanm	0:9b334a45a8ff	3757	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
bogdanm	0:9b334a45a8ff	3758	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
bogdanm	0:9b334a45a8ff	3759	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
bogdanm	0:9b334a45a8ff	3760	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
bogdanm	0:9b334a45a8ff	3761	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
bogdanm	0:9b334a45a8ff	3762	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
bogdanm	0:9b334a45a8ff	3763	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
bogdanm	0:9b334a45a8ff	3764
bogdanm	0:9b334a45a8ff	3765	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
bogdanm	0:9b334a45a8ff	3766	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
bogdanm	0:9b334a45a8ff	3767	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
bogdanm	0:9b334a45a8ff	3768	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
bogdanm	0:9b334a45a8ff	3769
bogdanm	0:9b334a45a8ff	3770	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
bogdanm	0:9b334a45a8ff	3771	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
bogdanm	0:9b334a45a8ff	3772	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
bogdanm	0:9b334a45a8ff	3773	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
bogdanm	0:9b334a45a8ff	3774
bogdanm	0:9b334a45a8ff	3775	/***************** Bit definition for CAN_RF0R register *****************/
bogdanm	0:9b334a45a8ff	3776	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
bogdanm	0:9b334a45a8ff	3777	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
bogdanm	0:9b334a45a8ff	3778	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
bogdanm	0:9b334a45a8ff	3779	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
bogdanm	0:9b334a45a8ff	3780
bogdanm	0:9b334a45a8ff	3781	/***************** Bit definition for CAN_RF1R register *****************/
bogdanm	0:9b334a45a8ff	3782	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
bogdanm	0:9b334a45a8ff	3783	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
bogdanm	0:9b334a45a8ff	3784	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
bogdanm	0:9b334a45a8ff	3785	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
bogdanm	0:9b334a45a8ff	3786
bogdanm	0:9b334a45a8ff	3787	/****************** Bit definition for CAN_IER register *****************/
bogdanm	0:9b334a45a8ff	3788	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	3789	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
bogdanm	0:9b334a45a8ff	3790	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
bogdanm	0:9b334a45a8ff	3791	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
bogdanm	0:9b334a45a8ff	3792	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
bogdanm	0:9b334a45a8ff	3793	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
bogdanm	0:9b334a45a8ff	3794	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
bogdanm	0:9b334a45a8ff	3795	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
bogdanm	0:9b334a45a8ff	3796	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
bogdanm	0:9b334a45a8ff	3797	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
bogdanm	0:9b334a45a8ff	3798	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
bogdanm	0:9b334a45a8ff	3799	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	3800	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
bogdanm	0:9b334a45a8ff	3801	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
bogdanm	0:9b334a45a8ff	3802
bogdanm	0:9b334a45a8ff	3803	/****************** Bit definition for CAN_ESR register *****************/
bogdanm	0:9b334a45a8ff	3804	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
bogdanm	0:9b334a45a8ff	3805	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
bogdanm	0:9b334a45a8ff	3806	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
bogdanm	0:9b334a45a8ff	3807
bogdanm	0:9b334a45a8ff	3808	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
bogdanm	0:9b334a45a8ff	3809	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	3810	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	3811	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	3812
bogdanm	0:9b334a45a8ff	3813	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
bogdanm	0:9b334a45a8ff	3814	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
bogdanm	0:9b334a45a8ff	3815
bogdanm	0:9b334a45a8ff	3816	/***************** Bit definition for CAN_BTR register ******************/
bogdanm	0:9b334a45a8ff	3817	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
bogdanm	0:9b334a45a8ff	3818	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
bogdanm	0:9b334a45a8ff	3819	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
bogdanm	0:9b334a45a8ff	3820	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
bogdanm	0:9b334a45a8ff	3821	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
bogdanm	0:9b334a45a8ff	3822	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
bogdanm	0:9b334a45a8ff	3823
bogdanm	0:9b334a45a8ff	3824	/!<Mailbox registers /
bogdanm	0:9b334a45a8ff	3825	/**************** Bit definition for CAN_TI0R register ******************/
bogdanm	0:9b334a45a8ff	3826	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	3827	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	3828	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	3829	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	3830	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	3831
bogdanm	0:9b334a45a8ff	3832	/**************** Bit definition for CAN_TDT0R register *****************/
bogdanm	0:9b334a45a8ff	3833	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	3834	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	3835	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	3836
bogdanm	0:9b334a45a8ff	3837	/**************** Bit definition for CAN_TDL0R register *****************/
bogdanm	0:9b334a45a8ff	3838	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	3839	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	3840	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	3841	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	3842
bogdanm	0:9b334a45a8ff	3843	/**************** Bit definition for CAN_TDH0R register *****************/
bogdanm	0:9b334a45a8ff	3844	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	3845	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	3846	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	3847	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	3848
bogdanm	0:9b334a45a8ff	3849	/***************** Bit definition for CAN_TI1R register *****************/
bogdanm	0:9b334a45a8ff	3850	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	3851	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	3852	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	3853	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	3854	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	3855
bogdanm	0:9b334a45a8ff	3856	/***************** Bit definition for CAN_TDT1R register ****************/
bogdanm	0:9b334a45a8ff	3857	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	3858	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	3859	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	3860
bogdanm	0:9b334a45a8ff	3861	/***************** Bit definition for CAN_TDL1R register ****************/
bogdanm	0:9b334a45a8ff	3862	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	3863	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	3864	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	3865	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	3866
bogdanm	0:9b334a45a8ff	3867	/***************** Bit definition for CAN_TDH1R register ****************/
bogdanm	0:9b334a45a8ff	3868	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	3869	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	3870	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	3871	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	3872
bogdanm	0:9b334a45a8ff	3873	/***************** Bit definition for CAN_TI2R register *****************/
bogdanm	0:9b334a45a8ff	3874	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	0:9b334a45a8ff	3875	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	3876	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	3877	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	0:9b334a45a8ff	3878	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	3879
bogdanm	0:9b334a45a8ff	3880	/***************** Bit definition for CAN_TDT2R register ****************/
bogdanm	0:9b334a45a8ff	3881	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	3882	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	0:9b334a45a8ff	3883	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	3884
bogdanm	0:9b334a45a8ff	3885	/***************** Bit definition for CAN_TDL2R register ****************/
bogdanm	0:9b334a45a8ff	3886	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	3887	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	3888	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	3889	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	3890
bogdanm	0:9b334a45a8ff	3891	/***************** Bit definition for CAN_TDH2R register ****************/
bogdanm	0:9b334a45a8ff	3892	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	3893	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	3894	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	3895	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	3896
bogdanm	0:9b334a45a8ff	3897	/***************** Bit definition for CAN_RI0R register *****************/
bogdanm	0:9b334a45a8ff	3898	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	3899	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	3900	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	0:9b334a45a8ff	3901	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	3902
bogdanm	0:9b334a45a8ff	3903	/***************** Bit definition for CAN_RDT0R register ****************/
bogdanm	0:9b334a45a8ff	3904	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	3905	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	0:9b334a45a8ff	3906	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	3907
bogdanm	0:9b334a45a8ff	3908	/***************** Bit definition for CAN_RDL0R register ****************/
bogdanm	0:9b334a45a8ff	3909	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	3910	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	3911	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	3912	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	3913
bogdanm	0:9b334a45a8ff	3914	/***************** Bit definition for CAN_RDH0R register ****************/
bogdanm	0:9b334a45a8ff	3915	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	3916	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	3917	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	3918	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	3919
bogdanm	0:9b334a45a8ff	3920	/***************** Bit definition for CAN_RI1R register *****************/
bogdanm	0:9b334a45a8ff	3921	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	0:9b334a45a8ff	3922	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	0:9b334a45a8ff	3923	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	0:9b334a45a8ff	3924	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	0:9b334a45a8ff	3925
bogdanm	0:9b334a45a8ff	3926	/***************** Bit definition for CAN_RDT1R register ****************/
bogdanm	0:9b334a45a8ff	3927	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	0:9b334a45a8ff	3928	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	0:9b334a45a8ff	3929	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	0:9b334a45a8ff	3930
bogdanm	0:9b334a45a8ff	3931	/***************** Bit definition for CAN_RDL1R register ****************/
bogdanm	0:9b334a45a8ff	3932	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	0:9b334a45a8ff	3933	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	0:9b334a45a8ff	3934	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	0:9b334a45a8ff	3935	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	0:9b334a45a8ff	3936
bogdanm	0:9b334a45a8ff	3937	/***************** Bit definition for CAN_RDH1R register ****************/
bogdanm	0:9b334a45a8ff	3938	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	0:9b334a45a8ff	3939	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	0:9b334a45a8ff	3940	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	0:9b334a45a8ff	3941	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	0:9b334a45a8ff	3942
bogdanm	0:9b334a45a8ff	3943	/!<CAN filter registers /
bogdanm	0:9b334a45a8ff	3944	/***************** Bit definition for CAN_FMR register ******************/
bogdanm	0:9b334a45a8ff	3945	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
bogdanm	0:9b334a45a8ff	3946
bogdanm	0:9b334a45a8ff	3947	/***************** Bit definition for CAN_FM1R register *****************/
bogdanm	0:9b334a45a8ff	3948	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
bogdanm	0:9b334a45a8ff	3949	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
bogdanm	0:9b334a45a8ff	3950	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
bogdanm	0:9b334a45a8ff	3951	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
bogdanm	0:9b334a45a8ff	3952	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
bogdanm	0:9b334a45a8ff	3953	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
bogdanm	0:9b334a45a8ff	3954	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
bogdanm	0:9b334a45a8ff	3955	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
bogdanm	0:9b334a45a8ff	3956	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
bogdanm	0:9b334a45a8ff	3957	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
bogdanm	0:9b334a45a8ff	3958	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
bogdanm	0:9b334a45a8ff	3959	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
bogdanm	0:9b334a45a8ff	3960	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
bogdanm	0:9b334a45a8ff	3961	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
bogdanm	0:9b334a45a8ff	3962	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
bogdanm	0:9b334a45a8ff	3963
bogdanm	0:9b334a45a8ff	3964	/***************** Bit definition for CAN_FS1R register *****************/
bogdanm	0:9b334a45a8ff	3965	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
bogdanm	0:9b334a45a8ff	3966	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
bogdanm	0:9b334a45a8ff	3967	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
bogdanm	0:9b334a45a8ff	3968	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
bogdanm	0:9b334a45a8ff	3969	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
bogdanm	0:9b334a45a8ff	3970	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
bogdanm	0:9b334a45a8ff	3971	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
bogdanm	0:9b334a45a8ff	3972	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
bogdanm	0:9b334a45a8ff	3973	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
bogdanm	0:9b334a45a8ff	3974	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
bogdanm	0:9b334a45a8ff	3975	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
bogdanm	0:9b334a45a8ff	3976	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
bogdanm	0:9b334a45a8ff	3977	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
bogdanm	0:9b334a45a8ff	3978	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
bogdanm	0:9b334a45a8ff	3979	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
bogdanm	0:9b334a45a8ff	3980
bogdanm	0:9b334a45a8ff	3981	/**************** Bit definition for CAN_FFA1R register *****************/
bogdanm	0:9b334a45a8ff	3982	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
bogdanm	0:9b334a45a8ff	3983	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
bogdanm	0:9b334a45a8ff	3984	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
bogdanm	0:9b334a45a8ff	3985	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
bogdanm	0:9b334a45a8ff	3986	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
bogdanm	0:9b334a45a8ff	3987	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
bogdanm	0:9b334a45a8ff	3988	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
bogdanm	0:9b334a45a8ff	3989	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
bogdanm	0:9b334a45a8ff	3990	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
bogdanm	0:9b334a45a8ff	3991	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
bogdanm	0:9b334a45a8ff	3992	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
bogdanm	0:9b334a45a8ff	3993	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
bogdanm	0:9b334a45a8ff	3994	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
bogdanm	0:9b334a45a8ff	3995	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
bogdanm	0:9b334a45a8ff	3996	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
bogdanm	0:9b334a45a8ff	3997
bogdanm	0:9b334a45a8ff	3998	/***************** Bit definition for CAN_FA1R register *****************/
bogdanm	0:9b334a45a8ff	3999	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
bogdanm	0:9b334a45a8ff	4000	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
bogdanm	0:9b334a45a8ff	4001	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
bogdanm	0:9b334a45a8ff	4002	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
bogdanm	0:9b334a45a8ff	4003	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
bogdanm	0:9b334a45a8ff	4004	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
bogdanm	0:9b334a45a8ff	4005	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
bogdanm	0:9b334a45a8ff	4006	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
bogdanm	0:9b334a45a8ff	4007	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
bogdanm	0:9b334a45a8ff	4008	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
bogdanm	0:9b334a45a8ff	4009	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
bogdanm	0:9b334a45a8ff	4010	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
bogdanm	0:9b334a45a8ff	4011	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
bogdanm	0:9b334a45a8ff	4012	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
bogdanm	0:9b334a45a8ff	4013	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
bogdanm	0:9b334a45a8ff	4014
bogdanm	0:9b334a45a8ff	4015	/***************** Bit definition for CAN_F0R1 register *****************/
bogdanm	0:9b334a45a8ff	4016	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4017	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4018	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4019	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4020	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4021	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4022	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4023	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4024	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4025	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4026	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4027	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4028	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4029	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4030	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4031	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4032	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4033	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4034	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4035	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4036	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4037	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4038	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4039	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4040	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4041	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4042	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4043	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4044	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4045	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4046	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4047	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4048
bogdanm	0:9b334a45a8ff	4049	/***************** Bit definition for CAN_F1R1 register *****************/
bogdanm	0:9b334a45a8ff	4050	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4051	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4052	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4053	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4054	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4055	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4056	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4057	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4058	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4059	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4060	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4061	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4062	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4063	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4064	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4065	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4066	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4067	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4068	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4069	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4070	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4071	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4072	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4073	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4074	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4075	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4076	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4077	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4078	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4079	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4080	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4081	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4082
bogdanm	0:9b334a45a8ff	4083	/***************** Bit definition for CAN_F2R1 register *****************/
bogdanm	0:9b334a45a8ff	4084	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4085	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4086	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4087	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4088	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4089	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4090	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4091	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4092	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4093	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4094	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4095	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4096	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4097	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4098	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4099	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4100	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4101	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4102	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4103	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4104	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4105	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4106	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4107	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4108	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4109	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4110	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4111	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4112	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4113	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4114	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4115	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4116
bogdanm	0:9b334a45a8ff	4117	/***************** Bit definition for CAN_F3R1 register *****************/
bogdanm	0:9b334a45a8ff	4118	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4119	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4120	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4121	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4122	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4123	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4124	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4125	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4126	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4127	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4128	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4129	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4130	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4131	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4132	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4133	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4134	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4135	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4136	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4137	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4138	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4139	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4140	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4141	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4142	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4143	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4144	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4145	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4146	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4147	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4148	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4149	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4150
bogdanm	0:9b334a45a8ff	4151	/***************** Bit definition for CAN_F4R1 register *****************/
bogdanm	0:9b334a45a8ff	4152	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4153	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4154	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4155	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4156	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4157	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4158	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4159	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4160	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4161	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4162	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4163	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4164	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4165	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4166	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4167	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4168	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4169	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4170	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4171	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4172	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4173	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4174	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4175	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4176	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4177	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4178	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4179	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4180	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4181	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4182	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4183	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4184
bogdanm	0:9b334a45a8ff	4185	/***************** Bit definition for CAN_F5R1 register *****************/
bogdanm	0:9b334a45a8ff	4186	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4187	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4188	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4189	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4190	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4191	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4192	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4193	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4194	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4195	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4196	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4197	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4198	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4199	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4200	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4201	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4202	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4203	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4204	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4205	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4206	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4207	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4208	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4209	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4210	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4211	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4212	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4213	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4214	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4215	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4216	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4217	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4218
bogdanm	0:9b334a45a8ff	4219	/***************** Bit definition for CAN_F6R1 register *****************/
bogdanm	0:9b334a45a8ff	4220	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4221	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4222	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4223	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4224	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4225	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4226	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4227	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4228	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4229	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4230	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4231	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4232	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4233	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4234	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4235	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4236	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4237	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4238	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4239	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4240	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4241	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4242	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4243	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4244	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4245	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4246	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4247	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4248	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4249	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4250	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4251	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4252
bogdanm	0:9b334a45a8ff	4253	/***************** Bit definition for CAN_F7R1 register *****************/
bogdanm	0:9b334a45a8ff	4254	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4255	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4256	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4257	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4258	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4259	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4260	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4261	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4262	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4263	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4264	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4265	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4266	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4267	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4268	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4269	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4270	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4271	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4272	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4273	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4274	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4275	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4276	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4277	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4278	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4279	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4280	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4281	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4282	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4283	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4284	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4285	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4286
bogdanm	0:9b334a45a8ff	4287	/***************** Bit definition for CAN_F8R1 register *****************/
bogdanm	0:9b334a45a8ff	4288	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4289	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4290	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4291	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4292	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4293	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4294	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4295	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4296	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4297	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4298	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4299	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4300	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4301	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4302	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4303	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4304	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4305	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4306	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4307	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4308	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4309	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4310	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4311	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4312	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4313	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4314	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4315	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4316	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4317	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4318	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4319	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4320
bogdanm	0:9b334a45a8ff	4321	/***************** Bit definition for CAN_F9R1 register *****************/
bogdanm	0:9b334a45a8ff	4322	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4323	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4324	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4325	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4326	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4327	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4328	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4329	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4330	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4331	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4332	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4333	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4334	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4335	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4336	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4337	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4338	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4339	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4340	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4341	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4342	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4343	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4344	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4345	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4346	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4347	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4348	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4349	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4350	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4351	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4352	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4353	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4354
bogdanm	0:9b334a45a8ff	4355	/***************** Bit definition for CAN_F10R1 register ****************/
bogdanm	0:9b334a45a8ff	4356	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4357	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4358	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4359	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4360	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4361	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4362	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4363	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4364	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4365	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4366	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4367	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4368	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4369	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4370	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4371	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4372	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4373	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4374	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4375	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4376	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4377	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4378	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4379	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4380	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4381	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4382	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4383	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4384	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4385	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4386	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4387	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4388
bogdanm	0:9b334a45a8ff	4389	/***************** Bit definition for CAN_F11R1 register ****************/
bogdanm	0:9b334a45a8ff	4390	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4391	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4392	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4393	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4394	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4395	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4396	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4397	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4398	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4399	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4400	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4401	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4402	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4403	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4404	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4405	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4406	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4407	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4408	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4409	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4410	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4411	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4412	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4413	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4414	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4415	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4416	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4417	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4418	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4419	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4420	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4421	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4422
bogdanm	0:9b334a45a8ff	4423	/***************** Bit definition for CAN_F12R1 register ****************/
bogdanm	0:9b334a45a8ff	4424	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4425	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4426	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4427	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4428	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4429	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4430	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4431	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4432	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4433	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4434	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4435	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4436	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4437	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4438	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4439	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4440	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4441	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4442	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4443	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4444	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4445	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4446	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4447	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4448	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4449	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4450	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4451	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4452	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4453	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4454	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4455	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4456
bogdanm	0:9b334a45a8ff	4457	/***************** Bit definition for CAN_F13R1 register ****************/
bogdanm	0:9b334a45a8ff	4458	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4459	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4460	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4461	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4462	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4463	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4464	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4465	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4466	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4467	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4468	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4469	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4470	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4471	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4472	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4473	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4474	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4475	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4476	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4477	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4478	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4479	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4480	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4481	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4482	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4483	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4484	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4485	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4486	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4487	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4488	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4489	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4490
bogdanm	0:9b334a45a8ff	4491	/***************** Bit definition for CAN_F0R2 register *****************/
bogdanm	0:9b334a45a8ff	4492	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4493	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4494	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4495	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4496	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4497	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4498	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4499	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4500	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4501	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4502	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4503	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4504	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4505	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4506	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4507	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4508	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4509	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4510	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4511	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4512	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4513	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4514	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4515	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4516	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4517	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4518	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4519	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4520	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4521	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4522	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4523	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4524
bogdanm	0:9b334a45a8ff	4525	/***************** Bit definition for CAN_F1R2 register *****************/
bogdanm	0:9b334a45a8ff	4526	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4527	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4528	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4529	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4530	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4531	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4532	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4533	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4534	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4535	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4536	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4537	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4538	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4539	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4540	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4541	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4542	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4543	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4544	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4545	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4546	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4547	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4548	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4549	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4550	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4551	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4552	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4553	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4554	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4555	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4556	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4557	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4558
bogdanm	0:9b334a45a8ff	4559	/***************** Bit definition for CAN_F2R2 register *****************/
bogdanm	0:9b334a45a8ff	4560	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4561	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4562	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4563	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4564	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4565	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4566	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4567	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4568	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4569	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4570	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4571	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4572	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4573	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4574	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4575	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4576	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4577	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4578	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4579	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4580	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4581	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4582	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4583	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4584	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4585	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4586	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4587	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4588	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4589	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4590	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4591	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4592
bogdanm	0:9b334a45a8ff	4593	/***************** Bit definition for CAN_F3R2 register *****************/
bogdanm	0:9b334a45a8ff	4594	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4595	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4596	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4597	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4598	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4599	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4600	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4601	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4602	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4603	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4604	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4605	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4606	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4607	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4608	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4609	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4610	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4611	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4612	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4613	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4614	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4615	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4616	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4617	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4618	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4619	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4620	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4621	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4622	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4623	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4624	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4625	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4626
bogdanm	0:9b334a45a8ff	4627	/***************** Bit definition for CAN_F4R2 register *****************/
bogdanm	0:9b334a45a8ff	4628	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4629	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4630	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4631	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4632	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4633	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4634	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4635	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4636	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4637	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4638	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4639	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4640	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4641	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4642	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4643	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4644	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4645	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4646	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4647	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4648	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4649	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4650	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4651	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4652	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4653	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4654	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4655	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4656	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4657	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4658	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4659	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4660
bogdanm	0:9b334a45a8ff	4661	/***************** Bit definition for CAN_F5R2 register *****************/
bogdanm	0:9b334a45a8ff	4662	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4663	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4664	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4665	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4666	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4667	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4668	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4669	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4670	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4671	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4672	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4673	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4674	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4675	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4676	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4677	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4678	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4679	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4680	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4681	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4682	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4683	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4684	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4685	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4686	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4687	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4688	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4689	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4690	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4691	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4692	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4693	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4694
bogdanm	0:9b334a45a8ff	4695	/***************** Bit definition for CAN_F6R2 register *****************/
bogdanm	0:9b334a45a8ff	4696	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4697	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4698	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4699	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4700	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4701	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4702	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4703	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4704	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4705	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4706	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4707	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4708	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4709	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4710	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4711	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4712	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4713	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4714	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4715	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4716	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4717	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4718	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4719	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4720	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4721	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4722	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4723	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4724	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4725	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4726	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4727	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4728
bogdanm	0:9b334a45a8ff	4729	/***************** Bit definition for CAN_F7R2 register *****************/
bogdanm	0:9b334a45a8ff	4730	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4731	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4732	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4733	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4734	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4735	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4736	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4737	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4738	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4739	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4740	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4741	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4742	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4743	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4744	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4745	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4746	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4747	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4748	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4749	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4750	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4751	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4752	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4753	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4754	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4755	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4756	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4757	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4758	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4759	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4760	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4761	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4762
bogdanm	0:9b334a45a8ff	4763	/***************** Bit definition for CAN_F8R2 register *****************/
bogdanm	0:9b334a45a8ff	4764	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4765	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4766	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4767	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4768	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4769	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4770	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4771	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4772	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4773	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4774	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4775	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4776	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4777	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4778	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4779	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4780	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4781	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4782	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4783	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4784	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4785	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4786	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4787	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4788	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4789	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4790	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4791	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4792	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4793	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4794	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4795	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4796
bogdanm	0:9b334a45a8ff	4797	/***************** Bit definition for CAN_F9R2 register *****************/
bogdanm	0:9b334a45a8ff	4798	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4799	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4800	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4801	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4802	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4803	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4804	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4805	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4806	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4807	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4808	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4809	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4810	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4811	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4812	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4813	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4814	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4815	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4816	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4817	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4818	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4819	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4820	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4821	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4822	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4823	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4824	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4825	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4826	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4827	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4828	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4829	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4830
bogdanm	0:9b334a45a8ff	4831	/***************** Bit definition for CAN_F10R2 register ****************/
bogdanm	0:9b334a45a8ff	4832	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4833	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4834	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4835	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4836	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4837	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4838	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4839	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4840	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4841	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4842	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4843	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4844	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4845	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4846	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4847	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4848	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4849	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4850	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4851	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4852	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4853	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4854	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4855	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4856	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4857	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4858	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4859	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4860	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4861	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4862	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4863	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4864
bogdanm	0:9b334a45a8ff	4865	/***************** Bit definition for CAN_F11R2 register ****************/
bogdanm	0:9b334a45a8ff	4866	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4867	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4868	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4869	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4870	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4871	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4872	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4873	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4874	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4875	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4876	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4877	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4878	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4879	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4880	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4881	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4882	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4883	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4884	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4885	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4886	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4887	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4888	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4889	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4890	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4891	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4892	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4893	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4894	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4895	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4896	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4897	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4898
bogdanm	0:9b334a45a8ff	4899	/***************** Bit definition for CAN_F12R2 register ****************/
bogdanm	0:9b334a45a8ff	4900	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4901	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4902	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4903	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4904	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4905	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4906	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4907	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4908	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4909	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4910	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4911	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4912	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4913	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4914	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4915	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4916	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4917	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4918	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4919	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4920	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4921	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4922	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4923	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4924	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4925	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4926	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4927	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4928	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4929	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4930	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4931	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4932
bogdanm	0:9b334a45a8ff	4933	/***************** Bit definition for CAN_F13R2 register ****************/
bogdanm	0:9b334a45a8ff	4934	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	0:9b334a45a8ff	4935	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	0:9b334a45a8ff	4936	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	0:9b334a45a8ff	4937	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	0:9b334a45a8ff	4938	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	0:9b334a45a8ff	4939	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	0:9b334a45a8ff	4940	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	0:9b334a45a8ff	4941	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	0:9b334a45a8ff	4942	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	0:9b334a45a8ff	4943	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	0:9b334a45a8ff	4944	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	0:9b334a45a8ff	4945	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	0:9b334a45a8ff	4946	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	0:9b334a45a8ff	4947	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	0:9b334a45a8ff	4948	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	0:9b334a45a8ff	4949	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	0:9b334a45a8ff	4950	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	0:9b334a45a8ff	4951	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	0:9b334a45a8ff	4952	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	0:9b334a45a8ff	4953	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	0:9b334a45a8ff	4954	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	0:9b334a45a8ff	4955	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	0:9b334a45a8ff	4956	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	0:9b334a45a8ff	4957	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	0:9b334a45a8ff	4958	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	0:9b334a45a8ff	4959	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	0:9b334a45a8ff	4960	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	0:9b334a45a8ff	4961	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	0:9b334a45a8ff	4962	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	0:9b334a45a8ff	4963	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	0:9b334a45a8ff	4964	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	0:9b334a45a8ff	4965	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	0:9b334a45a8ff	4966
bogdanm	0:9b334a45a8ff	4967	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4968	/* */
bogdanm	0:9b334a45a8ff	4969	/* CRC calculation unit (CRC) */
bogdanm	0:9b334a45a8ff	4970	/* */
bogdanm	0:9b334a45a8ff	4971	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4972	/***************** Bit definition for CRC_DR register *******************/
bogdanm	0:9b334a45a8ff	4973	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	0:9b334a45a8ff	4974
bogdanm	0:9b334a45a8ff	4975	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	0:9b334a45a8ff	4976	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
bogdanm	0:9b334a45a8ff	4977
bogdanm	0:9b334a45a8ff	4978	/****************** Bit definition for CRC_CR register ******************/
bogdanm	0:9b334a45a8ff	4979	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
bogdanm	0:9b334a45a8ff	4980	#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
bogdanm	0:9b334a45a8ff	4981	#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
bogdanm	0:9b334a45a8ff	4982	#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
bogdanm	0:9b334a45a8ff	4983	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
bogdanm	0:9b334a45a8ff	4984	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	4985	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	4986	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
bogdanm	0:9b334a45a8ff	4987
bogdanm	0:9b334a45a8ff	4988	/***************** Bit definition for CRC_INIT register *****************/
bogdanm	0:9b334a45a8ff	4989	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
bogdanm	0:9b334a45a8ff	4990
bogdanm	0:9b334a45a8ff	4991	/***************** Bit definition for CRC_POL register ******************/
bogdanm	0:9b334a45a8ff	4992	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
bogdanm	0:9b334a45a8ff	4993	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4994	/* */
bogdanm	0:9b334a45a8ff	4995	/* Digital to Analog Converter (DAC) */
bogdanm	0:9b334a45a8ff	4996	/* */
bogdanm	0:9b334a45a8ff	4997	/******************************************************************************/
bogdanm	0:9b334a45a8ff	4998	/****************** Bit definition for DAC_CR register ******************/
bogdanm	0:9b334a45a8ff	4999	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
bogdanm	0:9b334a45a8ff	5000	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
bogdanm	0:9b334a45a8ff	5001	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
bogdanm	0:9b334a45a8ff	5002
bogdanm	0:9b334a45a8ff	5003	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
bogdanm	0:9b334a45a8ff	5004	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5005	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5006	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5007
bogdanm	0:9b334a45a8ff	5008	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	5009	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5010	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5011
bogdanm	0:9b334a45a8ff	5012	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	5013	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5014	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5015	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5016	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	5017
bogdanm	0:9b334a45a8ff	5018	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
bogdanm	0:9b334a45a8ff	5019	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
bogdanm	0:9b334a45a8ff	5020	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
bogdanm	0:9b334a45a8ff	5021	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
bogdanm	0:9b334a45a8ff	5022
bogdanm	0:9b334a45a8ff	5023	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
bogdanm	0:9b334a45a8ff	5024	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5025	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5026	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5027
bogdanm	0:9b334a45a8ff	5028	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
bogdanm	0:9b334a45a8ff	5029	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5030	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5031
bogdanm	0:9b334a45a8ff	5032	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
bogdanm	0:9b334a45a8ff	5033	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5034	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5035	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5036	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	5037
bogdanm	0:9b334a45a8ff	5038	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
bogdanm	0:9b334a45a8ff	5039
bogdanm	0:9b334a45a8ff	5040	/*************** Bit definition for DAC_SWTRIGR register ****************/
bogdanm	0:9b334a45a8ff	5041	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!< DAC channel1 software trigger /
bogdanm	0:9b334a45a8ff	5042	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!< DAC channel2 software trigger /
bogdanm	0:9b334a45a8ff	5043
bogdanm	0:9b334a45a8ff	5044	/*************** Bit definition for DAC_DHR12R1 register ****************/
bogdanm	0:9b334a45a8ff	5045	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5046
bogdanm	0:9b334a45a8ff	5047	/*************** Bit definition for DAC_DHR12L1 register ****************/
bogdanm	0:9b334a45a8ff	5048	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	5049
bogdanm	0:9b334a45a8ff	5050	/**************** Bit definition for DAC_DHR8R1 register ****************/
bogdanm	0:9b334a45a8ff	5051	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5052
bogdanm	0:9b334a45a8ff	5053	/*************** Bit definition for DAC_DHR12R2 register ****************/
bogdanm	0:9b334a45a8ff	5054	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!< DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5055
bogdanm	0:9b334a45a8ff	5056	/*************** Bit definition for DAC_DHR12L2 register ****************/
bogdanm	0:9b334a45a8ff	5057	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!< DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	5058
bogdanm	0:9b334a45a8ff	5059	/**************** Bit definition for DAC_DHR8R2 register ****************/
bogdanm	0:9b334a45a8ff	5060	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!< DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5061
bogdanm	0:9b334a45a8ff	5062	/*************** Bit definition for DAC_DHR12RD register ****************/
bogdanm	0:9b334a45a8ff	5063	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5064	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5065
bogdanm	0:9b334a45a8ff	5066	/*************** Bit definition for DAC_DHR12LD register ****************/
bogdanm	0:9b334a45a8ff	5067	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	5068	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
bogdanm	0:9b334a45a8ff	5069
bogdanm	0:9b334a45a8ff	5070	/**************** Bit definition for DAC_DHR8RD register ****************/
bogdanm	0:9b334a45a8ff	5071	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5072	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!< DAC channel2 8-bit Right aligned data /
bogdanm	0:9b334a45a8ff	5073
bogdanm	0:9b334a45a8ff	5074	/***************** Bit definition for DAC_DOR1 register *****************/
bogdanm	0:9b334a45a8ff	5075	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!< DAC channel1 data output /
bogdanm	0:9b334a45a8ff	5076
bogdanm	0:9b334a45a8ff	5077	/***************** Bit definition for DAC_DOR2 register *****************/
bogdanm	0:9b334a45a8ff	5078	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!< DAC channel2 data output /
bogdanm	0:9b334a45a8ff	5079
bogdanm	0:9b334a45a8ff	5080	/****************** Bit definition for DAC_SR register ******************/
bogdanm	0:9b334a45a8ff	5081	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
bogdanm	0:9b334a45a8ff	5082	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
bogdanm	0:9b334a45a8ff	5083
bogdanm	0:9b334a45a8ff	5084	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5085	/* */
bogdanm	0:9b334a45a8ff	5086	/* Debug MCU (DBGMCU) */
bogdanm	0:9b334a45a8ff	5087	/* */
bogdanm	0:9b334a45a8ff	5088	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5089	/****************** Bit definition for DBGMCU_IDCODE register ***********/
bogdanm	0:9b334a45a8ff	5090	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm	0:9b334a45a8ff	5091	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm	0:9b334a45a8ff	5092
bogdanm	0:9b334a45a8ff	5093	/****************** Bit definition for DBGMCU_CR register ***************/
bogdanm	0:9b334a45a8ff	5094	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5095	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5096	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5097	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5098
bogdanm	0:9b334a45a8ff	5099	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	5100	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
bogdanm	0:9b334a45a8ff	5101	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
bogdanm	0:9b334a45a8ff	5102
bogdanm	0:9b334a45a8ff	5103	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
bogdanm	0:9b334a45a8ff	5104	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5105	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5106	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5107	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5108	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5109	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5110	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5111	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5112	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5113	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5114	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5115
bogdanm	0:9b334a45a8ff	5116	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
bogdanm	0:9b334a45a8ff	5117	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5118	#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5119	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5120	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5121	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5122
bogdanm	0:9b334a45a8ff	5123	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5124	/* */
bogdanm	0:9b334a45a8ff	5125	/* DMA Controller (DMA) */
bogdanm	0:9b334a45a8ff	5126	/* */
bogdanm	0:9b334a45a8ff	5127	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5128	/***************** Bit definition for DMA_ISR register ******************/
bogdanm	0:9b334a45a8ff	5129	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5130	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5131	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5132	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5133	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5134	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5135	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5136	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5137	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5138	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5139	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5140	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5141	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5142	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5143	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5144	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5145	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5146	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5147	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5148	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5149	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5150	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5151	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5152	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5153	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
bogdanm	0:9b334a45a8ff	5154	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
bogdanm	0:9b334a45a8ff	5155	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
bogdanm	0:9b334a45a8ff	5156	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
bogdanm	0:9b334a45a8ff	5157
bogdanm	0:9b334a45a8ff	5158	/***************** Bit definition for DMA_IFCR register *****************/
bogdanm	0:9b334a45a8ff	5159	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5160	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5161	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5162	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5163	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5164	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5165	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5166	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5167	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5168	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5169	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5170	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5171	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5172	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5173	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5174	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5175	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5176	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5177	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5178	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5179	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5180	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5181	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5182	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5183	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
bogdanm	0:9b334a45a8ff	5184	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
bogdanm	0:9b334a45a8ff	5185	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
bogdanm	0:9b334a45a8ff	5186	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
bogdanm	0:9b334a45a8ff	5187
bogdanm	0:9b334a45a8ff	5188	/***************** Bit definition for DMA_CCR register ******************/
bogdanm	0:9b334a45a8ff	5189	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
bogdanm	0:9b334a45a8ff	5190	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	5191	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
bogdanm	0:9b334a45a8ff	5192	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
bogdanm	0:9b334a45a8ff	5193	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
bogdanm	0:9b334a45a8ff	5194	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
bogdanm	0:9b334a45a8ff	5195	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
bogdanm	0:9b334a45a8ff	5196	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
bogdanm	0:9b334a45a8ff	5197
bogdanm	0:9b334a45a8ff	5198	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
bogdanm	0:9b334a45a8ff	5199	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5200	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5201
bogdanm	0:9b334a45a8ff	5202	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
bogdanm	0:9b334a45a8ff	5203	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5204	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5205
bogdanm	0:9b334a45a8ff	5206	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
bogdanm	0:9b334a45a8ff	5207	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5208	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5209
bogdanm	0:9b334a45a8ff	5210	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
bogdanm	0:9b334a45a8ff	5211
bogdanm	0:9b334a45a8ff	5212	/**************** Bit definition for DMA_CNDTR register *****************/
bogdanm	0:9b334a45a8ff	5213	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
bogdanm	0:9b334a45a8ff	5214
bogdanm	0:9b334a45a8ff	5215	/**************** Bit definition for DMA_CPAR register ******************/
bogdanm	0:9b334a45a8ff	5216	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
bogdanm	0:9b334a45a8ff	5217
bogdanm	0:9b334a45a8ff	5218	/**************** Bit definition for DMA_CMAR register ******************/
bogdanm	0:9b334a45a8ff	5219	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
bogdanm	0:9b334a45a8ff	5220
bogdanm	0:9b334a45a8ff	5221	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5222	/* */
bogdanm	0:9b334a45a8ff	5223	/* External Interrupt/Event Controller (EXTI) */
bogdanm	0:9b334a45a8ff	5224	/* */
bogdanm	0:9b334a45a8ff	5225	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5226	/***************** Bit definition for EXTI_IMR register *****************/
bogdanm	0:9b334a45a8ff	5227	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	0:9b334a45a8ff	5228	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	0:9b334a45a8ff	5229	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	0:9b334a45a8ff	5230	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	0:9b334a45a8ff	5231	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	0:9b334a45a8ff	5232	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	0:9b334a45a8ff	5233	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	0:9b334a45a8ff	5234	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	0:9b334a45a8ff	5235	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	0:9b334a45a8ff	5236	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	0:9b334a45a8ff	5237	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	0:9b334a45a8ff	5238	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	0:9b334a45a8ff	5239	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	0:9b334a45a8ff	5240	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	0:9b334a45a8ff	5241	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	0:9b334a45a8ff	5242	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	0:9b334a45a8ff	5243	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	0:9b334a45a8ff	5244	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	0:9b334a45a8ff	5245	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
bogdanm	0:9b334a45a8ff	5246	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	0:9b334a45a8ff	5247	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
bogdanm	0:9b334a45a8ff	5248	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
bogdanm	0:9b334a45a8ff	5249	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
bogdanm	0:9b334a45a8ff	5250	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
bogdanm	0:9b334a45a8ff	5251	#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /!< Interrupt Mask on line 24 /
bogdanm	0:9b334a45a8ff	5252	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
bogdanm	0:9b334a45a8ff	5253	#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /!< Interrupt Mask on line 26 /
bogdanm	0:9b334a45a8ff	5254	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
bogdanm	0:9b334a45a8ff	5255	#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /!< Interrupt Mask on line 28 /
bogdanm	0:9b334a45a8ff	5256
bogdanm	0:9b334a45a8ff	5257	/***************** Bit definition for EXTI_EMR register *****************/
bogdanm	0:9b334a45a8ff	5258	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	0:9b334a45a8ff	5259	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	0:9b334a45a8ff	5260	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	0:9b334a45a8ff	5261	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	0:9b334a45a8ff	5262	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	0:9b334a45a8ff	5263	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	0:9b334a45a8ff	5264	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	0:9b334a45a8ff	5265	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	0:9b334a45a8ff	5266	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	0:9b334a45a8ff	5267	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	0:9b334a45a8ff	5268	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	0:9b334a45a8ff	5269	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	0:9b334a45a8ff	5270	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	0:9b334a45a8ff	5271	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	0:9b334a45a8ff	5272	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	0:9b334a45a8ff	5273	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	0:9b334a45a8ff	5274	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	0:9b334a45a8ff	5275	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	0:9b334a45a8ff	5276	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
bogdanm	0:9b334a45a8ff	5277	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	0:9b334a45a8ff	5278	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
bogdanm	0:9b334a45a8ff	5279	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
bogdanm	0:9b334a45a8ff	5280	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
bogdanm	0:9b334a45a8ff	5281	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
bogdanm	0:9b334a45a8ff	5282	#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /!< Event Mask on line 24 /
bogdanm	0:9b334a45a8ff	5283	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
bogdanm	0:9b334a45a8ff	5284	#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /!< Event Mask on line 26 /
bogdanm	0:9b334a45a8ff	5285	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
bogdanm	0:9b334a45a8ff	5286	#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /!< Event Mask on line 28 /
bogdanm	0:9b334a45a8ff	5287
bogdanm	0:9b334a45a8ff	5288	/**************** Bit definition for EXTI_RTSR register *****************/
bogdanm	0:9b334a45a8ff	5289	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	5290	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	5291	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	5292	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	5293	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	5294	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	5295	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	5296	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	5297	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	5298	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	5299	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	5300	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	5301	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	5302	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	5303	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	5304	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	5305	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	5306	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	5307	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	5308	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	5309	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
bogdanm	0:9b334a45a8ff	5310	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
bogdanm	0:9b334a45a8ff	5311	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
bogdanm	0:9b334a45a8ff	5312	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
bogdanm	0:9b334a45a8ff	5313	#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /!< Rising trigger event configuration bit of line 24 /
bogdanm	0:9b334a45a8ff	5314	#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /!< Rising trigger event configuration bit of line 25 /
bogdanm	0:9b334a45a8ff	5315	#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /!< Rising trigger event configuration bit of line 26 /
bogdanm	0:9b334a45a8ff	5316	#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /!< Rising trigger event configuration bit of line 27 /
bogdanm	0:9b334a45a8ff	5317	#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /!< Rising trigger event configuration bit of line 28 /
bogdanm	0:9b334a45a8ff	5318
bogdanm	0:9b334a45a8ff	5319	/**************** Bit definition for EXTI_FTSR register *****************/
bogdanm	0:9b334a45a8ff	5320	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	0:9b334a45a8ff	5321	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	0:9b334a45a8ff	5322	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	0:9b334a45a8ff	5323	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	0:9b334a45a8ff	5324	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	0:9b334a45a8ff	5325	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	0:9b334a45a8ff	5326	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	0:9b334a45a8ff	5327	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	0:9b334a45a8ff	5328	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	0:9b334a45a8ff	5329	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	0:9b334a45a8ff	5330	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	0:9b334a45a8ff	5331	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	0:9b334a45a8ff	5332	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	0:9b334a45a8ff	5333	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	0:9b334a45a8ff	5334	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	0:9b334a45a8ff	5335	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	0:9b334a45a8ff	5336	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	0:9b334a45a8ff	5337	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
bogdanm	0:9b334a45a8ff	5338	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
bogdanm	0:9b334a45a8ff	5339	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	0:9b334a45a8ff	5340	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
bogdanm	0:9b334a45a8ff	5341	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
bogdanm	0:9b334a45a8ff	5342	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
bogdanm	0:9b334a45a8ff	5343	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
bogdanm	0:9b334a45a8ff	5344	#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /!< Falling trigger event configuration bit of line 24 /
bogdanm	0:9b334a45a8ff	5345	#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /!< Falling trigger event configuration bit of line 25 /
bogdanm	0:9b334a45a8ff	5346	#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /!< Falling trigger event configuration bit of line 26 /
bogdanm	0:9b334a45a8ff	5347	#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /!< Falling trigger event configuration bit of line 27 /
bogdanm	0:9b334a45a8ff	5348	#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /!< Falling trigger event configuration bit of line 28 /
bogdanm	0:9b334a45a8ff	5349
bogdanm	0:9b334a45a8ff	5350	/**************** Bit definition for EXTI_SWIER register ****************/
bogdanm	0:9b334a45a8ff	5351	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	0:9b334a45a8ff	5352	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	0:9b334a45a8ff	5353	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	0:9b334a45a8ff	5354	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	0:9b334a45a8ff	5355	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	0:9b334a45a8ff	5356	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	0:9b334a45a8ff	5357	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	0:9b334a45a8ff	5358	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	0:9b334a45a8ff	5359	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	0:9b334a45a8ff	5360	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	0:9b334a45a8ff	5361	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	0:9b334a45a8ff	5362	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	0:9b334a45a8ff	5363	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	0:9b334a45a8ff	5364	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	0:9b334a45a8ff	5365	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	0:9b334a45a8ff	5366	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	0:9b334a45a8ff	5367	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	0:9b334a45a8ff	5368	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
bogdanm	0:9b334a45a8ff	5369	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
bogdanm	0:9b334a45a8ff	5370	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	0:9b334a45a8ff	5371	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
bogdanm	0:9b334a45a8ff	5372	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
bogdanm	0:9b334a45a8ff	5373	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
bogdanm	0:9b334a45a8ff	5374	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
bogdanm	0:9b334a45a8ff	5375	#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /!< Software Interrupt on line 24 /
bogdanm	0:9b334a45a8ff	5376	#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /!< Software Interrupt on line 25 /
bogdanm	0:9b334a45a8ff	5377	#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /!< Software Interrupt on line 26 /
bogdanm	0:9b334a45a8ff	5378	#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /!< Software Interrupt on line 27 /
bogdanm	0:9b334a45a8ff	5379	#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /!< Software Interrupt on line 28 /
bogdanm	0:9b334a45a8ff	5380
bogdanm	0:9b334a45a8ff	5381	/***************** Bit definition for EXTI_PR register ******************/
bogdanm	0:9b334a45a8ff	5382	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
bogdanm	0:9b334a45a8ff	5383	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
bogdanm	0:9b334a45a8ff	5384	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
bogdanm	0:9b334a45a8ff	5385	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
bogdanm	0:9b334a45a8ff	5386	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
bogdanm	0:9b334a45a8ff	5387	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
bogdanm	0:9b334a45a8ff	5388	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
bogdanm	0:9b334a45a8ff	5389	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
bogdanm	0:9b334a45a8ff	5390	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
bogdanm	0:9b334a45a8ff	5391	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
bogdanm	0:9b334a45a8ff	5392	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
bogdanm	0:9b334a45a8ff	5393	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
bogdanm	0:9b334a45a8ff	5394	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
bogdanm	0:9b334a45a8ff	5395	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
bogdanm	0:9b334a45a8ff	5396	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
bogdanm	0:9b334a45a8ff	5397	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
bogdanm	0:9b334a45a8ff	5398	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
bogdanm	0:9b334a45a8ff	5399	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
bogdanm	0:9b334a45a8ff	5400	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
bogdanm	0:9b334a45a8ff	5401	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
bogdanm	0:9b334a45a8ff	5402	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
bogdanm	0:9b334a45a8ff	5403	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
bogdanm	0:9b334a45a8ff	5404	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
bogdanm	0:9b334a45a8ff	5405	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit for line 23 /
bogdanm	0:9b334a45a8ff	5406	#define EXTI_PR_PR24 ((uint32_t)0x01000000) /!< Pending bit for line 24 /
bogdanm	0:9b334a45a8ff	5407	#define EXTI_PR_PR25 ((uint32_t)0x02000000) /!< Pending bit for line 25 /
bogdanm	0:9b334a45a8ff	5408	#define EXTI_PR_PR26 ((uint32_t)0x04000000) /!< Pending bit for line 26 /
bogdanm	0:9b334a45a8ff	5409	#define EXTI_PR_PR27 ((uint32_t)0x08000000) /!< Pending bit for line 27 /
bogdanm	0:9b334a45a8ff	5410	#define EXTI_PR_PR28 ((uint32_t)0x10000000) /!< Pending bit for line 28 /
bogdanm	0:9b334a45a8ff	5411
bogdanm	0:9b334a45a8ff	5412	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5413	/* */
bogdanm	0:9b334a45a8ff	5414	/* FLASH */
bogdanm	0:9b334a45a8ff	5415	/* */
bogdanm	0:9b334a45a8ff	5416	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5417	/***************** Bit definition for FLASH_ACR register ****************/
bogdanm	0:9b334a45a8ff	5418	#define FLASH_ACR_LATENCY ((uint8_t)0x03) /!< LATENCY[2:0] bits (Latency) /
bogdanm	0:9b334a45a8ff	5419	#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5420	#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5421
bogdanm	0:9b334a45a8ff	5422	#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /!< Flash Half Cycle Access Enable /
bogdanm	0:9b334a45a8ff	5423	#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /!< Prefetch Buffer Enable /
bogdanm	0:9b334a45a8ff	5424	#define FLASH_ACR_PRFTBS ((uint8_t)0x20)
bogdanm	0:9b334a45a8ff	5425
bogdanm	0:9b334a45a8ff	5426	/**************** Bit definition for FLASH_KEYR register ****************/
bogdanm	0:9b334a45a8ff	5427	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
bogdanm	0:9b334a45a8ff	5428
bogdanm	0:9b334a45a8ff	5429	#define RDP_KEY ((uint16_t)0x00A5) /!< RDP Key /
bogdanm	0:9b334a45a8ff	5430	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
bogdanm	0:9b334a45a8ff	5431	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
bogdanm	0:9b334a45a8ff	5432
bogdanm	0:9b334a45a8ff	5433	/*************** Bit definition for FLASH_OPTKEYR register **************/
bogdanm	0:9b334a45a8ff	5434	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
bogdanm	0:9b334a45a8ff	5435
bogdanm	0:9b334a45a8ff	5436	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
bogdanm	0:9b334a45a8ff	5437	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
bogdanm	0:9b334a45a8ff	5438
bogdanm	0:9b334a45a8ff	5439	/**************** Bit definition for FLASH_SR register *****************/
bogdanm	0:9b334a45a8ff	5440	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
bogdanm	0:9b334a45a8ff	5441	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
bogdanm	0:9b334a45a8ff	5442	#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /!< Write Protection Error /
bogdanm	0:9b334a45a8ff	5443	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
bogdanm	0:9b334a45a8ff	5444
bogdanm	0:9b334a45a8ff	5445	/***************** Bit definition for FLASH_CR register *****************/
bogdanm	0:9b334a45a8ff	5446	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
bogdanm	0:9b334a45a8ff	5447	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
bogdanm	0:9b334a45a8ff	5448	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
bogdanm	0:9b334a45a8ff	5449	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
bogdanm	0:9b334a45a8ff	5450	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
bogdanm	0:9b334a45a8ff	5451	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
bogdanm	0:9b334a45a8ff	5452	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
bogdanm	0:9b334a45a8ff	5453	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
bogdanm	0:9b334a45a8ff	5454	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	5455	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
bogdanm	0:9b334a45a8ff	5456	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< OptionBytes Loader Launch /
bogdanm	0:9b334a45a8ff	5457
bogdanm	0:9b334a45a8ff	5458	/***************** Bit definition for FLASH_AR register *****************/
bogdanm	0:9b334a45a8ff	5459	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
bogdanm	0:9b334a45a8ff	5460
bogdanm	0:9b334a45a8ff	5461	/**************** Bit definition for FLASH_OBR register *****************/
bogdanm	0:9b334a45a8ff	5462	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
bogdanm	0:9b334a45a8ff	5463	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
bogdanm	0:9b334a45a8ff	5464	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
bogdanm	0:9b334a45a8ff	5465
bogdanm	0:9b334a45a8ff	5466	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
bogdanm	0:9b334a45a8ff	5467	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
bogdanm	0:9b334a45a8ff	5468	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
bogdanm	0:9b334a45a8ff	5469	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
bogdanm	0:9b334a45a8ff	5470
bogdanm	0:9b334a45a8ff	5471	/**************** Bit definition for FLASH_WRPR register ****************/
bogdanm	0:9b334a45a8ff	5472	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
bogdanm	0:9b334a45a8ff	5473
bogdanm	0:9b334a45a8ff	5474	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	5475
bogdanm	0:9b334a45a8ff	5476	/**************** Bit definition for OB_RDP register ********************/
bogdanm	0:9b334a45a8ff	5477	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
bogdanm	0:9b334a45a8ff	5478	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
bogdanm	0:9b334a45a8ff	5479
bogdanm	0:9b334a45a8ff	5480	/**************** Bit definition for OB_USER register *******************/
bogdanm	0:9b334a45a8ff	5481	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
bogdanm	0:9b334a45a8ff	5482	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
bogdanm	0:9b334a45a8ff	5483
bogdanm	0:9b334a45a8ff	5484	/**************** Bit definition for FLASH_WRP0 register ****************/
bogdanm	0:9b334a45a8ff	5485	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	5486	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	5487
bogdanm	0:9b334a45a8ff	5488	/**************** Bit definition for FLASH_WRP1 register ****************/
bogdanm	0:9b334a45a8ff	5489	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	5490	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	5491
bogdanm	0:9b334a45a8ff	5492	/**************** Bit definition for FLASH_WRP2 register ****************/
bogdanm	0:9b334a45a8ff	5493	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	5494	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	5495
bogdanm	0:9b334a45a8ff	5496	/**************** Bit definition for FLASH_WRP3 register ****************/
bogdanm	0:9b334a45a8ff	5497	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	0:9b334a45a8ff	5498	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	0:9b334a45a8ff	5499	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5500	/* */
bogdanm	0:9b334a45a8ff	5501	/* General Purpose I/O (GPIO) */
bogdanm	0:9b334a45a8ff	5502	/* */
bogdanm	0:9b334a45a8ff	5503	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5504	/***************** Bit definition for GPIO_MODER register ***************/
bogdanm	0:9b334a45a8ff	5505	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	5506	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5507	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5508	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	5509	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5510	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5511	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	5512	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5513	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5514	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	5515	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5516	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5517	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	5518	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5519	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5520	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	5521	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5522	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5523	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	5524	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5525	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5526	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	5527	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5528	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5529	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	5530	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5531	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5532	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	5533	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5534	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5535	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	5536	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5537	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5538	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	5539	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5540	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5541	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	5542	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5543	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5544	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	5545	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5546	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5547	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	5548	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5549	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5550	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	5551	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5552	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5553
bogdanm	0:9b334a45a8ff	5554
bogdanm	0:9b334a45a8ff	5555	/**************** Bit definition for GPIO_OTYPER register ***************/
bogdanm	0:9b334a45a8ff	5556	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5557	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5558	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5559	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5560	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5561	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5562	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5563	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5564	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5565	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5566	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5567	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5568	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5569	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5570	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5571	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5572
bogdanm	0:9b334a45a8ff	5573
bogdanm	0:9b334a45a8ff	5574	/************** Bit definition for GPIO_OSPEEDR register ****************/
bogdanm	0:9b334a45a8ff	5575	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	5576	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5577	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5578	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	5579	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5580	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5581	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	5582	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5583	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5584	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	5585	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5586	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5587	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	5588	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5589	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5590	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	5591	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5592	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5593	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	5594	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5595	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5596	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	5597	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5598	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5599	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	5600	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5601	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5602	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	5603	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5604	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5605	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	5606	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5607	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5608	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	5609	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5610	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5611	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	5612	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5613	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5614	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	5615	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5616	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5617	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	5618	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5619	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5620	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	5621	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5622	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5623
bogdanm	0:9b334a45a8ff	5624	/***************** Bit definition for GPIO_PUPDR register ****************/
bogdanm	0:9b334a45a8ff	5625	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	5626	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5627	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5628	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm	0:9b334a45a8ff	5629	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5630	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5631	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	5632	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5633	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5634	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm	0:9b334a45a8ff	5635	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5636	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5637	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm	0:9b334a45a8ff	5638	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5639	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5640	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	5641	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5642	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5643	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm	0:9b334a45a8ff	5644	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5645	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5646	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm	0:9b334a45a8ff	5647	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5648	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5649	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm	0:9b334a45a8ff	5650	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5651	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5652	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm	0:9b334a45a8ff	5653	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5654	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5655	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	5656	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5657	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5658	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm	0:9b334a45a8ff	5659	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5660	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5661	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm	0:9b334a45a8ff	5662	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5663	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5664	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm	0:9b334a45a8ff	5665	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5666	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5667	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	5668	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5669	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5670	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm	0:9b334a45a8ff	5671	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5672	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5673
bogdanm	0:9b334a45a8ff	5674	/***************** Bit definition for GPIO_IDR register *****************/
bogdanm	0:9b334a45a8ff	5675	#define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5676	#define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5677	#define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5678	#define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5679	#define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5680	#define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5681	#define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5682	#define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5683	#define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5684	#define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5685	#define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5686	#define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5687	#define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5688	#define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5689	#define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5690	#define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5691
bogdanm	0:9b334a45a8ff	5692	/**************** Bit definition for GPIO_ODR register ******************/
bogdanm	0:9b334a45a8ff	5693	#define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5694	#define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5695	#define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5696	#define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5697	#define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5698	#define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5699	#define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5700	#define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5701	#define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5702	#define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5703	#define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5704	#define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5705	#define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5706	#define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5707	#define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5708	#define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5709
bogdanm	0:9b334a45a8ff	5710	/**************** Bit definition for GPIO_BSRR register ******************/
bogdanm	0:9b334a45a8ff	5711	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5712	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5713	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5714	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5715	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5716	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5717	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5718	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5719	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5720	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5721	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5722	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5723	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5724	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5725	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5726	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5727	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5728	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5729	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5730	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	5731	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	5732	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	5733	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	5734	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	5735	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	5736	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	5737	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	5738	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	5739	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	5740	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	5741	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	5742	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	5743
bogdanm	0:9b334a45a8ff	5744	/**************** Bit definition for GPIO_LCKR register ******************/
bogdanm	0:9b334a45a8ff	5745	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5746	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5747	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5748	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5749	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5750	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5751	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5752	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5753	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5754	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5755	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5756	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5757	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5758	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5759	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5760	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5761	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5762
bogdanm	0:9b334a45a8ff	5763	/**************** Bit definition for GPIO_AFRL register ******************/
bogdanm	0:9b334a45a8ff	5764	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	5765	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	5766	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	5767	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	5768	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	5769	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	5770	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	5771	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	5772
bogdanm	0:9b334a45a8ff	5773	/**************** Bit definition for GPIO_AFRH register ******************/
bogdanm	0:9b334a45a8ff	5774	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	5775	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm	0:9b334a45a8ff	5776	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	5777	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm	0:9b334a45a8ff	5778	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	5779	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	5780	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	5781	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm	0:9b334a45a8ff	5782
bogdanm	0:9b334a45a8ff	5783	/**************** Bit definition for GPIO_BRR register *******************/
bogdanm	0:9b334a45a8ff	5784	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5785	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5786	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	5787	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	5788	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	5789	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	5790	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	5791	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	5792	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	5793	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	5794	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	5795	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	5796	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	5797	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	5798	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	5799	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	5800
bogdanm	0:9b334a45a8ff	5801	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5802	/* */
bogdanm	0:9b334a45a8ff	5803	/* Inter-integrated Circuit Interface (I2C) */
bogdanm	0:9b334a45a8ff	5804	/* */
bogdanm	0:9b334a45a8ff	5805	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5806	/***************** Bit definition for I2C_CR1 register *****************/
bogdanm	0:9b334a45a8ff	5807	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
bogdanm	0:9b334a45a8ff	5808	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
bogdanm	0:9b334a45a8ff	5809	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
bogdanm	0:9b334a45a8ff	5810	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
bogdanm	0:9b334a45a8ff	5811	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
bogdanm	0:9b334a45a8ff	5812	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
bogdanm	0:9b334a45a8ff	5813	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
bogdanm	0:9b334a45a8ff	5814	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
bogdanm	0:9b334a45a8ff	5815	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
bogdanm	0:9b334a45a8ff	5816	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
bogdanm	0:9b334a45a8ff	5817	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
bogdanm	0:9b334a45a8ff	5818	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
bogdanm	0:9b334a45a8ff	5819	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
bogdanm	0:9b334a45a8ff	5820	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
bogdanm	0:9b334a45a8ff	5821	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
bogdanm	0:9b334a45a8ff	5822	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
bogdanm	0:9b334a45a8ff	5823	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
bogdanm	0:9b334a45a8ff	5824	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
bogdanm	0:9b334a45a8ff	5825	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
bogdanm	0:9b334a45a8ff	5826	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
bogdanm	0:9b334a45a8ff	5827	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
bogdanm	0:9b334a45a8ff	5828
bogdanm	0:9b334a45a8ff	5829	/**************** Bit definition for I2C_CR2 register ******************/
bogdanm	0:9b334a45a8ff	5830	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
bogdanm	0:9b334a45a8ff	5831	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
bogdanm	0:9b334a45a8ff	5832	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
bogdanm	0:9b334a45a8ff	5833	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
bogdanm	0:9b334a45a8ff	5834	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
bogdanm	0:9b334a45a8ff	5835	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
bogdanm	0:9b334a45a8ff	5836	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
bogdanm	0:9b334a45a8ff	5837	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
bogdanm	0:9b334a45a8ff	5838	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
bogdanm	0:9b334a45a8ff	5839	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
bogdanm	0:9b334a45a8ff	5840	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
bogdanm	0:9b334a45a8ff	5841
bogdanm	0:9b334a45a8ff	5842	/***************** Bit definition for I2C_OAR1 register ****************/
bogdanm	0:9b334a45a8ff	5843	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
bogdanm	0:9b334a45a8ff	5844	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
bogdanm	0:9b334a45a8ff	5845	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
bogdanm	0:9b334a45a8ff	5846
bogdanm	0:9b334a45a8ff	5847	/***************** Bit definition for I2C_OAR2 register *****************/
bogdanm	0:9b334a45a8ff	5848	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
bogdanm	0:9b334a45a8ff	5849	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
bogdanm	0:9b334a45a8ff	5850	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
bogdanm	0:9b334a45a8ff	5851
bogdanm	0:9b334a45a8ff	5852	/***************** Bit definition for I2C_TIMINGR register ***************/
bogdanm	0:9b334a45a8ff	5853	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
bogdanm	0:9b334a45a8ff	5854	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
bogdanm	0:9b334a45a8ff	5855	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
bogdanm	0:9b334a45a8ff	5856	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
bogdanm	0:9b334a45a8ff	5857	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
bogdanm	0:9b334a45a8ff	5858
bogdanm	0:9b334a45a8ff	5859	/***************** Bit definition for I2C_TIMEOUTR register ***************/
bogdanm	0:9b334a45a8ff	5860	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
bogdanm	0:9b334a45a8ff	5861	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
bogdanm	0:9b334a45a8ff	5862	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
bogdanm	0:9b334a45a8ff	5863	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
bogdanm	0:9b334a45a8ff	5864	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
bogdanm	0:9b334a45a8ff	5865
bogdanm	0:9b334a45a8ff	5866	/**************** Bit definition for I2C_ISR register *******************/
bogdanm	0:9b334a45a8ff	5867	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
bogdanm	0:9b334a45a8ff	5868	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
bogdanm	0:9b334a45a8ff	5869	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
bogdanm	0:9b334a45a8ff	5870	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
bogdanm	0:9b334a45a8ff	5871	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
bogdanm	0:9b334a45a8ff	5872	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
bogdanm	0:9b334a45a8ff	5873	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
bogdanm	0:9b334a45a8ff	5874	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
bogdanm	0:9b334a45a8ff	5875	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
bogdanm	0:9b334a45a8ff	5876	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
bogdanm	0:9b334a45a8ff	5877	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
bogdanm	0:9b334a45a8ff	5878	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
bogdanm	0:9b334a45a8ff	5879	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
bogdanm	0:9b334a45a8ff	5880	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
bogdanm	0:9b334a45a8ff	5881	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
bogdanm	0:9b334a45a8ff	5882	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
bogdanm	0:9b334a45a8ff	5883	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
bogdanm	0:9b334a45a8ff	5884
bogdanm	0:9b334a45a8ff	5885	/**************** Bit definition for I2C_ICR register *******************/
bogdanm	0:9b334a45a8ff	5886	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
bogdanm	0:9b334a45a8ff	5887	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
bogdanm	0:9b334a45a8ff	5888	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
bogdanm	0:9b334a45a8ff	5889	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
bogdanm	0:9b334a45a8ff	5890	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
bogdanm	0:9b334a45a8ff	5891	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
bogdanm	0:9b334a45a8ff	5892	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
bogdanm	0:9b334a45a8ff	5893	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
bogdanm	0:9b334a45a8ff	5894	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
bogdanm	0:9b334a45a8ff	5895
bogdanm	0:9b334a45a8ff	5896	/**************** Bit definition for I2C_PECR register ******************/
bogdanm	0:9b334a45a8ff	5897	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
bogdanm	0:9b334a45a8ff	5898
bogdanm	0:9b334a45a8ff	5899	/**************** Bit definition for I2C_RXDR register *******************/
bogdanm	0:9b334a45a8ff	5900	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
bogdanm	0:9b334a45a8ff	5901
bogdanm	0:9b334a45a8ff	5902	/**************** Bit definition for I2C_TXDR register *******************/
bogdanm	0:9b334a45a8ff	5903	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
bogdanm	0:9b334a45a8ff	5904
bogdanm	0:9b334a45a8ff	5905
bogdanm	0:9b334a45a8ff	5906	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5907	/* */
bogdanm	0:9b334a45a8ff	5908	/* Independent WATCHDOG (IWDG) */
bogdanm	0:9b334a45a8ff	5909	/* */
bogdanm	0:9b334a45a8ff	5910	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5911	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	0:9b334a45a8ff	5912	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!< Key value (write only, read 0000h) /
bogdanm	0:9b334a45a8ff	5913
bogdanm	0:9b334a45a8ff	5914	/***************** Bit definition for IWDG_PR register ******************/
bogdanm	0:9b334a45a8ff	5915	#define IWDG_PR_PR ((uint8_t)0x07) /!< PR[2:0] (Prescaler divider) /
bogdanm	0:9b334a45a8ff	5916	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5917	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5918	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5919
bogdanm	0:9b334a45a8ff	5920	/***************** Bit definition for IWDG_RLR register *****************/
bogdanm	0:9b334a45a8ff	5921	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!< Watchdog counter reload value /
bogdanm	0:9b334a45a8ff	5922
bogdanm	0:9b334a45a8ff	5923	/***************** Bit definition for IWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	5924	#define IWDG_SR_PVU ((uint8_t)0x01) /!< Watchdog prescaler value update /
bogdanm	0:9b334a45a8ff	5925	#define IWDG_SR_RVU ((uint8_t)0x02) /!< Watchdog counter reload value update /
bogdanm	0:9b334a45a8ff	5926	#define IWDG_SR_WVU ((uint8_t)0x04) /!< Watchdog counter window value update /
bogdanm	0:9b334a45a8ff	5927
bogdanm	0:9b334a45a8ff	5928	/***************** Bit definition for IWDG_KR register ******************/
bogdanm	0:9b334a45a8ff	5929	#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /!< Watchdog counter window value /
bogdanm	0:9b334a45a8ff	5930
bogdanm	0:9b334a45a8ff	5931	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5932	/* */
bogdanm	0:9b334a45a8ff	5933	/* Power Control */
bogdanm	0:9b334a45a8ff	5934	/* */
bogdanm	0:9b334a45a8ff	5935	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5936	/****************** Bit definition for PWR_CR register ******************/
bogdanm	0:9b334a45a8ff	5937	#define PWR_CR_LPSDSR ((uint16_t)0x0001) /!< Low-power deepsleep/sleep/low power run /
bogdanm	0:9b334a45a8ff	5938	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
bogdanm	0:9b334a45a8ff	5939	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
bogdanm	0:9b334a45a8ff	5940	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
bogdanm	0:9b334a45a8ff	5941	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
bogdanm	0:9b334a45a8ff	5942
bogdanm	0:9b334a45a8ff	5943	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
bogdanm	0:9b334a45a8ff	5944	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	5945	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	5946	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	5947
bogdanm	0:9b334a45a8ff	5948	/!< PVD level configuration /
bogdanm	0:9b334a45a8ff	5949	#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /!< PVD level 0 /
bogdanm	0:9b334a45a8ff	5950	#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /!< PVD level 1 /
bogdanm	0:9b334a45a8ff	5951	#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /!< PVD level 2 /
bogdanm	0:9b334a45a8ff	5952	#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /!< PVD level 3 /
bogdanm	0:9b334a45a8ff	5953	#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /!< PVD level 4 /
bogdanm	0:9b334a45a8ff	5954	#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /!< PVD level 5 /
bogdanm	0:9b334a45a8ff	5955	#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /!< PVD level 6 /
bogdanm	0:9b334a45a8ff	5956	#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /!< PVD level 7 /
bogdanm	0:9b334a45a8ff	5957
bogdanm	0:9b334a45a8ff	5958	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
bogdanm	0:9b334a45a8ff	5959
bogdanm	0:9b334a45a8ff	5960	/***************** Bit definition for PWR_CSR register ******************/
bogdanm	0:9b334a45a8ff	5961	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
bogdanm	0:9b334a45a8ff	5962	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
bogdanm	0:9b334a45a8ff	5963	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
bogdanm	0:9b334a45a8ff	5964	#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /!< Internal voltage reference (VREFINT) ready flag /
bogdanm	0:9b334a45a8ff	5965
bogdanm	0:9b334a45a8ff	5966	#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /!< Enable WKUP pin 1 /
bogdanm	0:9b334a45a8ff	5967	#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /!< Enable WKUP pin 2 /
bogdanm	0:9b334a45a8ff	5968	#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /!< Enable WKUP pin 3 /
bogdanm	0:9b334a45a8ff	5969
bogdanm	0:9b334a45a8ff	5970	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5971	/* */
bogdanm	0:9b334a45a8ff	5972	/* Reset and Clock Control */
bogdanm	0:9b334a45a8ff	5973	/* */
bogdanm	0:9b334a45a8ff	5974	/******************************************************************************/
bogdanm	0:9b334a45a8ff	5975	/****************** Bit definition for RCC_CR register ******************/
bogdanm	0:9b334a45a8ff	5976	#define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	5977	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	5978
bogdanm	0:9b334a45a8ff	5979	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm	0:9b334a45a8ff	5980	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/!<Bit 0 /
bogdanm	0:9b334a45a8ff	5981	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/!<Bit 1 /
bogdanm	0:9b334a45a8ff	5982	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/!<Bit 2 /
bogdanm	0:9b334a45a8ff	5983	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/!<Bit 3 /
bogdanm	0:9b334a45a8ff	5984	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/!<Bit 4 /
bogdanm	0:9b334a45a8ff	5985
bogdanm	0:9b334a45a8ff	5986	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm	0:9b334a45a8ff	5987	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/!<Bit 0 /
bogdanm	0:9b334a45a8ff	5988	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/!<Bit 1 /
bogdanm	0:9b334a45a8ff	5989	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/!<Bit 2 /
bogdanm	0:9b334a45a8ff	5990	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/!<Bit 3 /
bogdanm	0:9b334a45a8ff	5991	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/!<Bit 4 /
bogdanm	0:9b334a45a8ff	5992	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/!<Bit 5 /
bogdanm	0:9b334a45a8ff	5993	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/!<Bit 6 /
bogdanm	0:9b334a45a8ff	5994	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/!<Bit 7 /
bogdanm	0:9b334a45a8ff	5995
bogdanm	0:9b334a45a8ff	5996	#define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	5997	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	5998	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	5999	#define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6000
bogdanm	0:9b334a45a8ff	6001	#define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6002	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6003
bogdanm	0:9b334a45a8ff	6004	/****************** Bit definition for RCC_CFGR register ****************/
bogdanm	0:9b334a45a8ff	6005	/!< SW configuration /
bogdanm	0:9b334a45a8ff	6006	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	0:9b334a45a8ff	6007	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6008	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6009
bogdanm	0:9b334a45a8ff	6010	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
bogdanm	0:9b334a45a8ff	6011	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
bogdanm	0:9b334a45a8ff	6012	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	6013
bogdanm	0:9b334a45a8ff	6014	/!< SWS configuration /
bogdanm	0:9b334a45a8ff	6015	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	0:9b334a45a8ff	6016	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6017	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6018
bogdanm	0:9b334a45a8ff	6019	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
bogdanm	0:9b334a45a8ff	6020	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
bogdanm	0:9b334a45a8ff	6021	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
bogdanm	0:9b334a45a8ff	6022
bogdanm	0:9b334a45a8ff	6023	/!< HPRE configuration /
bogdanm	0:9b334a45a8ff	6024	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	0:9b334a45a8ff	6025	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6026	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6027	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6028	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6029
bogdanm	0:9b334a45a8ff	6030	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	6031	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	6032	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	6033	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	6034	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	6035	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	6036	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	6037	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	6038	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	6039
bogdanm	0:9b334a45a8ff	6040	/!< PPRE1 configuration /
bogdanm	0:9b334a45a8ff	6041	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
bogdanm	0:9b334a45a8ff	6042	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6043	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6044	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6045
bogdanm	0:9b334a45a8ff	6046	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	6047	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	6048	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	6049	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	6050	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	6051
bogdanm	0:9b334a45a8ff	6052	/!< PPRE2 configuration /
bogdanm	0:9b334a45a8ff	6053	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
bogdanm	0:9b334a45a8ff	6054	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6055	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6056	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6057
bogdanm	0:9b334a45a8ff	6058	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	6059	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	6060	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	6061	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	6062	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	6063
bogdanm	0:9b334a45a8ff	6064	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
bogdanm	0:9b334a45a8ff	6065
bogdanm	0:9b334a45a8ff	6066	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
bogdanm	0:9b334a45a8ff	6067
bogdanm	0:9b334a45a8ff	6068	/!< PLLMUL configuration /
bogdanm	0:9b334a45a8ff	6069	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
bogdanm	0:9b334a45a8ff	6070	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6071	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6072	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6073	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6074
bogdanm	0:9b334a45a8ff	6075	#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	6076	#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /!< PREDIV1 clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	6077
bogdanm	0:9b334a45a8ff	6078	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
bogdanm	0:9b334a45a8ff	6079	#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
bogdanm	0:9b334a45a8ff	6080
bogdanm	0:9b334a45a8ff	6081	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
bogdanm	0:9b334a45a8ff	6082	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
bogdanm	0:9b334a45a8ff	6083	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
bogdanm	0:9b334a45a8ff	6084	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
bogdanm	0:9b334a45a8ff	6085	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
bogdanm	0:9b334a45a8ff	6086	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
bogdanm	0:9b334a45a8ff	6087	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
bogdanm	0:9b334a45a8ff	6088	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
bogdanm	0:9b334a45a8ff	6089	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
bogdanm	0:9b334a45a8ff	6090	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
bogdanm	0:9b334a45a8ff	6091	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
bogdanm	0:9b334a45a8ff	6092	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
bogdanm	0:9b334a45a8ff	6093	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
bogdanm	0:9b334a45a8ff	6094	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
bogdanm	0:9b334a45a8ff	6095	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
bogdanm	0:9b334a45a8ff	6096
bogdanm	0:9b334a45a8ff	6097	/!< USB configuration /
bogdanm	0:9b334a45a8ff	6098	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
bogdanm	0:9b334a45a8ff	6099
bogdanm	0:9b334a45a8ff	6100	/!< I2S configuration /
bogdanm	0:9b334a45a8ff	6101	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /!< I2S external clock source selection /
bogdanm	0:9b334a45a8ff	6102
bogdanm	0:9b334a45a8ff	6103	/!< MCO configuration /
bogdanm	0:9b334a45a8ff	6104	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
bogdanm	0:9b334a45a8ff	6105	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6106	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6107	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6108
bogdanm	0:9b334a45a8ff	6109	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	6110	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
bogdanm	0:9b334a45a8ff	6111	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
bogdanm	0:9b334a45a8ff	6112	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
bogdanm	0:9b334a45a8ff	6113	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
bogdanm	0:9b334a45a8ff	6114	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
bogdanm	0:9b334a45a8ff	6115	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
bogdanm	0:9b334a45a8ff	6116
bogdanm	0:9b334a45a8ff	6117	#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /!< Microcontroller Clock Output Flag /
bogdanm	0:9b334a45a8ff	6118
bogdanm	0:9b334a45a8ff	6119	#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /!< MCO prescaler /
bogdanm	0:9b334a45a8ff	6120	#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
bogdanm	0:9b334a45a8ff	6121	#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
bogdanm	0:9b334a45a8ff	6122	#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
bogdanm	0:9b334a45a8ff	6123	#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
bogdanm	0:9b334a45a8ff	6124	#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
bogdanm	0:9b334a45a8ff	6125	#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
bogdanm	0:9b334a45a8ff	6126	#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
bogdanm	0:9b334a45a8ff	6127	#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
bogdanm	0:9b334a45a8ff	6128
bogdanm	0:9b334a45a8ff	6129	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
bogdanm	0:9b334a45a8ff	6130
bogdanm	0:9b334a45a8ff	6131	/******************* Bit definition for RCC_CIR register ******************/
bogdanm	0:9b334a45a8ff	6132	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	6133	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	6134	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	6135	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	6136	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	6137	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	6138	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	6139	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	6140	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	6141	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	6142	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
bogdanm	0:9b334a45a8ff	6143	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	6144	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	6145	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	6146	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	6147	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
bogdanm	0:9b334a45a8ff	6148	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
bogdanm	0:9b334a45a8ff	6149
bogdanm	0:9b334a45a8ff	6150	/**************** Bit definition for RCC_APB2RSTR register ***************/
bogdanm	0:9b334a45a8ff	6151	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG reset /
bogdanm	0:9b334a45a8ff	6152	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /!< TIM1 reset /
bogdanm	0:9b334a45a8ff	6153	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 reset /
bogdanm	0:9b334a45a8ff	6154	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /!< TIM8 reset /
bogdanm	0:9b334a45a8ff	6155	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
bogdanm	0:9b334a45a8ff	6156	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 reset /
bogdanm	0:9b334a45a8ff	6157	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 reset /
bogdanm	0:9b334a45a8ff	6158	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 reset /
bogdanm	0:9b334a45a8ff	6159	#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /!< HRTIM1 reset /
bogdanm	0:9b334a45a8ff	6160
bogdanm	0:9b334a45a8ff	6161	/**************** Bit definition for RCC_APB1RSTR register ****************/
bogdanm	0:9b334a45a8ff	6162	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
bogdanm	0:9b334a45a8ff	6163	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
bogdanm	0:9b334a45a8ff	6164	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
bogdanm	0:9b334a45a8ff	6165	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
bogdanm	0:9b334a45a8ff	6166	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
bogdanm	0:9b334a45a8ff	6167	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
bogdanm	0:9b334a45a8ff	6168	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 reset /
bogdanm	0:9b334a45a8ff	6169	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI3 reset /
bogdanm	0:9b334a45a8ff	6170	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
bogdanm	0:9b334a45a8ff	6171	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
bogdanm	0:9b334a45a8ff	6172	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
bogdanm	0:9b334a45a8ff	6173	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
bogdanm	0:9b334a45a8ff	6174	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
bogdanm	0:9b334a45a8ff	6175	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
bogdanm	0:9b334a45a8ff	6176	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB reset /
bogdanm	0:9b334a45a8ff	6177	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN reset /
bogdanm	0:9b334a45a8ff	6178	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR reset /
bogdanm	0:9b334a45a8ff	6179	#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /!< DAC 1 reset /
bogdanm	0:9b334a45a8ff	6180	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /!< I2C 3 reset /
bogdanm	0:9b334a45a8ff	6181	#define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /!< DAC 2 reset /
bogdanm	0:9b334a45a8ff	6182	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /!< DAC reset /
bogdanm	0:9b334a45a8ff	6183
bogdanm	0:9b334a45a8ff	6184	/**************** Bit definition for RCC_AHBENR register ****************/
bogdanm	0:9b334a45a8ff	6185	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
bogdanm	0:9b334a45a8ff	6186	#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /!< DMA2 clock enable /
bogdanm	0:9b334a45a8ff	6187	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
bogdanm	0:9b334a45a8ff	6188	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
bogdanm	0:9b334a45a8ff	6189	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
bogdanm	0:9b334a45a8ff	6190	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
bogdanm	0:9b334a45a8ff	6191	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
bogdanm	0:9b334a45a8ff	6192	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
bogdanm	0:9b334a45a8ff	6193	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
bogdanm	0:9b334a45a8ff	6194	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /!< GPIOE clock enable /
bogdanm	0:9b334a45a8ff	6195	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
bogdanm	0:9b334a45a8ff	6196	#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /!< TS clock enable /
bogdanm	0:9b334a45a8ff	6197	#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /!< ADC1/ ADC2 clock enable /
bogdanm	0:9b334a45a8ff	6198	#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /!< ADC1/ ADC2 clock enable /
bogdanm	0:9b334a45a8ff	6199
bogdanm	0:9b334a45a8ff	6200	/*************** Bit definition for RCC_APB2ENR register ****************/
bogdanm	0:9b334a45a8ff	6201	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /!< SYSCFG clock enable /
bogdanm	0:9b334a45a8ff	6202	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
bogdanm	0:9b334a45a8ff	6203	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
bogdanm	0:9b334a45a8ff	6204	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /!< TIM8 clock enable /
bogdanm	0:9b334a45a8ff	6205	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
bogdanm	0:9b334a45a8ff	6206	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
bogdanm	0:9b334a45a8ff	6207	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
bogdanm	0:9b334a45a8ff	6208	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
bogdanm	0:9b334a45a8ff	6209	#define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /!< HRTIM1 clock enable /
bogdanm	0:9b334a45a8ff	6210
bogdanm	0:9b334a45a8ff	6211	/**************** Bit definition for RCC_APB1ENR register ****************/
bogdanm	0:9b334a45a8ff	6212	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
bogdanm	0:9b334a45a8ff	6213	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
bogdanm	0:9b334a45a8ff	6214	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
bogdanm	0:9b334a45a8ff	6215	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
bogdanm	0:9b334a45a8ff	6216	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
bogdanm	0:9b334a45a8ff	6217	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
bogdanm	0:9b334a45a8ff	6218	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
bogdanm	0:9b334a45a8ff	6219	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI3 clock enable /
bogdanm	0:9b334a45a8ff	6220	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
bogdanm	0:9b334a45a8ff	6221	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
bogdanm	0:9b334a45a8ff	6222	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
bogdanm	0:9b334a45a8ff	6223	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
bogdanm	0:9b334a45a8ff	6224	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
bogdanm	0:9b334a45a8ff	6225	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
bogdanm	0:9b334a45a8ff	6226	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
bogdanm	0:9b334a45a8ff	6227	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN clock enable /
bogdanm	0:9b334a45a8ff	6228	#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /!< DAC 2 clock enable /
bogdanm	0:9b334a45a8ff	6229	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
bogdanm	0:9b334a45a8ff	6230	#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /!< DAC clock enable /
bogdanm	0:9b334a45a8ff	6231	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /!< I2C 3 clock enable /
bogdanm	0:9b334a45a8ff	6232	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN
bogdanm	0:9b334a45a8ff	6233
bogdanm	0:9b334a45a8ff	6234	/****************** Bit definition for RCC_BDCR register ****************/
bogdanm	0:9b334a45a8ff	6235	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	6236	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	6237	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
bogdanm	0:9b334a45a8ff	6238
bogdanm	0:9b334a45a8ff	6239	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
bogdanm	0:9b334a45a8ff	6240	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6241	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6242
bogdanm	0:9b334a45a8ff	6243
bogdanm	0:9b334a45a8ff	6244	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
bogdanm	0:9b334a45a8ff	6245	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6246	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6247
bogdanm	0:9b334a45a8ff	6248	/!< RTC configuration /
bogdanm	0:9b334a45a8ff	6249	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	0:9b334a45a8ff	6250	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	6251	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	6252	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 32 used as RTC clock /
bogdanm	0:9b334a45a8ff	6253
bogdanm	0:9b334a45a8ff	6254	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
bogdanm	0:9b334a45a8ff	6255	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
bogdanm	0:9b334a45a8ff	6256
bogdanm	0:9b334a45a8ff	6257	/****************** Bit definition for RCC_CSR register *****************/
bogdanm	0:9b334a45a8ff	6258	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
bogdanm	0:9b334a45a8ff	6259	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	6260	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
bogdanm	0:9b334a45a8ff	6261	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
bogdanm	0:9b334a45a8ff	6262	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	6263	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
bogdanm	0:9b334a45a8ff	6264	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	6265	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	6266	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	6267	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	6268
bogdanm	0:9b334a45a8ff	6269	/***************** Bit definition for RCC_AHBRSTR register **************/
bogdanm	0:9b334a45a8ff	6270	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA reset /
bogdanm	0:9b334a45a8ff	6271	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB reset /
bogdanm	0:9b334a45a8ff	6272	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC reset /
bogdanm	0:9b334a45a8ff	6273	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /!< GPIOD reset /
bogdanm	0:9b334a45a8ff	6274	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /!< GPIOF reset /
bogdanm	0:9b334a45a8ff	6275	#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /!< TS reset /
bogdanm	0:9b334a45a8ff	6276	#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /!< ADC1 & ADC2 reset /
bogdanm	0:9b334a45a8ff	6277	#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /!< ADC3 & ADC4 reset /
bogdanm	0:9b334a45a8ff	6278
bogdanm	0:9b334a45a8ff	6279	/***************** Bit definition for RCC_CFGR2 register ****************/
bogdanm	0:9b334a45a8ff	6280	/!< PREDIV1 configuration /
bogdanm	0:9b334a45a8ff	6281	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
bogdanm	0:9b334a45a8ff	6282	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6283	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6284	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6285	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6286
bogdanm	0:9b334a45a8ff	6287	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
bogdanm	0:9b334a45a8ff	6288	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
bogdanm	0:9b334a45a8ff	6289	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
bogdanm	0:9b334a45a8ff	6290	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
bogdanm	0:9b334a45a8ff	6291	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
bogdanm	0:9b334a45a8ff	6292	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
bogdanm	0:9b334a45a8ff	6293	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
bogdanm	0:9b334a45a8ff	6294	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
bogdanm	0:9b334a45a8ff	6295	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
bogdanm	0:9b334a45a8ff	6296	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
bogdanm	0:9b334a45a8ff	6297	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
bogdanm	0:9b334a45a8ff	6298	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
bogdanm	0:9b334a45a8ff	6299	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
bogdanm	0:9b334a45a8ff	6300	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
bogdanm	0:9b334a45a8ff	6301	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
bogdanm	0:9b334a45a8ff	6302	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
bogdanm	0:9b334a45a8ff	6303
bogdanm	0:9b334a45a8ff	6304	/!< ADCPRE12 configuration /
bogdanm	0:9b334a45a8ff	6305	#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /!< ADCPRE12[8:4] bits /
bogdanm	0:9b334a45a8ff	6306	#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6307	#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6308	#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6309	#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6310	#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6311
bogdanm	0:9b334a45a8ff	6312	#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /!< ADC12 clock disabled, ADC12 can use AHB clock /
bogdanm	0:9b334a45a8ff	6313	#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /!< ADC12 PLL clock divided by 1 /
bogdanm	0:9b334a45a8ff	6314	#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /!< ADC12 PLL clock divided by 2 /
bogdanm	0:9b334a45a8ff	6315	#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /!< ADC12 PLL clock divided by 4 /
bogdanm	0:9b334a45a8ff	6316	#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /!< ADC12 PLL clock divided by 6 /
bogdanm	0:9b334a45a8ff	6317	#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /!< ADC12 PLL clock divided by 8 /
bogdanm	0:9b334a45a8ff	6318	#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /!< ADC12 PLL clock divided by 10 /
bogdanm	0:9b334a45a8ff	6319	#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /!< ADC12 PLL clock divided by 12 /
bogdanm	0:9b334a45a8ff	6320	#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /!< ADC12 PLL clock divided by 16 /
bogdanm	0:9b334a45a8ff	6321	#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /!< ADC12 PLL clock divided by 32 /
bogdanm	0:9b334a45a8ff	6322	#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /!< ADC12 PLL clock divided by 64 /
bogdanm	0:9b334a45a8ff	6323	#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /!< ADC12 PLL clock divided by 128 /
bogdanm	0:9b334a45a8ff	6324	#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /!< ADC12 PLL clock divided by 256 /
bogdanm	0:9b334a45a8ff	6325
bogdanm	0:9b334a45a8ff	6326	/!< ADCPRE34 configuration /
bogdanm	0:9b334a45a8ff	6327	#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /!< ADCPRE34[13:5] bits /
bogdanm	0:9b334a45a8ff	6328	#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6329	#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6330	#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6331	#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6332	#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	6333
bogdanm	0:9b334a45a8ff	6334	#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /!< ADC34 clock disabled, ADC34 can use AHB clock /
bogdanm	0:9b334a45a8ff	6335	#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /!< ADC34 PLL clock divided by 1 /
bogdanm	0:9b334a45a8ff	6336	#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /!< ADC34 PLL clock divided by 2 /
bogdanm	0:9b334a45a8ff	6337	#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /!< ADC34 PLL clock divided by 4 /
bogdanm	0:9b334a45a8ff	6338	#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /!< ADC34 PLL clock divided by 6 /
bogdanm	0:9b334a45a8ff	6339	#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /!< ADC34 PLL clock divided by 8 /
bogdanm	0:9b334a45a8ff	6340	#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /!< ADC34 PLL clock divided by 10 /
bogdanm	0:9b334a45a8ff	6341	#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /!< ADC34 PLL clock divided by 12 /
bogdanm	0:9b334a45a8ff	6342	#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /!< ADC34 PLL clock divided by 16 /
bogdanm	0:9b334a45a8ff	6343	#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /!< ADC34 PLL clock divided by 32 /
bogdanm	0:9b334a45a8ff	6344	#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /!< ADC34 PLL clock divided by 64 /
bogdanm	0:9b334a45a8ff	6345	#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /!< ADC34 PLL clock divided by 128 /
bogdanm	0:9b334a45a8ff	6346	#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /!< ADC34 PLL clock divided by 256 /
bogdanm	0:9b334a45a8ff	6347
bogdanm	0:9b334a45a8ff	6348	/***************** Bit definition for RCC_CFGR3 register ****************/
bogdanm	0:9b334a45a8ff	6349	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
bogdanm	0:9b334a45a8ff	6350	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6351	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6352
bogdanm	0:9b334a45a8ff	6353	#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /!< I2CSW bits /
bogdanm	0:9b334a45a8ff	6354	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
bogdanm	0:9b334a45a8ff	6355	#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /!< I2C2SW bits /
bogdanm	0:9b334a45a8ff	6356	#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /!< I2C3SW bits /
bogdanm	0:9b334a45a8ff	6357
bogdanm	0:9b334a45a8ff	6358	#define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /!< TIMSW bits /
bogdanm	0:9b334a45a8ff	6359	#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /!< TIM1SW bits /
bogdanm	0:9b334a45a8ff	6360	#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /!< TIM8SW bits /
bogdanm	0:9b334a45a8ff	6361	#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /!< TIM15SW bits /
bogdanm	0:9b334a45a8ff	6362	#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /!< TIM16SW bits /
bogdanm	0:9b334a45a8ff	6363	#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /!< TIM17SW bits /
bogdanm	0:9b334a45a8ff	6364
bogdanm	0:9b334a45a8ff	6365	#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /!< HRTIM1SW bits /
bogdanm	0:9b334a45a8ff	6366
bogdanm	0:9b334a45a8ff	6367	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
bogdanm	0:9b334a45a8ff	6368	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6369	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6370
bogdanm	0:9b334a45a8ff	6371	#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /!< USART3SW[1:0] bits /
bogdanm	0:9b334a45a8ff	6372	#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6373	#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6374
bogdanm	0:9b334a45a8ff	6375	#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /!< UART4SW[1:0] bits /
bogdanm	0:9b334a45a8ff	6376	#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6377	#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6378
bogdanm	0:9b334a45a8ff	6379	#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /!< UART5SW[1:0] bits /
bogdanm	0:9b334a45a8ff	6380	#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6381	#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6382
bogdanm	0:9b334a45a8ff	6383	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6384	/* */
bogdanm	0:9b334a45a8ff	6385	/* Real-Time Clock (RTC) */
bogdanm	0:9b334a45a8ff	6386	/* */
bogdanm	0:9b334a45a8ff	6387	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6388	/****************** Bits definition for RTC_TR register *****************/
bogdanm	0:9b334a45a8ff	6389	#define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6390	#define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6391	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6392	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6393	#define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6394	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6395	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6396	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6397	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6398	#define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6399	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6400	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6401	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6402	#define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6403	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6404	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6405	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6406	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6407	#define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6408	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6409	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6410	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6411	#define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6412	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6413	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6414	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6415	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6416
bogdanm	0:9b334a45a8ff	6417	/****************** Bits definition for RTC_DR register *****************/
bogdanm	0:9b334a45a8ff	6418	#define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm	0:9b334a45a8ff	6419	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6420	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6421	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6422	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6423	#define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6424	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6425	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6426	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6427	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6428	#define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	6429	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6430	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6431	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6432	#define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6433	#define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6434	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6435	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6436	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6437	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6438	#define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	6439	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6440	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6441	#define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6442	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6443	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6444	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6445	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6446
bogdanm	0:9b334a45a8ff	6447	/****************** Bits definition for RTC_CR register *****************/
bogdanm	0:9b334a45a8ff	6448	#define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6449	#define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm	0:9b334a45a8ff	6450	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6451	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6452	#define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6453	#define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6454	#define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6455	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6456	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6457	#define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6458	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6459	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6460	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6461	#define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6462	#define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6463	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6464	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6465	#define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6466	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6467	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6468	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6469	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm	0:9b334a45a8ff	6470	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6471	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6472	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6473
bogdanm	0:9b334a45a8ff	6474	/****************** Bits definition for RTC_ISR register ****************/
bogdanm	0:9b334a45a8ff	6475	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6476	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6477	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6478	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6479	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6480	#define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6481	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6482	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6483	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6484	#define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6485	#define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6486	#define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6487	#define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6488	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6489	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6490	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6491	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6492
bogdanm	0:9b334a45a8ff	6493	/****************** Bits definition for RTC_PRER register ***************/
bogdanm	0:9b334a45a8ff	6494	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm	0:9b334a45a8ff	6495	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6496
bogdanm	0:9b334a45a8ff	6497	/****************** Bits definition for RTC_WUTR register ***************/
bogdanm	0:9b334a45a8ff	6498	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6499
bogdanm	0:9b334a45a8ff	6500	/****************** Bits definition for RTC_ALRMAR register *************/
bogdanm	0:9b334a45a8ff	6501	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6502	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	6503	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	6504	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	6505	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	6506	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6507	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6508	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6509	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6510	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6511	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6512	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6513	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6514	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6515	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6516	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6517	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6518	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6519	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6520	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6521	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6522	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6523	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6524	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6525	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6526	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6527	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6528	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6529	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6530	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6531	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6532	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6533	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6534	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6535	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6536	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6537	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6538	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6539	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6540	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6541
bogdanm	0:9b334a45a8ff	6542	/****************** Bits definition for RTC_ALRMBR register *************/
bogdanm	0:9b334a45a8ff	6543	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6544	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	6545	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	6546	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	6547	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	6548	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6549	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6550	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6551	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6552	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6553	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm	0:9b334a45a8ff	6554	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6555	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6556	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6557	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6558	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6559	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6560	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6561	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6562	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6563	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6564	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6565	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6566	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6567	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6568	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6569	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6570	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6571	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6572	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6573	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6574	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6575	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6576	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6577	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6578	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6579	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6580	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6581	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6582	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6583
bogdanm	0:9b334a45a8ff	6584	/****************** Bits definition for RTC_WPR register ****************/
bogdanm	0:9b334a45a8ff	6585	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm	0:9b334a45a8ff	6586
bogdanm	0:9b334a45a8ff	6587	/****************** Bits definition for RTC_SSR register ****************/
bogdanm	0:9b334a45a8ff	6588	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6589
bogdanm	0:9b334a45a8ff	6590	/****************** Bits definition for RTC_SHIFTR register *************/
bogdanm	0:9b334a45a8ff	6591	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6592	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm	0:9b334a45a8ff	6593
bogdanm	0:9b334a45a8ff	6594	/****************** Bits definition for RTC_TSTR register ***************/
bogdanm	0:9b334a45a8ff	6595	#define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm	0:9b334a45a8ff	6596	#define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm	0:9b334a45a8ff	6597	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	6598	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm	0:9b334a45a8ff	6599	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm	0:9b334a45a8ff	6600	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	6601	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	6602	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6603	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	6604	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm	0:9b334a45a8ff	6605	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6606	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6607	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6608	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6609	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6610	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6611	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6612	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6613	#define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm	0:9b334a45a8ff	6614	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6615	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6616	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6617	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6618	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6619	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6620	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6621	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6622
bogdanm	0:9b334a45a8ff	6623	/****************** Bits definition for RTC_TSDR register ***************/
bogdanm	0:9b334a45a8ff	6624	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm	0:9b334a45a8ff	6625	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6626	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6627	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6628	#define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6629	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm	0:9b334a45a8ff	6630	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6631	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6632	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6633	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6634	#define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm	0:9b334a45a8ff	6635	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6636	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6637	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm	0:9b334a45a8ff	6638	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6639	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6640	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6641	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6642
bogdanm	0:9b334a45a8ff	6643	/****************** Bits definition for RTC_TSSSR register **************/
bogdanm	0:9b334a45a8ff	6644	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm	0:9b334a45a8ff	6645
bogdanm	0:9b334a45a8ff	6646	/****************** Bits definition for RTC_CAL register ***************/
bogdanm	0:9b334a45a8ff	6647	#define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6648	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6649	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6650	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm	0:9b334a45a8ff	6651	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6652	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6653	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6654	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6655	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6656	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6657	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6658	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6659	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6660
bogdanm	0:9b334a45a8ff	6661	/****************** Bits definition for RTC_TAFCR register **************/
bogdanm	0:9b334a45a8ff	6662	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	6663	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	6664	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm	0:9b334a45a8ff	6665	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	6666	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	6667	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm	0:9b334a45a8ff	6668	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	6669	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	6670	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm	0:9b334a45a8ff	6671	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	6672	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	6673	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	6674	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	6675	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	6676	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	6677	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	6678	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	6679	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	6680	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	6681	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	6682
bogdanm	0:9b334a45a8ff	6683	/****************** Bits definition for RTC_ALRMASSR register ***********/
bogdanm	0:9b334a45a8ff	6684	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6685	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6686	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6687	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6688	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6689	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6690
bogdanm	0:9b334a45a8ff	6691	/****************** Bits definition for RTC_ALRMBSSR register ***********/
bogdanm	0:9b334a45a8ff	6692	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	0:9b334a45a8ff	6693	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	0:9b334a45a8ff	6694	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	0:9b334a45a8ff	6695	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	0:9b334a45a8ff	6696	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	0:9b334a45a8ff	6697	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm	0:9b334a45a8ff	6698
bogdanm	0:9b334a45a8ff	6699	/****************** Bits definition for RTC_BKP0R register **************/
bogdanm	0:9b334a45a8ff	6700	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6701
bogdanm	0:9b334a45a8ff	6702	/****************** Bits definition for RTC_BKP1R register **************/
bogdanm	0:9b334a45a8ff	6703	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6704
bogdanm	0:9b334a45a8ff	6705	/****************** Bits definition for RTC_BKP2R register **************/
bogdanm	0:9b334a45a8ff	6706	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6707
bogdanm	0:9b334a45a8ff	6708	/****************** Bits definition for RTC_BKP3R register **************/
bogdanm	0:9b334a45a8ff	6709	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6710
bogdanm	0:9b334a45a8ff	6711	/****************** Bits definition for RTC_BKP4R register **************/
bogdanm	0:9b334a45a8ff	6712	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6713
bogdanm	0:9b334a45a8ff	6714	/****************** Bits definition for RTC_BKP5R register **************/
bogdanm	0:9b334a45a8ff	6715	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6716
bogdanm	0:9b334a45a8ff	6717	/****************** Bits definition for RTC_BKP6R register **************/
bogdanm	0:9b334a45a8ff	6718	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6719
bogdanm	0:9b334a45a8ff	6720	/****************** Bits definition for RTC_BKP7R register **************/
bogdanm	0:9b334a45a8ff	6721	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6722
bogdanm	0:9b334a45a8ff	6723	/****************** Bits definition for RTC_BKP8R register **************/
bogdanm	0:9b334a45a8ff	6724	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6725
bogdanm	0:9b334a45a8ff	6726	/****************** Bits definition for RTC_BKP9R register **************/
bogdanm	0:9b334a45a8ff	6727	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6728
bogdanm	0:9b334a45a8ff	6729	/****************** Bits definition for RTC_BKP10R register *************/
bogdanm	0:9b334a45a8ff	6730	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6731
bogdanm	0:9b334a45a8ff	6732	/****************** Bits definition for RTC_BKP11R register *************/
bogdanm	0:9b334a45a8ff	6733	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6734
bogdanm	0:9b334a45a8ff	6735	/****************** Bits definition for RTC_BKP12R register *************/
bogdanm	0:9b334a45a8ff	6736	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6737
bogdanm	0:9b334a45a8ff	6738	/****************** Bits definition for RTC_BKP13R register *************/
bogdanm	0:9b334a45a8ff	6739	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6740
bogdanm	0:9b334a45a8ff	6741	/****************** Bits definition for RTC_BKP14R register *************/
bogdanm	0:9b334a45a8ff	6742	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6743
bogdanm	0:9b334a45a8ff	6744	/****************** Bits definition for RTC_BKP15R register *************/
bogdanm	0:9b334a45a8ff	6745	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	6746
bogdanm	0:9b334a45a8ff	6747	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6748	/* */
bogdanm	0:9b334a45a8ff	6749	/* Serial Peripheral Interface (SPI) */
bogdanm	0:9b334a45a8ff	6750	/* */
bogdanm	0:9b334a45a8ff	6751	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6752	/***************** Bit definition for SPI_CR1 register ******************/
bogdanm	0:9b334a45a8ff	6753	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	6754	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	6755	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!< Master Selection /
bogdanm	0:9b334a45a8ff	6756
bogdanm	0:9b334a45a8ff	6757	#define SPI_CR1_BR ((uint16_t)0x0038) /!< BR[2:0] bits (Baud Rate Control) /
bogdanm	0:9b334a45a8ff	6758	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6759	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6760	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6761
bogdanm	0:9b334a45a8ff	6762	#define SPI_CR1_SPE ((uint16_t)0x0040) /!< SPI Enable /
bogdanm	0:9b334a45a8ff	6763	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!< Frame Format /
bogdanm	0:9b334a45a8ff	6764	#define SPI_CR1_SSI ((uint16_t)0x0100) /!< Internal slave select /
bogdanm	0:9b334a45a8ff	6765	#define SPI_CR1_SSM ((uint16_t)0x0200) /!< Software slave management /
bogdanm	0:9b334a45a8ff	6766	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!< Receive only /
bogdanm	0:9b334a45a8ff	6767	#define SPI_CR1_CRCL ((uint16_t)0x0800) /!< CRC Length /
bogdanm	0:9b334a45a8ff	6768	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!< Transmit CRC next /
bogdanm	0:9b334a45a8ff	6769	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!< Hardware CRC calculation enable /
bogdanm	0:9b334a45a8ff	6770	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!< Output enable in bidirectional mode /
bogdanm	0:9b334a45a8ff	6771	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!< Bidirectional data mode enable /
bogdanm	0:9b334a45a8ff	6772
bogdanm	0:9b334a45a8ff	6773	/***************** Bit definition for SPI_CR2 register ******************/
bogdanm	0:9b334a45a8ff	6774	#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /!< Rx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	6775	#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /!< Tx Buffer DMA Enable /
bogdanm	0:9b334a45a8ff	6776	#define SPI_CR2_SSOE ((uint16_t)0x0004) /!< SS Output Enable /
bogdanm	0:9b334a45a8ff	6777	#define SPI_CR2_NSSP ((uint16_t)0x0008) /!< NSS pulse management Enable /
bogdanm	0:9b334a45a8ff	6778	#define SPI_CR2_FRF ((uint16_t)0x0010) /!< Frame Format Enable /
bogdanm	0:9b334a45a8ff	6779	#define SPI_CR2_ERRIE ((uint16_t)0x0020) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	6780	#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /!< RX buffer Not Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	6781	#define SPI_CR2_TXEIE ((uint16_t)0x0080) /!< Tx buffer Empty Interrupt Enable /
bogdanm	0:9b334a45a8ff	6782
bogdanm	0:9b334a45a8ff	6783	#define SPI_CR2_DS ((uint16_t)0x0F00) /!< DS[3:0] Data Size /
bogdanm	0:9b334a45a8ff	6784	#define SPI_CR2_DS_0 ((uint16_t)0x0100) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6785	#define SPI_CR2_DS_1 ((uint16_t)0x0200) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6786	#define SPI_CR2_DS_2 ((uint16_t)0x0400) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	6787	#define SPI_CR2_DS_3 ((uint16_t)0x0800) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	6788
bogdanm	0:9b334a45a8ff	6789	#define SPI_CR2_FRXTH ((uint16_t)0x1000) /!< FIFO reception Threshold /
bogdanm	0:9b334a45a8ff	6790	#define SPI_CR2_LDMARX ((uint16_t)0x2000) /!< Last DMA transfer for reception /
bogdanm	0:9b334a45a8ff	6791	#define SPI_CR2_LDMATX ((uint16_t)0x4000) /!< Last DMA transfer for transmission /
bogdanm	0:9b334a45a8ff	6792
bogdanm	0:9b334a45a8ff	6793	/****************** Bit definition for SPI_SR register ******************/
bogdanm	0:9b334a45a8ff	6794	#define SPI_SR_RXNE ((uint16_t)0x0001) /!< Receive buffer Not Empty /
bogdanm	0:9b334a45a8ff	6795	#define SPI_SR_TXE ((uint16_t)0x0002) /!< Transmit buffer Empty /
bogdanm	0:9b334a45a8ff	6796	#define SPI_SR_CRCERR ((uint16_t)0x0010) /!< CRC Error flag /
bogdanm	0:9b334a45a8ff	6797	#define SPI_SR_MODF ((uint16_t)0x0020) /!< Mode fault /
bogdanm	0:9b334a45a8ff	6798	#define SPI_SR_OVR ((uint16_t)0x0040) /!< Overrun flag /
bogdanm	0:9b334a45a8ff	6799	#define SPI_SR_BSY ((uint16_t)0x0080) /!< Busy flag /
bogdanm	0:9b334a45a8ff	6800	#define SPI_SR_FRE ((uint16_t)0x0100) /!< TI frame format error /
bogdanm	0:9b334a45a8ff	6801	#define SPI_SR_FRLVL ((uint16_t)0x0600) /!< FIFO Reception Level /
bogdanm	0:9b334a45a8ff	6802	#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6803	#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6804	#define SPI_SR_FTLVL ((uint16_t)0x1800) /!< FIFO Transmission Level /
bogdanm	0:9b334a45a8ff	6805	#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6806	#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6807
bogdanm	0:9b334a45a8ff	6808	/****************** Bit definition for SPI_DR register ******************/
bogdanm	0:9b334a45a8ff	6809	#define SPI_DR_DR ((uint16_t)0xFFFF) /!< Data Register /
bogdanm	0:9b334a45a8ff	6810
bogdanm	0:9b334a45a8ff	6811	/***************** Bit definition for SPI_CRCPR register ****************/
bogdanm	0:9b334a45a8ff	6812	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!< CRC polynomial register /
bogdanm	0:9b334a45a8ff	6813
bogdanm	0:9b334a45a8ff	6814	/**************** Bit definition for SPI_RXCRCR register ****************/
bogdanm	0:9b334a45a8ff	6815	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!< Rx CRC Register /
bogdanm	0:9b334a45a8ff	6816
bogdanm	0:9b334a45a8ff	6817	/**************** Bit definition for SPI_TXCRCR register ****************/
bogdanm	0:9b334a45a8ff	6818	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!< Tx CRC Register /
bogdanm	0:9b334a45a8ff	6819
bogdanm	0:9b334a45a8ff	6820	/**************** Bit definition for SPI_I2SCFGR register ***************/
bogdanm	0:9b334a45a8ff	6821	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
bogdanm	0:9b334a45a8ff	6822
bogdanm	0:9b334a45a8ff	6823	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
bogdanm	0:9b334a45a8ff	6824	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6825	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6826
bogdanm	0:9b334a45a8ff	6827	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
bogdanm	0:9b334a45a8ff	6828
bogdanm	0:9b334a45a8ff	6829	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
bogdanm	0:9b334a45a8ff	6830	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6831	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6832
bogdanm	0:9b334a45a8ff	6833	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
bogdanm	0:9b334a45a8ff	6834
bogdanm	0:9b334a45a8ff	6835	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
bogdanm	0:9b334a45a8ff	6836	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	6837	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	6838
bogdanm	0:9b334a45a8ff	6839	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
bogdanm	0:9b334a45a8ff	6840	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
bogdanm	0:9b334a45a8ff	6841
bogdanm	0:9b334a45a8ff	6842	/**************** Bit definition for SPI_I2SPR register *****************/
bogdanm	0:9b334a45a8ff	6843	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
bogdanm	0:9b334a45a8ff	6844	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
bogdanm	0:9b334a45a8ff	6845	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
bogdanm	0:9b334a45a8ff	6846
bogdanm	0:9b334a45a8ff	6847	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6848	/* */
bogdanm	0:9b334a45a8ff	6849	/* System Configuration(SYSCFG) */
bogdanm	0:9b334a45a8ff	6850	/* */
bogdanm	0:9b334a45a8ff	6851	/******************************************************************************/
bogdanm	0:9b334a45a8ff	6852	/*************** Bit definition for SYSCFG_CFGR1 register ***************/
bogdanm	0:9b334a45a8ff	6853	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
bogdanm	0:9b334a45a8ff	6854	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	6855	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	6856	#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /!< USB interrupt remap /
bogdanm	0:9b334a45a8ff	6857	#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /!< Timer 1 ITR3 selection /
bogdanm	0:9b334a45a8ff	6858	#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /!< DAC1 Trigger1 remap /
bogdanm	0:9b334a45a8ff	6859	#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /!< ADC2 and ADC4 DMA remap /
bogdanm	0:9b334a45a8ff	6860	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
bogdanm	0:9b334a45a8ff	6861	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
bogdanm	0:9b334a45a8ff	6862	#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /!< Timer 6 / DAC1 CH1 DMA remap /
bogdanm	0:9b334a45a8ff	6863	#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /!< Timer 7 / DAC1 CH2 DMA remap /
bogdanm	0:9b334a45a8ff	6864	#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /!< DAC2 CH1 DMA remap /
bogdanm	0:9b334a45a8ff	6865	#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
bogdanm	0:9b334a45a8ff	6866	#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
bogdanm	0:9b334a45a8ff	6867	#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
bogdanm	0:9b334a45a8ff	6868	#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
bogdanm	0:9b334a45a8ff	6869	#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /!< I2C1 Fast mode plus /
bogdanm	0:9b334a45a8ff	6870	#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /!< I2C2 Fast mode plus /
bogdanm	0:9b334a45a8ff	6871	#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /!< Encoder Mode /
bogdanm	0:9b334a45a8ff	6872	#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /!< Encoder Mode 0 /
bogdanm	0:9b334a45a8ff	6873	#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /!< Encoder Mode 1 /
bogdanm	0:9b334a45a8ff	6874	#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /!< Floating Point Unit Interrupt Enable /
bogdanm	0:9b334a45a8ff	6875	#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /!< Floating Point Unit Interrupt Enable 0 /
bogdanm	0:9b334a45a8ff	6876	#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /!< Floating Point Unit Interrupt Enable 1 /
bogdanm	0:9b334a45a8ff	6877	#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /!< Floating Point Unit Interrupt Enable 2 /
bogdanm	0:9b334a45a8ff	6878	#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /!< Floating Point Unit Interrupt Enable 3 /
bogdanm	0:9b334a45a8ff	6879	#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /!< Floating Point Unit Interrupt Enable 4 /
bogdanm	0:9b334a45a8ff	6880	#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /!< Floating Point Unit Interrupt Enable 5 /
bogdanm	0:9b334a45a8ff	6881	#define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /!< Old define maintained for legacy purpose /
bogdanm	0:9b334a45a8ff	6882	#define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /!< Old define maintained for legacy purpose /
bogdanm	0:9b334a45a8ff	6883	#define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /!< Old define maintained for legacy purpose /
bogdanm	0:9b334a45a8ff	6884	/*************** Bit definition for SYSCFG_RCR register *****************/
bogdanm	0:9b334a45a8ff	6885	#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /!< ICODE SRAM Write protection page 0 /
bogdanm	0:9b334a45a8ff	6886	#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /!< ICODE SRAM Write protection page 1 /
bogdanm	0:9b334a45a8ff	6887	#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /!< ICODE SRAM Write protection page 2 /
bogdanm	0:9b334a45a8ff	6888	#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /!< ICODE SRAM Write protection page 3 /
bogdanm	0:9b334a45a8ff	6889	#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /!< ICODE SRAM Write protection page 4 /
bogdanm	0:9b334a45a8ff	6890	#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /!< ICODE SRAM Write protection page 5 /
bogdanm	0:9b334a45a8ff	6891	#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /!< ICODE SRAM Write protection page 6 /
bogdanm	0:9b334a45a8ff	6892	#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /!< ICODE SRAM Write protection page 7 /
bogdanm	0:9b334a45a8ff	6893
bogdanm	0:9b334a45a8ff	6894	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
bogdanm	0:9b334a45a8ff	6895	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
bogdanm	0:9b334a45a8ff	6896	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
bogdanm	0:9b334a45a8ff	6897	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
bogdanm	0:9b334a45a8ff	6898	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
bogdanm	0:9b334a45a8ff	6899
bogdanm	0:9b334a45a8ff	6900	/**
bogdanm	0:9b334a45a8ff	6901	* @brief EXTI0 configuration
bogdanm	0:9b334a45a8ff	6902	*/
bogdanm	0:9b334a45a8ff	6903	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
bogdanm	0:9b334a45a8ff	6904	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
bogdanm	0:9b334a45a8ff	6905	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
bogdanm	0:9b334a45a8ff	6906	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
bogdanm	0:9b334a45a8ff	6907	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
bogdanm	0:9b334a45a8ff	6908	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
bogdanm	0:9b334a45a8ff	6909
bogdanm	0:9b334a45a8ff	6910	/**
bogdanm	0:9b334a45a8ff	6911	* @brief EXTI1 configuration
bogdanm	0:9b334a45a8ff	6912	*/
bogdanm	0:9b334a45a8ff	6913	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
bogdanm	0:9b334a45a8ff	6914	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
bogdanm	0:9b334a45a8ff	6915	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
bogdanm	0:9b334a45a8ff	6916	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
bogdanm	0:9b334a45a8ff	6917	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
bogdanm	0:9b334a45a8ff	6918	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
bogdanm	0:9b334a45a8ff	6919
bogdanm	0:9b334a45a8ff	6920	/**
bogdanm	0:9b334a45a8ff	6921	* @brief EXTI2 configuration
bogdanm	0:9b334a45a8ff	6922	*/
bogdanm	0:9b334a45a8ff	6923	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
bogdanm	0:9b334a45a8ff	6924	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
bogdanm	0:9b334a45a8ff	6925	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
bogdanm	0:9b334a45a8ff	6926	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
bogdanm	0:9b334a45a8ff	6927	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
bogdanm	0:9b334a45a8ff	6928	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
bogdanm	0:9b334a45a8ff	6929
bogdanm	0:9b334a45a8ff	6930	/**
bogdanm	0:9b334a45a8ff	6931	* @brief EXTI3 configuration
bogdanm	0:9b334a45a8ff	6932	*/
bogdanm	0:9b334a45a8ff	6933	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
bogdanm	0:9b334a45a8ff	6934	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
bogdanm	0:9b334a45a8ff	6935	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
bogdanm	0:9b334a45a8ff	6936	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
bogdanm	0:9b334a45a8ff	6937	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
bogdanm	0:9b334a45a8ff	6938
bogdanm	0:9b334a45a8ff	6939	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
bogdanm	0:9b334a45a8ff	6940	#define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
bogdanm	0:9b334a45a8ff	6941	#define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
bogdanm	0:9b334a45a8ff	6942	#define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
bogdanm	0:9b334a45a8ff	6943	#define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
bogdanm	0:9b334a45a8ff	6944
bogdanm	0:9b334a45a8ff	6945	/**
bogdanm	0:9b334a45a8ff	6946	* @brief EXTI4 configuration
bogdanm	0:9b334a45a8ff	6947	*/
bogdanm	0:9b334a45a8ff	6948	#define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
bogdanm	0:9b334a45a8ff	6949	#define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
bogdanm	0:9b334a45a8ff	6950	#define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
bogdanm	0:9b334a45a8ff	6951	#define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
bogdanm	0:9b334a45a8ff	6952	#define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
bogdanm	0:9b334a45a8ff	6953	#define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
bogdanm	0:9b334a45a8ff	6954
bogdanm	0:9b334a45a8ff	6955	/**
bogdanm	0:9b334a45a8ff	6956	* @brief EXTI5 configuration
bogdanm	0:9b334a45a8ff	6957	*/
bogdanm	0:9b334a45a8ff	6958	#define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
bogdanm	0:9b334a45a8ff	6959	#define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
bogdanm	0:9b334a45a8ff	6960	#define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
bogdanm	0:9b334a45a8ff	6961	#define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
bogdanm	0:9b334a45a8ff	6962	#define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
bogdanm	0:9b334a45a8ff	6963	#define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
bogdanm	0:9b334a45a8ff	6964
bogdanm	0:9b334a45a8ff	6965	/**
bogdanm	0:9b334a45a8ff	6966	* @brief EXTI6 configuration
bogdanm	0:9b334a45a8ff	6967	*/
bogdanm	0:9b334a45a8ff	6968	#define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
bogdanm	0:9b334a45a8ff	6969	#define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
bogdanm	0:9b334a45a8ff	6970	#define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
bogdanm	0:9b334a45a8ff	6971	#define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
bogdanm	0:9b334a45a8ff	6972	#define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
bogdanm	0:9b334a45a8ff	6973	#define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
bogdanm	0:9b334a45a8ff	6974
bogdanm	0:9b334a45a8ff	6975	/**
bogdanm	0:9b334a45a8ff	6976	* @brief EXTI7 configuration
bogdanm	0:9b334a45a8ff	6977	*/
bogdanm	0:9b334a45a8ff	6978	#define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
bogdanm	0:9b334a45a8ff	6979	#define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
bogdanm	0:9b334a45a8ff	6980	#define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
bogdanm	0:9b334a45a8ff	6981	#define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
bogdanm	0:9b334a45a8ff	6982	#define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
bogdanm	0:9b334a45a8ff	6983
bogdanm	0:9b334a45a8ff	6984	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
bogdanm	0:9b334a45a8ff	6985	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
bogdanm	0:9b334a45a8ff	6986	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
bogdanm	0:9b334a45a8ff	6987	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
bogdanm	0:9b334a45a8ff	6988	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
bogdanm	0:9b334a45a8ff	6989
bogdanm	0:9b334a45a8ff	6990	/**
bogdanm	0:9b334a45a8ff	6991	* @brief EXTI8 configuration
bogdanm	0:9b334a45a8ff	6992	*/
bogdanm	0:9b334a45a8ff	6993	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
bogdanm	0:9b334a45a8ff	6994	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
bogdanm	0:9b334a45a8ff	6995	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
bogdanm	0:9b334a45a8ff	6996	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
bogdanm	0:9b334a45a8ff	6997	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
bogdanm	0:9b334a45a8ff	6998
bogdanm	0:9b334a45a8ff	6999	/**
bogdanm	0:9b334a45a8ff	7000	* @brief EXTI9 configuration
bogdanm	0:9b334a45a8ff	7001	*/
bogdanm	0:9b334a45a8ff	7002	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
bogdanm	0:9b334a45a8ff	7003	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
bogdanm	0:9b334a45a8ff	7004	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
bogdanm	0:9b334a45a8ff	7005	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
bogdanm	0:9b334a45a8ff	7006	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
bogdanm	0:9b334a45a8ff	7007	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
bogdanm	0:9b334a45a8ff	7008
bogdanm	0:9b334a45a8ff	7009	/**
bogdanm	0:9b334a45a8ff	7010	* @brief EXTI10 configuration
bogdanm	0:9b334a45a8ff	7011	*/
bogdanm	0:9b334a45a8ff	7012	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
bogdanm	0:9b334a45a8ff	7013	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
bogdanm	0:9b334a45a8ff	7014	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
bogdanm	0:9b334a45a8ff	7015	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
bogdanm	0:9b334a45a8ff	7016	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PE[10] pin /
bogdanm	0:9b334a45a8ff	7017	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
bogdanm	0:9b334a45a8ff	7018
bogdanm	0:9b334a45a8ff	7019	/**
bogdanm	0:9b334a45a8ff	7020	* @brief EXTI11 configuration
bogdanm	0:9b334a45a8ff	7021	*/
bogdanm	0:9b334a45a8ff	7022	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
bogdanm	0:9b334a45a8ff	7023	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
bogdanm	0:9b334a45a8ff	7024	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
bogdanm	0:9b334a45a8ff	7025	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
bogdanm	0:9b334a45a8ff	7026	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
bogdanm	0:9b334a45a8ff	7027
bogdanm	0:9b334a45a8ff	7028	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
bogdanm	0:9b334a45a8ff	7029	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
bogdanm	0:9b334a45a8ff	7030	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
bogdanm	0:9b334a45a8ff	7031	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
bogdanm	0:9b334a45a8ff	7032	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
bogdanm	0:9b334a45a8ff	7033
bogdanm	0:9b334a45a8ff	7034	/**
bogdanm	0:9b334a45a8ff	7035	* @brief EXTI12 configuration
bogdanm	0:9b334a45a8ff	7036	*/
bogdanm	0:9b334a45a8ff	7037	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
bogdanm	0:9b334a45a8ff	7038	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
bogdanm	0:9b334a45a8ff	7039	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
bogdanm	0:9b334a45a8ff	7040	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
bogdanm	0:9b334a45a8ff	7041	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
bogdanm	0:9b334a45a8ff	7042
bogdanm	0:9b334a45a8ff	7043	/**
bogdanm	0:9b334a45a8ff	7044	* @brief EXTI13 configuration
bogdanm	0:9b334a45a8ff	7045	*/
bogdanm	0:9b334a45a8ff	7046	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
bogdanm	0:9b334a45a8ff	7047	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
bogdanm	0:9b334a45a8ff	7048	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
bogdanm	0:9b334a45a8ff	7049	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
bogdanm	0:9b334a45a8ff	7050	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
bogdanm	0:9b334a45a8ff	7051
bogdanm	0:9b334a45a8ff	7052	/**
bogdanm	0:9b334a45a8ff	7053	* @brief EXTI14 configuration
bogdanm	0:9b334a45a8ff	7054	*/
bogdanm	0:9b334a45a8ff	7055	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
bogdanm	0:9b334a45a8ff	7056	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
bogdanm	0:9b334a45a8ff	7057	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
bogdanm	0:9b334a45a8ff	7058	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
bogdanm	0:9b334a45a8ff	7059	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
bogdanm	0:9b334a45a8ff	7060
bogdanm	0:9b334a45a8ff	7061	/**
bogdanm	0:9b334a45a8ff	7062	* @brief EXTI15 configuration
bogdanm	0:9b334a45a8ff	7063	*/
bogdanm	0:9b334a45a8ff	7064	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
bogdanm	0:9b334a45a8ff	7065	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
bogdanm	0:9b334a45a8ff	7066	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
bogdanm	0:9b334a45a8ff	7067	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
bogdanm	0:9b334a45a8ff	7068	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
bogdanm	0:9b334a45a8ff	7069
bogdanm	0:9b334a45a8ff	7070	/*************** Bit definition for SYSCFG_CFGR2 register ***************/
bogdanm	0:9b334a45a8ff	7071	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
bogdanm	0:9b334a45a8ff	7072	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 /
bogdanm	0:9b334a45a8ff	7073	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 /
bogdanm	0:9b334a45a8ff	7074	#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /!< Disables the address parity check on RAM /
bogdanm	0:9b334a45a8ff	7075	#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /!< SRAM Parity error flag /
bogdanm	0:9b334a45a8ff	7076
bogdanm	0:9b334a45a8ff	7077	/*************** Bit definition for SYSCFG_CFGR3 register ***************/
bogdanm	0:9b334a45a8ff	7078	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /!< SPI1 RX DMA remap /
bogdanm	0:9b334a45a8ff	7079	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /!< SPI1 RX DMA remap bit 0 /
bogdanm	0:9b334a45a8ff	7080	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /!< SPI1 RX DMA remap bit 1 /
bogdanm	0:9b334a45a8ff	7081	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /!< SPI1 TX DMA remap /
bogdanm	0:9b334a45a8ff	7082	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /!< SPI1 TX DMA remap bit 0 /
bogdanm	0:9b334a45a8ff	7083	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /!< SPI1 TX DMA remap bit 1 /
bogdanm	0:9b334a45a8ff	7084	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /!< I2C1 RX DMA remap /
bogdanm	0:9b334a45a8ff	7085	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /!< I2C1 RX DMA remap bit 0 /
bogdanm	0:9b334a45a8ff	7086	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /!< I2C1 RX DMA remap bit 1 /
bogdanm	0:9b334a45a8ff	7087	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /!< I2C1 RX DMA remap /
bogdanm	0:9b334a45a8ff	7088	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /!< I2C1 TX DMA remap bit 0 /
bogdanm	0:9b334a45a8ff	7089	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /!< I2C1 TX DMA remap bit 1 /
bogdanm	0:9b334a45a8ff	7090	#define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /!< ADC2 DMA remap /
bogdanm	0:9b334a45a8ff	7091	#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /!< ADC2 DMA remap bit 0 /
bogdanm	0:9b334a45a8ff	7092	#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /!< ADC2 DMA remap bit 1 /
bogdanm	0:9b334a45a8ff	7093	#define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /!< DAC1 TRG3 remap /
bogdanm	0:9b334a45a8ff	7094	#define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /!< DAC1 TRG5 remap /
bogdanm	0:9b334a45a8ff	7095
bogdanm	0:9b334a45a8ff	7096	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7097	/* */
bogdanm	0:9b334a45a8ff	7098	/* TIM */
bogdanm	0:9b334a45a8ff	7099	/* */
bogdanm	0:9b334a45a8ff	7100	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7101	/***************** Bit definition for TIM_CR1 register ******************/
bogdanm	0:9b334a45a8ff	7102	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
bogdanm	0:9b334a45a8ff	7103	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
bogdanm	0:9b334a45a8ff	7104	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
bogdanm	0:9b334a45a8ff	7105	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
bogdanm	0:9b334a45a8ff	7106	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
bogdanm	0:9b334a45a8ff	7107
bogdanm	0:9b334a45a8ff	7108	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	0:9b334a45a8ff	7109	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7110	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7111
bogdanm	0:9b334a45a8ff	7112	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
bogdanm	0:9b334a45a8ff	7113
bogdanm	0:9b334a45a8ff	7114	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
bogdanm	0:9b334a45a8ff	7115	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7116	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7117
bogdanm	0:9b334a45a8ff	7118	#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /!<Update interrupt flag remap /
bogdanm	0:9b334a45a8ff	7119
bogdanm	0:9b334a45a8ff	7120	/***************** Bit definition for TIM_CR2 register ******************/
bogdanm	0:9b334a45a8ff	7121	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
bogdanm	0:9b334a45a8ff	7122	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
bogdanm	0:9b334a45a8ff	7123	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
bogdanm	0:9b334a45a8ff	7124
bogdanm	0:9b334a45a8ff	7125	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	7126	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7127	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7128	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7129
bogdanm	0:9b334a45a8ff	7130	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
bogdanm	0:9b334a45a8ff	7131	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
bogdanm	0:9b334a45a8ff	7132	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
bogdanm	0:9b334a45a8ff	7133	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
bogdanm	0:9b334a45a8ff	7134	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
bogdanm	0:9b334a45a8ff	7135	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
bogdanm	0:9b334a45a8ff	7136	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
bogdanm	0:9b334a45a8ff	7137	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	7138	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	7139	#define TIM_CR2_OIS6 ((uint32_t)0x00020000) /!<Output Idle state 4 (OC4 output) /
bogdanm	0:9b334a45a8ff	7140
bogdanm	0:9b334a45a8ff	7141	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	0:9b334a45a8ff	7142	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7143	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7144	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7145	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7146
bogdanm	0:9b334a45a8ff	7147	/***************** Bit definition for TIM_SMCR register *****************/
bogdanm	0:9b334a45a8ff	7148	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	0:9b334a45a8ff	7149	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7150	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7151	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7152	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7153
bogdanm	0:9b334a45a8ff	7154	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
bogdanm	0:9b334a45a8ff	7155
bogdanm	0:9b334a45a8ff	7156	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	0:9b334a45a8ff	7157	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7158	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7159	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7160
bogdanm	0:9b334a45a8ff	7161	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
bogdanm	0:9b334a45a8ff	7162
bogdanm	0:9b334a45a8ff	7163	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	0:9b334a45a8ff	7164	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7165	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7166	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7167	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7168
bogdanm	0:9b334a45a8ff	7169	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	0:9b334a45a8ff	7170	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7171	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7172
bogdanm	0:9b334a45a8ff	7173	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
bogdanm	0:9b334a45a8ff	7174	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
bogdanm	0:9b334a45a8ff	7175
bogdanm	0:9b334a45a8ff	7176	/***************** Bit definition for TIM_DIER register *****************/
bogdanm	0:9b334a45a8ff	7177	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
bogdanm	0:9b334a45a8ff	7178	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	7179	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	7180	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	7181	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	7182	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!<COM interrupt enable /
bogdanm	0:9b334a45a8ff	7183	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
bogdanm	0:9b334a45a8ff	7184	#define TIM_DIER_BIE ((uint16_t)0x0080) /!<Break interrupt enable /
bogdanm	0:9b334a45a8ff	7185	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
bogdanm	0:9b334a45a8ff	7186	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	7187	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	7188	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	7189	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	7190	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
bogdanm	0:9b334a45a8ff	7191	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
bogdanm	0:9b334a45a8ff	7192
bogdanm	0:9b334a45a8ff	7193	/****************** Bit definition for TIM_SR register ******************/
bogdanm	0:9b334a45a8ff	7194	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
bogdanm	0:9b334a45a8ff	7195	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	0:9b334a45a8ff	7196	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	0:9b334a45a8ff	7197	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	0:9b334a45a8ff	7198	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	0:9b334a45a8ff	7199	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
bogdanm	0:9b334a45a8ff	7200	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
bogdanm	0:9b334a45a8ff	7201	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
bogdanm	0:9b334a45a8ff	7202	#define TIM_SR_B2IF ((uint32_t)0x00000100) /!<Break2 interrupt Flag /
bogdanm	0:9b334a45a8ff	7203	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Over capture Flag /
bogdanm	0:9b334a45a8ff	7204	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Over capture Flag /
bogdanm	0:9b334a45a8ff	7205	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Over capture Flag /
bogdanm	0:9b334a45a8ff	7206	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Over capture Flag /
bogdanm	0:9b334a45a8ff	7207	#define TIM_SR_CC5IF ((uint32_t)0x00010000) /!<Capture/Compare 5 interrupt Flag /
bogdanm	0:9b334a45a8ff	7208	#define TIM_SR_CC6IF ((uint32_t)0x00020000) /!<Capture/Compare 6 interrupt Flag /
bogdanm	0:9b334a45a8ff	7209
bogdanm	0:9b334a45a8ff	7210
bogdanm	0:9b334a45a8ff	7211	/***************** Bit definition for TIM_EGR register ******************/
bogdanm	0:9b334a45a8ff	7212	#define TIM_EGR_UG ((uint16_t)0x0001) /!<Update Generation /
bogdanm	0:9b334a45a8ff	7213	#define TIM_EGR_CC1G ((uint16_t)0x0002) /!<Capture/Compare 1 Generation /
bogdanm	0:9b334a45a8ff	7214	#define TIM_EGR_CC2G ((uint16_t)0x0004) /!<Capture/Compare 2 Generation /
bogdanm	0:9b334a45a8ff	7215	#define TIM_EGR_CC3G ((uint16_t)0x0008) /!<Capture/Compare 3 Generation /
bogdanm	0:9b334a45a8ff	7216	#define TIM_EGR_CC4G ((uint16_t)0x0010) /!<Capture/Compare 4 Generation /
bogdanm	0:9b334a45a8ff	7217	#define TIM_EGR_COMG ((uint16_t)0x0020) /!<Capture/Compare Control Update Generation /
bogdanm	0:9b334a45a8ff	7218	#define TIM_EGR_TG ((uint16_t)0x0040) /!<Trigger Generation /
bogdanm	0:9b334a45a8ff	7219	#define TIM_EGR_BG ((uint16_t)0x0080) /!<Break Generation /
bogdanm	0:9b334a45a8ff	7220	#define TIM_EGR_B2G ((uint16_t)0x0100) /!<Break Generation /
bogdanm	0:9b334a45a8ff	7221
bogdanm	0:9b334a45a8ff	7222
bogdanm	0:9b334a45a8ff	7223	/**************** Bit definition for TIM_CCMR1 register *****************/
bogdanm	0:9b334a45a8ff	7224	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	0:9b334a45a8ff	7225	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7226	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7227
bogdanm	0:9b334a45a8ff	7228	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
bogdanm	0:9b334a45a8ff	7229	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
bogdanm	0:9b334a45a8ff	7230
bogdanm	0:9b334a45a8ff	7231	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	0:9b334a45a8ff	7232	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7233	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7234	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7235	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7236
bogdanm	0:9b334a45a8ff	7237	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
bogdanm	0:9b334a45a8ff	7238
bogdanm	0:9b334a45a8ff	7239	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	0:9b334a45a8ff	7240	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7241	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7242
bogdanm	0:9b334a45a8ff	7243	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
bogdanm	0:9b334a45a8ff	7244	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
bogdanm	0:9b334a45a8ff	7245
bogdanm	0:9b334a45a8ff	7246	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	0:9b334a45a8ff	7247	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7248	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7249	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7250	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7251
bogdanm	0:9b334a45a8ff	7252	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
bogdanm	0:9b334a45a8ff	7253
bogdanm	0:9b334a45a8ff	7254	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	7255
bogdanm	0:9b334a45a8ff	7256	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	0:9b334a45a8ff	7257	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7258	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7259
bogdanm	0:9b334a45a8ff	7260	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	0:9b334a45a8ff	7261	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7262	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7263	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7264	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7265
bogdanm	0:9b334a45a8ff	7266	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	0:9b334a45a8ff	7267	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7268	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7269
bogdanm	0:9b334a45a8ff	7270	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	0:9b334a45a8ff	7271	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7272	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7273	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7274	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7275
bogdanm	0:9b334a45a8ff	7276	/**************** Bit definition for TIM_CCMR2 register *****************/
bogdanm	0:9b334a45a8ff	7277	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	0:9b334a45a8ff	7278	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7279	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7280
bogdanm	0:9b334a45a8ff	7281	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
bogdanm	0:9b334a45a8ff	7282	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
bogdanm	0:9b334a45a8ff	7283
bogdanm	0:9b334a45a8ff	7284	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	0:9b334a45a8ff	7285	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7286	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7287	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7288	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7289
bogdanm	0:9b334a45a8ff	7290	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
bogdanm	0:9b334a45a8ff	7291
bogdanm	0:9b334a45a8ff	7292	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	0:9b334a45a8ff	7293	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7294	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7295
bogdanm	0:9b334a45a8ff	7296	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	0:9b334a45a8ff	7297	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	0:9b334a45a8ff	7298
bogdanm	0:9b334a45a8ff	7299	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	0:9b334a45a8ff	7300	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7301	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7302	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7303	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7304
bogdanm	0:9b334a45a8ff	7305	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	0:9b334a45a8ff	7306
bogdanm	0:9b334a45a8ff	7307	/----------------------------------------------------------------------------/
bogdanm	0:9b334a45a8ff	7308
bogdanm	0:9b334a45a8ff	7309	#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	0:9b334a45a8ff	7310	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7311	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7312
bogdanm	0:9b334a45a8ff	7313	#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	0:9b334a45a8ff	7314	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7315	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7316	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7317	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7318
bogdanm	0:9b334a45a8ff	7319	#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	0:9b334a45a8ff	7320	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7321	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7322
bogdanm	0:9b334a45a8ff	7323	#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	0:9b334a45a8ff	7324	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7325	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7326	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7327	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7328
bogdanm	0:9b334a45a8ff	7329	/***************** Bit definition for TIM_CCER register *****************/
bogdanm	0:9b334a45a8ff	7330	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
bogdanm	0:9b334a45a8ff	7331	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
bogdanm	0:9b334a45a8ff	7332	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	0:9b334a45a8ff	7333	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7334	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
bogdanm	0:9b334a45a8ff	7335	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
bogdanm	0:9b334a45a8ff	7336	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	0:9b334a45a8ff	7337	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7338	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
bogdanm	0:9b334a45a8ff	7339	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
bogdanm	0:9b334a45a8ff	7340	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	0:9b334a45a8ff	7341	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7342	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
bogdanm	0:9b334a45a8ff	7343	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
bogdanm	0:9b334a45a8ff	7344	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	0:9b334a45a8ff	7345	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
bogdanm	0:9b334a45a8ff	7346	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
bogdanm	0:9b334a45a8ff	7347	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
bogdanm	0:9b334a45a8ff	7348	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
bogdanm	0:9b334a45a8ff	7349	/***************** Bit definition for TIM_CNT register ******************/
bogdanm	0:9b334a45a8ff	7350	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	0:9b334a45a8ff	7351	#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /!<Update interrupt flag copy /
bogdanm	0:9b334a45a8ff	7352	/***************** Bit definition for TIM_PSC register ******************/
bogdanm	0:9b334a45a8ff	7353	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
bogdanm	0:9b334a45a8ff	7354
bogdanm	0:9b334a45a8ff	7355	/***************** Bit definition for TIM_ARR register ******************/
bogdanm	0:9b334a45a8ff	7356	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
bogdanm	0:9b334a45a8ff	7357
bogdanm	0:9b334a45a8ff	7358	/***************** Bit definition for TIM_RCR register ******************/
bogdanm	0:9b334a45a8ff	7359	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
bogdanm	0:9b334a45a8ff	7360
bogdanm	0:9b334a45a8ff	7361	/***************** Bit definition for TIM_CCR1 register *****************/
bogdanm	0:9b334a45a8ff	7362	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
bogdanm	0:9b334a45a8ff	7363
bogdanm	0:9b334a45a8ff	7364	/***************** Bit definition for TIM_CCR2 register *****************/
bogdanm	0:9b334a45a8ff	7365	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
bogdanm	0:9b334a45a8ff	7366
bogdanm	0:9b334a45a8ff	7367	/***************** Bit definition for TIM_CCR3 register *****************/
bogdanm	0:9b334a45a8ff	7368	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
bogdanm	0:9b334a45a8ff	7369
bogdanm	0:9b334a45a8ff	7370	/***************** Bit definition for TIM_CCR4 register *****************/
bogdanm	0:9b334a45a8ff	7371	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
bogdanm	0:9b334a45a8ff	7372
bogdanm	0:9b334a45a8ff	7373	/***************** Bit definition for TIM_CCR5 register *****************/
bogdanm	0:9b334a45a8ff	7374	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
bogdanm	0:9b334a45a8ff	7375	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
bogdanm	0:9b334a45a8ff	7376	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
bogdanm	0:9b334a45a8ff	7377	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
bogdanm	0:9b334a45a8ff	7378
bogdanm	0:9b334a45a8ff	7379	/***************** Bit definition for TIM_CCR6 register *****************/
bogdanm	0:9b334a45a8ff	7380	#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /!<Capture/Compare 6 Value /
bogdanm	0:9b334a45a8ff	7381
bogdanm	0:9b334a45a8ff	7382	/***************** Bit definition for TIM_BDTR register *****************/
bogdanm	0:9b334a45a8ff	7383	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	0:9b334a45a8ff	7384	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7385	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7386	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7387	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7388	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7389	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	7390	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	7391	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	0:9b334a45a8ff	7392
bogdanm	0:9b334a45a8ff	7393	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	0:9b334a45a8ff	7394	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7395	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7396
bogdanm	0:9b334a45a8ff	7397	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
bogdanm	0:9b334a45a8ff	7398	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
bogdanm	0:9b334a45a8ff	7399	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable for Break1 /
bogdanm	0:9b334a45a8ff	7400	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity for Break1 /
bogdanm	0:9b334a45a8ff	7401	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
bogdanm	0:9b334a45a8ff	7402	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
bogdanm	0:9b334a45a8ff	7403
bogdanm	0:9b334a45a8ff	7404	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break1 /
bogdanm	0:9b334a45a8ff	7405	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break2 /
bogdanm	0:9b334a45a8ff	7406
bogdanm	0:9b334a45a8ff	7407	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break2 /
bogdanm	0:9b334a45a8ff	7408	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break2 /
bogdanm	0:9b334a45a8ff	7409
bogdanm	0:9b334a45a8ff	7410	/***************** Bit definition for TIM_DCR register ******************/
bogdanm	0:9b334a45a8ff	7411	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	0:9b334a45a8ff	7412	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7413	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7414	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7415	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7416	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7417
bogdanm	0:9b334a45a8ff	7418	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	0:9b334a45a8ff	7419	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7420	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7421	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7422	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7423	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7424
bogdanm	0:9b334a45a8ff	7425	/***************** Bit definition for TIM_DMAR register *****************/
bogdanm	0:9b334a45a8ff	7426	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
bogdanm	0:9b334a45a8ff	7427
bogdanm	0:9b334a45a8ff	7428	/***************** Bit definition for TIM16_OR register *******************/
bogdanm	0:9b334a45a8ff	7429	#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) /
bogdanm	0:9b334a45a8ff	7430	#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7431	#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7432
bogdanm	0:9b334a45a8ff	7433	/***************** Bit definition for TIM1_OR register *******************/
bogdanm	0:9b334a45a8ff	7434	#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /!<ETR_RMP[3:0] bits (TIM1 ETR remap) /
bogdanm	0:9b334a45a8ff	7435	#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7436	#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7437	#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7438	#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7439
bogdanm	0:9b334a45a8ff	7440	/***************** Bit definition for TIM8_OR register *******************/
bogdanm	0:9b334a45a8ff	7441	#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /!<ETR_RMP[3:0] bits (TIM8 ETR remap) /
bogdanm	0:9b334a45a8ff	7442	#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7443	#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7444	#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7445	#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7446
bogdanm	0:9b334a45a8ff	7447	/**************** Bit definition for TIM_CCMR3 register *****************/
bogdanm	0:9b334a45a8ff	7448	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
bogdanm	0:9b334a45a8ff	7449	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
bogdanm	0:9b334a45a8ff	7450
bogdanm	0:9b334a45a8ff	7451	#define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /!<OC5M[2:0] bits (Output Compare 5 Mode) /
bogdanm	0:9b334a45a8ff	7452	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7453	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7454	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7455	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7456
bogdanm	0:9b334a45a8ff	7457	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
bogdanm	0:9b334a45a8ff	7458
bogdanm	0:9b334a45a8ff	7459	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	0:9b334a45a8ff	7460	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	0:9b334a45a8ff	7461
bogdanm	0:9b334a45a8ff	7462	#define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	0:9b334a45a8ff	7463	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7464	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7465	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7466	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7467
bogdanm	0:9b334a45a8ff	7468	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	0:9b334a45a8ff	7469
bogdanm	0:9b334a45a8ff	7470	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7471	/* */
bogdanm	0:9b334a45a8ff	7472	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm	0:9b334a45a8ff	7473	/* */
bogdanm	0:9b334a45a8ff	7474	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7475	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	0:9b334a45a8ff	7476	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
bogdanm	0:9b334a45a8ff	7477	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
bogdanm	0:9b334a45a8ff	7478	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
bogdanm	0:9b334a45a8ff	7479	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
bogdanm	0:9b334a45a8ff	7480	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
bogdanm	0:9b334a45a8ff	7481	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
bogdanm	0:9b334a45a8ff	7482	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
bogdanm	0:9b334a45a8ff	7483	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
bogdanm	0:9b334a45a8ff	7484	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
bogdanm	0:9b334a45a8ff	7485	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
bogdanm	0:9b334a45a8ff	7486	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
bogdanm	0:9b334a45a8ff	7487	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
bogdanm	0:9b334a45a8ff	7488	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
bogdanm	0:9b334a45a8ff	7489	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
bogdanm	0:9b334a45a8ff	7490	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
bogdanm	0:9b334a45a8ff	7491	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
bogdanm	0:9b334a45a8ff	7492	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
bogdanm	0:9b334a45a8ff	7493	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7494	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7495	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	7496	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	7497	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	7498	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
bogdanm	0:9b334a45a8ff	7499	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7500	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7501	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	7502	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
bogdanm	0:9b334a45a8ff	7503	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
bogdanm	0:9b334a45a8ff	7504	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
bogdanm	0:9b334a45a8ff	7505	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
bogdanm	0:9b334a45a8ff	7506
bogdanm	0:9b334a45a8ff	7507	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	0:9b334a45a8ff	7508	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
bogdanm	0:9b334a45a8ff	7509	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
bogdanm	0:9b334a45a8ff	7510	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
bogdanm	0:9b334a45a8ff	7511	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
bogdanm	0:9b334a45a8ff	7512	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
bogdanm	0:9b334a45a8ff	7513	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
bogdanm	0:9b334a45a8ff	7514	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
bogdanm	0:9b334a45a8ff	7515	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
bogdanm	0:9b334a45a8ff	7516	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7517	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7518	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
bogdanm	0:9b334a45a8ff	7519	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
bogdanm	0:9b334a45a8ff	7520	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
bogdanm	0:9b334a45a8ff	7521	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
bogdanm	0:9b334a45a8ff	7522	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
bogdanm	0:9b334a45a8ff	7523	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
bogdanm	0:9b334a45a8ff	7524	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
bogdanm	0:9b334a45a8ff	7525	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
bogdanm	0:9b334a45a8ff	7526	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7527	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7528	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
bogdanm	0:9b334a45a8ff	7529	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
bogdanm	0:9b334a45a8ff	7530
bogdanm	0:9b334a45a8ff	7531	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	0:9b334a45a8ff	7532	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
bogdanm	0:9b334a45a8ff	7533	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
bogdanm	0:9b334a45a8ff	7534	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
bogdanm	0:9b334a45a8ff	7535	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
bogdanm	0:9b334a45a8ff	7536	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
bogdanm	0:9b334a45a8ff	7537	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
bogdanm	0:9b334a45a8ff	7538	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
bogdanm	0:9b334a45a8ff	7539	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
bogdanm	0:9b334a45a8ff	7540	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
bogdanm	0:9b334a45a8ff	7541	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
bogdanm	0:9b334a45a8ff	7542	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
bogdanm	0:9b334a45a8ff	7543	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
bogdanm	0:9b334a45a8ff	7544	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
bogdanm	0:9b334a45a8ff	7545	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
bogdanm	0:9b334a45a8ff	7546	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
bogdanm	0:9b334a45a8ff	7547	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
bogdanm	0:9b334a45a8ff	7548	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
bogdanm	0:9b334a45a8ff	7549	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7550	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7551	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
bogdanm	0:9b334a45a8ff	7552	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
bogdanm	0:9b334a45a8ff	7553	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	0:9b334a45a8ff	7554	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	0:9b334a45a8ff	7555	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
bogdanm	0:9b334a45a8ff	7556
bogdanm	0:9b334a45a8ff	7557	/**************** Bit definition for USART_BRR register *****************/
bogdanm	0:9b334a45a8ff	7558	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
bogdanm	0:9b334a45a8ff	7559	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
bogdanm	0:9b334a45a8ff	7560
bogdanm	0:9b334a45a8ff	7561	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	0:9b334a45a8ff	7562	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
bogdanm	0:9b334a45a8ff	7563	#define USART_GTPR_GT ((uint16_t)0xFF00) /!< GT[7:0] bits (Guard time value) /
bogdanm	0:9b334a45a8ff	7564
bogdanm	0:9b334a45a8ff	7565
bogdanm	0:9b334a45a8ff	7566	/***************** Bit definition for USART_RTOR register ***************/
bogdanm	0:9b334a45a8ff	7567	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
bogdanm	0:9b334a45a8ff	7568	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
bogdanm	0:9b334a45a8ff	7569
bogdanm	0:9b334a45a8ff	7570	/***************** Bit definition for USART_RQR register ****************/
bogdanm	0:9b334a45a8ff	7571	#define USART_RQR_ABRRQ ((uint16_t)0x0001) /!< Auto-Baud Rate Request /
bogdanm	0:9b334a45a8ff	7572	#define USART_RQR_SBKRQ ((uint16_t)0x0002) /!< Send Break Request /
bogdanm	0:9b334a45a8ff	7573	#define USART_RQR_MMRQ ((uint16_t)0x0004) /!< Mute Mode Request /
bogdanm	0:9b334a45a8ff	7574	#define USART_RQR_RXFRQ ((uint16_t)0x0008) /!< Receive Data flush Request /
bogdanm	0:9b334a45a8ff	7575	#define USART_RQR_TXFRQ ((uint16_t)0x0010) /!< Transmit data flush Request /
bogdanm	0:9b334a45a8ff	7576
bogdanm	0:9b334a45a8ff	7577	/***************** Bit definition for USART_ISR register ****************/
bogdanm	0:9b334a45a8ff	7578	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
bogdanm	0:9b334a45a8ff	7579	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
bogdanm	0:9b334a45a8ff	7580	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
bogdanm	0:9b334a45a8ff	7581	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
bogdanm	0:9b334a45a8ff	7582	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
bogdanm	0:9b334a45a8ff	7583	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
bogdanm	0:9b334a45a8ff	7584	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
bogdanm	0:9b334a45a8ff	7585	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
bogdanm	0:9b334a45a8ff	7586	#define USART_ISR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
bogdanm	0:9b334a45a8ff	7587	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
bogdanm	0:9b334a45a8ff	7588	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
bogdanm	0:9b334a45a8ff	7589	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
bogdanm	0:9b334a45a8ff	7590	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
bogdanm	0:9b334a45a8ff	7591	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
bogdanm	0:9b334a45a8ff	7592	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
bogdanm	0:9b334a45a8ff	7593	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
bogdanm	0:9b334a45a8ff	7594	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
bogdanm	0:9b334a45a8ff	7595	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
bogdanm	0:9b334a45a8ff	7596	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
bogdanm	0:9b334a45a8ff	7597	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
bogdanm	0:9b334a45a8ff	7598	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	7599	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
bogdanm	0:9b334a45a8ff	7600
bogdanm	0:9b334a45a8ff	7601	/***************** Bit definition for USART_ICR register ****************/
bogdanm	0:9b334a45a8ff	7602	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
bogdanm	0:9b334a45a8ff	7603	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
bogdanm	0:9b334a45a8ff	7604	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
bogdanm	0:9b334a45a8ff	7605	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
bogdanm	0:9b334a45a8ff	7606	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
bogdanm	0:9b334a45a8ff	7607	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
bogdanm	0:9b334a45a8ff	7608	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
bogdanm	0:9b334a45a8ff	7609	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
bogdanm	0:9b334a45a8ff	7610	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
bogdanm	0:9b334a45a8ff	7611	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
bogdanm	0:9b334a45a8ff	7612	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
bogdanm	0:9b334a45a8ff	7613	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
bogdanm	0:9b334a45a8ff	7614
bogdanm	0:9b334a45a8ff	7615	/***************** Bit definition for USART_RDR register ****************/
bogdanm	0:9b334a45a8ff	7616	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
bogdanm	0:9b334a45a8ff	7617
bogdanm	0:9b334a45a8ff	7618	/***************** Bit definition for USART_TDR register ****************/
bogdanm	0:9b334a45a8ff	7619	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
bogdanm	0:9b334a45a8ff	7620
bogdanm	0:9b334a45a8ff	7621	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7622	/* */
bogdanm	0:9b334a45a8ff	7623	/* Window WATCHDOG */
bogdanm	0:9b334a45a8ff	7624	/* */
bogdanm	0:9b334a45a8ff	7625	/******************************************************************************/
bogdanm	0:9b334a45a8ff	7626	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	0:9b334a45a8ff	7627	#define WWDG_CR_T ((uint8_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	0:9b334a45a8ff	7628	#define WWDG_CR_T0 ((uint8_t)0x01) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7629	#define WWDG_CR_T1 ((uint8_t)0x02) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7630	#define WWDG_CR_T2 ((uint8_t)0x04) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7631	#define WWDG_CR_T3 ((uint8_t)0x08) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7632	#define WWDG_CR_T4 ((uint8_t)0x10) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7633	#define WWDG_CR_T5 ((uint8_t)0x20) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	7634	#define WWDG_CR_T6 ((uint8_t)0x40) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	7635
bogdanm	0:9b334a45a8ff	7636	#define WWDG_CR_WDGA ((uint8_t)0x80) /!<Activation bit /
bogdanm	0:9b334a45a8ff	7637
bogdanm	0:9b334a45a8ff	7638	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	0:9b334a45a8ff	7639	#define WWDG_CFR_W ((uint16_t)0x007F) /!<W[6:0] bits (7-bit window value) /
bogdanm	0:9b334a45a8ff	7640	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7641	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7642	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!<Bit 2 /
bogdanm	0:9b334a45a8ff	7643	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!<Bit 3 /
bogdanm	0:9b334a45a8ff	7644	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!<Bit 4 /
bogdanm	0:9b334a45a8ff	7645	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!<Bit 5 /
bogdanm	0:9b334a45a8ff	7646	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!<Bit 6 /
bogdanm	0:9b334a45a8ff	7647
bogdanm	0:9b334a45a8ff	7648	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
bogdanm	0:9b334a45a8ff	7649	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!<Bit 0 /
bogdanm	0:9b334a45a8ff	7650	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!<Bit 1 /
bogdanm	0:9b334a45a8ff	7651
bogdanm	0:9b334a45a8ff	7652	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!<Early Wakeup Interrupt /
bogdanm	0:9b334a45a8ff	7653
bogdanm	0:9b334a45a8ff	7654	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	0:9b334a45a8ff	7655	#define WWDG_SR_EWIF ((uint8_t)0x01) /!<Early Wakeup Interrupt Flag /
bogdanm	0:9b334a45a8ff	7656
bogdanm	0:9b334a45a8ff	7657	/**
bogdanm	0:9b334a45a8ff	7658	* @}
bogdanm	0:9b334a45a8ff	7659	*/
bogdanm	0:9b334a45a8ff	7660
bogdanm	0:9b334a45a8ff	7661	/**
bogdanm	0:9b334a45a8ff	7662	* @}
bogdanm	0:9b334a45a8ff	7663	*/
bogdanm	0:9b334a45a8ff	7664
bogdanm	0:9b334a45a8ff	7665	#ifdef USE_STDPERIPH_DRIVER
bogdanm	0:9b334a45a8ff	7666	#include "stm32f30x_conf.h"
bogdanm	0:9b334a45a8ff	7667	#endif /!< USE_STDPERIPH_DRIVER /
bogdanm	0:9b334a45a8ff	7668
bogdanm	0:9b334a45a8ff	7669	/** @addtogroup Exported_macro
bogdanm	0:9b334a45a8ff	7670	* @{
bogdanm	0:9b334a45a8ff	7671	*/
bogdanm	0:9b334a45a8ff	7672
bogdanm	0:9b334a45a8ff	7673	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
bogdanm	0:9b334a45a8ff	7674
bogdanm	0:9b334a45a8ff	7675	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
bogdanm	0:9b334a45a8ff	7676
bogdanm	0:9b334a45a8ff	7677	#define READ_BIT(REG, BIT) ((REG) & (BIT))
bogdanm	0:9b334a45a8ff	7678
bogdanm	0:9b334a45a8ff	7679	#define CLEAR_REG(REG) ((REG) = (0x0))
bogdanm	0:9b334a45a8ff	7680
bogdanm	0:9b334a45a8ff	7681	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
bogdanm	0:9b334a45a8ff	7682
bogdanm	0:9b334a45a8ff	7683	#define READ_REG(REG) ((REG))
bogdanm	0:9b334a45a8ff	7684
bogdanm	0:9b334a45a8ff	7685	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
bogdanm	0:9b334a45a8ff	7686
bogdanm	0:9b334a45a8ff	7687	/**
bogdanm	0:9b334a45a8ff	7688	* @}
bogdanm	0:9b334a45a8ff	7689	*/
bogdanm	0:9b334a45a8ff	7690
bogdanm	0:9b334a45a8ff	7691	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	7692	}
bogdanm	0:9b334a45a8ff	7693	#endif /* __cplusplus */
bogdanm	0:9b334a45a8ff	7694
bogdanm	0:9b334a45a8ff	7695	#endif /* __STM32F30x_H */
bogdanm	0:9b334a45a8ff	7696
bogdanm	0:9b334a45a8ff	7697	/**
bogdanm	0:9b334a45a8ff	7698	* @}
bogdanm	0:9b334a45a8ff	7699	*/
bogdanm	0:9b334a45a8ff	7700
bogdanm	0:9b334a45a8ff	7701	/**
bogdanm	0:9b334a45a8ff	7702	* @}
bogdanm	0:9b334a45a8ff	7703	*/
bogdanm	0:9b334a45a8ff	7704
bogdanm	0:9b334a45a8ff	7705	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	07 Aug 2016
Imports:	4
Forks:	0
Commits:	145
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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