Sean Wilson / Mbed OS AdiSense1000_V21

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Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register
Enumerations

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register. More...

Enumerations

enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En { ADISENSE_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER = 1 }
enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_SPI_Clock {
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_13MHZ = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_6_5MHZ = 1, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_3_25MHZ = 2, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_1_625MHZ = 3,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_812KHZ = 4, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_406KHZ = 5, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_203KHZ = 6, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_101KHZ = 7,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_50KHZ = 8, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_25KHZ = 9, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_12KHZ = 10, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_6KHZ = 11,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_3KHZ = 12, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_1_5KHZ = 13, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_793HZ = 14, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_396HZ = 15
}
enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_I2C_Clock { ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_100K = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_400K = 1, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 = 2, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 = 3 }
enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_Uart_Baud {
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_115200 = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_57600 = 1, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_38400 = 2, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_19200 = 3,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_9600 = 4, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_4800 = 5, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_2400 = 6, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_1200 = 7
}
enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_SPI_Mode { ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 }
enum  ADI_ADISENSE_CORE_Digital_Sensor_Comms_Uart_Mode {
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N1 = 0, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N2 = 1, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N3 = 2, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E1 = 4,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E2 = 5, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E3 = 6, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O1 = 8, ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O2 = 9,
  ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O3 = 10
}

Detailed Description

Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register.

Enumeration Type Documentation

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 

Default Parameters Used for Digital Sensor Communications.

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 

User Supplied Parameters Used for Digital Sensor Communications.

Definition at line 1921 of file ADISENSE1000_REGISTERS_typedefs.h.

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_I2C_Clock
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_100K 

100kHz SCL

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_400K 

400kHz SCL

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 

Reserved.

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 

Reserved.

Definition at line 1957 of file ADISENSE1000_REGISTERS_typedefs.h.

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_SPI_Clock
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_13MHZ 

13 MHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_6_5MHZ 

6.5 MHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_3_25MHZ 

3.25 MHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_1_625MHZ 

1.625 MHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_812KHZ 

812.5kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_406KHZ 

406.2kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_203KHZ 

203.1kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_101KHZ 

101.5kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_50KHZ 

50.8kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_25KHZ 

25.4kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_12KHZ 

12.7kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_6KHZ 

6.3kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_3KHZ 

3.2kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_1_5KHZ 

1.58kHz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_793HZ 

793Hz

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_396HZ 

396Hz

Definition at line 1932 of file ADISENSE1000_REGISTERS_typedefs.h.

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_SPI_Mode
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 

Clock Polarity = 0 Clock Phase = 0.

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 

Clock Polarity = 0 Clock Phase = 1.

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 

Clock Polarity = 1 Clock Phase = 0.

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 

Clock Polarity = 1 Clock Phase = 1.

Definition at line 1987 of file ADISENSE1000_REGISTERS_typedefs.h.

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_Uart_Baud
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_115200 

115200 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_57600 

57600 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_38400 

38400 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_19200 

19200 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_9600 

9600 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_4800 

4800 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_2400 

2400 bps

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_UART_1200 

1200 bps

Definition at line 1970 of file ADISENSE1000_REGISTERS_typedefs.h.

enum ADI_ADISENSE_CORE_Digital_Sensor_Comms_Uart_Mode
Enumerator:
ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N1 

8 Data Bits No Parity 1 Stop Bit

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N2 

8 Data Bits No Parity 2 Stop Bits

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8N3 

8 Data Bits No Parity 3 Stop Bits

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E1 

8 Data Bits Even Parity 1 Stop Bit

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E2 

8 Data Bits Even Parity 2 Stop Bits

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8E3 

8 Data Bits Even Parity 3 Stop Bits

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O1 

8 Data Bits Odd Parity 1 Stop Bit

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O2 

8 Data Bits Odd Parity 2 Stop Bits

ADISENSE_CORE_DIGITAL_SENSOR_COMMS_LINECONTROL_8O3 

8 Data Bits Odd Parity 3 Stop Bits

Definition at line 2000 of file ADISENSE1000_REGISTERS_typedefs.h.

Generated on Wed Jul 13 2022 13:02:05 by  doxygen 1.7.2