Max41461_2_regs.h

00001 /*******************************************************************************
00002 * Copyright (C) 2019 Maxim Integrated Products, Inc., All rights Reserved.
00003 *
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00012 *
00013 * The above copyright notice and this permission notice shall be included
00014 * in all copies or substantial portions of the Software.
00015 *
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00023 *
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00027 *
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00034 */
00035 
00036 #ifndef MAX41461_2_REGS_H_
00037 #define MAX41461_2_REGS_H_
00038 
00039 /**
00040  * @brief CFG1  (0X00)
00041  *
00042  */
00043 typedef union {
00044     unsigned char raw;
00045     struct {
00046         unsigned char modmode    : 1;    /**< Configures modulator mode */
00047         unsigned char sync       : 1;    /**< Controls if clock output acts as an input.
00048                                               When an input, it will sample the DATA pin. */
00049         unsigned char fskshape   : 1;    /**< Sets the state of FSK Gaussian Shaping */
00050         unsigned char            : 1;
00051         unsigned char xoclkdiv   : 2;    /**< XO clock division ratio for digital block */
00052         unsigned char xoclkdelay : 2;    /**< Start delay before enabling XO clock to digital block */
00053     } bits;
00054 } max41461_2_reg_cfg1_t;
00055 
00056 /**
00057  * @brief CFG2  (0X01)
00058  *
00059  */
00060 typedef union {
00061     unsigned char raw;
00062     struct {
00063         unsigned char bclk_postdiv : 3;    /**< Select the Baud Clock Post Division Ratio.
00064                                                 Valid values are from 1 to 5. */
00065         unsigned char              : 3;
00066         unsigned char clkout_delay : 2;    /**< Selects the delay when CLKOUT starts toggling upon
00067                                                 exiting SHUTDOWN mode, in divided XO clock cycles */
00068     } bits;
00069 } max41461_2_reg_cfg2_t;
00070 
00071 /**
00072  * @brief CFG3  (0X02)
00073  *
00074  */
00075 typedef union {
00076     unsigned char raw;
00077     struct {
00078         unsigned char bclk_prediv : 8;    /**< Baud clock predivision ratio. Valid values are from 3 to 255 */
00079     } bits;
00080 } max41461_2_reg_cfg3_t;
00081 
00082 /**
00083  * @brief CFG4  (0X03)
00084  *
00085  */
00086 typedef union {
00087     unsigned char raw;
00088     struct {
00089         unsigned char pwdn_mode : 2;    /**< Power Down Mode Select */
00090         unsigned char           : 6;
00091     } bits;
00092 } max41461_2_reg_cfg4_t;
00093 
00094 /**
00095  * @brief CFG5  (0X04)
00096  *
00097  */
00098 typedef union {
00099     unsigned char raw;
00100     struct {
00101         unsigned char tstep : 6;    /**< Controls GFSK shaping. See Digital FSK Modulation section. */
00102         unsigned char       : 2;
00103     } bits;
00104 } max41461_2_reg_cfg5_t;
00105 
00106 /**
00107  * @brief SHDN  (0X05)
00108  *
00109  */
00110 typedef union {
00111     unsigned char raw;
00112     struct {
00113         unsigned char pa_boost        : 1;    /**< Enables a boost in PA output power for frequencies above 850MHz.
00114                                                    This requires a different PA match compared to normal operation. */
00115         unsigned char                 : 7;
00116     } bits;
00117 } max41461_2_reg_shdn_t;
00118 
00119 /**
00120  * @brief PA1  (0X06)
00121  *
00122  */
00123 typedef union {
00124     unsigned char raw;
00125     struct {
00126         unsigned char papwr  : 3;    /**< Controls the PA output power by enabling parallel drivers. */
00127         unsigned char        : 5;
00128     } bits;
00129 } max41461_2_reg_pa1_t;
00130 
00131 /**
00132  * @brief PA2  (0X07)
00133  *
00134  */
00135 typedef union {
00136     unsigned char raw;
00137     struct {
00138         unsigned char pacap     : 5;    /**< Controls shunt capacitance on PA output in fF. */
00139         unsigned char           : 3;
00140     } bits;
00141 } max41461_2_reg_pa2_t;
00142 
00143 /**
00144  * @brief PLL1  (0X08)
00145  *
00146  */
00147 typedef union {
00148     unsigned char raw;
00149     struct {
00150         unsigned char lomode      : 1;    /**< Sets LO generation. For lower power, choose LOWCURRENT.
00151                                                For higher performance, choose LOWNOISE. */
00152         unsigned char lodiv       : 2;    /**< LC VCO divider value*/
00153         unsigned char loopbw      : 2;    /**< Write to 00 binary.Sets PLL loop bandwidth. */
00154         unsigned char fracmode    : 1;    /**< Sets PLL between fractional-N and integer-N mode. */
00155         unsigned char cplin       : 2;    /**< Sets the level of charge pump offset current for fractional N mode to
00156                                                improve close in phase noise. Set to DISABLED for integer N mode. */
00157     } bits;
00158 } max41461_2_reg_pll1_t;
00159 
00160 /**
00161  * @brief PLL2  (0X09)
00162  *
00163  */
00164 typedef union {
00165     unsigned char raw;
00166     struct {
00167         unsigned char cpval            : 2;    /**< Sets Charge Pump Current */
00168         unsigned char                  : 4;
00169         unsigned char lcvco_fast_start : 1;    /**< Write to 0 binary.Enables fast start of LC VCO
00170                                                     because of bias filtering */
00171         unsigned char lcvco_pwr        : 1;    /**< Write to 0 binary.Controls power in LC VCO */
00172     } bits;
00173 } max41461_2_reg_pll2_t;
00174 
00175 /**
00176  * @brief CFG6  (0X0A)
00177  *
00178  */
00179 typedef union {
00180     unsigned char raw;
00181     struct {
00182         unsigned char fourwire1 : 1;    /**<  */
00183         unsigned char spi_txen1 : 1;    /**<  */
00184         unsigned char i2c_txen1 : 1;    /**< Enables DATA transmission in I2C mode. Aliased address for I2C_TXEN1 */
00185         unsigned char           : 5;
00186     } bits;
00187 } max41461_2_reg_cfg6_t;
00188 
00189 /**
00190  * @brief PLL3  (0X0B)
00191  *
00192  */
00193 typedef union {
00194     unsigned char raw;
00195     struct {
00196         unsigned char freq_23_to_16 : 8;    /**< FREQ value to PLL. LO frequency= FREQ<23:0>/2^16*fXTAL */
00197     } bits;
00198 } max41461_2_reg_pll3_t;
00199 
00200 /**
00201  * @brief PLL4  (0X0C)
00202  *
00203  */
00204 typedef union {
00205     unsigned char raw;
00206     struct {
00207         unsigned char freq_15_to_8 : 8;    /**< FREQ value to PLL */
00208     } bits;
00209 } max41461_2_reg_pll4_t;
00210 
00211 /**
00212  * @brief PLL5  (0X0D)
00213  *
00214  */
00215 typedef union {
00216     unsigned char raw;
00217     struct {
00218         unsigned char freq_7_to_0 : 8;    /**< FREQ value to PLL */
00219     } bits;
00220 } max41461_2_reg_pll5_t;
00221 
00222 /**
00223  * @brief PLL6  (0X0E)
00224  *
00225  */
00226 typedef union {
00227     unsigned char raw;
00228     struct {
00229         unsigned char deltaf : 7;    /**< For FSK mode, MODMODE=1 and FSKSHAPE=0, sets the frequency deviation from the
00230                                           space frequency for the mark frequency. fDELTA = DELTAF[6:0]*fXTAL/8192 */
00231         unsigned char        : 1;
00232     } bits;
00233 } max41461_2_reg_pll6_t;
00234 
00235 /**
00236  * @brief PLL7  (0X0F)
00237  *
00238  */
00239 typedef union {
00240     unsigned char raw;
00241     struct {
00242         unsigned char deltaf_shape : 4;    /**< For FSK mode, MODMODE = 1 and FSKSHAPE = 1, sets the frequency deviation
00243                                                 from the space frequency for the mark frequency.
00244                                                 fDELTA = DELTAF_SHAPE[3:0]*fXTAL/81920 */
00245         unsigned char              : 4;
00246     } bits;
00247 } max41461_2_reg_pll7_t;
00248 
00249 /**
00250  * @brief CFG7  (0X10)
00251  *
00252  */
00253 typedef union {
00254     unsigned char raw;
00255     struct {
00256         unsigned char fourwire2 : 1;    /**<  */
00257         unsigned char spi_txen2 : 1;    /**<  */
00258         unsigned char i2c_txen2 : 1;    /**< When set, enables DATA transmission in I2C mode.
00259                                              Aliased address for I2C_TXEN1 */
00260         unsigned char           : 5;
00261     } bits;
00262 } max41461_2_reg_cfg7_t;
00263 
00264 /**
00265  * @brief I2C1  (0X11)
00266  *
00267  */
00268 typedef union {
00269     unsigned char raw;
00270     struct {
00271         unsigned char pktlen_14_to_8 : 7;    /**< Packet Length */
00272         unsigned char pktlen_mode    : 1;    /**< Packet Length Mode */
00273     } bits;
00274 } max41461_2_reg_i2c1_t;
00275 
00276 /**
00277  * @brief I2C2  (0X012)
00278  *
00279  */
00280 typedef union {
00281     unsigned char raw;
00282     struct {
00283         unsigned char pktlen_7_to_0 : 8;    /**< Packet Length */
00284     } bits;
00285 } max41461_2_reg_i2c2_t;
00286 
00287 /**
00288  * @brief I2C3  (0X13)
00289  *
00290  */
00291 typedef union {
00292     unsigned char raw;
00293     struct {
00294         unsigned char i2c_tx_data : 8;    /**< Transmit data to be written into FIFO for I2C mode of operation.
00295                                                At this address, I2C register address will not auto increment within an
00296                                                I2C transaction burst, and subsequent writes will keep going to FIFO */
00297     } bits;
00298 } max41461_2_reg_i2c3_t;
00299 
00300 /**
00301  * @brief I2C4  (0X14)
00302  *
00303  */
00304 typedef union {
00305     unsigned char raw;
00306     struct {
00307         unsigned char tx_pktlen_14_to_8 : 7;    /**< Provides status information of bits
00308                                                      transmitted for the current packet */
00309         unsigned char pktcomplete       : 1;    /**< Indicates if Packet transmission is completed */
00310     } bits;
00311 } max41461_2_reg_i2c4_t;
00312 
00313 /**
00314  * @brief I2C5  (0X15)
00315  *
00316  */
00317 typedef union {
00318     unsigned char raw;
00319     struct {
00320         unsigned char tx_pktlen_7_to_0 : 8;    /**< Provides status information of bits
00321                                                     transmitted for the current packet */
00322     } bits;
00323 } max41461_2_reg_i2c5_t;
00324 
00325 /**
00326  * @brief I2C6  (0X16)
00327  *
00328  */
00329 typedef union {
00330     unsigned char raw;
00331     struct {
00332         unsigned char fifo_words : 3;    /**< This field captures the number of locations currently filled in FIFO.
00333                                               Each location corresponds to 8-bit data word */
00334         unsigned char            : 1;
00335         unsigned char fifo_full  : 1;    /**< FIFO Full Status */
00336         unsigned char fifo_empty : 1;    /**< FIFO Empty Status */
00337         unsigned char oflow      : 1;    /**< FIFO Overflow status */
00338         unsigned char uflow      : 1;    /**< FIFO Underflow status */
00339     } bits;
00340 } max41461_2_reg_i2c6_t;
00341 
00342 /**
00343  * @brief CFG8  (0X17)
00344  *
00345  */
00346 typedef union {
00347     unsigned char raw;
00348     struct {
00349         unsigned char softreset : 1;    /**< Places DUT into software reset. */
00350         unsigned char           : 7;
00351     } bits;
00352 } max41461_2_reg_cfg8_t;
00353 
00354 /**
00355  * @brief CFG9  (0X18)
00356  *
00357  */
00358 typedef union {
00359     unsigned char raw;
00360     struct {
00361         unsigned char xoen     : 1;    /**< Write to 0 binary.XO Enable register for test purpose */
00362         unsigned char pllen    : 1;    /**< Write to 0 binary.PLL Enable register for test purpose */
00363         unsigned char paen     : 1;    /**< Write to 0 binary.PA Enable register for test purpose */
00364         unsigned char test_ana : 5;    /**< Write to 0_0000 binary.Test modes for analog block */
00365     } bits;
00366 } max41461_2_reg_cfg9_t;
00367 
00368 /**
00369  * @brief ADDL1  (0X19)
00370  *
00371  */
00372 typedef union {
00373     unsigned char raw;
00374     struct {
00375         unsigned char ring_bias : 2;    /**< Write to 00 binary.Controls the current mirror ratio in Ring Oscillator
00376                                              control. For lower frequencies, the number can be reduced for
00377                                              slightly better phase noise. */
00378         unsigned char ring_trim : 2;    /**< Write to 00 binary.
00379                                              Adjusts the current control value for ring oscillator. */
00380         unsigned char bias_trim : 2;    /**< Write to 00 binary.
00381                                              Adjusts bias current for PLL block. */
00382         unsigned char xtal_gm   : 2;    /**< Write to 00 binary.
00383                                              Controls crystal oscillator GM current for startup time control */
00384     } bits;
00385 } max41461_2_reg_addl1_t;
00386 
00387 /**
00388  * @brief ADDL2  (0X1A)
00389  *
00390  */
00391 typedef union {
00392     unsigned char raw;
00393     struct {
00394         unsigned char addlctrl2       : 7;    /**< Write to 000_0000 binary.Additional control fields for future use */
00395         unsigned char scl_stretch_dly : 1;    /**< Write to 1 binary. I2C SCL Stretch Release delay enable */
00396     } bits;
00397 } max41461_2_reg_addl2_t;
00398 
00399 /**
00400  * @brief Register Set
00401  *
00402  */
00403 typedef struct {
00404     max41461_2_reg_cfg1_t reg_cfg1;
00405     max41461_2_reg_cfg2_t reg_cfg2;
00406     max41461_2_reg_cfg3_t reg_cfg3;
00407     max41461_2_reg_cfg4_t reg_cfg4;
00408     max41461_2_reg_cfg5_t reg_cfg5;
00409     max41461_2_reg_shdn_t reg_shdn;
00410     max41461_2_reg_pa1_t reg_pa1;
00411     max41461_2_reg_pa2_t reg_pa2;
00412     max41461_2_reg_pll1_t reg_pll1;
00413     max41461_2_reg_pll2_t reg_pll2;
00414     max41461_2_reg_cfg6_t reg_cfg6;
00415     max41461_2_reg_pll3_t reg_pll3;
00416     max41461_2_reg_pll4_t reg_pll4;
00417     max41461_2_reg_pll5_t reg_pll5;
00418     max41461_2_reg_pll6_t reg_pll6;
00419     max41461_2_reg_pll7_t reg_pll7;
00420     max41461_2_reg_cfg7_t reg_cfg7;
00421     max41461_2_reg_i2c1_t reg_i2c1;
00422     max41461_2_reg_i2c2_t reg_i2c2;
00423     max41461_2_reg_i2c3_t reg_i2c3;
00424     max41461_2_reg_i2c4_t reg_i2c4;
00425     max41461_2_reg_i2c5_t reg_i2c5;
00426     max41461_2_reg_i2c6_t reg_i2c6;
00427     max41461_2_reg_cfg8_t reg_cfg8;
00428     max41461_2_reg_cfg9_t reg_cfg9;
00429     max41461_2_reg_addl1_t reg_addl1;
00430     max41461_2_reg_addl2_t reg_addl2;
00431 } max41461_2_reg_map_t;
00432 
00433 
00434 #endif /* MAX41461_2_REGS_H_ */