Sinan Divarci / Mbed OS max4146x_comp

max4146x_comp

Dependencies:   MAX14690

max4146x/Max4146x.cpp@0:0061165683ee, 2020-10-25 (annotated)

Committer:
sdivarci
Date:
Sun Oct 25 20:10:02 2020 +0000
Revision:
0:0061165683ee
sdivarci

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sdivarci 0:0061165683ee 1 /*******************************************************************************
sdivarci 0:0061165683ee 2 * Copyright (C) 2019 Maxim Integrated Products, Inc., All rights Reserved.
sdivarci 0:0061165683ee 3 *
sdivarci 0:0061165683ee 4 * This software is protected by copyright laws of the United States and
sdivarci 0:0061165683ee 5 * of foreign countries. This material may also be protected by patent laws
sdivarci 0:0061165683ee 6 * and technology transfer regulations of the United States and of foreign
sdivarci 0:0061165683ee 7 * countries. This software is furnished under a license agreement and/or a
sdivarci 0:0061165683ee 8 * nondisclosure agreement and may only be used or reproduced in accordance
sdivarci 0:0061165683ee 9 * with the terms of those agreements. Dissemination of this information to
sdivarci 0:0061165683ee 10 * any party or parties not specified in the license agreement and/or
sdivarci 0:0061165683ee 11 * nondisclosure agreement is expressly prohibited.
sdivarci 0:0061165683ee 12 *
sdivarci 0:0061165683ee 13 * The above copyright notice and this permission notice shall be included
sdivarci 0:0061165683ee 14 * in all copies or substantial portions of the Software.
sdivarci 0:0061165683ee 15 *
sdivarci 0:0061165683ee 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sdivarci 0:0061165683ee 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sdivarci 0:0061165683ee 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sdivarci 0:0061165683ee 19 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sdivarci 0:0061165683ee 20 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sdivarci 0:0061165683ee 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sdivarci 0:0061165683ee 22 * OTHER DEALINGS IN THE SOFTWARE.
sdivarci 0:0061165683ee 23 *
sdivarci 0:0061165683ee 24 * Except as contained in this notice, the name of Maxim Integrated
sdivarci 0:0061165683ee 25 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sdivarci 0:0061165683ee 26 * Products, Inc. Branding Policy.
sdivarci 0:0061165683ee 27 *
sdivarci 0:0061165683ee 28 * The mere transfer of this software does not imply any licenses
sdivarci 0:0061165683ee 29 * of trade secrets, proprietary technology, copyrights, patents,
sdivarci 0:0061165683ee 30 * trademarks, maskwork rights, or any other form of intellectual
sdivarci 0:0061165683ee 31 * property whatsoever. Maxim Integrated Products, Inc. retains all
sdivarci 0:0061165683ee 32 * ownership rights.
sdivarci 0:0061165683ee 33 *******************************************************************************
sdivarci 0:0061165683ee 34 */
sdivarci 0:0061165683ee 35
sdivarci 0:0061165683ee 36 #include "Max4146x.h"
sdivarci 0:0061165683ee 37 #include <iostream>
sdivarci 0:0061165683ee 38
sdivarci 0:0061165683ee 39 using namespace std;
sdivarci 0:0061165683ee 40
sdivarci 0:0061165683ee 41 const uint8_t default_register_value_0[17] = {0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60, 0x00,
sdivarci 0:0061165683ee 42 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x02};
sdivarci 0:0061165683ee 43 const uint8_t default_register_value_1[20] = {0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60, 0x00,
sdivarci 0:0061165683ee 44 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x04, 0x00, 0xFF, 0x00};
sdivarci 0:0061165683ee 45
sdivarci 0:0061165683ee 46 template <class REG>
sdivarci 0:0061165683ee 47 MAX4146X<REG>::MAX4146X(REG *reg, SPI *spi, DigitalOut *cs)
sdivarci 0:0061165683ee 48 {
sdivarci 0:0061165683ee 49 operation_mode = UNINITIALIZED;
sdivarci 0:0061165683ee 50
sdivarci 0:0061165683ee 51 if (reg == NULL) {
sdivarci 0:0061165683ee 52 return;
sdivarci 0:0061165683ee 53 }
sdivarci 0:0061165683ee 54
sdivarci 0:0061165683ee 55 if (cs == NULL) {
sdivarci 0:0061165683ee 56 return;
sdivarci 0:0061165683ee 57 }
sdivarci 0:0061165683ee 58
sdivarci 0:0061165683ee 59 this->reg = reg;
sdivarci 0:0061165683ee 60 ssel = cs;
sdivarci 0:0061165683ee 61
sdivarci 0:0061165683ee 62 if (spi == NULL) {
sdivarci 0:0061165683ee 63 return;
sdivarci 0:0061165683ee 64 }
sdivarci 0:0061165683ee 65
sdivarci 0:0061165683ee 66 spi_handler = spi;
sdivarci 0:0061165683ee 67 i2c_handler = NULL;
sdivarci 0:0061165683ee 68 preset_mode = 0;
sdivarci 0:0061165683ee 69
sdivarci 0:0061165683ee 70 if (initial_programming() < 0) {
sdivarci 0:0061165683ee 71 return;
sdivarci 0:0061165683ee 72 }
sdivarci 0:0061165683ee 73
sdivarci 0:0061165683ee 74 this->crystal_frequency = 16.0;
sdivarci 0:0061165683ee 75 this->center_frequency = 315.0;
sdivarci 0:0061165683ee 76 this->baud_rate = 5000.0; //5 kHz
sdivarci 0:0061165683ee 77
sdivarci 0:0061165683ee 78 operation_mode = INITIALIZED;
sdivarci 0:0061165683ee 79 }
sdivarci 0:0061165683ee 80
sdivarci 0:0061165683ee 81 template <class REG>
sdivarci 0:0061165683ee 82 MAX4146X<REG>::MAX4146X(REG *reg, SPI *spi)
sdivarci 0:0061165683ee 83 {
sdivarci 0:0061165683ee 84 operation_mode = UNINITIALIZED;
sdivarci 0:0061165683ee 85
sdivarci 0:0061165683ee 86 if (reg == NULL) {
sdivarci 0:0061165683ee 87 return;
sdivarci 0:0061165683ee 88 }
sdivarci 0:0061165683ee 89
sdivarci 0:0061165683ee 90 this->reg = reg;
sdivarci 0:0061165683ee 91
sdivarci 0:0061165683ee 92 if (spi == NULL) {
sdivarci 0:0061165683ee 93 return;
sdivarci 0:0061165683ee 94 }
sdivarci 0:0061165683ee 95
sdivarci 0:0061165683ee 96 spi_handler = spi;
sdivarci 0:0061165683ee 97 i2c_handler = NULL;
sdivarci 0:0061165683ee 98 ssel = NULL;
sdivarci 0:0061165683ee 99 preset_mode = 0;
sdivarci 0:0061165683ee 100
sdivarci 0:0061165683ee 101 if (initial_programming() < 0) {
sdivarci 0:0061165683ee 102 return;
sdivarci 0:0061165683ee 103 }
sdivarci 0:0061165683ee 104
sdivarci 0:0061165683ee 105 this->crystal_frequency = 16.0;
sdivarci 0:0061165683ee 106 this->center_frequency = 315.0;
sdivarci 0:0061165683ee 107 this->baud_rate = 5000.0; //5 kHz
sdivarci 0:0061165683ee 108
sdivarci 0:0061165683ee 109 operation_mode = INITIALIZED;
sdivarci 0:0061165683ee 110 }
sdivarci 0:0061165683ee 111
sdivarci 0:0061165683ee 112 template <class REG>
sdivarci 0:0061165683ee 113 MAX4146X<REG>::MAX4146X(REG *reg, I2C *i2c)
sdivarci 0:0061165683ee 114 {
sdivarci 0:0061165683ee 115 operation_mode = UNINITIALIZED;
sdivarci 0:0061165683ee 116
sdivarci 0:0061165683ee 117 if (reg == NULL) {
sdivarci 0:0061165683ee 118 return;
sdivarci 0:0061165683ee 119 }
sdivarci 0:0061165683ee 120
sdivarci 0:0061165683ee 121 this->reg = reg;
sdivarci 0:0061165683ee 122
sdivarci 0:0061165683ee 123 if (i2c == NULL) {
sdivarci 0:0061165683ee 124 return;
sdivarci 0:0061165683ee 125 }
sdivarci 0:0061165683ee 126
sdivarci 0:0061165683ee 127 i2c_handler = i2c;
sdivarci 0:0061165683ee 128 spi_handler = NULL;
sdivarci 0:0061165683ee 129 ssel = NULL;
sdivarci 0:0061165683ee 130 preset_mode = 0;
sdivarci 0:0061165683ee 131
sdivarci 0:0061165683ee 132 if (initial_programming() < 0) {
sdivarci 0:0061165683ee 133 return;
sdivarci 0:0061165683ee 134 }
sdivarci 0:0061165683ee 135
sdivarci 0:0061165683ee 136 this->crystal_frequency = 16.0;
sdivarci 0:0061165683ee 137 this->center_frequency = 315.0;
sdivarci 0:0061165683ee 138 this->baud_rate = 5000.0; //5 kHz
sdivarci 0:0061165683ee 139
sdivarci 0:0061165683ee 140 operation_mode = INITIALIZED;
sdivarci 0:0061165683ee 141 }
sdivarci 0:0061165683ee 142
sdivarci 0:0061165683ee 143 template <class REG>
sdivarci 0:0061165683ee 144 MAX4146X<REG>::MAX4146X(DigitalOut *cs)
sdivarci 0:0061165683ee 145 {
sdivarci 0:0061165683ee 146 operation_mode = UNINITIALIZED;
sdivarci 0:0061165683ee 147
sdivarci 0:0061165683ee 148 if (cs == NULL) {
sdivarci 0:0061165683ee 149 return;
sdivarci 0:0061165683ee 150 }
sdivarci 0:0061165683ee 151
sdivarci 0:0061165683ee 152 data_sent = cs;
sdivarci 0:0061165683ee 153
sdivarci 0:0061165683ee 154 data_rate = 5;
sdivarci 0:0061165683ee 155
sdivarci 0:0061165683ee 156 this->reg = NULL;
sdivarci 0:0061165683ee 157 this->ssel = NULL;
sdivarci 0:0061165683ee 158 spi_handler = NULL;
sdivarci 0:0061165683ee 159 i2c_handler = NULL;
sdivarci 0:0061165683ee 160 preset_mode = 1;
sdivarci 0:0061165683ee 161
sdivarci 0:0061165683ee 162 operation_mode = INITIALIZED;
sdivarci 0:0061165683ee 163 }
sdivarci 0:0061165683ee 164
sdivarci 0:0061165683ee 165 template <>
sdivarci 0:0061165683ee 166 int MAX4146X<max41460_reg_map_t>::read_register(uint8_t reg, uint8_t *value, uint8_t len)
sdivarci 0:0061165683ee 167 {
sdivarci 0:0061165683ee 168 int rtn_val = -1;
sdivarci 0:0061165683ee 169
sdivarci 0:0061165683ee 170 if (value == NULL) {
sdivarci 0:0061165683ee 171 return -1;
sdivarci 0:0061165683ee 172 }
sdivarci 0:0061165683ee 173
sdivarci 0:0061165683ee 174 if (this->reg == NULL) {
sdivarci 0:0061165683ee 175 return -1;
sdivarci 0:0061165683ee 176 }
sdivarci 0:0061165683ee 177
sdivarci 0:0061165683ee 178 if (ssel != NULL) {
sdivarci 0:0061165683ee 179 *ssel = 0;
sdivarci 0:0061165683ee 180 }
sdivarci 0:0061165683ee 181 spi_handler->write((uint8_t)0x80 | reg);
sdivarci 0:0061165683ee 182 for (uint8_t i = 0; i < len; i++) {
sdivarci 0:0061165683ee 183 *(value++) = spi_handler->write(0x00); // read back data bytes
sdivarci 0:0061165683ee 184 }
sdivarci 0:0061165683ee 185 if (ssel != NULL) {
sdivarci 0:0061165683ee 186 *ssel = 1;
sdivarci 0:0061165683ee 187 }
sdivarci 0:0061165683ee 188 return 0;
sdivarci 0:0061165683ee 189 }
sdivarci 0:0061165683ee 190
sdivarci 0:0061165683ee 191 template <class REG>
sdivarci 0:0061165683ee 192 int MAX4146X<REG>::read_register(uint8_t reg, uint8_t *value, uint8_t len)
sdivarci 0:0061165683ee 193 {
sdivarci 0:0061165683ee 194 int rtn_val = -1;
sdivarci 0:0061165683ee 195
sdivarci 0:0061165683ee 196 if (value == NULL) {
sdivarci 0:0061165683ee 197 return -1;
sdivarci 0:0061165683ee 198 }
sdivarci 0:0061165683ee 199
sdivarci 0:0061165683ee 200 if (this->reg == NULL) {
sdivarci 0:0061165683ee 201 return -1;
sdivarci 0:0061165683ee 202 }
sdivarci 0:0061165683ee 203
sdivarci 0:0061165683ee 204 rtn_val = i2c_handler->write(I2C_ADDRESS, (const char *)&reg, 1, true);
sdivarci 0:0061165683ee 205 if (rtn_val != 0) {
sdivarci 0:0061165683ee 206 return -1;
sdivarci 0:0061165683ee 207 }
sdivarci 0:0061165683ee 208
sdivarci 0:0061165683ee 209 rtn_val = i2c_handler->read(I2C_ADDRESS, (char *) value, len, false);
sdivarci 0:0061165683ee 210 if (rtn_val < 0) {
sdivarci 0:0061165683ee 211 return rtn_val;
sdivarci 0:0061165683ee 212 }
sdivarci 0:0061165683ee 213
sdivarci 0:0061165683ee 214 return 0;
sdivarci 0:0061165683ee 215 }
sdivarci 0:0061165683ee 216
sdivarci 0:0061165683ee 217 template <>
sdivarci 0:0061165683ee 218 int MAX4146X<max41460_reg_map_t>::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
sdivarci 0:0061165683ee 219 {
sdivarci 0:0061165683ee 220 int rtn_val = -1;
sdivarci 0:0061165683ee 221 uint8_t local_data[1 + len];
sdivarci 0:0061165683ee 222
sdivarci 0:0061165683ee 223 if (value == NULL) {
sdivarci 0:0061165683ee 224 return -1;
sdivarci 0:0061165683ee 225 }
sdivarci 0:0061165683ee 226
sdivarci 0:0061165683ee 227 memcpy(&local_data[0], value, len);
sdivarci 0:0061165683ee 228
sdivarci 0:0061165683ee 229 rtn_val = spi_handler->write(0x7F & reg); // write mode and adress send
sdivarci 0:0061165683ee 230 for (int i = 0; i < len; i++) {
sdivarci 0:0061165683ee 231 rtn_val = spi_handler->write(local_data[i]); // write adress
sdivarci 0:0061165683ee 232 }
sdivarci 0:0061165683ee 233 if (rtn_val != 0) {
sdivarci 0:0061165683ee 234 return rtn_val;
sdivarci 0:0061165683ee 235 }
sdivarci 0:0061165683ee 236
sdivarci 0:0061165683ee 237 return 0;
sdivarci 0:0061165683ee 238 }
sdivarci 0:0061165683ee 239
sdivarci 0:0061165683ee 240 template <class REG>
sdivarci 0:0061165683ee 241 int MAX4146X<REG>::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
sdivarci 0:0061165683ee 242 {
sdivarci 0:0061165683ee 243 int rtn_val = -1;
sdivarci 0:0061165683ee 244 uint8_t local_data[1 + len];
sdivarci 0:0061165683ee 245
sdivarci 0:0061165683ee 246 if (value == NULL) {
sdivarci 0:0061165683ee 247 return -1;
sdivarci 0:0061165683ee 248 }
sdivarci 0:0061165683ee 249
sdivarci 0:0061165683ee 250 local_data[0] = reg;
sdivarci 0:0061165683ee 251
sdivarci 0:0061165683ee 252 memcpy(&local_data[1], value, len);
sdivarci 0:0061165683ee 253
sdivarci 0:0061165683ee 254 rtn_val = i2c_handler->write(I2C_ADDRESS, (const char *)local_data,
sdivarci 0:0061165683ee 255 sizeof(local_data));
sdivarci 0:0061165683ee 256 if (rtn_val != 0) {
sdivarci 0:0061165683ee 257 return -1;
sdivarci 0:0061165683ee 258 }
sdivarci 0:0061165683ee 259
sdivarci 0:0061165683ee 260 return 0;
sdivarci 0:0061165683ee 261 }
sdivarci 0:0061165683ee 262
sdivarci 0:0061165683ee 263 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
sdivarci 0:0061165683ee 264 int ret; \
sdivarci 0:0061165683ee 265 ret = read_register(address, (uint8_t *)&(reg_name), 1); \
sdivarci 0:0061165683ee 266 if (ret) { \
sdivarci 0:0061165683ee 267 return ret; \
sdivarci 0:0061165683ee 268 } \
sdivarci 0:0061165683ee 269 bit_field_name = value; \
sdivarci 0:0061165683ee 270 ret = write_register(address, (uint8_t *)&(reg_name), 1); \
sdivarci 0:0061165683ee 271 if (ret) { \
sdivarci 0:0061165683ee 272 return ret; \
sdivarci 0:0061165683ee 273 }
sdivarci 0:0061165683ee 274
sdivarci 0:0061165683ee 275 template <class REG>
sdivarci 0:0061165683ee 276 int MAX4146X<REG>::set_crystal_frequency(float freq)
sdivarci 0:0061165683ee 277 {
sdivarci 0:0061165683ee 278 if (freq < 250 || freq > 950) {
sdivarci 0:0061165683ee 279 return -1;
sdivarci 0:0061165683ee 280 }
sdivarci 0:0061165683ee 281 this->crystal_frequency = freq;
sdivarci 0:0061165683ee 282
sdivarci 0:0061165683ee 283 return 0;
sdivarci 0:0061165683ee 284 }
sdivarci 0:0061165683ee 285
sdivarci 0:0061165683ee 286 template <class REG>
sdivarci 0:0061165683ee 287 float MAX4146X<REG>::get_crystal_frequency()
sdivarci 0:0061165683ee 288 {
sdivarci 0:0061165683ee 289 return this->crystal_frequency;
sdivarci 0:0061165683ee 290 }
sdivarci 0:0061165683ee 291
sdivarci 0:0061165683ee 292 template <class REG>
sdivarci 0:0061165683ee 293 int MAX4146X<REG>::set_center_frequency(float freq)
sdivarci 0:0061165683ee 294 {
sdivarci 0:0061165683ee 295 if (freq < 250 || freq > 950) {
sdivarci 0:0061165683ee 296 return -1;
sdivarci 0:0061165683ee 297 }
sdivarci 0:0061165683ee 298
sdivarci 0:0061165683ee 299 this->center_frequency = freq;
sdivarci 0:0061165683ee 300
sdivarci 0:0061165683ee 301 uint32_t value = (uint32_t)((65536 * freq) / this->crystal_frequency); //65536 is constant defined in the datasheet
sdivarci 0:0061165683ee 302
sdivarci 0:0061165683ee 303 return this->set_frequency(value);
sdivarci 0:0061165683ee 304 }
sdivarci 0:0061165683ee 305
sdivarci 0:0061165683ee 306 template <class REG>
sdivarci 0:0061165683ee 307 float MAX4146X<REG>::get_center_frequency()
sdivarci 0:0061165683ee 308 {
sdivarci 0:0061165683ee 309 return this->center_frequency;
sdivarci 0:0061165683ee 310 }
sdivarci 0:0061165683ee 311
sdivarci 0:0061165683ee 312 template <class REG>
sdivarci 0:0061165683ee 313 int MAX4146X<REG>::adjust_baudrate(float rate)
sdivarci 0:0061165683ee 314 {
sdivarci 0:0061165683ee 315 if (rate < 195.3 || rate > 200000.0) {
sdivarci 0:0061165683ee 316 return -1;
sdivarci 0:0061165683ee 317 }
sdivarci 0:0061165683ee 318
sdivarci 0:0061165683ee 319 if (this->preset_mode == 1) {
sdivarci 0:0061165683ee 320 this->baud_rate = rate;
sdivarci 0:0061165683ee 321 }
sdivarci 0:0061165683ee 322
sdivarci 0:0061165683ee 323 int error = 0;
sdivarci 0:0061165683ee 324 uint8_t prediv = 3;
sdivarci 0:0061165683ee 325
sdivarci 0:0061165683ee 326 if (rate < 12500.0) {
sdivarci 0:0061165683ee 327 error = this->set_bclk_postdiv(this->BCLK_POSTDIV_BY_5);
sdivarci 0:0061165683ee 328 prediv = (uint8_t)((50000.0 / rate) - 1);
sdivarci 0:0061165683ee 329 } else if (rate < 25000.0) {
sdivarci 0:0061165683ee 330 error = this->set_bclk_postdiv(this->BCLK_POSTDIV_BY_4);
sdivarci 0:0061165683ee 331 prediv = (uint8_t)((100000.0 / rate) - 1);
sdivarci 0:0061165683ee 332 } else if (rate < 50000.0) {
sdivarci 0:0061165683ee 333 error = this->set_bclk_postdiv(this->BCLK_POSTDIV_BY_3);
sdivarci 0:0061165683ee 334 prediv = (uint8_t)((200000.0 / rate) - 1);
sdivarci 0:0061165683ee 335 } else if (rate < 100000.0) {
sdivarci 0:0061165683ee 336 error = this->set_bclk_postdiv(this->BCLK_POSTDIV_BY_2);
sdivarci 0:0061165683ee 337 prediv = (uint8_t)((400000.0 / rate) - 1);
sdivarci 0:0061165683ee 338 } else {
sdivarci 0:0061165683ee 339 error = this->set_bclk_postdiv(this->BCLK_POSTDIV_BY_1);
sdivarci 0:0061165683ee 340 prediv = (uint8_t)((800000.0 / rate) - 1);
sdivarci 0:0061165683ee 341 }
sdivarci 0:0061165683ee 342
sdivarci 0:0061165683ee 343 if (error < 0) {
sdivarci 0:0061165683ee 344 return -1;
sdivarci 0:0061165683ee 345 }
sdivarci 0:0061165683ee 346
sdivarci 0:0061165683ee 347 return this->set_bclk_prediv(prediv);
sdivarci 0:0061165683ee 348 }
sdivarci 0:0061165683ee 349
sdivarci 0:0061165683ee 350 template <class REG>
sdivarci 0:0061165683ee 351 float MAX4146X<REG>::get_baudrate()
sdivarci 0:0061165683ee 352 {
sdivarci 0:0061165683ee 353 return this->baud_rate;
sdivarci 0:0061165683ee 354 }
sdivarci 0:0061165683ee 355
sdivarci 0:0061165683ee 356 template <class REG>
sdivarci 0:0061165683ee 357 int MAX4146X<REG>::adjust_frequency_deviation(float deviation)
sdivarci 0:0061165683ee 358 {
sdivarci 0:0061165683ee 359 uint8_t dev = 0;
sdivarci 0:0061165683ee 360
sdivarci 0:0061165683ee 361 if (this->read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1) < 0) {
sdivarci 0:0061165683ee 362 return -1;
sdivarci 0:0061165683ee 363 }
sdivarci 0:0061165683ee 364
sdivarci 0:0061165683ee 365 if (this->reg->reg_cfg1.bits.fskshape == 0) {
sdivarci 0:0061165683ee 366 dev = (uint8_t)(deviation * 8.192 / crystal_frequency);
sdivarci 0:0061165683ee 367 if (dev < 127) {
sdivarci 0:0061165683ee 368 return this->set_deltaf(dev);
sdivarci 0:0061165683ee 369 }
sdivarci 0:0061165683ee 370 } else {
sdivarci 0:0061165683ee 371 dev = (uint8_t)(deviation * 81.92 / crystal_frequency); // crystal_frequency in MHz form
sdivarci 0:0061165683ee 372 if (dev < 15) {
sdivarci 0:0061165683ee 373 return this->set_deltaf_shape(dev);
sdivarci 0:0061165683ee 374 }
sdivarci 0:0061165683ee 375 }
sdivarci 0:0061165683ee 376
sdivarci 0:0061165683ee 377 return -1;
sdivarci 0:0061165683ee 378 }
sdivarci 0:0061165683ee 379
sdivarci 0:0061165683ee 380 template <class REG>
sdivarci 0:0061165683ee 381 int MAX4146X<REG>::adjust_manchester_bitrate(char rate)
sdivarci 0:0061165683ee 382 {
sdivarci 0:0061165683ee 383 this->data_rate = rate;
sdivarci 0:0061165683ee 384
sdivarci 0:0061165683ee 385 return 0;
sdivarci 0:0061165683ee 386 }
sdivarci 0:0061165683ee 387
sdivarci 0:0061165683ee 388 template <class REG>
sdivarci 0:0061165683ee 389 char MAX4146X<REG>::get_manchester_bitrate()
sdivarci 0:0061165683ee 390 {
sdivarci 0:0061165683ee 391 return this->data_rate;
sdivarci 0:0061165683ee 392 }
sdivarci 0:0061165683ee 393
sdivarci 0:0061165683ee 394 template <>
sdivarci 0:0061165683ee 395 int MAX4146X<max41460_reg_map_t>::send_data(uint8_t *data, uint32_t length)
sdivarci 0:0061165683ee 396 {
sdivarci 0:0061165683ee 397 if (this->preset_mode == 0) {
sdivarci 0:0061165683ee 398
sdivarci 0:0061165683ee 399 if (ssel != NULL) {
sdivarci 0:0061165683ee 400 *ssel = 0;
sdivarci 0:0061165683ee 401 }
sdivarci 0:0061165683ee 402
sdivarci 0:0061165683ee 403 spi_handler->write(0x7F & 0x0A); /*write mode and adress send*/
sdivarci 0:0061165683ee 404
sdivarci 0:0061165683ee 405 spi_handler->write(0x01); /*write data SPI_EN1 clear*/
sdivarci 0:0061165683ee 406
sdivarci 0:0061165683ee 407
sdivarci 0:0061165683ee 408 if (ssel != NULL) {
sdivarci 0:0061165683ee 409 *ssel = 1;
sdivarci 0:0061165683ee 410 }
sdivarci 0:0061165683ee 411
sdivarci 0:0061165683ee 412 wait_us(300); /* for waiting another SPI operation*/
sdivarci 0:0061165683ee 413
sdivarci 0:0061165683ee 414 if (ssel != NULL) {
sdivarci 0:0061165683ee 415 *ssel = 0;
sdivarci 0:0061165683ee 416 }
sdivarci 0:0061165683ee 417
sdivarci 0:0061165683ee 418 spi_handler->write(0x7F & 0x10); /*write mode and adress send*/
sdivarci 0:0061165683ee 419
sdivarci 0:0061165683ee 420 spi_handler->write(0x03); /*write data SPI_EN2 set*/
sdivarci 0:0061165683ee 421
sdivarci 0:0061165683ee 422 if (ssel != NULL) {
sdivarci 0:0061165683ee 423 *ssel = 0;
sdivarci 0:0061165683ee 424 }
sdivarci 0:0061165683ee 425
sdivarci 0:0061165683ee 426 wait_us(300); /* for waiting another SPI operation*/
sdivarci 0:0061165683ee 427
sdivarci 0:0061165683ee 428 }
sdivarci 0:0061165683ee 429
sdivarci 0:0061165683ee 430 return this->io_write(data, length);
sdivarci 0:0061165683ee 431 }
sdivarci 0:0061165683ee 432
sdivarci 0:0061165683ee 433 template <class REG>
sdivarci 0:0061165683ee 434 int MAX4146X<REG>::send_data(uint8_t *data, uint32_t length)
sdivarci 0:0061165683ee 435 {
sdivarci 0:0061165683ee 436 if (this->preset_mode == 0) {
sdivarci 0:0061165683ee 437 if (length > 32767) {
sdivarci 0:0061165683ee 438 return -100;
sdivarci 0:0061165683ee 439 }
sdivarci 0:0061165683ee 440
sdivarci 0:0061165683ee 441 this->adjust_baudrate(this->baud_rate);
sdivarci 0:0061165683ee 442
sdivarci 0:0061165683ee 443 // this->set_i2c_txen1(I2C_TXEN1_DISABLE);
sdivarci 0:0061165683ee 444
sdivarci 0:0061165683ee 445 char * value = (char *)malloc(17 * sizeof(char));
sdivarci 0:0061165683ee 446
sdivarci 0:0061165683ee 447 if (value == NULL) {
sdivarci 0:0061165683ee 448 return -99;
sdivarci 0:0061165683ee 449 }
sdivarci 0:0061165683ee 450
sdivarci 0:0061165683ee 451 int rtn_val = i2c_handler->write(I2C_ADDRESS, (char *) 0x00, 1, true);
sdivarci 0:0061165683ee 452 rtn_val = i2c_handler->read(I2C_ADDRESS, value, length, true);
sdivarci 0:0061165683ee 453 if (rtn_val != 0) {
sdivarci 0:0061165683ee 454 return rtn_val;
sdivarci 0:0061165683ee 455 }
sdivarci 0:0061165683ee 456
sdivarci 0:0061165683ee 457 free(value);
sdivarci 0:0061165683ee 458
sdivarci 0:0061165683ee 459 uint8_t local_data[4+length];
sdivarci 0:0061165683ee 460
sdivarci 0:0061165683ee 461 local_data[0] = CFG7_ADDR;
sdivarci 0:0061165683ee 462 local_data[1] = 0x04;
sdivarci 0:0061165683ee 463 local_data[2] = (uint8_t)((length >> 8) | 0x80);
sdivarci 0:0061165683ee 464 local_data[3] = (uint8_t)((length) & 0x0FF);
sdivarci 0:0061165683ee 465
sdivarci 0:0061165683ee 466 memcpy(&local_data[4], data, length);
sdivarci 0:0061165683ee 467
sdivarci 0:0061165683ee 468 i2c_handler->write(I2C_ADDRESS, (const char *)local_data, sizeof(local_data), false);
sdivarci 0:0061165683ee 469
sdivarci 0:0061165683ee 470 } else {
sdivarci 0:0061165683ee 471 this->io_write(data, length);
sdivarci 0:0061165683ee 472 }
sdivarci 0:0061165683ee 473
sdivarci 0:0061165683ee 474 return 0;
sdivarci 0:0061165683ee 475 }
sdivarci 0:0061165683ee 476
sdivarci 0:0061165683ee 477 template <class REG>
sdivarci 0:0061165683ee 478 int MAX4146X<REG>::io_write(uint8_t *data, uint32_t length)
sdivarci 0:0061165683ee 479 {
sdivarci 0:0061165683ee 480 //manchester array
sdivarci 0:0061165683ee 481 manchester_bit_array = new unsigned char[length * 2 * 8];
sdivarci 0:0061165683ee 482
sdivarci 0:0061165683ee 483 //bit array
sdivarci 0:0061165683ee 484 bits_array = new unsigned char[length * 8];
sdivarci 0:0061165683ee 485
sdivarci 0:0061165683ee 486 //byte to bit conversion
sdivarci 0:0061165683ee 487 for (int i = 0; i < length; i++) {
sdivarci 0:0061165683ee 488 for (int j = 0; j < 8; j++) {
sdivarci 0:0061165683ee 489 // Mask each bit in the byte and store it
sdivarci 0:0061165683ee 490 if (data[i] & (mask << j)) {
sdivarci 0:0061165683ee 491 bits_array[i * 8 + j] = 1;
sdivarci 0:0061165683ee 492 } else {
sdivarci 0:0061165683ee 493 bits_array[i * 8 + j] = 0;
sdivarci 0:0061165683ee 494 }
sdivarci 0:0061165683ee 495 }
sdivarci 0:0061165683ee 496 }
sdivarci 0:0061165683ee 497
sdivarci 0:0061165683ee 498 //manchester encode
sdivarci 0:0061165683ee 499 for (int i = 0; i < length * 8; i++) {
sdivarci 0:0061165683ee 500 if (bits_array[i] == 0) {
sdivarci 0:0061165683ee 501 //falling edge
sdivarci 0:0061165683ee 502 manchester_bit_array[2 * i] = 1;
sdivarci 0:0061165683ee 503 manchester_bit_array[2 * i + 1] = 0;
sdivarci 0:0061165683ee 504 } else {
sdivarci 0:0061165683ee 505 //rising edge
sdivarci 0:0061165683ee 506 manchester_bit_array[2 * i] = 0;
sdivarci 0:0061165683ee 507 manchester_bit_array[2 * i + 1] = 1;
sdivarci 0:0061165683ee 508 }
sdivarci 0:0061165683ee 509 }
sdivarci 0:0061165683ee 510
sdivarci 0:0061165683ee 511 delete[] bits_array; //delete bit array anymore not used
sdivarci 0:0061165683ee 512
sdivarci 0:0061165683ee 513 float result = (500.0 / data_rate);
sdivarci 0:0061165683ee 514
sdivarci 0:0061165683ee 515 bool rxFinished = false;
sdivarci 0:0061165683ee 516 Timer t;
sdivarci 0:0061165683ee 517 core_util_critical_section_enter();
sdivarci 0:0061165683ee 518 *this->data_sent = 0;
sdivarci 0:0061165683ee 519 wait_us(100);
sdivarci 0:0061165683ee 520 *this->data_sent = 1;
sdivarci 0:0061165683ee 521 wait_us(350);
sdivarci 0:0061165683ee 522 *this->data_sent = 0;
sdivarci 0:0061165683ee 523 wait_us(10);
sdivarci 0:0061165683ee 524 t.start();
sdivarci 0:0061165683ee 525 int manch_bit_counter = 0;
sdivarci 0:0061165683ee 526 do {
sdivarci 0:0061165683ee 527 if (t.read_us() >= (result * manch_bit_counter)) {
sdivarci 0:0061165683ee 528 if (manchester_bit_array[manch_bit_counter] == 0) {
sdivarci 0:0061165683ee 529 *this->data_sent = 0;
sdivarci 0:0061165683ee 530 } else {
sdivarci 0:0061165683ee 531 *this->data_sent = 1;
sdivarci 0:0061165683ee 532 }
sdivarci 0:0061165683ee 533
sdivarci 0:0061165683ee 534 manch_bit_counter++;
sdivarci 0:0061165683ee 535
sdivarci 0:0061165683ee 536 if (manch_bit_counter >= (length * 2 * 8)) {
sdivarci 0:0061165683ee 537 rxFinished = true;
sdivarci 0:0061165683ee 538 t.stop();
sdivarci 0:0061165683ee 539 if (this->ssel != NULL) {
sdivarci 0:0061165683ee 540 *this->ssel = 1;
sdivarci 0:0061165683ee 541 }
sdivarci 0:0061165683ee 542 }
sdivarci 0:0061165683ee 543
sdivarci 0:0061165683ee 544 }
sdivarci 0:0061165683ee 545 } while (!rxFinished);
sdivarci 0:0061165683ee 546 *this->data_sent = 0;
sdivarci 0:0061165683ee 547 core_util_critical_section_exit();
sdivarci 0:0061165683ee 548
sdivarci 0:0061165683ee 549 delete[] manchester_bit_array; //manchester array clean
sdivarci 0:0061165683ee 550
sdivarci 0:0061165683ee 551 return 0;
sdivarci 0:0061165683ee 552 }
sdivarci 0:0061165683ee 553
sdivarci 0:0061165683ee 554 template <class REG>
sdivarci 0:0061165683ee 555 int MAX4146X<REG>::set_softreset(softreset_t softreset)
sdivarci 0:0061165683ee 556 {
sdivarci 0:0061165683ee 557 SET_BIT_FIELD(CFG8_ADDR, this->reg->reg_cfg8, this->reg->reg_cfg8.bits.softreset, softreset);
sdivarci 0:0061165683ee 558
sdivarci 0:0061165683ee 559 return 0;
sdivarci 0:0061165683ee 560 }
sdivarci 0:0061165683ee 561
sdivarci 0:0061165683ee 562 template <class REG>
sdivarci 0:0061165683ee 563 int MAX4146X<REG>::set_xoclkdelay(xoclkdelay_t delay)
sdivarci 0:0061165683ee 564 {
sdivarci 0:0061165683ee 565 SET_BIT_FIELD(CFG1_ADDR, this->reg->reg_cfg1, this->reg->reg_cfg1.bits.xoclkdelay, delay);
sdivarci 0:0061165683ee 566
sdivarci 0:0061165683ee 567 return 0;
sdivarci 0:0061165683ee 568 }
sdivarci 0:0061165683ee 569
sdivarci 0:0061165683ee 570 template <class REG>
sdivarci 0:0061165683ee 571 int MAX4146X<REG>::get_xoclkdelay(xoclkdelay_t *delay)
sdivarci 0:0061165683ee 572 {
sdivarci 0:0061165683ee 573 int ret;
sdivarci 0:0061165683ee 574
sdivarci 0:0061165683ee 575 ret = read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1);
sdivarci 0:0061165683ee 576 if (ret < 0) {
sdivarci 0:0061165683ee 577 return ret;
sdivarci 0:0061165683ee 578 }
sdivarci 0:0061165683ee 579
sdivarci 0:0061165683ee 580 *delay = (xoclkdelay_t)this->reg->reg_cfg1.bits.xoclkdelay;
sdivarci 0:0061165683ee 581
sdivarci 0:0061165683ee 582 return 0;
sdivarci 0:0061165683ee 583 }
sdivarci 0:0061165683ee 584
sdivarci 0:0061165683ee 585 template <class REG>
sdivarci 0:0061165683ee 586 int MAX4146X<REG>::get_fifo_flags(uint8_t *fifo_flags)
sdivarci 0:0061165683ee 587 {
sdivarci 0:0061165683ee 588 return read_register(I2C6_ADDR, fifo_flags, 1);
sdivarci 0:0061165683ee 589 }
sdivarci 0:0061165683ee 590
sdivarci 0:0061165683ee 591 template <class REG>
sdivarci 0:0061165683ee 592 int MAX4146X<REG>::get_pktcomplete(uint8_t *pktcomplete)
sdivarci 0:0061165683ee 593 {
sdivarci 0:0061165683ee 594 int ret;
sdivarci 0:0061165683ee 595
sdivarci 0:0061165683ee 596 ret = read_register(I2C4_ADDR, (uint8_t *) & (this->reg->reg_i2c4), 1);
sdivarci 0:0061165683ee 597 if (ret < 0) {
sdivarci 0:0061165683ee 598 return ret;
sdivarci 0:0061165683ee 599 }
sdivarci 0:0061165683ee 600
sdivarci 0:0061165683ee 601 *pktcomplete = (uint8_t)this->reg->reg_i2c4.bits.pktcomplete;
sdivarci 0:0061165683ee 602
sdivarci 0:0061165683ee 603 return 0;
sdivarci 0:0061165683ee 604 }
sdivarci 0:0061165683ee 605
sdivarci 0:0061165683ee 606 template <class REG>
sdivarci 0:0061165683ee 607 int MAX4146X<REG>::get_tx_pktlen(uint16_t *pktlen)
sdivarci 0:0061165683ee 608 {
sdivarci 0:0061165683ee 609 int ret;
sdivarci 0:0061165683ee 610
sdivarci 0:0061165683ee 611 ret = read_register(I2C4_ADDR, (uint8_t *) & (this->reg->reg_i2c4), 2);
sdivarci 0:0061165683ee 612 if (ret < 0) {
sdivarci 0:0061165683ee 613 return ret;
sdivarci 0:0061165683ee 614 }
sdivarci 0:0061165683ee 615
sdivarci 0:0061165683ee 616 *pktlen = (uint16_t)(((this->reg->reg_i2c4.bits.tx_pktlen_14_to_8) << 8) + (this->reg->reg_i2c5.raw)) ;
sdivarci 0:0061165683ee 617
sdivarci 0:0061165683ee 618 return 0;
sdivarci 0:0061165683ee 619 }
sdivarci 0:0061165683ee 620
sdivarci 0:0061165683ee 621 template <class REG>
sdivarci 0:0061165683ee 622 int MAX4146X<REG>::set_xoclkdiv(xoclkdiv_t div)
sdivarci 0:0061165683ee 623 {
sdivarci 0:0061165683ee 624 SET_BIT_FIELD(CFG1_ADDR, this->reg->reg_cfg1, this->reg->reg_cfg1.bits.xoclkdiv, div);
sdivarci 0:0061165683ee 625
sdivarci 0:0061165683ee 626 return 0;
sdivarci 0:0061165683ee 627 }
sdivarci 0:0061165683ee 628
sdivarci 0:0061165683ee 629 template <class REG>
sdivarci 0:0061165683ee 630 int MAX4146X<REG>::get_xoclkdiv(xoclkdiv_t* div)
sdivarci 0:0061165683ee 631 {
sdivarci 0:0061165683ee 632 int ret;
sdivarci 0:0061165683ee 633
sdivarci 0:0061165683ee 634 ret = read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1);
sdivarci 0:0061165683ee 635 if (ret < 0) {
sdivarci 0:0061165683ee 636 return ret;
sdivarci 0:0061165683ee 637 }
sdivarci 0:0061165683ee 638
sdivarci 0:0061165683ee 639 *div = (xoclkdiv_t)this->reg->reg_cfg1.bits.xoclkdiv;
sdivarci 0:0061165683ee 640
sdivarci 0:0061165683ee 641 return 0;
sdivarci 0:0061165683ee 642 }
sdivarci 0:0061165683ee 643
sdivarci 0:0061165683ee 644 template <class REG>
sdivarci 0:0061165683ee 645 int MAX4146X<REG>::set_fskshape(fskshape_t shape)
sdivarci 0:0061165683ee 646 {
sdivarci 0:0061165683ee 647 SET_BIT_FIELD(CFG1_ADDR, this->reg->reg_cfg1, this->reg->reg_cfg1.bits.fskshape, shape);
sdivarci 0:0061165683ee 648
sdivarci 0:0061165683ee 649 return 0;
sdivarci 0:0061165683ee 650 }
sdivarci 0:0061165683ee 651
sdivarci 0:0061165683ee 652 template <class REG>
sdivarci 0:0061165683ee 653 int MAX4146X<REG>::get_fskshape(fskshape_t* shape)
sdivarci 0:0061165683ee 654 {
sdivarci 0:0061165683ee 655 int ret;
sdivarci 0:0061165683ee 656
sdivarci 0:0061165683ee 657 ret = read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1);
sdivarci 0:0061165683ee 658 if (ret < 0) {
sdivarci 0:0061165683ee 659 return ret;
sdivarci 0:0061165683ee 660 }
sdivarci 0:0061165683ee 661
sdivarci 0:0061165683ee 662 *shape = (fskshape_t)this->reg->reg_cfg1.bits.fskshape;
sdivarci 0:0061165683ee 663
sdivarci 0:0061165683ee 664 return 0;
sdivarci 0:0061165683ee 665 }
sdivarci 0:0061165683ee 666
sdivarci 0:0061165683ee 667 template <class REG>
sdivarci 0:0061165683ee 668 int MAX4146X<REG>::set_sync(sync_t state)
sdivarci 0:0061165683ee 669 {
sdivarci 0:0061165683ee 670 SET_BIT_FIELD(CFG1_ADDR, this->reg->reg_cfg1, this->reg->reg_cfg1.bits.sync, state);
sdivarci 0:0061165683ee 671
sdivarci 0:0061165683ee 672 return 0;
sdivarci 0:0061165683ee 673 }
sdivarci 0:0061165683ee 674
sdivarci 0:0061165683ee 675 template <class REG>
sdivarci 0:0061165683ee 676 int MAX4146X<REG>::get_sync(sync_t* state)
sdivarci 0:0061165683ee 677 {
sdivarci 0:0061165683ee 678 int ret;
sdivarci 0:0061165683ee 679
sdivarci 0:0061165683ee 680 ret = read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1);
sdivarci 0:0061165683ee 681 if (ret < 0) {
sdivarci 0:0061165683ee 682 return ret;
sdivarci 0:0061165683ee 683 }
sdivarci 0:0061165683ee 684
sdivarci 0:0061165683ee 685 *state = (sync_t)this->reg->reg_cfg1.bits.sync;
sdivarci 0:0061165683ee 686
sdivarci 0:0061165683ee 687 return 0;
sdivarci 0:0061165683ee 688 }
sdivarci 0:0061165683ee 689
sdivarci 0:0061165683ee 690 template <class REG>
sdivarci 0:0061165683ee 691 int MAX4146X<REG>::set_modmode(modmode_t mode)
sdivarci 0:0061165683ee 692 {
sdivarci 0:0061165683ee 693 SET_BIT_FIELD(CFG1_ADDR, this->reg->reg_cfg1, this->reg->reg_cfg1.bits.modmode, mode);
sdivarci 0:0061165683ee 694
sdivarci 0:0061165683ee 695 return 0;
sdivarci 0:0061165683ee 696 }
sdivarci 0:0061165683ee 697
sdivarci 0:0061165683ee 698 template <class REG>
sdivarci 0:0061165683ee 699 int MAX4146X<REG>::get_modmode(modmode_t* mode)
sdivarci 0:0061165683ee 700 {
sdivarci 0:0061165683ee 701 int ret;
sdivarci 0:0061165683ee 702
sdivarci 0:0061165683ee 703 ret = read_register(CFG1_ADDR, (uint8_t *) & (this->reg->reg_cfg1), 1);
sdivarci 0:0061165683ee 704 if (ret < 0) {
sdivarci 0:0061165683ee 705 return ret;
sdivarci 0:0061165683ee 706 }
sdivarci 0:0061165683ee 707
sdivarci 0:0061165683ee 708 *mode = (modmode_t)this->reg->reg_cfg1.bits.modmode;
sdivarci 0:0061165683ee 709
sdivarci 0:0061165683ee 710 return 0;
sdivarci 0:0061165683ee 711 }
sdivarci 0:0061165683ee 712
sdivarci 0:0061165683ee 713 template <class REG>
sdivarci 0:0061165683ee 714 int MAX4146X<REG>::set_clkout_delay(clkout_delay_t delay)
sdivarci 0:0061165683ee 715 {
sdivarci 0:0061165683ee 716 SET_BIT_FIELD(CFG2_ADDR, this->reg->reg_cfg2, this->reg->reg_cfg2.bits.clkout_delay, delay);
sdivarci 0:0061165683ee 717
sdivarci 0:0061165683ee 718 return 0;
sdivarci 0:0061165683ee 719 }
sdivarci 0:0061165683ee 720
sdivarci 0:0061165683ee 721 template <class REG>
sdivarci 0:0061165683ee 722 int MAX4146X<REG>::get_clkout_delay(clkout_delay_t* delay)
sdivarci 0:0061165683ee 723 {
sdivarci 0:0061165683ee 724 int ret;
sdivarci 0:0061165683ee 725
sdivarci 0:0061165683ee 726 ret = read_register(CFG2_ADDR, (uint8_t *) & (this->reg->reg_cfg2), 1);
sdivarci 0:0061165683ee 727 if (ret < 0) {
sdivarci 0:0061165683ee 728 return ret;
sdivarci 0:0061165683ee 729 }
sdivarci 0:0061165683ee 730
sdivarci 0:0061165683ee 731 *delay = (clkout_delay_t)this->reg->reg_cfg2.bits.clkout_delay;
sdivarci 0:0061165683ee 732
sdivarci 0:0061165683ee 733 return 0;
sdivarci 0:0061165683ee 734 }
sdivarci 0:0061165683ee 735
sdivarci 0:0061165683ee 736 template <class REG>
sdivarci 0:0061165683ee 737 int MAX4146X<REG>::set_bclk_postdiv(bclk_postdiv_t div)
sdivarci 0:0061165683ee 738 {
sdivarci 0:0061165683ee 739 SET_BIT_FIELD(CFG2_ADDR, this->reg->reg_cfg2, this->reg->reg_cfg2.bits.bclk_postdiv, div);
sdivarci 0:0061165683ee 740
sdivarci 0:0061165683ee 741 return 0;
sdivarci 0:0061165683ee 742 }
sdivarci 0:0061165683ee 743
sdivarci 0:0061165683ee 744 template <class REG>
sdivarci 0:0061165683ee 745 int MAX4146X<REG>::get_bclk_postdiv(bclk_postdiv_t* div)
sdivarci 0:0061165683ee 746 {
sdivarci 0:0061165683ee 747 int ret;
sdivarci 0:0061165683ee 748
sdivarci 0:0061165683ee 749 ret = read_register(CFG2_ADDR, (uint8_t *) & (this->reg->reg_cfg2), 1);
sdivarci 0:0061165683ee 750 if (ret < 0) {
sdivarci 0:0061165683ee 751 return ret;
sdivarci 0:0061165683ee 752 }
sdivarci 0:0061165683ee 753
sdivarci 0:0061165683ee 754 *div = (bclk_postdiv_t)this->reg->reg_cfg2.bits.bclk_postdiv;
sdivarci 0:0061165683ee 755
sdivarci 0:0061165683ee 756 return 0;
sdivarci 0:0061165683ee 757 }
sdivarci 0:0061165683ee 758
sdivarci 0:0061165683ee 759 template <class REG>
sdivarci 0:0061165683ee 760 int MAX4146X<REG>::set_bclk_prediv(uint8_t prediv)
sdivarci 0:0061165683ee 761 {
sdivarci 0:0061165683ee 762 if (prediv < 3) {
sdivarci 0:0061165683ee 763 return -1;
sdivarci 0:0061165683ee 764 }
sdivarci 0:0061165683ee 765
sdivarci 0:0061165683ee 766 SET_BIT_FIELD(CFG3_ADDR, this->reg->reg_cfg3, this->reg->reg_cfg3.bits.bclk_prediv, prediv);
sdivarci 0:0061165683ee 767
sdivarci 0:0061165683ee 768 return 0;
sdivarci 0:0061165683ee 769 }
sdivarci 0:0061165683ee 770
sdivarci 0:0061165683ee 771 template <class REG>
sdivarci 0:0061165683ee 772 int MAX4146X<REG>::get_bclk_prediv(uint8_t* prediv)
sdivarci 0:0061165683ee 773 {
sdivarci 0:0061165683ee 774 int ret;
sdivarci 0:0061165683ee 775
sdivarci 0:0061165683ee 776 ret = read_register(CFG3_ADDR, (uint8_t *) & (this->reg->reg_cfg3), 1);
sdivarci 0:0061165683ee 777 if (ret < 0) {
sdivarci 0:0061165683ee 778 return ret;
sdivarci 0:0061165683ee 779 }
sdivarci 0:0061165683ee 780
sdivarci 0:0061165683ee 781 *prediv = (uint8_t)this->reg->reg_cfg3.bits.bclk_prediv;
sdivarci 0:0061165683ee 782
sdivarci 0:0061165683ee 783 return 0;
sdivarci 0:0061165683ee 784 }
sdivarci 0:0061165683ee 785
sdivarci 0:0061165683ee 786 template <class REG>
sdivarci 0:0061165683ee 787 int MAX4146X<REG>::set_pwdn_mode(pwdn_mode_t pwdn_mode)
sdivarci 0:0061165683ee 788 {
sdivarci 0:0061165683ee 789 SET_BIT_FIELD(CFG4_ADDR, this->reg->reg_cfg4, this->reg->reg_cfg4.bits.pwdn_mode, pwdn_mode);
sdivarci 0:0061165683ee 790
sdivarci 0:0061165683ee 791 return 0;
sdivarci 0:0061165683ee 792 }
sdivarci 0:0061165683ee 793
sdivarci 0:0061165683ee 794 template <class REG>
sdivarci 0:0061165683ee 795 int MAX4146X<REG>::get_pwdn_mode(pwdn_mode_t* pwdn_mode)
sdivarci 0:0061165683ee 796 {
sdivarci 0:0061165683ee 797 int ret;
sdivarci 0:0061165683ee 798
sdivarci 0:0061165683ee 799 ret = read_register(CFG4_ADDR, (uint8_t *) & (this->reg->reg_cfg4), 1);
sdivarci 0:0061165683ee 800 if (ret < 0) {
sdivarci 0:0061165683ee 801 return ret;
sdivarci 0:0061165683ee 802 }
sdivarci 0:0061165683ee 803
sdivarci 0:0061165683ee 804 *pwdn_mode = (pwdn_mode_t)this->reg->reg_cfg4.bits.pwdn_mode;
sdivarci 0:0061165683ee 805
sdivarci 0:0061165683ee 806 return 0;
sdivarci 0:0061165683ee 807 }
sdivarci 0:0061165683ee 808
sdivarci 0:0061165683ee 809 template <class REG>
sdivarci 0:0061165683ee 810 int MAX4146X<REG>::set_tstep(uint8_t tstep)
sdivarci 0:0061165683ee 811 {
sdivarci 0:0061165683ee 812 SET_BIT_FIELD(CFG5_ADDR, this->reg->reg_cfg5, this->reg->reg_cfg5.bits.tstep, tstep);
sdivarci 0:0061165683ee 813
sdivarci 0:0061165683ee 814 return 0;
sdivarci 0:0061165683ee 815 }
sdivarci 0:0061165683ee 816
sdivarci 0:0061165683ee 817 template <class REG>
sdivarci 0:0061165683ee 818 int MAX4146X<REG>::get_tstep(uint8_t* tstep)
sdivarci 0:0061165683ee 819 {
sdivarci 0:0061165683ee 820 int ret;
sdivarci 0:0061165683ee 821
sdivarci 0:0061165683ee 822 ret = read_register(CFG5_ADDR, (uint8_t *) & (this->reg->reg_cfg5), 1);
sdivarci 0:0061165683ee 823 if (ret < 0) {
sdivarci 0:0061165683ee 824 return ret;
sdivarci 0:0061165683ee 825 }
sdivarci 0:0061165683ee 826
sdivarci 0:0061165683ee 827 *tstep = (uint8_t)this->reg->reg_cfg5.bits.tstep;
sdivarci 0:0061165683ee 828
sdivarci 0:0061165683ee 829 return 0;
sdivarci 0:0061165683ee 830 }
sdivarci 0:0061165683ee 831 /*sdivarci*/
sdivarci 0:0061165683ee 832 template <class REG>
sdivarci 0:0061165683ee 833 int MAX4146X<REG>::set_i2c_txen1(i2c_txen1_t setting)
sdivarci 0:0061165683ee 834 {
sdivarci 0:0061165683ee 835 SET_BIT_FIELD(CFG6_ADDR, this->reg->reg_cfg6, this->reg->reg_cfg6.bits.i2c_txen1, setting);
sdivarci 0:0061165683ee 836
sdivarci 0:0061165683ee 837 return 0;
sdivarci 0:0061165683ee 838 }
sdivarci 0:0061165683ee 839
sdivarci 0:0061165683ee 840 template <class REG>
sdivarci 0:0061165683ee 841 int MAX4146X<REG>::set_i2c_txen2(i2c_txen2_t setting)
sdivarci 0:0061165683ee 842 {
sdivarci 0:0061165683ee 843 SET_BIT_FIELD(CFG7_ADDR, this->reg->reg_cfg7, this->reg->reg_cfg7.bits.i2c_txen2, setting);
sdivarci 0:0061165683ee 844
sdivarci 0:0061165683ee 845 return 0;
sdivarci 0:0061165683ee 846 }
sdivarci 0:0061165683ee 847
sdivarci 0:0061165683ee 848 template <class REG>
sdivarci 0:0061165683ee 849 int MAX4146X<REG>::set_i2c_data(uint8_t setting)
sdivarci 0:0061165683ee 850 {
sdivarci 0:0061165683ee 851 return write_register(I2C3_ADDR, (uint8_t *)&setting, 1);
sdivarci 0:0061165683ee 852 }
sdivarci 0:0061165683ee 853
sdivarci 0:0061165683ee 854
sdivarci 0:0061165683ee 855
sdivarci 0:0061165683ee 856
sdivarci 0:0061165683ee 857 template <class REG>
sdivarci 0:0061165683ee 858 int MAX4146X<REG>::set_pa_boost(pa_boost_t pa_boost)
sdivarci 0:0061165683ee 859 {
sdivarci 0:0061165683ee 860 SET_BIT_FIELD(SHDN_ADDR, this->reg->reg_shdn, this->reg->reg_shdn.bits.pa_boost, pa_boost);
sdivarci 0:0061165683ee 861
sdivarci 0:0061165683ee 862 return 0;
sdivarci 0:0061165683ee 863 }
sdivarci 0:0061165683ee 864
sdivarci 0:0061165683ee 865 template <class REG>
sdivarci 0:0061165683ee 866 int MAX4146X<REG>::get_pa_boost(pa_boost_t* pa_boost)
sdivarci 0:0061165683ee 867 {
sdivarci 0:0061165683ee 868 int ret;
sdivarci 0:0061165683ee 869
sdivarci 0:0061165683ee 870 ret = read_register(CFG5_ADDR, (uint8_t *) & (this->reg->reg_shdn), 1);
sdivarci 0:0061165683ee 871 if (ret < 0) {
sdivarci 0:0061165683ee 872 return ret;
sdivarci 0:0061165683ee 873 }
sdivarci 0:0061165683ee 874
sdivarci 0:0061165683ee 875 *pa_boost = (pa_boost_t)this->reg->reg_shdn.bits.pa_boost;
sdivarci 0:0061165683ee 876
sdivarci 0:0061165683ee 877 return 0;
sdivarci 0:0061165683ee 878 }
sdivarci 0:0061165683ee 879
sdivarci 0:0061165683ee 880 template <class REG>
sdivarci 0:0061165683ee 881 int MAX4146X<REG>::set_papwr(papwr_t papwr)
sdivarci 0:0061165683ee 882 {
sdivarci 0:0061165683ee 883 SET_BIT_FIELD(PA1_ADDR, this->reg->reg_pa1, this->reg->reg_pa1.bits.papwr, papwr);
sdivarci 0:0061165683ee 884
sdivarci 0:0061165683ee 885 return 0;
sdivarci 0:0061165683ee 886 }
sdivarci 0:0061165683ee 887
sdivarci 0:0061165683ee 888 template <class REG>
sdivarci 0:0061165683ee 889 int MAX4146X<REG>::get_papwr(papwr_t* papwr)
sdivarci 0:0061165683ee 890 {
sdivarci 0:0061165683ee 891 int ret;
sdivarci 0:0061165683ee 892
sdivarci 0:0061165683ee 893 ret = read_register(PA1_ADDR, (uint8_t *) & (this->reg->reg_pa1), 1);
sdivarci 0:0061165683ee 894 if (ret < 0) {
sdivarci 0:0061165683ee 895 return ret;
sdivarci 0:0061165683ee 896 }
sdivarci 0:0061165683ee 897
sdivarci 0:0061165683ee 898 *papwr = (papwr_t)this->reg->reg_pa1.bits.papwr;
sdivarci 0:0061165683ee 899
sdivarci 0:0061165683ee 900 return 0;
sdivarci 0:0061165683ee 901 }
sdivarci 0:0061165683ee 902
sdivarci 0:0061165683ee 903 template <class REG>
sdivarci 0:0061165683ee 904 int MAX4146X<REG>::set_pacap(pacap_t pacap)
sdivarci 0:0061165683ee 905 {
sdivarci 0:0061165683ee 906 SET_BIT_FIELD(PA2_ADDR, this->reg->reg_pa2, this->reg->reg_pa2.bits.pacap, pacap);
sdivarci 0:0061165683ee 907
sdivarci 0:0061165683ee 908 return 0;
sdivarci 0:0061165683ee 909 }
sdivarci 0:0061165683ee 910
sdivarci 0:0061165683ee 911 template <class REG>
sdivarci 0:0061165683ee 912 int MAX4146X<REG>::get_pacap(pacap_t* pacap)
sdivarci 0:0061165683ee 913 {
sdivarci 0:0061165683ee 914 int ret;
sdivarci 0:0061165683ee 915
sdivarci 0:0061165683ee 916 ret = read_register(CFG5_ADDR, (uint8_t *) & (this->reg->reg_pa2), 1);
sdivarci 0:0061165683ee 917 if (ret < 0) {
sdivarci 0:0061165683ee 918 return ret;
sdivarci 0:0061165683ee 919 }
sdivarci 0:0061165683ee 920
sdivarci 0:0061165683ee 921 *pacap = (pacap_t)this->reg->reg_pa2.bits.pacap;
sdivarci 0:0061165683ee 922
sdivarci 0:0061165683ee 923 return 0;
sdivarci 0:0061165683ee 924 }
sdivarci 0:0061165683ee 925
sdivarci 0:0061165683ee 926 template <class REG>
sdivarci 0:0061165683ee 927 int MAX4146X<REG>::set_cplin(cplin_t cplin)
sdivarci 0:0061165683ee 928 {
sdivarci 0:0061165683ee 929 SET_BIT_FIELD(PLL1_ADDR, this->reg->reg_pll1, this->reg->reg_pll1.bits.cplin, cplin);
sdivarci 0:0061165683ee 930
sdivarci 0:0061165683ee 931 return 0;
sdivarci 0:0061165683ee 932 }
sdivarci 0:0061165683ee 933
sdivarci 0:0061165683ee 934 template <class REG>
sdivarci 0:0061165683ee 935 int MAX4146X<REG>::get_cplin(cplin_t* cplin)
sdivarci 0:0061165683ee 936 {
sdivarci 0:0061165683ee 937 int ret;
sdivarci 0:0061165683ee 938
sdivarci 0:0061165683ee 939 ret = read_register(PLL1_ADDR, (uint8_t *) & (this->reg->reg_pll1), 1);
sdivarci 0:0061165683ee 940 if (ret < 0) {
sdivarci 0:0061165683ee 941 return ret;
sdivarci 0:0061165683ee 942 }
sdivarci 0:0061165683ee 943
sdivarci 0:0061165683ee 944 *cplin = (cplin_t)this->reg->reg_pll1.bits.cplin;
sdivarci 0:0061165683ee 945
sdivarci 0:0061165683ee 946 return 0;
sdivarci 0:0061165683ee 947 }
sdivarci 0:0061165683ee 948
sdivarci 0:0061165683ee 949 template <class REG>
sdivarci 0:0061165683ee 950 int MAX4146X<REG>::set_fracmode(fracmode_t fracmode)
sdivarci 0:0061165683ee 951 {
sdivarci 0:0061165683ee 952 SET_BIT_FIELD(PLL1_ADDR, this->reg->reg_pll1, this->reg->reg_pll1.bits.fracmode, fracmode);
sdivarci 0:0061165683ee 953
sdivarci 0:0061165683ee 954 return 0;
sdivarci 0:0061165683ee 955 }
sdivarci 0:0061165683ee 956
sdivarci 0:0061165683ee 957 template <class REG>
sdivarci 0:0061165683ee 958 int MAX4146X<REG>::get_fracmode(fracmode_t* fracmode)
sdivarci 0:0061165683ee 959 {
sdivarci 0:0061165683ee 960 int ret;
sdivarci 0:0061165683ee 961
sdivarci 0:0061165683ee 962 ret = read_register(PLL1_ADDR, (uint8_t *) & (this->reg->reg_pll1), 1);
sdivarci 0:0061165683ee 963 if (ret < 0) {
sdivarci 0:0061165683ee 964 return ret;
sdivarci 0:0061165683ee 965 }
sdivarci 0:0061165683ee 966
sdivarci 0:0061165683ee 967 *fracmode = (fracmode_t)this->reg->reg_pll1.bits.fracmode;
sdivarci 0:0061165683ee 968
sdivarci 0:0061165683ee 969 return 0;
sdivarci 0:0061165683ee 970 }
sdivarci 0:0061165683ee 971
sdivarci 0:0061165683ee 972 template <class REG>
sdivarci 0:0061165683ee 973 int MAX4146X<REG>::set_lodiv(lodiv_t lodiv)
sdivarci 0:0061165683ee 974 {
sdivarci 0:0061165683ee 975 SET_BIT_FIELD(PLL1_ADDR, this->reg->reg_pll1, this->reg->reg_pll1.bits.lodiv, lodiv);
sdivarci 0:0061165683ee 976
sdivarci 0:0061165683ee 977 return 0;
sdivarci 0:0061165683ee 978 }
sdivarci 0:0061165683ee 979
sdivarci 0:0061165683ee 980 template <class REG>
sdivarci 0:0061165683ee 981 int MAX4146X<REG>::get_lodiv(lodiv_t* lodiv)
sdivarci 0:0061165683ee 982 {
sdivarci 0:0061165683ee 983 int ret;
sdivarci 0:0061165683ee 984
sdivarci 0:0061165683ee 985 ret = read_register(PLL1_ADDR, (uint8_t *) & (this->reg->reg_pll1), 1);
sdivarci 0:0061165683ee 986 if (ret < 0) {
sdivarci 0:0061165683ee 987 return ret;
sdivarci 0:0061165683ee 988 }
sdivarci 0:0061165683ee 989
sdivarci 0:0061165683ee 990 *lodiv = (lodiv_t)this->reg->reg_pll1.bits.lodiv;
sdivarci 0:0061165683ee 991
sdivarci 0:0061165683ee 992 return 0;
sdivarci 0:0061165683ee 993 }
sdivarci 0:0061165683ee 994
sdivarci 0:0061165683ee 995 template <class REG>
sdivarci 0:0061165683ee 996 int MAX4146X<REG>::set_lomode(lomode_t lomode)
sdivarci 0:0061165683ee 997 {
sdivarci 0:0061165683ee 998 SET_BIT_FIELD(PLL1_ADDR, this->reg->reg_pll1, this->reg->reg_pll1.bits.lomode, lomode);
sdivarci 0:0061165683ee 999
sdivarci 0:0061165683ee 1000 return 0;
sdivarci 0:0061165683ee 1001 }
sdivarci 0:0061165683ee 1002
sdivarci 0:0061165683ee 1003 template <class REG>
sdivarci 0:0061165683ee 1004 int MAX4146X<REG>::get_lomode(lomode_t* lomode)
sdivarci 0:0061165683ee 1005 {
sdivarci 0:0061165683ee 1006 int ret;
sdivarci 0:0061165683ee 1007
sdivarci 0:0061165683ee 1008 ret = read_register(PLL1_ADDR, (uint8_t *) & (this->reg->reg_pll1), 1);
sdivarci 0:0061165683ee 1009 if (ret < 0) {
sdivarci 0:0061165683ee 1010 return ret;
sdivarci 0:0061165683ee 1011 }
sdivarci 0:0061165683ee 1012
sdivarci 0:0061165683ee 1013 *lomode = (lomode_t)this->reg->reg_pll1.bits.lomode;
sdivarci 0:0061165683ee 1014
sdivarci 0:0061165683ee 1015 return 0;
sdivarci 0:0061165683ee 1016 }
sdivarci 0:0061165683ee 1017
sdivarci 0:0061165683ee 1018 template <class REG>
sdivarci 0:0061165683ee 1019 int MAX4146X<REG>::set_cpval(cpval_t cpval)
sdivarci 0:0061165683ee 1020 {
sdivarci 0:0061165683ee 1021
sdivarci 0:0061165683ee 1022 SET_BIT_FIELD(PLL2_ADDR, this->reg->reg_pll2, this->reg->reg_pll2.bits.cpval, cpval);
sdivarci 0:0061165683ee 1023
sdivarci 0:0061165683ee 1024 return 0;
sdivarci 0:0061165683ee 1025 }
sdivarci 0:0061165683ee 1026
sdivarci 0:0061165683ee 1027 template <class REG>
sdivarci 0:0061165683ee 1028 int MAX4146X<REG>::get_cpval(cpval_t* cpval)
sdivarci 0:0061165683ee 1029 {
sdivarci 0:0061165683ee 1030 int ret;
sdivarci 0:0061165683ee 1031
sdivarci 0:0061165683ee 1032 ret = read_register(PLL2_ADDR, (uint8_t *) & (this->reg->reg_pll2), 1);
sdivarci 0:0061165683ee 1033 if (ret < 0) {
sdivarci 0:0061165683ee 1034 return ret;
sdivarci 0:0061165683ee 1035 }
sdivarci 0:0061165683ee 1036
sdivarci 0:0061165683ee 1037 *cpval = (cpval_t)this->reg->reg_pll2.bits.cpval;
sdivarci 0:0061165683ee 1038
sdivarci 0:0061165683ee 1039 return 0;
sdivarci 0:0061165683ee 1040 }
sdivarci 0:0061165683ee 1041
sdivarci 0:0061165683ee 1042 template <class REG>
sdivarci 0:0061165683ee 1043 int MAX4146X<REG>::set_frequency(uint32_t freq)
sdivarci 0:0061165683ee 1044 {
sdivarci 0:0061165683ee 1045 uint8_t value[3] = {(uint8_t)(freq >> 16), (uint8_t)(freq >> 8), (uint8_t)freq};
sdivarci 0:0061165683ee 1046
sdivarci 0:0061165683ee 1047 return write_register(PLL3_ADDR, (uint8_t *)&value, 3);
sdivarci 0:0061165683ee 1048
sdivarci 0:0061165683ee 1049 }
sdivarci 0:0061165683ee 1050
sdivarci 0:0061165683ee 1051 template <class REG>
sdivarci 0:0061165683ee 1052 int MAX4146X<REG>::get_frequency(uint32_t* freq)
sdivarci 0:0061165683ee 1053 {
sdivarci 0:0061165683ee 1054 int ret;
sdivarci 0:0061165683ee 1055
sdivarci 0:0061165683ee 1056 uint8_t value[3];
sdivarci 0:0061165683ee 1057
sdivarci 0:0061165683ee 1058 ret = read_register(PLL3_ADDR, (uint8_t *)&value, 3);
sdivarci 0:0061165683ee 1059 if (ret < 0) {
sdivarci 0:0061165683ee 1060 return ret;
sdivarci 0:0061165683ee 1061 }
sdivarci 0:0061165683ee 1062
sdivarci 0:0061165683ee 1063 *freq = (uint32_t)((value[0] << 16) + (value[1] << 8) + value[2]);
sdivarci 0:0061165683ee 1064
sdivarci 0:0061165683ee 1065 return 0;
sdivarci 0:0061165683ee 1066 }
sdivarci 0:0061165683ee 1067
sdivarci 0:0061165683ee 1068 template <class REG>
sdivarci 0:0061165683ee 1069 int MAX4146X<REG>::set_deltaf(uint8_t deltaf)
sdivarci 0:0061165683ee 1070 {
sdivarci 0:0061165683ee 1071 if (deltaf > 127) {
sdivarci 0:0061165683ee 1072 return -1;
sdivarci 0:0061165683ee 1073 }
sdivarci 0:0061165683ee 1074
sdivarci 0:0061165683ee 1075 SET_BIT_FIELD(PLL6_ADDR, this->reg->reg_pll6, this->reg->reg_pll6.bits.deltaf, deltaf);
sdivarci 0:0061165683ee 1076
sdivarci 0:0061165683ee 1077 return 0;
sdivarci 0:0061165683ee 1078 }
sdivarci 0:0061165683ee 1079
sdivarci 0:0061165683ee 1080 template <class REG>
sdivarci 0:0061165683ee 1081 int MAX4146X<REG>::get_deltaf(uint8_t* deltaf)
sdivarci 0:0061165683ee 1082 {
sdivarci 0:0061165683ee 1083 int ret;
sdivarci 0:0061165683ee 1084
sdivarci 0:0061165683ee 1085 ret = read_register(PLL6_ADDR, (uint8_t *) & (this->reg->reg_pll6), 1);
sdivarci 0:0061165683ee 1086 if (ret < 0) {
sdivarci 0:0061165683ee 1087 return ret;
sdivarci 0:0061165683ee 1088 }
sdivarci 0:0061165683ee 1089
sdivarci 0:0061165683ee 1090 *deltaf = (uint8_t)this->reg->reg_pll6.bits.deltaf;
sdivarci 0:0061165683ee 1091
sdivarci 0:0061165683ee 1092 return 0;
sdivarci 0:0061165683ee 1093 }
sdivarci 0:0061165683ee 1094
sdivarci 0:0061165683ee 1095 template <class REG>
sdivarci 0:0061165683ee 1096 int MAX4146X<REG>::set_deltaf_shape(uint8_t deltaf_shape)
sdivarci 0:0061165683ee 1097 {
sdivarci 0:0061165683ee 1098 if (deltaf_shape > 15) {
sdivarci 0:0061165683ee 1099 return -1;
sdivarci 0:0061165683ee 1100 }
sdivarci 0:0061165683ee 1101
sdivarci 0:0061165683ee 1102 SET_BIT_FIELD(PLL7_ADDR, this->reg->reg_pll7, this->reg->reg_pll7.bits.deltaf_shape, deltaf_shape);
sdivarci 0:0061165683ee 1103
sdivarci 0:0061165683ee 1104 return 0;
sdivarci 0:0061165683ee 1105 }
sdivarci 0:0061165683ee 1106
sdivarci 0:0061165683ee 1107 template <class REG>
sdivarci 0:0061165683ee 1108 int MAX4146X<REG>::get_deltaf_shape(uint8_t* deltaf_shape)
sdivarci 0:0061165683ee 1109 {
sdivarci 0:0061165683ee 1110 int ret;
sdivarci 0:0061165683ee 1111
sdivarci 0:0061165683ee 1112 ret = read_register(PLL7_ADDR, (uint8_t *) & (this->reg->reg_pll7), 1);
sdivarci 0:0061165683ee 1113 if (ret < 0) {
sdivarci 0:0061165683ee 1114 return ret;
sdivarci 0:0061165683ee 1115 }
sdivarci 0:0061165683ee 1116
sdivarci 0:0061165683ee 1117 *deltaf_shape = (uint8_t)this->reg->reg_pll7.bits.deltaf_shape;
sdivarci 0:0061165683ee 1118
sdivarci 0:0061165683ee 1119 return 0;
sdivarci 0:0061165683ee 1120 }
sdivarci 0:0061165683ee 1121
sdivarci 0:0061165683ee 1122 template <class REG>
sdivarci 0:0061165683ee 1123 int MAX4146X<REG>::set_pktlen_mode(pktlen_mode_t pktlen_mode)
sdivarci 0:0061165683ee 1124 {
sdivarci 0:0061165683ee 1125 SET_BIT_FIELD(I2C1_ADDR, this->reg->reg_i2c1, this->reg->reg_i2c1.bits.pktlen_mode, pktlen_mode);
sdivarci 0:0061165683ee 1126
sdivarci 0:0061165683ee 1127 return 0;
sdivarci 0:0061165683ee 1128 }
sdivarci 0:0061165683ee 1129
sdivarci 0:0061165683ee 1130 template <class REG>
sdivarci 0:0061165683ee 1131 int MAX4146X<REG>::get_pktlen_mode(pktlen_mode_t* pktlen_mode)
sdivarci 0:0061165683ee 1132 {
sdivarci 0:0061165683ee 1133 int ret;
sdivarci 0:0061165683ee 1134
sdivarci 0:0061165683ee 1135 ret = read_register(I2C1_ADDR, (uint8_t *) & (this->reg->reg_i2c1), 1);
sdivarci 0:0061165683ee 1136 if (ret < 0) {
sdivarci 0:0061165683ee 1137 return ret;
sdivarci 0:0061165683ee 1138 }
sdivarci 0:0061165683ee 1139
sdivarci 0:0061165683ee 1140 *pktlen_mode = (pktlen_mode_t)this->reg->reg_i2c1.bits.pktlen_mode;
sdivarci 0:0061165683ee 1141
sdivarci 0:0061165683ee 1142 return 0;
sdivarci 0:0061165683ee 1143 }
sdivarci 0:0061165683ee 1144
sdivarci 0:0061165683ee 1145
sdivarci 0:0061165683ee 1146 template <class REG>
sdivarci 0:0061165683ee 1147 int MAX4146X<REG>::set_i2c_pktlen(uint16_t pktlen)
sdivarci 0:0061165683ee 1148 {
sdivarci 0:0061165683ee 1149 if (pktlen > 0x7FF) {
sdivarci 0:0061165683ee 1150 return -1;
sdivarci 0:0061165683ee 1151 }
sdivarci 0:0061165683ee 1152
sdivarci 0:0061165683ee 1153 SET_BIT_FIELD(I2C1_ADDR, this->reg->reg_i2c1, this->reg->reg_i2c1.bits.pktlen_14_to_8, (uint8_t)((pktlen >> 8) & 0x07));
sdivarci 0:0061165683ee 1154
sdivarci 0:0061165683ee 1155 uint8_t value = (uint8_t)(pktlen & 0xFF);
sdivarci 0:0061165683ee 1156
sdivarci 0:0061165683ee 1157 return write_register(I2C2_ADDR, (uint8_t *)&value, 1);
sdivarci 0:0061165683ee 1158 }
sdivarci 0:0061165683ee 1159
sdivarci 0:0061165683ee 1160 template <class REG>
sdivarci 0:0061165683ee 1161 int MAX4146X<REG>::get_i2c_pktlen(uint16_t* pktlen)
sdivarci 0:0061165683ee 1162 {
sdivarci 0:0061165683ee 1163 int ret;
sdivarci 0:0061165683ee 1164
sdivarci 0:0061165683ee 1165 ret = read_register(I2C1_ADDR, (uint8_t *) & (this->reg->reg_i2c1), 1);
sdivarci 0:0061165683ee 1166 if (ret < 0) {
sdivarci 0:0061165683ee 1167 return ret;
sdivarci 0:0061165683ee 1168 }
sdivarci 0:0061165683ee 1169
sdivarci 0:0061165683ee 1170 ret = read_register(I2C2_ADDR, (uint8_t *) & (this->reg->reg_i2c2), 1);
sdivarci 0:0061165683ee 1171 if (ret < 0) {
sdivarci 0:0061165683ee 1172 return ret;
sdivarci 0:0061165683ee 1173 }
sdivarci 0:0061165683ee 1174
sdivarci 0:0061165683ee 1175 *pktlen = (uint16_t)(((this->reg->reg_i2c1.raw & 0x7F)<<8) + (this->reg->reg_i2c2.raw &0x7F));
sdivarci 0:0061165683ee 1176
sdivarci 0:0061165683ee 1177 return 0;
sdivarci 0:0061165683ee 1178 }
sdivarci 0:0061165683ee 1179
sdivarci 0:0061165683ee 1180 template <class REG>
sdivarci 0:0061165683ee 1181 int MAX4146X<REG>::initial_programming(void)
sdivarci 0:0061165683ee 1182 {
sdivarci 0:0061165683ee 1183 uint8_t value = 0x80;
sdivarci 0:0061165683ee 1184 write_register(ADDL2_ADDR, (uint8_t *)&value, 1);
sdivarci 0:0061165683ee 1185
sdivarci 0:0061165683ee 1186 return write_register(CFG1_ADDR, default_register_value_1, 20);
sdivarci 0:0061165683ee 1187 }
sdivarci 0:0061165683ee 1188
sdivarci 0:0061165683ee 1189 template <>
sdivarci 0:0061165683ee 1190 int MAX4146X<max41460_reg_map_t>::initial_programming(void)
sdivarci 0:0061165683ee 1191 {
sdivarci 0:0061165683ee 1192 if (this->ssel != NULL){
sdivarci 0:0061165683ee 1193 *this->ssel = 0;
sdivarci 0:0061165683ee 1194 wait_us(100);
sdivarci 0:0061165683ee 1195 }
sdivarci 0:0061165683ee 1196
sdivarci 0:0061165683ee 1197 int rtn = write_register(CFG1_ADDR, default_register_value_0, 17);
sdivarci 0:0061165683ee 1198
sdivarci 0:0061165683ee 1199 if (this->ssel != NULL){
sdivarci 0:0061165683ee 1200 wait_us(90);
sdivarci 0:0061165683ee 1201 *this->ssel = 1;
sdivarci 0:0061165683ee 1202 }
sdivarci 0:0061165683ee 1203
sdivarci 0:0061165683ee 1204 return rtn;
sdivarci 0:0061165683ee 1205 }
sdivarci 0:0061165683ee 1206
sdivarci 0:0061165683ee 1207
sdivarci 0:0061165683ee 1208 template class MAX4146X<max41460_reg_map_t>;
sdivarci 0:0061165683ee 1209 template class MAX4146X<max41461_2_reg_map_t>;
sdivarci 0:0061165683ee 1210 template class MAX4146X<max41463_4_reg_map_t>;
sdivarci 0:0061165683ee 1211
sdivarci 0:0061165683ee 1212