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TPI_Type Struct Reference

TPI_Type Struct Reference
[Trace Port Interface (TPI)]

Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_cm3.h>

Data Fields

__IO uint32_t SSPSR
__IO uint32_t CSPSR
__IO uint32_t ACPR
__IO uint32_t SPPR
__I uint32_t FFSR
__IO uint32_t FFCR
__I uint32_t FSCR
__I uint32_t TRIGGER
__I uint32_t FIFO0
__I uint32_t ITATBCTR2
__I uint32_t ITATBCTR0
__I uint32_t FIFO1
__IO uint32_t ITCTRL
__IO uint32_t CLAIMSET
__IO uint32_t CLAIMCLR
__I uint32_t DEVID
__I uint32_t DEVTYPE

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 827 of file core_cm3.h.


Field Documentation

__IO uint32_t ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 832 of file core_cm3.h.

__IO uint32_t CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 849 of file core_cm3.h.

__IO uint32_t CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

Definition at line 848 of file core_cm3.h.

__IO uint32_t CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 830 of file core_cm3.h.

__I uint32_t DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 851 of file core_cm3.h.

__I uint32_t DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 852 of file core_cm3.h.

__IO uint32_t FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 837 of file core_cm3.h.

__I uint32_t FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 836 of file core_cm3.h.

__I uint32_t FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 841 of file core_cm3.h.

__I uint32_t FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 845 of file core_cm3.h.

__I uint32_t FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 838 of file core_cm3.h.

__I uint32_t ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 844 of file core_cm3.h.

__I uint32_t ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 842 of file core_cm3.h.

__IO uint32_t ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 846 of file core_cm3.h.

__IO uint32_t SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 834 of file core_cm3.h.

__IO uint32_t SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 829 of file core_cm3.h.

__I uint32_t TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

Definition at line 840 of file core_cm3.h.